MC74HC251A D

MC74HC251A
8-Input Data Selector/
Multiplexer with
3-State Outputs
High−Performance Silicon−Gate CMOS
The MC54/74HC251 is identical in pinout to the LS251. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device selects one of the eight binary Data Inputs, as
determined by the Address Inputs. The Output Enable pin must be a
low level for the selected data to appear at the outputs. If Output
Enable is high, both the Y and the Y outputs are in the
high−impedance state. This 3−state feature allows the HC251 to be
used in bus−oriented systems.
The HC251 is similar in function to the HC251 which does not have
3−state outputs.
16
MARKING
DIAGRAMS
SOIC−16
D SUFFIX
CASE 751B
16
1
HC251AG
AWLYWW
1
16
TSSOP−16
DT SUFFIX
CASE 948F
16
HC
251A
ALYWG
G
1
Features
•
•
•
•
•
•
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1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 mA
High Noise Immunity Characteristic of CMOS Devices
These are Pb−Free Devices
PIN ASSIGNMENT
D3
1
16
VCC
D2
2
15
D4
D1
3
14
D5
D0
4
13
D6
Y
5
12
D7
Y
OUTPUT
ENABLE
GND
6
11
A0
7
10
A1
8
9
A2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
© Semiconductor Components Industries, LLC, 2010
January, 2010 − Rev. 0
1
Publication Order Number:
MC74HC251A/D
MC74HC251A
DATA
INPUTS
D0
4
D1
3
D2
2
D3
1
FUNCTION TABLE
Inputs
5 Y
DATA
OUTPUTS
D4 15
D5 14
6 Y
D6 13
D7 12
ADDRESS
INPUTS
A0 11
10
A1
A2 9
OUTPUT ENABLE
Outputs
A2
A1
A0
Output
Enabled
X
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
H
L
L
L
L
L
L
L
L
Y
Y
Z
D0
D1
D2
D3
D4
D5
D6
D7
Z
D0
D1
D2
D3
D4
D5
D6
D7
Z = high impedance
D0, D1, …, D7 = the level of the respective
D input.
7
PIN 16 = VCC
PIN 8 = GND
Figure 1. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
−0.5 to + 7.0
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
DC Input Voltage (Referenced to GND)
−1.5 to VCC + 1.5
V
Vout
DC Output Voltage (Referenced to GND)
−0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
±25
mA
Iout
DC Output Current, per Pin
±50
mA
ICC
DC Supply Current, VCC and GND Pins
±75
mA
PD
Power Dissipation in Still Air
500
TBD
mW
Tstg
Storage Temperature
−65 to + 150
°C
SOIC Package
TSSOP Package
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time
(Figure 2)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
−55
+125
°C
0
0
0
1000
500
400
ns
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2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC74HC251A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
− 55 to
25°C
v 85°C
v 125°C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC − 0.1 V
|Iout| v 20 mA
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC − 0.1 V
|Iout| v 20 mA
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
Vin = VIH or VIL
VOL
Maximum Low−Level Output
Voltage
|Iout| v 4.0 mA
|Iout| v 5.2 mA
Vin = VIH or VIL
|Iout| v 20 mA
Vin = VIH or VIL
|Iout| v 4.0 mA
|Iout| v 5.2 mA
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
± 0.1
± 1.0
± 1.0
mA
IOZ
Maximum Three−State
Leakage Current
Output in High−Impedance State
Vin = VIL or VIH
Vout = VCC or GND
6.0
± 0.5
± 5.0
± 10
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 mA
6.0
8
80
160
mA
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MC74HC251A
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
− 55 to
25°C
v 85°C
v 125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input D to Output Y or Y
(Figures 2, 3 and 6)
2.0
4.5
6.0
185
37
31
230
46
39
280
56
48
ns
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y or Y
(Figures 3 and 6)
2.0
4.5
6.0
205
41
35
255
51
43
310
62
53
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 5 and 7)
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 5 and 7)
2.0
4.5
6.0
145
29
25
180
36
31
220
44
38
ns
tPLZ,
tPHZ
Maximum Propagation Delay, Output Enable to Output Y
(Figures 5 and 7)
2.0
4.5
6.0
220
44
37
275
55
47
330
66
56
ns
tPZL,
tPZH
Maximum Propagation Delay, Output Enable to Output Y
(Figures 5 and 7)
2.0
4.5
6.0
150
30
26
190
38
33
225
45
38
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 2 and 6)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
Cin
Maximum Input Capacitance
−
10
10
10
pF
Cout
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
−
15
15
15
pF
Typical @ 25°C, VCC = 5.0 V
CPD
36
Power Dissipation Capacitance (Per Package)
pF
PIN DESCRIPTIONS
INPUTS
Output Enable (Pin 7)
D0, D1, …, D7 (Pins 4, 3, 2, 1, 15, 14, 13, 12)
Output Enable. This input pin must be at a low level for
the selected data to appear at the outputs. If the Output
Enable pin is high, both the Y and Y outputs are taken to the
high−impedance state.
Data inputs. Data on one of these eight binary inputs may
be selected to appear on the output.
CONTROL INPUTS
OUTPUTS
A0, A1, A2 (Pins 11, 10, 9)
Y, Y (Pins 5, 6)
Address inputs. The data on these pins are the binary
address of the selected input (see the Function Table).
Data outputs. The selected data is presented at these pins
in both true (Y output) and complemented (Y output) forms.
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MC74HC251A
SWITCHING WAVEFORMS
tr
tf
INPUT D
tr
VCC
90%
50%
10%
tPHL
tPLH
90%
50%
10%
OUTPUT Y
tTHL
tTLH
GND
tPHL
90%
50%
10%
OUTPUT Y
VCC
90%
50%
10%
INPUT D
GND
tPLH
tf
tTLH
tTHL
Figure 2.
Figure 3.
VCC
VALID
OUTPUT
ENABLE
VALID
VCC
INPUT A
OUTPUT
Y OR Y
GND
tPZL
50%
GND
tPLH
50%
Y OR Y
tPHL
tPLZ
50%
tPZH
tPHZ
50%
Y OR Y
HIGH
IMPEDANCE
10%
VOL
90%
VOH
50%
Figure 4.
HIGH
IMPEDANCE
Figure 5.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance
1 kW
CL*
CONNECT TO VCC WHEN
TESTING tPLZ AND tPZL.
CONNECT TO GND WHEN
TESTING tPHZ AND tPZH.
*Includes all probe and jig capacitance
Figure 6.
Figure 7.
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MC74HC251A
4
D0
3
D1
D2 2
D3 1
DATA
INPUTS
5 Y
D4 15
6 Y
D5 14
DATA
OUTPUTS
D6 13
D7 12
A 11
B 10
9
C
OUTPUT 7
ENABLE
Figure 8. Expanded Logic Diagram
ORDERING INFORMATION
Package
Shipping†
MC74HC251ADG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74HC251ADR2G
SOIC−16
(Pb−Free)
2500 Tape & Reel
TSSOP−16*
2500 Tape & Reel
Device
MC74HC251ADTR2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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MC74HC251A
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
−A−
16
9
1
8
−B−
P
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
8 PL
0.25 (0.010)
M
B
S
G
R
K
F
X 45 _
C
−T−
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
SOLDERING FOOTPRINT*
8X
6.40
16X
1
1.12
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC74HC251A
PACKAGE DIMENSIONS
TSSOP−16
DT SUFFIX
CASE 948F−01
ISSUE B
16X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
M
S
V
S
K
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
ÉÉÉ
S
K1
2X
L/2
16
9
J1
B
−U−
L
SECTION N−N
J
PIN 1
IDENT.
N
8
1
0.25 (0.010)
M
0.15 (0.006) T U
S
A
−V−
N
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
4.90
5.10 0.193 0.200
B
4.30
4.50 0.169 0.177
C
−−−
1.20
−−− 0.047
D
0.05
0.15 0.002 0.006
F
0.50
0.75 0.020 0.030
G
0.65 BSC
0.026 BSC
H
0.18
0.28 0.007
0.011
−W−
J
0.09
0.20 0.004 0.008
J1
0.09
0.16 0.004 0.006
K
0.19
0.30 0.007 0.012
K1
0.19
0.25 0.007 0.010
L
6.40 BSC
0.252 BSC
M
0_
8_
0_
8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MC74HC251A
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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Sales Representative
MC74HC251A/D