NCP361 D

NCP361, NCV361
USB Positive Overvoltage
Protection Controller with
Internal PMOS FET and
Overcurrent Protection
The NCP361 disconnects systems at its output when wrong VBUS
operating conditions are detected at its input. The system is positive
over−voltage protected up to +20 V.
Thanks to an integrated PMOS FET, no external device is
necessary, reducing the system cost and the PCB area of the
application board.
The NCP361 is able to instantaneously disconnect the output from
the input if the input voltage exceeds the overvoltage threshold
(5.675 V). Thanks to an overcurrent protection, the integrated PMOS
is turning off when the charge current exceeds current limit (see
options in ordering information).
The NCP361 provides a negative going flag (FLAG) output, which
alerts the system that voltage, current or overtemperature faults have
occurred.
In addition, the device has ESD−protected input (15 kV Air) when
bypassed with a 1 mF or larger capacitor.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Overvoltage Protection up to 20 V
On−chip PMOS Transistor
Overvoltage Lockout (OVLO)
Undervoltage Lockout (UVLO)
Overcurrent Protection
Alert FLAG Output
EN Enable Pin
Thermal Shutdown
Compliance to IEC61000−4−2 (Level 4)
8 kV (Contact)
15 kV (Air)
ESD Ratings: Machine Model = B
ESD Ratings: Human Body Model = 2
UDFN6 2x2 mm and TSOP−5 3x3 mm Packages
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This is a Pb−Free Device
MARKING
DIAGRAMS
6 PIN UDFN
CASE 517AB
1
xx M
G
5
1
xxx AYWG
G
TSOP−5
CASE 483
1
xxx
= Specific Device Code
M
= Date Code
A
= Assembly Location
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
EN 1
6 FLAG
GND 2
5 OUT
IN 3
4 OUT
UDFN
IN
1
GND
2
EN
3
5
OUT
4
FLAG
TSOP−5
(Top View)
Applications
•
•
•
•
•
•
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USB Devices
Mobile Phones
Peripheral
Personal Digital Applications
MP3 Players
Set Top Boxes
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
Q
© Semiconductor Components Industries, LLC, 2012
March, 2012 − Rev. 4
1
Publication Order Number:
NCP361/D
NCP361, NCV361
INPUT
OUTPUT
3
1 mF 25 V X5R 0603
C1
4
OUT
5
OUT
IN
C2
NCP361
1
EN
FLAG
GND
FLAG Power
1 mF 25 V X5R 0603
6
FLAG
2
R1
1M
J2
2
1
FLAG_State
Figure 1. Typical Application Circuit (UDFN Pinout)
OUTPUT
INPUT
(2 out pins in
UDFN package)
Thermal Shutdown
Soft Start
FLAGV
EN
LDO
UVLO
OVLO
VREF
Figure 2. Functional Block Diagram
PIN FUNCTION DESCRIPTION (UDFN Package)
Pin No.
Name
Type
Description
1
EN
INPUT
2
GND
POWER
Ground
3
IN
POWER
Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger,
must be connected between this pin and GND.
4, 5
OUT
OUTPUT
Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is
above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to these pins.
The two OUT pins must be hardwired to common supply.
6
FLAG
OUTPUT
Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin
goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality,
an external pull up resistor to VCC must be added.
Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND or to a I/O pin. This pin does not have an impact on the fault detection.
PIN FUNCTION DESCRIPTION (TSOP−5 Package)
Pin No.
Name
Type
1
IN
POWER
Input Voltage Pin. This pin is connected to the VBUS. A 1 mF low ESR ceramic capacitor, or larger,
must be connected between this pin and GND.
2
GND
POWER
Ground
3
EN
INPUT
4
FLAG
OUTPUT
Fault Indication Pin. This pin allows an external system to detect a fault on VBUS pin. The FLAG pin
goes low when input voltage exceeds OVLO threshold. Since the FLAG pin is open drain functionality,
an external pull up resistor to VCC must be added.
5
OUT
OUTPUT
Output Voltage Pin. The output is disconnected from the VBUS power supply when the input voltage is
above OVLO threshold or below UVLO threshold. A 1 mF capacitor must be connected to this pin.
NOTE:
Description
Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND or to a I/O pin. This pin does not have an impact on the fault detection.
Pin out provided for concept purpose only and might change in the final product
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2
NCP361, NCV361
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Vminin
−0.3
V
Vmin
−0.3
V
Vmaxin
21
V
Maximum Voltage (All others to GND)
Vmax
7.0
V
Maximum DC Current from Vin to Vout (PMOS) (Note 1)
Imax
600
mA
RqJA
305
240
°C/W
Operating Ambient Temperature Range
TA
−40 to +85
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Junction Operating Temperature
TJ
150
°C
ESD Withstand Voltage (IEC 61000−4−2)
Human Body Model (HBM), Model = 2 (Note 2)
Machine Model (MM) Model = B (Note 3)
Vesd
15 Air, 8.0 Contact
2000
200
kV
V
V
Moisture Sensitivity
MSL
Level 1
−
Minimum Voltage (IN to GND)
Minimum Voltage (All others to GND)
Maximum Voltage (IN to GND)
Thermal Resistance, Junction−to−Air
TSOP−5
UDFN
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. With minimum PCB area. By decreasing RqJA, the current capability increases. See PCB recommendation page 9.
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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3
NCP361, NCV361
ELECTRICAL CHARACTERISTICS
(Min/Max limits values (−40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C, unless otherwise noted.)
Characteristic
Input Voltage Range
Symbol
Vin
Undervoltage Lockout Threshold
UVLO
Uvervoltage Lockout Hysteresis
UVLOhyst
Overvoltage Lockout Threshold
OVLO
Overvoltage Lockout Hysteresis
OVLOhyst
Vin versus Vout Dopout
Conditions
Min
Typ
1.2
Vin falls down UVLO threshold
Vin rises up OVLO threshold
Max
Unit
20
V
2.85
3.0
3.15
V
50
70
90
mV
5.43
5.675
5.9
V
50
100
125
mV
150
200
mV
750
950
mA
Vdrop
Vin = 5 V, I charge = 500 mA
Overcurrent Limit
Ilim
Vin = 5 V
Supply Quiescent Current
Idd
No Load, Vin = 5.25 V
20
35
mA
Standby Current
Istd
Vin = 5 V, EN = 1.2 V
26
37
mA
IDSS
VDS = 20 V, VGS = 0 V
0.08
Volflag
Vin > OVLO
Sink 1 mA on FLAG pin
Zero Gate Voltage Drain Current
FLAG Output Low Voltage
FLAG Leakage Current
550
mA
400
5.0
mV
FLAGleak
FLAG level = 5 V
EN Voltage High
Vih
Vin from 3.3 V to 5.5 V
nA
EN Voltage Low
Vil
Vin from 3.3 V to 5.5 V
EN Leakage Current
ENleak
EN = 5.5 V or GND
170
ton
From Vin > UVLO to Vout = 0.8xVin, See Fig 3 & 9
4.0
tstart
From Vin > UVLO to FLAG = 1.2 V, See Fig 3 & 10
3.0
toff
From Vin > OVLO to Vout ≤ 0.3 V, See Fig 4 & 11
Vin increasing from 5 V to 8 V at 3 V/ms.
No output capacitor.
0.7
Alert Delay
tstop
From Vin > OVLO to FLAG ≤ 0.4 V, See Fig 4 & 12
Vin increasing from 5 V to 8 V at 3 V/ms
1.0
ms
Disable Time
tdis
From EN 0.4 to 1.2V to Vout ≤ 0.3 V, See Fig 5 & 13
Vin = 4.75 V.
No output capacitor.
3.0
ms
Thermal Shutdown Temperature
Tsd
150
°C
Tsdhyst
30
°C
1.2
V
0.55
V
nA
TIMINGS
Start Up Delay
FLAG going up Delay
Output Turn Off Time
Thermal Shutdown Hysteresis
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4
15
ms
ms
1.5
ms
NCP361, NCV361
<OVLO
UVLO
Vin
ton
0.8 Vin
Vout
OVLO
Vin
toff
Vin − RDSon x I
Vin − RDS(on) x I
Vout
0.3 V
tstop
tstart
FLAG
FLAG
1.2 V
Figure 3. Start Up Sequence
Figure 4. Shutdown on Over Voltage Detection
EN
1.2 V
EN
0.4 V
1.2 V
tdis
Vout
Vin − RDS(on) x I
OVLO
Vout
0.3 V
UVLO
tstart
FLAG
FLAG
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
CONDITIONS
IN
OUT
VIN > OVLO or VIN < UVLO
Voltage, Current and Thermal Detection
Figure 7.
CONDITIONS
IN
OUT
Voltage, Current and Thermal Detection
Figure 8.
TYPICAL OPERATING CHARACTERISTICS
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UVLO < VIN < OVLO
NCP361, NCV361
Figure 9. Start Up. Vin=Ch1, Vout=Ch2
Figure 10. FLAG Going Up Delay. Vin=Ch1,
FL:AG=Ch3
Figure 12. Alert Delay. Vout=Ch1, FLAG=Ch3
Figure 11. Output Turn Off time. Vin=Ch1,
Vout=Ch2
Figure 13. Disable Time. EN=Ch4, Vin=Ch1,
Vout=Ch2
Figure 14. Thermal Shutdown. Vin=Ch1,
Vout=Ch2, FLAG=Ch3
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NCP361, NCV361
TYPICAL OPERATING CHARACTERISTICS
450
400
RDS(on) (mW)
350
300
Vin = 3.6 V
250
200
150
Vin = 5 V
100
50
0
−50
0
50
100
150
TEMPERATURE (°C)
Figure 16. Output Short Circuit
900
OVERCURRENT THRESHOLD (mA)
180
160
140
120
100
80
25°C
125°C
60
40
−40°C
20
0
1
3
5
7
9
11
13
15
17
19
880
Vin = 3.25 V
860
Vin = 3.6 V
840
820
Vin = 4.2 V
800
Vin = 5 V
780
760
Vin = 5.25 V
740
720
−50
21
0
Vin, INPUT VOLTAGE (V)
50
Figure 18. Overcurrent Protection Threshold
vs. Temperature
900
25°C
880
860
840
85°C
820
125°C
800
780
760
0°C
−25°C
740
720
−40°C
3
100
TEMPERATURE (°C)
Figure 17. Quiescent Current vs. Input Voltage
OVERCURRENT THRESHOLD (mA)
SUPPLY QUIESCENT CURRENT (mA)
Figure 15. RDS(on) vs. Temperature
(Load = 500 mA)
3.5
4
4.5
5
5.5
INPUT VOLTAGE (V)
Figure 19. Overcurrent Protection Threshold
vs. Input Voltage
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150
NCP361, NCV361
Operation
Vout
NCP361 provides overvoltage protection for positive
voltage, up to 20 V. A PMOS FET protects the systems
(i.e.: VBUS) connected on the Vout pin, against positive
overvoltage. The Output follows the VBUS level until
OVLO threshold is overtaken.
Undervoltage Lockout (UVLO)
Overload
Iload
To ensure proper operation under any conditions, the
device has a built−in undervoltage lock out (UVLO)
circuit. During Vin positive going slope, the output remains
disconnected from input until Vin voltage is above 3.0 V
nominal. The FLAGV output is pulled to low as long as Vin
does not reach UVLO threshold. This circuit has a 70 mV
hysteresis to provide noise immunity to transient condition.
Retrieve
normal
operation
Ilim
ton
Vin (V)
Figure 21. Overcurrent Event Example
20 V
FLAG Output
OVLO
NCP361 provides a FLAG output, which alerts external
systems that a fault has occurred.
This pin is tied to low as soon as: 1.2 V < Vin < UVLO,
Vin > OVLO, Icharge > Ilimit, TJ > 150°C. When NCP361
recovers normal condition, FLAG is held high. The pin is
an open drain output, thus a pull up resistor (typically 1 MW
− Minimum 10 kW) must be provided to VCC. FLAG pin is
an open drain output.
UVLO
0
Vout
OVLO
UVLO
EN Input
0
To enable normal operation, the EN pin shall be forced
to low or connected to ground. A high level on the pin
disconnects OUT pin from IN pin. EN does not overdrive
an OVLO or UVLO fault.
Figure 20. Output Characteristic vs. Vin
Overvoltage Lockout (OVLO)
To protect connected systems on Vout pin from
overvoltage, the device has a built−in overvoltage lock out
(OVLO) circuit. During overvoltage condition (OVLO
exceeds), the output remains disabled and FLAG is tied
low, as long as the input voltage is higher than OVLO −
hysteresis. This circuit has a 100 mV hysteresis to provide
noise immunity to transient conditions.
Internal PMOS FET
The NCP361 includes an internal PMOS FET to protect
the systems, connected on OUT pin, from positive
overvoltage. Regarding electrical characteristics, the
RDS(on), during normal operation, will create low losses on
Vout pin, characterized by Vin versus Vout dropout.
Overcurrent Protection (OCP)
ESD Tests
The NCP361 integrates overcurrent protection to
prevent system/battery overload or defect. The current
limit threshold is internally set at 750 mA. This value can
be changed from 150 mA to 750 mA by a metal tweak,
please contact your ON Semiconductor representative for
availability. During current fault, the internal PMOS FET
is automatically turned off (5 ms) if the charge current
exceeds Ilim. NCP361 goes into turn on and turn off mode
as long as defect is present. The internal ton delay (4 ms
typical) allows limiting thermal dissipation. The Flag pin
goes to low level when an overcurrent fault appears. That
allows the microcontroller to count defect events and turns
off the PMOS with EN pin.
The NCP361 fully supports the IEC61000−4−2, level 4
(Input pin, 1 mF mounted on board). That means, in Air
condition, Vin has a ±15 kV ESD protected input. In
Contact condition, Vin has ±8 kV ESD protected input.
Please refer to Figure 22 to see the IEC61000−4−2
electrostatic discharge waveform.
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8
NCP361, NCV361
from an application standpoint. Of course, in any case, this
pad shall be not connected to any other potential.
By increasing PCB area, the RqJA of the package can be
decreased, allowing higher charge current to fill the battery.
Taking into account that internal bondings (wires
between package and silicon) can handle up to 1 A (higher
than thermal capability), the following calculation shows
two different example of current capability, depending on
PCB area:
• With 305°C/W (without PCB area), allowing DC
current is 500 mA
• With 260°C/W (200 mm2), the charge DC current
allows with a 85°C ambient temperature is:
I = √(TJ-TA)/(RqJA x RDSON)
I = 625 mA
In every case, we recommend to make thermal
measurement on final application board to make sure of the
final Thermal Resistance.
Figure 22.
PCB Recommendations
The NCP361 integrates a 500 mA rated PMOS FET, and
the PCB rules must be respected to properly evacuate the
heat out of the silicon. The UDFN PAD1 must be connected
to ground plane to increase the heat transfer if necessary
380
50%
45%
TSOP−5 1.0 oz
TSOP−5 2.0 oz
DFN 2x2.2 1.0 oz
DFN 2x2.2 2.0 oz
% Delta DFN vs TSOP−5
Theta JA (C/W)
280
230
40%
35%
30%
25%
20%
180
15%
% Delta DFN vs TSOP−5
330
10%
130
5%
80
0
100
200
300
400
500
600
0%
700
Copper heat spreader area (mm^2)
Figure 23. Thermal Resistance of UDFN 2x2 and TSOP Packages as a Function of PCB Area and Thickness
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9
NCP361, NCV361
ORDERING INFORMATION
Marking
Package
Shipping†
NCP361MUTBG
AD
UDFN6
(Pb−Free)
3000 / Tape & Reel
NCP361SNT1G
ACD
TSOP−5
(Pb−Free)
3000 / Tape & Reel
NCV361SNT1G*
VET
TSOP−5
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements
SELECTION GUIDE
The NCP361 can be available in several undervoltage and overvoltage thresholds versions. Part number is designated as follows:
NCP361xxxxxTxG
a b cd
e
Code
Contents
a
Overcurrent Threshold
−: 750 mA
b
Package
MU: UDFN
SN: TSOP−5
c
UVLO Typical Threshold
−: 3.00 V
d
OVLO Typical Threshold
−: 5.675 V
e
Tape & Reel Type
B: = 3000
1: = 3000
NOTE: Additional current limit, UVLO and OVLO can be available.
Please contact your ON Semiconductor representative for
availability.
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10
NCP361, NCV361
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517AB
ISSUE B
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
PIN ONE
REFERENCE
0.10 C
2X
2X
ÍÍÍ
ÍÍÍ
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
E
0.10 C
A3
SOLDERING FOOTPRINT*
0.10 C
A
6X
0.08 C
MILLIMETERS
MIN
MAX
0.45
0.55
0.00
0.05
0.127 REF
0.25
0.35
2.00 BSC
1.50
1.70
2.00 BSC
0.80
1.00
0.65 BSC
0.20
--0.25
0.35
6X
0.47
0.95
6X
A1
C
0.40
1
SEATING
PLANE
D2
6X
e
L
1
4X
1.70
3
E2
2.30
6X
K
6
4
BOTTOM VIEW
6X
b
0.65
PITCH
DIMENSIONS: MILLIMETERS
0.10 C A
0.05 C
B
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCP361, NCV361
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE G
D 5X
NOTE 5
2X
0.10 T
2X
0.20 T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
0.20 C A B
M
5
1
4
2
L
3
B
S
K
DETAIL Z
G
A
J
C
0.05
DIM
A
B
C
D
G
H
J
K
L
M
S
DETAIL Z
SEATING
PLANE
H
T
MILLIMETERS
MIN
MAX
3.00 BSC
1.50 BSC
0.90
1.10
0.25
0.50
0.95 BSC
0.01
0.10
0.10
0.26
0.20
0.60
1.25
1.55
0_
10 _
2.50
3.00
SOLDERING FOOTPRINT*
0.95
0.037
1.9
0.074
2.4
0.094
1.0
0.039
0.7
0.028
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
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Phone: 81−3−5817−1050
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your loca
Sales Representative
NCP361/D