ONSEMI NUS6160MN

NUS6160MN
Low Profile Overvoltage
Protection IC with
Integrated MOSFET
This device represents a new level of safety and integration by
combining an overvoltage protection circuit (OVP) with a dual 20 V
P−channel power MOSFET. The OVP is specifically designed to
protect sensitive electronic circuitry from overvoltage transients and
power supply faults. During such events, the IC quickly disconnects
the input supply from the load, thus protecting it. The integration of
the additional transistor and power MOSFET reduces layout space and
promotes better charging performance.
The IC is optimized for applications that use an external AC−DC
adapter or a car accessory charger to power a portable product or
recharge its internal batteries.
Features
•
•
•
•
•
•
•
•
Overvoltage Turn−Off Time of Less Than 1.5 ms
Undervoltage Lockout Protection; 3.0 V, Nominal
High Accuracy Undervoltage Threshold of 5.0%
−20 V Integrated P−Channel Power MOSFET
Low RDS(on) = 64 mW @ −4.5 V
Compact 3.0 x 4.0 mm QFN Package
Maximum Solder Reflow Temperature @ 260°C
This is a Pb−Free Device
Benefits
•
•
•
•
Provide Battery Protection
Integrated Solution Offers Cost and Space Savings
Integrated Solution Improves System Reliability
Optimized for Commercial PMUs from Top Suppliers
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MARKING
DIAGRAM
1
NUS
6160
ALYWG
G
QFN22
CASE 485AT
NUS6160 = Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Device
Package
Shipping†
NUS6160MNTWG
QFN22
(Pb−Free)
3000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Applications
• Portable Computers and PDAs
• Cell Phones and Handheld Products
• Digital Cameras
© Semiconductor Components Industries, LLC, 2008
December, 2008 − Rev. 0
Publication Order Number:
NUS6160MN/D
En
GND
In
N/C
N/C
NUS6160MN
18
22
Out
17
1
N/C
N/C
N/C
N/C
Gate1
Flag
Drain1
Gate2
Drain2
6
12
11
Drain2
Source1
Drain1
Source2
7
N/C
Drain2
Drain1
FETREG
Drain2
FETSW
Drain1
Drain1
(Top View)
Figure 1. Pinout
Vbat
15
1
8
FLAG
3
FETSW
20
Wall Adaptor
IN
4, 5, 6, 7
OUT
10
GND
EN
NUS6160
14
FETREG
18
19
9, 11, 13
Battery
Figure 2. Typical Charging Solution
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2
ChargeSW
ChargeREG
NUS6160MN
MAXIMUM RATINGS (TJ = 25°C, unless otherwise stated)
Rating
VIN to Ground
OUT, EN, FLAG Pins Voltage to Ground
Symbol
Min
Max
Unit
VIN
VOUT, VEN, VFLAG
−0.3
21
V
−0.3
7.0
V
Maximum Current from VIN to VOUT (PMOS)
Imax
600
mA
Drain−to−Source Voltage
VDSS
−20
V
Gate−to−Source Voltage
VGS
8.0
V
ID
−2.0
A
Continuous Drain Current, Steady State
Pulsed Drain Current, tp = 10 ms
−8.0
IDM
−4.0
A
Source Current
IS
−1.1
A
Operating Ambient Temperature
TA
−40
85
°C
TSTG
−55
150
°C
150
°C
Storage Temperature
Operating Junction Temperature
TJ
Thermal Resistance (Note 1)
1 in2 (645 mm2) (All devices fully enhanced)
OVP FET
FETSW
FETREG
1 in2 (645 mm2) (OVP and FETSW fully enhanced, 1 V drop across FETREG)
OVP FET
FETSW
FETREG
0.25 in2 (161 mm2) (All devices fully enhanced)
OVP FET
FETSW
FETREG
0.25 in2 (161 mm2) (OVP and FETSW fully enhanced, 1 V drop across FETREG)
OVP FET
FETSW
FETREG
qJA
°C/W
68
42
46
43
39
80
79
53
56
53
49
92
ESD Performance (Human Body Model) Pins 1, 15, 18, 19, 20
−
2.5
kV
Lead Temperature for Soldering Purposes (1/8” from case for 10 s)
TL
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 1 oz. copper, double sided board. Thermal impedance requires total for DT calculations. See example in thermal description.
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3
NUS6160MN
PIN DESCRIPTION
Pin
Name
1
Out
Description
3
Gate FETSW
This pin is the gate of the upper FET which is normally used for a switch in series with the battery.
It is controlled by the PMU.
4, 5, 6, 7
Drain FETSW
These pins are the drain of the upper FET. For the lowest on resistance connect all pins together.
This set of pins must be connected to the source of the lower (regulator) FET, Pin 10.
8
Source FETSW
This pin is the source of the upper FET and must be connected to the output pin of the internal
OVP chip (Pin 1).
9, 11, 13
Drain FETREG
These pins are the drain of the lower FET which is normally used for the regulation function. It
connects to the positive terminal of the battery.
10
Source FETREG
12
N/C
14
Gate FETREG
15
FLAG
2, 16, 17,
21, 22
N/C
These pins are connected to the ground of the analog chip. This is a medium impedance
connection and should not be used for the ground signal. These pins should either be left floating
or connected to ground, but not any other potential. If these pins are connected to ground, the
ground pin (19) must still be used.
18
EN
The ENABLE pin must be held low for normal operation. When this pin is tied high the unit will be
shut down. The state of the enable pin has no impact on the FAULT pin.
19
Gnd
This is the ground reference pin for the internal OVP chip.
20
In
This pin is the output of the internal OVP chip. It must be connected to the source of the upper
FET (Pin 8).
This pin is the source of the lower FET and must be connected to the drain pins of the upper FET.
This pin has no internal connections and is isolated from all internal circuitry within the chip.
This pin is the gate of the lower FET which is normally used for the regulation function in series
with the battery. It is controlled by the PMU.
The fault flag is an open drain output and therefore requires a pullup resistor. The FLAG pin will be
driven low when the input voltage exceeds the OVLO trip level.
This pin is the input to the internal OVP chip and connects to the wall, or car adaptor.
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4
NUS6160MN
OVP ELECTRICAL CHARACTERISTICS
(Min/Max limits values (−40°C < TA < +85°C) and Vin = +5.0 V. Typical values are TA = +25°C, unless otherwise noted.)
Characteristic
Input Voltage Range
Symbol
Vin
Undervoltage Lockout
Threshold
UVLO
Undervoltage Lockout
Hysteresis
UVLOhyst
Overvoltage Lockout Threshold
OVLO
Overvoltage Lockout Hysteresis
OVLOhyst
Vin versus Vout Dropout
Supply Quiescent Current
OVLO Supply Current
Output Off State Current
FLAG Output Low Voltage
FLAG Leakage Current
Conditions
Vdrop
Idd
Iddovlo
Istd
Volflag
FLAGleak
Vin falls down UVLO threshold
Max
Unit
20
V
2.85
3.0
3.15
V
30
50
70
mV
6.9
7.07
7.4
V
50
100
125
mV
Vin = 5 V, I charge = 500 mA
105
200
mV
No Load, Vin = 5.25 V
24
35
mA
Vin = 8 V
50
85
mA
Vin = 5.25 V, EN = 1.2 V
26
37
mA
400
mV
Vin rises up OVLO threshold
Vin > OVLO, Sink 1 mA on FLAG pin
FLAG level = 5 V
Vih
Vin from 3.3 V to 5.25 V
EN Voltage Low
Vol
Vin from 3.3 V to 5.25 V
ENleak
Typ
1.2
EN Voltage High
EN Leakage Current
Min
5.0
nA
1.2
V
0.4
V
EN = 5.5 V or GND
170
nA
From Vin > UVLO to Vout = 0.8xVin, See Fig 3 & 9
4.0
From Vin > UVLO to FLAG = 1.2 V, See Fig 3 &
10
3.0
toff
From Vin > OVLO to Vout ≤ 0.3 V, See Fig 4 & 11
Vin increasing from normal operation to >OVLO at
1V/ms. No output capacitor.
0.8
1.5
ms
Alert Delay
tstop
From Vin > OVLO to FLAG ≤ 0.4 V, See Fig 4 &
12
Vin increasing from normal operation to >OVLO at
1V/ms
1.0
2.0
ms
Disable Time
tdis
From EN 0.4 to 1.2V to Vout ≤ 0.3V, See Fig 5 &
13
Vin = 4.75 V. No output capacitor.
2.0
ms
Tsd
150
°C
Tsdhyst
30
°C
TIMINGS
Start Up Delay
FLAG going up Delay
Output Turn Off Time
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
NOTE:
ton
tstart
Thermal Shutdown parameter has been fully characterized and guaranteed by design.
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5
15
ms
ms
NUS6160MN
MOSFET ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted, all parameters apply to both FETSW and
FETREG)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(Br)DSS
VGS = 0 V, ID = −250 mA
−20
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(Br)DSS/TJ
Characteristic
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
−15
VGS = 0 V
VDS = −16 V
mV/°C
TJ = 25°C
−1.0
TJ = 85°C
−5.0
IGSS
VDS = 0 V, VGS = "8.0 V
VGS(TH)
VGS = VDS, ID = −250 mA
mA
"100
nA
−1.5
V
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage
Gate Threshold Temperature Coefficient
VGS(TH)/TJ
Drain−to−Source On Resistance
RDS(ON)
Forward Transconductance
gFS
−0.45
2.7
mV/°C
VGS = −4.5 V, ID = −1.0 A
64
80
mW
VGS = −4.5 V, ID = −0.6 A
62
80
VDS = −10 V, ID = −2.9 A
7.0
S
750
pF
CHARGES, CAPACITANCES, AND GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Total Gate Charge
VGS = 0 V, f = 1.0 MHz,
VDS = −16 V
45
QG(TOT)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
100
7.6
VGS = −4.5 V, VDS = −16 V,
ID = −2.6 A
8.6
nC
1.3
2.6
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
ns
5.5
tr
VGS = −4.5 V, VDD = −16 V,
ID = −2.6 A, RG = 2.0 W
td(OFF)
tf
12
32
23
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
VGS = 0 V, IS = −1.1 A
−0.8
20
VGS = 0 V, dIS/dt = 100 A/ms,
IS = 1.0 A
QRR
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6
V
ns
15
5
0.01
2. Pulse test: pulse width ≤ 300 ms, duty cycle ≤ 2%
3. Switching characteristics are independent of operating junction temperatures
−1.2
mC
NUS6160MN
<OVLO
UVLO
Vin
Vin
ton
0.8 Vin
Vout
Vin − (RDS(on)
Figure 3. Start Up Sequence
EN
tdis
Vin − RDS(on) x I
0.3
V
tstop
0.4
V
Figure 4. Shutdown on Over Voltage
Detection
1.2 V
Vout
I)
FLA
G
1.2 V
EN
toff
Vout
Vin − RDS(on) x I
tstart
FLAG
OVLO
1.2 V
OVLO
Vin
0.3 V
UVLO
3 ms
FLAG
FLAG
Figure 5. Disable on EN = 1
Figure 6. FLAG Response with EN = 1
CONDITIONS
IN
OUT
VIN > OVLO or VIN < UVLO
Voltage Detection
Figure 7.
CONDITIONS
IN
OUT
Voltage Detection
Figure 8.
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7
UVLO < VIN < OVLO
NUS6160MN
TYPICAL OPERATING CHARACTERISTICS
Figure 9. Startup
Vin = Ch1, Vout = Ch3
Figure 10. FLAG Going Up Delay
Vout = Ch3, FLAG = Ch2
Figure 11. Output Turn Off Time
Vin = Ch1, Vout = Ch2
Figure 12. Alert Delay
Vout = Ch1, FLAG = Ch3
Figure 13. Disable Time
EN = Ch1, Vout = Ch2, FLAG = Ch3
Figure 14. Thermal Shutdown
Vin = Ch1, Vout = Ch2, FLAG = Ch3
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8
NUS6160MN
TYPICAL OPERATING CHARACTERISTICS
450
400
Vin = 3.6 V
RDS(on) (mW)
350
300
250
Vin = 5 V
200
150
100
50
0
−50
0
50
100
TEMPERATURE (°C)
IQ, SUPPLY QUIESCENT CURRENT (mA)
Figure 15. Direct Output Short Circuit
Figure 16. RDS(on) vs. Temperature
(Load = 500 mA)
180
160
140
120
100
80
125°C
25°C
60
40
−40°C
20
0
1
3
5
7
9
11
13
15
17
19
Vin, INPUT VOLTAGE (V)
Figure 17. Supply Quiescent Current vs. Vin
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9
21
150
NUS6160MN
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
8
−2.4 V
7
6
5
4
3
2
−1.8 V
1
−1.6 V
−1.4 V
0
1
0
2
3
5
4
6
7
7
6
5
4
3
125°C
2
25°C
1
TJ = −55°C
0
8
0
1
1.5
2
3
3.5
0.5
2.5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 18. On−Region Characteristics
Figure 19. Transfer Characteristics
4
1.5
0.2
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
0.18
0.16
VGS = −2.5 V
0.14
0.12
0.1
VGS = −4.5 V
0.08
0.06
0.04
0.02
0
8
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
2
VGS = −4.5 V
1.3
1.1
0.9
0.7
0.5
−50
6
3
4
5
−ID, DRAIN CURRENT (AMPS)
−25
0
25
VGS = 0 V
1000
TJ = 125°C
TJ = 100°C
100
10
1
TJ = 25°C
2
3
75
100
125
Figure 21. On−Resistance Variation with
Temperature
10000
0.1
50
TJ, JUNCTION TEMPERATURE (°C)
Figure 20. On−Resistance vs. Drain Current
and Gate Voltage
−IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
9
TJ = 25°C
VGS = −10 V to −2.8 V
9
−ID, DRAIN CURRENT (AMPS)
−ID, DRAIN CURRENT (AMPS)
10
4
5
6
7
8
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 22. Drain−to−Source Leakage Current
vs. Voltage
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10
150
NUS6160MN
TJ = 25°C
C, CAPACITANCE (pF)
900
800
700
Ciss
600
500
400
300
200
100
0
Coss
Crss
0
2
−VGS −VDS
4
6
8
12
10
14
16
18
20
5
QT
4
3
1
0
ID = −2.7 A
TJ = 25°C
8
Figure 24. Gate−to−Source and
Drain−to−Source Voltage vs. Total Gate Charge
−IS, SOURCE CURRENT (AMPS)
100
td(off)
tf
tr
td(on)
1
10
4
2
1
0
0.4
100
VGS = 0 V
TJ = 25°C
3
0.5
0.6
0.7
Figure 25. Resistive Switching Time Variation
vs. Gate Resistance
10
10 ms
1
100 ms
1 ms
10 ms
0.01
0.1
0.9
1.0
1.1
1.2
Figure 26. Diode Forward Voltage vs. Current
100
0.1
0.8
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
RG, GATE RESISTANCE (OHMS)
−I D, DRAIN CURRENT (AMPS)
t, TIME (ns)
7
4
2
3
5
6
Qg, TOTAL GATE CHARGE (nC)
5
VDD = −10 V
ID = −1.0 A
VGS = −4.5 V
1
1
0
Figure 23. Capacitance Variation
10
Q2
Q1
2
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
VGS = −8 V
SINGLE PULSE
TC = 25°C
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
dc
10
1
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 27. Maximum Rated Forward Biased
Safe Operating Area
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11
100
NUS6160MN
Operational Description
in the event of an overvoltage condition to protect the output
from a positive overvoltage condition. The low Rds(on),
during normal operation will minimize the voltage drop
across the device. (See Figure 16).
The NUS6160 provides overvoltage protection for
positive voltages up to 20 V. A P−Channel FET protects the
load connected on the Vout pin, against positive overvoltage
conditions. The Output follows the VBUS level until OVLO
threshold is reached.
ESD Tests
The NUS6160 meets the requirements of
the
IEC61000*4*2, level 4 (Input pin, 1 mF mounted on
board). For the air discharge condition, Vin is protected up
to $15 kV. In the contact condition, Vin is protected up to
±8 kV ESD. Please refer to Figure 29 to see the IEC
61000−4−2 electrostatic discharge waveform.
Undervoltage Lockout (UVLO)
To ensure proper operation under all conditions, the
device has a built−in undervoltage lock out (UVLO) circuit.
As the input ramps from 0 V, the output remains
disconnected from input until the Vin voltage is above 3.2 V
nominal. The FLAG output is pulled to low as long as Vin
does not reach the UVLO threshold. This circuit
incorporates hysteresis on the UVLO pin to provide noise
immunity to transient condition.
Figure 29. IEC 61000−4−2 Curve
Thermal Impedance
Figure 28. Output Characteristic vs. Vin
Due to cross heating of the three dice in the package, the
equivalent thetas are given for this device rather than the
individual thetas. To calculate the junction temperatures of
a single die, the total power must be used. For example,
given the following parameters, the die temperatures will be
as shown:
Idc = 500 mA
RDS(on) OVP = 305 mW
RDS(on) FETsw = 72 mW
FETreg has a 1.0 V Drop
Board copper area = 161 mm2
Calculate the individual power dissipations:
POVP = (0.50 A)2 x .305 W = 0.076 W
PSW = (0.50 A)2 x .072 W = 0.018 W
PREG = 0.50 A x 1.0 V = 0.50 W
PTOT = 0.076 + 0.018 + 0.50 = 0.594 W
From the Maximum ratings table for thetas, 161 mm2 and
1 V drop across FETREG:
OVP FET
53°C/W
FETSW
49°C/W
FETREG
92°C/W
The die temperature rises above ambient are:
TOVP = 53°C/W x 0.594 W = 32°C
TSW = 49°C/W x 0.594 W = 29°C
TREG = 92°C/W x 0.594 W = 55°C
Overvoltage Lockout (OVLO)
To protect connected systems on Vout Pin from
overvoltage, the device has a built−in overvoltage lock out
(OVLO) circuit. During an overvoltage condition, the
output remains disabled until the input voltage is reduced to
below the OVLO hysteresis level. The FLAG output is tied
to low until Vin is higher than OVLO. This circuit
incorporates hysteresis on the OVLO pin to provide noise
immunity from transient conditions.
FLAG Output
The NUS6160 provides a FLAG output, which alerts
external systems that a fault has occurred. This pin goes low
as soon as the OVLO threshold is exceeded. When Vin level
recovers to its normal range the FLAG is set high.
The FLAG Pin is an open drain output, thus a pullup
resistor (typically 1 MW − Minimum 10 kW) must be
provided to Vbattery.
EN Input
To enable normal operation, the EN pin shall be forced
low or connected to ground. A high level on the pin
disconnects the OUT Pin from IN Pin. EN does not override
an OVLO or UVLO fault.
Internal PMOS FET
The NUS6160 includes an internal PMOS FET which
connects the input to the output pin. This FET is turned off
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12
NUS6160MN
PACKAGE DIMENSIONS
QFN22, 3x4, 0.5P
CASE 485AT−01
ISSUE B
D
PIN 1
REFERENCE
ÈÈÈ
ÈÈÈ
ÈÈÈ
ÈÈÈ
L
L
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PADS AS WELL AS THE TERMINALS.
L1
DETAIL A
OPTIONAL
CONSTRUCTIONS
ÉÉ
ÉÉ
E
EXPOSED Cu
2X
0.15 C
MOLD CMPD
2X
ÉÉÉ
ÉÉÉ
ÇÇÇ
A3
A1
DETAIL B
0.15 C
OPTIONAL
CONSTRUCTIONS
TOP VIEW
DETAIL B
0.10 C
A
25X
0.08 C
NOTE 4
A3
SIDE VIEW
C
A1
SEATING
PLANE
SOLDERING FOOTPRINT*
G1
D3
22X
D4
7
DETAIL A
MILLIMETERS
DIM MIN
NOM MAX
A
0.80
0.90
1.00
A1
0.00 0.025
0.05
A3
0.20 REF
b
0.20
0.25
0.30
D
3.00 BSC
D2
1.45
1.50
1.55
D3
0.52
0.57
0.62
D4
1.02
1.07
1.12
E
4.00 BSC
E2
1.05
1.10
1.15
E3
1.30
1.35
1.40
E4
1.40
1.45
1.50
e
0.50 BSC
K
0.25
−−−
−−−
L
0.30 0.325
0.35
L1
−−−
−−−
0.15
G
1.35
1.40
1.50
G1
0.95
1.05
1.15
G2 0.855 0.885 0.915
3.30
1.55
L
0.50
PITCH
0.925
PACKAGE
OUTLINE
12
G
G
E3
E2
1
E4
22X
b
1
K
1.21
1.47
1.47 1.58
4.30
0.10 C A B
0.05 C
16X
1.47
NOTE 3
18
e
G2
D2
22X
0.39
0.52
BOTTOM VIEW
22X
0.30
1.14
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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