ISL9008A ® Data Sheet March 11, 2008 FN6300.4 Low Noise LDO with Low IQ, High PSRR Features ISL9008A is a high performance single low noise, high PSRR LDO that delivers a continuous 150mA of load current. It has a low standby current and is stable with 1μF of MLCC output capacitance with an ESR of up to 200mΩ. • High performance LDO with 150mA continuous output The ISL9008A has a high PSRR of 65dB and output noise less than 45μVRMS. When coupled with a no load quiescent current of 46μA (typical), and 0.5μA shutdown current, the ISL9008A is an ideal choice for portable wireless equipment. The ISL9008A comes in several fixed voltage options with ±1.8% output voltage accuracy over-temperature, line and load. Other output voltage options may be available upon request. ISL9008A (5 LD SC-70) TOP VIEW 1 GND 2 EN 3 • Excellent load regulation: <0.1% voltage change across full range of load current • High PSRR: 65dB @ 1kHz • Wide input voltage capability: 2.3V to 6.5V • Very low quiescent current: 46µA • Low dropout voltage: typically 200mV @ 150mA • Low output noise: typically 45µVRMS @ 100µA (1.5V) • Stable with 1µF to 4.7µF ceramic capacitors • Shutdown pin turns off LDO with 1µA (max) standby current Pinouts VIN • Excellent transient response to large current steps • Soft-start limits input current surge during enable • Current limit and overheat protection VO 5 • ±1.8% accuracy over all operating conditions • 5 Ld SC-70 package or 6 Ld µTDFN package NC 4 • -40°C to +85°C operating temperature range • Pb-free (RoHS compliant) Applications ISL9008A (6 LD 1.6x1.6 µTDFN) TOP VIEW VO 1 6 VIN GND 2 5 NC NC 3 4 EN 1 • PDAs, cell phones and smart phones • Portable instruments, MP3 players • Handheld devices including medical handhelds CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2006, 2007, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL9008A Ordering Information PART NUMBER (Note 4) PART MARKING VO VOLTAGE (V) (Note 1) TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL9008AIENZ-T (Note 2) CBV 3.3 -40 to +85 5 Ld SC-70 P5.049 ISL9008AIEMZ-T (Note 2) CBT 3.0 -40 to +85 5 Ld SC-70 P5.049 ISL9008AIEKZ-T (Note 2) CBS 2.85 -40 to +85 5 Ld SC-70 P5.049 ISL9008AIEJZ-T (Note 2) CBR 2.8 -40 to +85 5 Ld SC-70 P5.049 ISL9008AIEHZ-T (Note 2) CBP 2.75 -40 to +85 5 Ld SC-70 P5.049 ISL9008AIEFZ-T (Note 2) CBN 2.5 -40 to +85 5 Ld SC-70 P5.049 ISL9008AIETZ-T (Note 2) CDW 1.9 -40 to +85 5 Ld SC-70 P5.049 ISL9008AIECZ-T (Note 2) CBM 1.8 -40 to +85 5 Ld SC-70 P5.049 ISL9008AIEBZ-T (Note 2) CBL 1.5 -40 to +85 5 Ld SC-70 P5.049 ISL9008AIRUBZ-T (Note 3) P 1.5 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9008AIRUCZ-T (Note 3) Q 1.8 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9008AIRUFZ-T (Note 3) R 2.5 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9008AIRUHZ-T (Note 3) S 2.75 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9008AIRUJZ-T (Note 3) T 2.8 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9008AIRUKZ-T (Note 3) V 2.85 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9008AIRUMZ-T (Note 3) W 3.0 -40 to +85 6 Ld µTDFN L6.1.6x1.6A ISL9008AIRUNZ-T (Note 3) Y 3.3 -40 to +85 6 Ld µTDFN L6.1.6x1.6A NOTES: 1. For other output voltages, contact Intersil Marketing. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. Please refer to TB347 for details on reel specifications. 2 FN6300.4 March 11, 2008 ISL9008A Absolute Maximum Ratings Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V VO Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN+0.3V) Thermal Resistance Recommended Operating Conditions Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 to 6.5V θJA (°C/W) 5 Ld SC-70 Package (Note 5) . . . . . . . . . . . . . . . . . 231 6 Ld µTDFN Package (Note 6) . . . . . . . . . . . . . . . . 125 Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. Electrical Specifications PARAMETER Unless otherwise noted, all parameters are established over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF. SYMBOL TEST CONDITIONS MIN (Note 9) TYP MAX (Note 9) UNITS 6.5 V DC CHARACTERISTICS Supply Voltage Ground Current IDD Shutdown Current IDDS UVLO Threshold VUV+ VUV- Regulation Voltage Accuracy Maximum Output Current IMAX Thermal Shutdown Temperature Quiescent condition: IO = 0µA 46 66 µA 0.5 1.2 µA 1.9 2.1 2.3 V 1.6 1.8 2.0 V Initial accuracy at VIN = VO + 0.5V, IO = 10mA, TJ = +25°C -0.7 +0.7 % VIN = VO + 0.5V to 6.5V, IO = 10μA to150mA, TJ = +25°C -0.8 +0.8 % VIN = VO + 0.5V to 6.5V, IO = 10μA to 150mA, TJ = -40°C to +125°C -1.8 +1.8 % Continuous 150 175 mA 265 355 mA VDO1 IO = 150mA; VO < 2.5V 300 500 mV VDO2 IO = 150mA; 2.5V ≤ VO ≤ 2.8V 250 400 mV VDO3 IO = 150mA; 2.8V < VO 200 325 mV Internal Current Limit Drop-out Voltage (Note 8) 2.3 VIN ILIM TSD+ 140 °C TSD- 110 °C @ 1kHz 65 dB @ 10kHz 45 dB @ 100kHz 35 dB BW = 10Hz to 100kHz, IO = 100µA 45 µVRMS BW = 10Hz to 100kHz, IO = 10mA 65 µVRMS AC CHARACTERISTICS IO = 10mA, VIN = 2.8V(min), VO = 1.8V Ripple Rejection (Note 7) VO = 1.5V, TA = +25°C Output Noise Voltage (Note 7) DEVICE START-UP CHARACTERISTICS Device Enable Time tEN Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO(nom) 250 500 µs LDO Soft-start Ramp Rate tSSR Slope of linear portion of LDO output voltage ramp during start-up 30 60 µs/V 3 FN6300.4 March 11, 2008 ISL9008A Electrical Specifications Unless otherwise noted, all parameters are established over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF. (Continued) PARAMETER SYMBOL MIN (Note 9) TEST CONDITIONS TYP MAX (Note 9) UNITS EN PIN CHARACTERISTICS Input Low Voltage VIL -0.3 0.4 V Input High Voltage VIH 1.4 VIN + 0.3 V 0.1 μA Input Leakage Current IIL, IIH Pin Capacitance CPIN Informative 5 pF NOTES: 7. Limits established by characterization and are not production tested. 8. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V. 9. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. Typical Performance Curves 0.8 0.2 OUTPUT VOLTAGE CHANGE (%) 0.6 OUTPUT VOLTAGE, VO (%) VO = 3.3V +25°C VO = 3.3V ILOAD = 0mA 0.4 +25°C 0.2 0.0 -0.2 +85°C -0.4 -0.6 0.1 IO = 0mA 0.0 -0.1 IO = 75mA IO = 150mA -0.2 -0.3 -40°C -0.8 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2 -0.4 3.3 6.6 3.8 1.0 5.3 5.8 6.3 0.10 VIN = 3.8V VO = 3.3V 0.8 0.6 VIN = 3.8V VO = 3.3V 0.08 0.06 0.4 OUTPUT VOLTAGE (%) OUTPUT VOLTAGE CHANGE (%) 4.8 FIGURE 2. OUTPUT VOLTAGE CHANGE (%) vs INPUT VOLTAGE (3.3V OUTPUT) FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) -40°C 0.2 0.0 -0.2 -0.4 +25°C +85°C 0.04 0.00 IO = 150mA -0.04 -0.8 -0.08 25 50 75 100 125 150 LOAD CURRENT - IO (mA) FIGURE 3. OUTPUT VOLTAGE vs LOAD CURRENT 4 175 IO = 75mA -0.02 -0.06 0 IO = 0mA 0.02 -0.6 -1.0 4.3 INPUT VOLTAGE (V) INPUT VOLTAGE (V) -0.10 -40 -25 0 25 TEMPERATURE (°C) 55 85 FIGURE 4. OUTPUT VOLTAGE vs TEMPERATURE FN6300.4 March 11, 2008 ISL9008A Typical Performance Curves (Continued) 3.4 2.9 3.3 2.8 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE, VO (V) 3.2 VO = 3.3V +25°C 3.1 3.0 IO = 0mA 2.9 IO = 75mA 2.8 IO = 150mA 2.7 2.6 2.5 2.7 IO = 0mA 2.6 IO = 75mA IO = 150mA 2.5 2.4 VO = 2.8V +25°C 2.4 2.3 2.6 3.1 3.6 4.1 4.6 5.1 5.6 6.1 2.3 2.5 6.6 3.0 3.5 4.0 INPUT VOLTAGE (V) 4.5 5.0 5.5 6.0 6.5 INPUT VOLTAGE (V) FIGURE 5. DROPOUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) FIGURE 6. DROPOUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT) 250 225 VO = 3.3V DROP OUT VOLTAGE, VDO (mV) DROP OUT VOLTAGE, VDO (mV) 200 200 150 VO = 2.8V VO = 3.3V 100 50 175 +85°C 150 125 100 -40°C 75 +25°C 50 25 0 0 25 50 75 100 125 150 0 175 0 25 50 FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT 125 150 175 140 120 GROUND CURRENT (µA) 75 GROUND CURRENT (µA) 100 FIGURE 8. DROPOUT VOLTAGE vs LOAD CURRENT 90 +85°C 60 45 +25°C -40°C 30 15 100 -40°C +25°C 80 +85°C 60 40 20 VO = 3.3V IO = 0µA 0 1.5 75 OUTPUT LOAD (mA) OUTPUT LOAD (mA) VIN = 3.8V VO = 3.3V 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 INPUT VOLTAGE (V) FIGURE 9. GROUND CURRENT vs INPUT VOLTAGE 5 6.5 0 25 50 75 100 125 150 175 LOAD CURRENT (mA) FIGURE 10. GROUND CURRENT vs LOAD FN6300.4 March 11, 2008 ISL9008A Typical Performance Curves (Continued) 115 3 85 2 VO(V) 95 75 VIN = 5.0V VO = 3.3V IL = 150mA CL = 1µF IL = 150mA IL = 75mA VIN = 3.8V VO = 3.3V 65 55 45 IL = 0mA 35 -40 -30 -20 -10 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 80 1 0 VEN (V) GROUND CURRENT (µA) 105 5 0 0 90 100 200 300 400 500 600 700 800 900 1000 TIME (µs) FIGURE 11. GROUND CURRENT vs TEMPERATURE FIGURE 12. TURN ON/TURN OFF RESPONSE VO = 3.3V ILOAD = 150mA VO = 2.8V ILOAD = 150mA CLOAD = 1μF CBYP = 0.01μF CLOAD = 1μF CBYP = 0.01μF 4.3V 4.2V 3.6V 3.5V 10mV/DIV 10mV/DIV 400µs/DIV 400µs/DIV FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT 80 10mA VO = 3.3V 70 VIN = 3.8V 100mA 100μA PSRR (dB) 60 ILOAD 50mA 50 40 30 VO (10mV/DIV) 1.0 ms/DIV 20 VIN = 3.9V VO = 1.8V CLOAD = 1μF 10 0.1k 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 15. LOAD TRANSIENT RESPONSE 6 FIGURE 16. PSRR vs FREQUENCY FN6300.4 March 11, 2008 ISL9008A Typical Performance Curves (Continued) SPECTRAL NOISE DENSITY (μV/√Hz) 2.000 1.000 10mA 0.100 0.010 100µA VIN = 3.9V VO = 1.8V CIN = 1µF CLOAD = 1µF 0.001 10 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY Pin Description 5 LD SC-70 PIN NUMBER 6 LD µTDFN PIN NUMBER PIN NAME 5 1 VO 2 2 GND 4 3 and 5 NC No connect. 3 4 EN Output Enable. When this signal goes high, the LDO is turned on. 1 6 VIN Supply Voltage/LDO Input. Connect a 1µF capacitor to GND. DESCRIPTION LDO Output. Connect a 1µF capacitor of value to GND GND is the connection to system ground. Connect to PCB Ground plane. Typical Application ISL9008A 1 VIN (2.3 TO 5V) 2 ON 3 ENABLE OFF VIN VO 5 VOUT GND EN NC 4 C1 C2 C1, C2: 1µF X5R CERAMIC CAPACITOR VOUT 1 2 3 C2 ISL9008A (µTDFN) 6 VO VIN GND NC NC EN VIN (2.3 TO 5V) 5 ON ENABLE 4 OFF C1 C1, C2: 1µF X5R CERAMIC CAPACITOR 7 FN6300.4 March 11, 2008 ISL9008A Block Diagram VIN VO UVLO CONTROL LOGIC SHORT CIRCUIT, THERMAL PROTECTION, SOFT-START GND + - SD BANDGAP AND TEMPERATURE SENSOR VOLTAGE AND REFERENCE GENERATOR 1.0V 0.94V 0.9V GND Functional Description Reference Generation The ISL9008A contains all circuitry required to implement a high performance LDO. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9008A adjusts its biasing to achieve the lowest standby current consumption. The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The device also integrates current limit protection, smart thermal shutdown protection, and soft-start. Smart Thermal shutdown protects the device against overheating. Soft-start minimizes start-up input current surges without causing excessive device turn-on time. A current generator provides references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination. Power Control The ISL9008A has an enable pin, EN, to control power to the LDO output. When EN is low, the device is in shutdown mode. In this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.3μA. When the EN pin goes high, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least 2.1V (typical). Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry turn on. Once the references are stable, the LDO powers up. During operation, whenever the VIN voltage drops below about 1.84V, the ISL9008A immediately disables the LDO output. When VIN rises back above 2.1V (assuming the EN pin is high), the device re-initiates its start-up sequence and LDO operation resumes automatically. 8 The bandgap generates a zero temperature coefficient (TC) voltage for the regulator reference and other voltage references required for current generation and over-temperature detection. LDO Regulation and Programmable Output Divider The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9008A provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1µF to 4.7µF output capacitor that has a tolerance better than 20% and ESR less than 200mΩ. The design is performance-optimized for a 1µF capacitor. Unless limited by the application, use of an output capacitor value above 4.7µF is not recommended as LDO performance improvement is minimal. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30µs/V to minimize current surge. The ISL9008A provides short-circuit protection by limiting the output current to about 265mA (typ). The LDO uses an independently trimmed 1V reference as its input. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory. FN6300.4 March 11, 2008 ISL9008A Overheat Detection The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about +140°C, the LDO momentarily shuts down until the die cools sufficiently. In the overheat condition, if the LDO sources more than 50mA it will be shut off. Once the die temperature falls back below about +110°C, the disabled LDO is re-enabled and soft-start automatically takes place. 9 FN6300.4 March 11, 2008 ISL9008A Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN) A A E 6 B 6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE 4 MILLIMETERS D PIN 1 REFERENCE 2X 0.15 C 1 2X L6.1.6x1.6A 3 MIN NOMINAL MAX NOTES A 0.45 0.50 0.55 - A1 - - 0.05 - A1 TOP VIEW e 1.00 REF 4 6 L CO.2 0.15 0.20 0.25 - D 1.55 1.60 1.65 4 D2 0.40 0.45 0.50 - E 1.55 1.60 1.65 4 E2 0.95 1.00 1.05 - 0.50 BSC e L 3 1 b 6X 0.10 M C A B E2 - b DAP SIZE 1.30 x 0.76 0.25 0.30 0.35 Rev. 1 6/06 NOTES: 1. Dimensions are in mm. Angles in degrees. BOTTOM VIEW DETAIL A 6X 0.127 REF A3 0.15 C D2 SYMBOL 2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall not exceed 0.08mm. 0.10 C 3. Warpage shall not exceed 0.10mm. 0.08 C 4. Package length/package width are considered as special characteristics. 5. JEDEC Reference MO-229. A3 SIDE VIEW C SEATING PLANE 6. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389. 0.127±0.008 0.127 +0.058 -0.008 TERMINAL THICKNESS A1 DETAIL A 0.25 0.50 1.00 0.45 1.00 2.00 0.30 1.25 LAND PATTERN 6 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN6300.4 March 11, 2008 ISL9008A Small Outline Transistor Plastic Packages (SC70-5) P5.049 D VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES 5 SYMBOL 4 E CL 1 2 CL 3 e E1 b CL 0.20 (0.008) M C C CL A A2 SEATING PLANE A1 -C- PLATING b1 0.043 0.80 1.10 - 0.004 0.00 0.10 - A2 0.031 0.039 0.80 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L2 c1 NOTES 0.031 0.010 0.018 0.017 Ref. 0.26 0.46 4 0.420 Ref. 0.006 BSC 0o N c MAX 0.000 α WITH MIN A L b MILLIMETERS MAX A1 L1 0.10 (0.004) C MIN - 0.15 BSC 8o 0o 5 8o - 5 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 Rev. 3 7/07 NOTES: BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 4X θ1 VIEW C 0.4mm 0.75mm 2.1mm 0.65mm TYPICAL RECOMMENDED LAND PATTERN 11 FN6300.4 March 11, 2008