ISL9014A ® Data Sheet March 11, 2008 Dual LDO with Low Noise, Low IQ, and High PSRR ISL9014A is a high performance dual LDO capable of sourcing 300mA current from both outputs. The device has a low standby current and high-PSRR and is stable with output capacitance of 1µF to 10µF with ESR of up to 200mΩ. A reference bypass pin allows an external capacitor for adjusting a noise filter for low noise and high PSRR applications. The quiescent current is typically only 45µA with both LDOs enabled and active. Separate enable pins control each individual LDO output. When both enable pins are low, the device is in shutdown, typically drawing less than 0.1µA. Several combinations of voltage outputs are standard. Output voltage options for each LDO range from 1.5V to 3.3V. Other output voltage options are available on request. FN6438.1 Features • Integrates two high performance LDOs - VO1 - 300mA output - VO2 - 300mA output • Excellent transient response to large current steps • Excellent load regulation: <1% voltage change across full range of load current • High PSRR: 70dB @ 1kHz • Wide input voltage capability: 2.3V to 6.5V • Extremely low quiescent current: 45µA (both LDOs active) • Low dropout voltage: typically 200mV @ 300mA • Low output noise: typically 30µVRMS @ 100µA (1.5V) • Stable with 1µF to 10µF ceramic capacitors • Separate enable pins for each LDO • Soft-start to limit input current surge during enable Pinout • Current limit and overheat protection ISL9014A (10 LD 3x3 DFN) TOP VIEW • ±1.8% accuracy over all operating conditions • Tiny 10 Ld 3mmx3mm DFN package VIN 1 10 VO1 • -40°C to +85°C operating temperature range EN1 2 9 VO2 • Pin compatible with Micrel MIC2211 EN2 3 8 NC CBYP 4 7 NC NC 5 6 GND • Pb-free (RoHS compliant) Applications • PDAs, Cell Phones and Smart Phones • Portable Instruments, MP3 Players • Handheld Devices including Medical Handhelds 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2007, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. ISL9014A Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING VO1 VOLTAGE VO2 VOLTAGE TEMP RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL9014AIRNNZ DKNA 3.3V 3.3V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRNJZ DKMA 3.3V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRNFZ DKLA 3.3V 2.5V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRNCZ DKKA 3.3V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRMNZ DKJA 3.0V 3.3V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRMMZ DKHA 3.0V 3.0V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRMGZ DKGA 3.0V 2.7V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRLLZ DKFA 2.9V 2.9V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRKNZ DKDA 2.85V 3.3V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRKKZ DKCA 2.85V 2.85V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRKJZ DKBA 2.85V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRKFZ DJYA 2.85V 2.5V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRKPZ DKEA 2.85V 1.85V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRKCZ DJWA 2.85V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRJNZ DJTA 2.8V 3.3V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRJMZ DJSA 2.8V 3.0V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRJRZ DJVA 2.8V 2.6V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRJCZ DJRA 2.8V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRJBZ DJPA 2.8V 1.5V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRGPZ DJNA 2.7V 1.85V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRGCZ DJMA 2.7V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRFJZ DJLA 2.5V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRFDZ DJKA 2.5V 2.0V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRFCZ DJJA 2.5V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRPLZ DKPA 1.85V 2.9V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRPPZ DKRA 1.85V 1.85V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRCJZ DJHA 1.8V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRCCZ DJGA 1.8V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRBLZ DJFA 1.5V 2.9V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRBJZ DJEA 1.5V 2.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRBCZ DJDA 1.5V 1.8V -40 to +85 10 Ld 3x3 DFN L10.3x3C ISL9014AIRBBZ DJCA 1.5V 1.5V -40 to +85 10 Ld 3x3 DFN L10.3x3C NOTES: 1. Please refer to TB347 for details on reel specifications. 2. For availability and lead time of devices with voltage combinations not listed in the table, contact Intersil Marketing. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2 FN6438.1 March 11, 2008 ISL9014A Absolute Maximum Ratings Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V VO1, VO2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.6V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN+0.3)V Thermal Resistance (Notes 4, 5) Recommended Operating Conditions Ambient Temperature Range (TA) . . . . . . . . . . . . . . .-40°C to +85°C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3V to 6.5V θJA (°C/W) θJC (°C/W) 3x3 DFN Package . . . . . . . . . . . . . . . . 50 10 Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications PARAMETER Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 1.0V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF SYMBOL TEST CONDITIONS MIN (Note 7) TYP MAX (Note 7) UNITS 6.5 V DC CHARACTERISTICS Supply Voltage VIN 2.3 Quiescent condition: IO1 = 0µA; IO2 = 0µA Ground Current IDD1 One LDO active 25 40 µA IDD2 Both LDO active 45 60 µA Shutdown Current IDDS @ +25°C 0.1 1.0 µA UVLO Threshold VUV+ 1.9 2.1 2.3 V 1.6 1.8 VUVRegulation Voltage Accuracy Variation from nominal voltage output, VIN = VO +0.5V to 5.5V, TJ = -40°C to +125°C -1.8 Line Regulation VIN = (VOUT + 1.0V relative to highest output voltage) to 5.5V -0.2 Load Regulation IOUT = 100µA to 150mA 2.0 V +1.8 % 0 0.2 %/V 0.1 0.7 % IOUT = 100µA to 300mA Maximum Output Current IMAX Internal Current Limit Thermal Shutdown Temperature % 300 mA VO2: Continuous 300 mA ILIM Dropout Voltage (Note 6) 1.0 VO1: Continuous 350 475 600 mA VDO1 IO = 150mA; VO > 2.1V 125 200 mV VDO2 IO = 300mA; VO < 2.5V 300 500 mV VDO3 IO = 300mA; 2.5V ≤ VO ≤ 2.8V 250 400 mV VDO4 IO = 300mA; VO > 2.8V 200 325 mV TSD+ 145 °C TSD- 110 °C @ 1kHz 70 dB @ 10kHz 55 dB @ 100kHz 40 dB AC CHARACTERISTICS Ripple Rejection IO = 10mA, VIN = 2.8V(min), VO = 1.8V, CBYP = 0.1µF 3 FN6438.1 March 11, 2008 ISL9014A Electrical Specifications PARAMETER Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO + 1.0V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF; CBYP = 0.01µF (Continued) SYMBOL Output Noise Voltage TEST CONDITIONS MIN (Note 7) TYP IO = 100µA, VO = 1.5V, TA = +25°C, CBYP = 0.1µF BW = 10Hz to 100kHz 30 MAX (Note 7) UNITS µVRMS DEVICE START-UP CHARACTERISTICS Device Enable tIme tEN Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO(nom) 250 500 µs LDO Soft-Start Ramp Rate tSSR Slope of linear portion of LDO output voltage ramp during start-up 30 60 µs/V EN1, EN2 PIN CHARACTERISTICS Input Low Voltage VIL -0.3 0.5 V Input High Voltage VIH 1.4 VIN + 0.3 V 0.1 µA Input Leakage Current IIL, IIH Pin Capacitance CPIN Informative 5 pF NOTES: 6. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V. 7. Parts are 100% tested at +25°C. Temperature limits established by characterization and are not production tested. 4 FN6438.1 March 11, 2008 ISL9014A Typical Performance Curves 0.10 0.8 VO = 3.3V ILOAD = 0mA 0.4 0.2 -40°C 0.0 +25°C -0.2 +85°C -0.4 VIN = 3.8V VO = 3.3V 0.08 OUTPUT VOLTAGE CHANGE (%) OUTPUT VOLTAGE, VO (%) 0.6 -0.6 0.06 0.04 -40°C 0.02 +25°C 0.00 -0.02 +85°C -0.04 -0.06 -0.08 -0.8 3.4 3.8 4.6 4.2 5.0 5.4 5.8 6.2 6.6 -0.10 50 0 200 250 300 350 400 LOAD CURRENT - IO (mA) FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT 0.10 3.4 VIN = 3.8V VO = 3.3V ILOAD = 0mA 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 VO = 3.3V IO = 0mA 3.3 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE CHANGE (%) 150 100 INPUT VOLTAGE (V) 3.2 IO = 150mA 3.1 IO = 300mA 3.0 2.9 -0.08 -0.10 -40 2.8 -25 -10 5 20 50 35 65 TEMPERATURE (°C) 80 95 110 125 3.1 4.6 5.1 5.6 6.1 6.5 FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) 2.9 350 VO2 = 2.8V IO = 0mA 300 DROPOUT VOLTAGE, VDO (mV) 2.8 OUTPUT VOLTAGE, VO (V) 4.1 INPUT VOLTAGE (V) FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE 2.7 IO = 150mA 2.6 IO = 300mA 2.5 2.4 2.3 3.6 2.6 3.1 3.6 4.1 4.6 5.1 5.6 INPUT VOLTAGE (V) FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (VO2 = 2.8V) 5 6.1 6.5 250 VO = 2.8V 200 VO = 3.3V 150 100 50 0 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 400 FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT FN6438.1 March 11, 2008 ISL9014A Typical Performance Curves (Continued) 55 175 VO1 = 3.3V 50 GROUND CURRENT (µA) DROPOUT VOLTAGE, VDO (mV) 150 125 +85°C +25°C 100 -40°C 75 50 +125°C +25°C 45 -40°C 40 35 VO1 = 3.3V VO2 = 2.8V 30 25 IO (BOTH CHANNELS) = 0µA 0 25 0 25 50 75 100 125 OUTPUT LOAD (mA) 150 175 200 3.0 3.5 4.58 4.0 5.5 5.0 6.0 6.5 INPUT VOLTAGE (V) FIGURE 7. VO1 DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE 55 200 180 50 140 GROUND CURRENT (µA) GROUND CURRENT (µA) 160 +85°C 120 100 +25°C 80 -40°C 60 40 VIN = 3.8V VO1 = 3.3V VO2 = 2.8V 20 50 100 150 200 250 300 350 40 35 VIN = 3.8V VO = 3.3V ILOAD = 0µA 30 BOTH OUTPUTS ON 0 0 45 25 -40 400 -25 -10 5 LOAD CURRENT (mA) VO1 (V) 2 1 1 0 0 5 VEN (V) VOLTAGE (V) VO2 0 1 2 3 4 5 TIME (s) 6 7 8 FIGURE 11. POWER-UP/POWER-DOWN 6 110 125 9 VIN = 5.0V VO1 = 3.3V VO2 = 2.8V IL1 = 300mA IL2 = 300mA CL-1, CL-2 = 1µF CBYP = 0.01µF 3 3 2 95 VO2 (10mV/DIV) VO1 = 3.3V VO2 = 2.8V IL1 = 300mA IL2 = 300mA VIN VO1 4 80 FIGURE 10. GROUND CURRENT vs TEMPERATURE FIGURE 9. GROUND CURRENT vs LOAD 5 35 50 65 20 TEMPERATURE (°C) 10 0 0 100 200 300 400 500 600 700 800 900 1000 TIME (µs) FIGURE 12. TURN-ON/TURN-OFF RESPONSE FN6438.1 March 11, 2008 Typical Performance Curves (Continued) VO = 3.3V ILOAD = 300mA VO2 = 2.8V ILOAD = 300mA CLOAD = 1µF CBYP = 0.01µF CLOAD = 1µF CBYP = 0.01µF 4.3V 4.2V 3.6V 3.5V 10mV/DIV 10mV/DIV 400µs/DIV 400µs/DIV FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT 100 VIN = 3.6V VO = 1.8V IO = 10mA CBYP = 0.1µF CLOAD = 1µF 90 80 VO (25mV/DIV) VO = 1.8V VIN = 2.8V 300mA PSRR (dB) 70 60 50 40 30 ILOAD 20 100μA 10 0 0.1 100µs/DIV 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 16. PSRR vs FREQUENCY FIGURE 15. LOAD TRANSIENT RESPONSE SPECTRAL NOISE DENSITY (nV/√Hz) 1000 100 10 VIN = 3.6V VO = 1.8V ILOAD = 10mA 1 CBYP = 0.1µF CIN = 1µF CLOAD = 1µF 0.1 10 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 17. SPECTRAL NOISE DENSITY vs FREQUENCY 7 FN6438.1 March 11, 2008 Pin Description PIN # PIN NAME 1 VIN Analog I/O Supply Voltage/LDO Input: Connect a 1µF capacitor to GND. 2 EN1 Low Voltage Compatible CMOS Input LDO-1 Enable. 3 EN2 Low Voltage Compatible CMOS Input LDO-2 Enable. 4 CBYP Analog I/O Reference Bypass Capacitor Pin: Optionally connect capacitor of value 0.01µF to 1µF between this pin and GND to tune in the desired noise and PSRR performance. 5, 7, 8 NC NC No Connection 6 GND Ground GND is the connection to system ground. Connect to PCB Ground plane. 9 VO2 Analog I/O LDO-2 Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended). 10 VO1 Analog I/O LDO-1 Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended). TYPE DESCRIPTION Typical Application ISL9014A VIN (2.3V to 6.5V) 10 1 VIN ON 2 ENABLE 1 OFF ON ENABLE 2 OFF 3 9 EN1 4 5 C1 VOUT 1 VO1 VOUT 2 VO2 8 EN2 NC CBYP NC 7 6 NC GND C2 C3 C4 C1, C3, C4: 1µF X5R CERAMIC CAPACITOR C2: 0.1µF X5R CERAMIC CAPACITOR 8 FN6438.1 March 11, 2008 Block Diagram VIN IS1 LDO VREF 1V VO1 ERROR TRIM VO1 AMPLIFIER QEN1 ~1.0V VO2 LDO-1 EN1 QEN2 QEN1 IS2 IS1 LDO-2 CONTROL LOGIC EN2 UVLO GND BANDGAP AND TEMPERATURE SENSOR 1.00V CBYP Functional Description The ISL9014A contains all circuitry required to implement two high performance LDO’s. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9014A adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, staged turn-on and soft-start. Smart Thermal shutdown protects the device against overheating. Staged turn-on and soft-start minimize start-up input current surges without causing excessive device turn-on time. Power Control The ISL9014A has two separate enable pins (EN1 and EN2) to individually control power to each of the LDO outputs. When both EN1 and EN2 are low, the device is in shutdown mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1µA. 9 VOLTAGE REFERENCE GENERATOR When one or both of the enable pins are asserted, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power up. Once the references are stable, a fast-start circuit quickly charges the external reference bypass capacitor (connected to the CBYP pin) to the proper operating voltage. After the bypass capacitor has been charged, the LDO’s power up. If EN1 is brought high, and EN2 goes high before the VO1 output stabilizes, the ISL9014A delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high, and EN1 goes high before VO2 starts its output ramp, then VO1 turns on first and the ISL9014A delays the VO2 turn-on until the VO1 output reaches its target level. FN6438.1 March 11, 2008 If EN2 is brought high, and EN1 goes high after VO2 starts its output ramp, then the ISL9014A immediately starts to ramp up the VO1 output. If both EN1 and EN2 are brought high at the same time, the VO1 output has priority, and is always powered up first. During operation, whenever the VIN voltage drops below about 1.8V, the ISL9014A immediately disables both LDO outputs. When VIN rises back above 2.1V, the device re-initiates its start-up sequence and LDO operation will resume automatically. Reference Generation LDO Regulation and Programmable Output Divider The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9014A provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1µF to 10µF output capacitor that has a tolerance better than 20% and ESR less than 200mΩ. The design is performance-optimized for a 1µF capacitor. Unless limited by the application, use of an output capacitor value above 4.7µF is not recommended as LDO performance improvement is minimal. The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01µF capacitor connected CBYP implements a 100Hz lowpass filter, and is recommended for most high performance applications. For the lowest noise application, a 0.1µF or greater CBYP capacitor should be used. This filters the reference noise to below the 10Hz to 1kHz frequency band, which is crucial in many noise-sensitive applications. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30µs/V to minimize current surge. The ISL9014A provides short-circuit protection by limiting the output current to about 475mA. The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference and other voltage references required for current generation and over-temperature detection. The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about +145°C, one or both of the LDO’s momentarily shut down until the die cools sufficiently. In the overheat condition, only the LDO sourcing more than 50mA will be shut off. This does not affect the operation of the other LDO. If both LDOs source more than 50mA and an overheat condition occurs, both LDO outputs are disabled. Once the die temperature falls back below about +110°C, the disabled LDO(s) are re-enabled and soft-start automatically takes place. The current generator outputs references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination. 10 Each LDO uses an independently trimmed 1V reference. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory. Overheat Detection FN6438.1 March 11, 2008 Dual Flat No-Lead Plastic Package (DFN) L10.3x3C 2X 0.10 C A A 10 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE D MILLIMETERS 2X 0.10 C B E SYMBOL MIN NOMINAL MAX NOTES A 0.85 0.90 0.95 - A1 - - 0.05 - A3 6 INDEX AREA b 0.20 REF 0.20 D TOP VIEW B D2 // A C SEATING PLANE D2 6 INDEX AREA 0.08 C 7 8 D2/2 1 2.33 2.38 2.43 7, 8 1.69 7, 8 3.00 BSC 1.59 e 1.64 - 0.50 BSC - k 0.20 - - - L 0.35 0.40 0.45 8 N 10 2 Nd 5 3 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. NX k 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. E2 E2/2 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. NX L N N-1 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX b e (Nd-1)Xe REF. BOTTOM VIEW 5 0.10 M C A B (A1) 9 L 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. CL NX (b) 5, 8 Rev. 1 4/06 2 (DATUM A) 8 0.30 3.00 BSC E E2 A3 SIDE VIEW (DATUM B) 0.10 C 0.25 - 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2. e SECTION "C-C" C C TERMINAL TIP FOR ODD TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6438.1 March 11, 2008