ISL9005 ® Datasheet December 22, 2005 LDO with Low ISUPPLY, High PSRR Features ISL9005 is a high performance Low Dropout linear regulator capable of sourcing 300mA current. It has a low standby current and high-PSRR and is stable with output capacitance of 1µF to 10µF with ESR of up to 200mΩ. • 300mA high performance LDO The ISL9005 has a high PSRR of 75dB and output noise less than 45µVRMS. When coupled with a no load quiescent current of 50µA (typical), and 0.1µA shutdown current, the ISL9005 is an ideal choice for portable wireless equipment. FN9234.0 • Excellent transient response to large current steps • Excellent load regulation: <0.1% voltage change across full range of load current • High PSRR: 75dB @ 1kHz • Wide input voltage capability: 2.3V - 6.5V • Very low quiescent current: 50µA Several different fixed voltage outputs are standard. Other output voltage options for the LDO are available on request and range from 1.3V to 3.6V. • Low dropout voltage: typically 200mV @ 300mA Pinout • Soft-start to limit input current surge during enable ISL9005 (8 LD DFN 2x3) TOP VIEW • Low output noise: typically 45µVRMS @ 100µA (1.5V) • Stable with 1-10µF ceramic capacitors • Current limit and overheat protection • ±1.8% accuracy over all operating conditions • Tiny 2x3mm 8 Ld DFN package VIN 1 8 VO EN 2 7 NC NC 3 6 NC NC 4 5 GND • -40°C to +85°C operating temperature range • Pb-free plus anneal available (RoHS compliant) Applications • PDAs, cell phones and smart phones • Portable instruments, MP3 players • Handheld devices including medical handhelds Ordering Information PART NUMBER (Note 1) PART MARKING VO VOLTAGE (V) (Note 2) TEMP RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL9005IRNZ-T ETA 3.3V -40 to 85 8 Ld DFN 2x3 Tape and Reel L8.2x3 ISL9005IRMZ-T ESA 3.0V -40 to 85 8 Ld DFN 2x3 Tape and Reel L8.2x3 ISL9005IRLZ-T ERA 2.9V -40 to 85 8 Ld DFN 2x3 Tape and Reel L8.2x3 ISL9005IRKZ-T EPA 2.85V -40 to 85 8 Ld DFN 2x3 Tape and Reel L8.2x3 ISL9005IRJZ-T ENA 2.8V -40 to 85 8 Ld DFN 2x3 Tape and Reel L8.2x3 ISL9005IRRZ-T EVA 2.6V -40 to 85 8 Ld DFN 2x3 Tape and Reel L8.2x3 ISL9005IRFZ-T EMA 2.5V -40 to 85 8 Ld DFN 2x3 Tape and Reel L8.2x3 ISL9005IRCZ-T ELA 1.8V -40 to 85 8 Ld DFN 2x3 Tape and Reel L8.2x3 ISL9005IRBZ-T EKA 1.5V -40 to 85 8 Ld DFN 2x3 Tape and Reel L8.2x3 NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. For other output voltages, contact Intersil Marketing. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL9005 Absolute Maximum Ratings Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.1V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN+0.3)V ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . .2500V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .200V Thermal Resistance (Notes 3, 4) θJA (°C/W) θJC (°C/W) 8 Ld DFN 2x3 Package . . . . . . . . . . . . 69 10 Junction Temperature Range . . . . . . . . . . . . . . . . .-40°C to +125°C Operating Temperature Range . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C Recommended Operating Conditions Ambient Temperature Range (TA) . . . . . . . . . . . . . . . .-40°C to 85°C Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 to 6.5V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 4. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO+0.5V) to 5.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 6.5 V DC CHARACTERISTICS Supply Voltage VIN Ground Current 2.3 Quiescent condition: IO = 0µA IDD LDO active 50 75 µA LDO disabled @ 25°C 0.1 1.0 µA Shutdown Current IDDS UVLO Threshold VUV+ 1.9 2.1 2.3 V VUV- 1.6 1.8 2.0 V Regulation Voltage Accuracy Maximum Output Current IMAX Internal Current Limit ILIM Dropout Voltage (Note 6) Thermal Shutdown Temperature Initial accuracy at VIN = VO+0.5V, IO = 10mA, TJ = 25°C -0.7 +0.7 % VIN = VO+0.5V to 5.5V, IO = 10µA to 300mA, TJ = 25°C -0.8 +0.8 % VIN = VO+0.5V to 5.5V, IO = 10µA to 300mA, TJ = -40°C to 125°C -1.8 +1.8 % Continuous 300 350 mA 475 600 mA VDO1 IO = 300mA; VO < 2.5V 300 500 mV VDO2 IO = 300mA; 2.5V ≤ VO ≤ 2.8V 250 400 mV VDO3 IO = 300mA; VO > 2.8V 200 325 mV TSD+ 145 °C TSD- 110 °C @ 1kHz 75 dB @ 10kHz 60 dB @ 100kHz 40 dB IO = 100µA, VO = 1.5V, TA = 25°C BW = 10Hz to 100kHz 45 µVRMS AC CHARACTERISTICS Ripple Rejection (Note 5) IO = 10mA, VIN = 2.8V (min), VO = 1.8V Output Noise Voltage (Note 5) 2 FN9234.0 December 22, 2005 ISL9005 Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and temperature range of the device as follows: TA = -40°C to +85°C; VIN = (VO+0.5V) to 5.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS DEVICE START-UP CHARACTERISTICS Device Enable TIme TEN Time from assertion of the ENx pin to when the output voltage reaches 95% of the VO (nom) 250 500 µs LDO Soft-start Ramp Rate TSSR Slope of linear portion of LDO output voltage ramp during start-up 30 60 µs/V EN PIN CHARACTERISTICS Input Low Voltage VIL -0.3 0.5 V Input High Voltage VIH 1.4 VIN+0.3 V 0.1 µA Input Leakage Current IIL, IIH Pin Capacitance CPIN Informative 5 pF NOTES: 5. Guaranteed by design and characterization. 6. VOx = 0.98 * VOx(NOM); Valid for VOx greater than 1.85V. 3 FN9234.0 December 22, 2005 ISL9005 Typical Performance Curves 0.10 VO = 3.3V ILOAD = 0mA 0.6 0.4 0.2 -40°C 0.0 25°C -0.2 85°C -0.4 VIN = 3.8V VO = 3.3V 0.08 OUTPUT VOLTAGE CHANGE (%) OUTPUT VOLTAGE, VO (%) 0.8 -0.6 0.06 0.04 -40°C 0.02 25°C 0.00 -0.02 85°C -0.04 -0.06 -0.08 -0.8 3.4 3.8 4.6 4.2 5.0 5.4 5.8 6.2 -0.10 6.6 0 100 50 FIGURE 1. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) 250 300 400 350 FIGURE 2. OUTPUT VOLTAGE CHANGE vs LOAD CURRENT 0.10 3.4 VIN = 3.8V VO = 3.3V ILOAD = 0mA 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 VO = 3.3V IO = 0mA 3.3 OUTPUT VOLTAGE, VO (V) OUTPUT VOLTAGE CHANGE (%) 200 150 LOAD CURRENT - IO (mA) INPUT VOLTAGE (V) 3.2 IO = 150mA 3.1 IO = 300mA 3.0 2.9 -0.08 -0.10 -40 2.8 -25 5 -10 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 DROPOUT VOLTAGE, VDO (mV) OUTPUT VOLTAGE, VO (V) 2.7 IO = 150mA 2.6 IO = 300mA 2.5 2.4 3.6 4.1 4.6 5.1 5.6 6.1 INPUT VOLTAGE (V) FIGURE 5. OUTPUT VOLTAGE vs INPUT VOLTAGE (2.8V OUTPUT) 4 4.6 5.1 5.6 6.1 6.5 350 VO = 2.8V 2.8 3.1 4.1 FIGURE 4. OUTPUT VOLTAGE vs INPUT VOLTAGE (3.3V OUTPUT) 2.9 2.3 2.6 3.6 INPUT VOLTAGE (V) FIGURE 3. OUTPUT VOLTAGE CHANGE vs TEMPERATURE IO = 0mA 3.1 6.5 300 250 VO = 2.8V 200 VO = 3.3V 150 100 50 0 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 400 FIGURE 6. DROPOUT VOLTAGE vs LOAD CURRENT FN9234.0 December 22, 2005 ISL9005 Typical Performance Curves (Continued) 80 350 VO = 3.3V 70 GROUND CURRENT (µA) DROPOUT VOLTAGE, VDO (mV) 300 250 85°C 25°C -40°C 200 150 100 125°C 60 25°C 50 -40°C 40 VO = 3.3V 30 50 0 0 50 100 150 200 250 OUTPUT LOAD (mA) 300 350 20 400 3.0 3.5 4.0 4.58 5.0 5.5 6.5 6.0 INPUT VOLTAGE (V) FIGURE 7. DROPOUT VOLTAGE vs LOAD CURRENT FIGURE 8. GROUND CURRENT vs INPUT VOLTAGE 80 200 180 70 140 GROUND CURRENT (µA) GROUND CURRENT (µA) 160 25°C 85°C 120 -40°C 100 80 60 40 50 40 VIN = 3.8V VO = 3.3V 20 0 60 0 50 100 150 200 250 300 350 VIN = 3.8V VO = 3.3V ILOAD = 0µA 30 20 -40 -25 400 -10 5 LOAD CURRENT (mA) FIGURE 9. GROUND CURRENT vs LOAD 20 35 50 65 TEMPERATURE (°C) 110 125 VIN = 5.0V VO = 2.85V IL = 150mA 5 CL = 1µF 3 4 VO (V) 2 VIN 3 VO 2 1 0 0.5 1 0 VEN (V) VOLTAGE (V) 95 FIGURE 10. GROUND CURRENT vs TEMPERATURE VO = 2.85V IL = 150mA 0 80 1 1.5 2 2.5 TIME (s) 3 3.5 4 FIGURE 11. POWER-UP/POWER-DOWN 5 4.5 5 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 TIME (ms) 1.4 1.6 1.8 2.0 FIGURE 12. TURN ON/TURN OFF RESPONSE FN9234.0 December 22, 2005 ISL9005 Typical Performance Curves (Continued) VO = 3.3V ILOAD = 300mA VO = 2.8V ILOAD = 300mA CLOAD = 1µF CLOAD = 1µF 4.3V 4.2V 3.6V 3.5V 10mV/DIV 10mV/DIV 400µs/DIV 400µs/DIV FIGURE 13. LINE TRANSIENT RESPONSE, 3.3V OUTPUT FIGURE 14. LINE TRANSIENT RESPONSE, 2.8V OUTPUT VO (25mV/DIV) VO = 1.8V VIN = 2.8V 300mA ILOAD SPECTRAL NOISE DENSITY (uV/√Hz) 10 1 0.1 VIN = 3.6V VO = 1.8V ILOAD = 10mA CIN = 1µF 0.01 CLOAD = 1µF 100µA 0.001 10 100 1k 10k FREQUENCY (Hz) 100µs/DIV FIGURE 15. LOAD TRANSIENT RESPONSE 100k 1M FIGURE 16. SPECTRAL NOISE DENSITY vs FREQUENCY 100 VIN = 3.6V VO = 1.8V IO = 10mA CLOAD = 1µF 90 80 PSRR (dB) 70 60 50 40 30 20 10 0 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 17. PSRR vs FREQUENCY 6 FN9234.0 December 22, 2005 ISL9005 Pin Description PIN # PIN NAME DESCRIPTION 1 VIN Supply Voltage/LDO Input: Connect a 1µF capacitor to GND. 2 EN LDO Enable. 3 NC Do not connect. 4 NC Do not connect. 5 GND 6 NC Do not connect. 7 NC Do not connect. 8 VO LDO Output: Connect capacitor of value 1µF to 10µF to GND (1µF recommended). GND is the connection to system ground. Connect to PCB Ground plane. Typical Application ISL9005 VIN (2.3-5V) 1 ON 2 ENABLE OFF 3 C1 4 VIN VO EN NC NC NC NC GND 8 VOUT 7 6 5 C2 C1, C2: 1µF X5R ceramic capacitor 7 FN9234.0 December 22, 2005 ISL9005 Block Diagram During operation, whenever the VIN voltage drops below about 1.84V, the ISL9005 immediately disables the LDO output. When VIN rises back above 2.1V, the device reinitiates its start-up sequence and LDO operation will resume automatically. VIN VO UVLO CONTROL LOGIC Reference Generation The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. SHORT CIRCUIT, THERMAL PROTECTION, SOFT-START The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference and other voltage references required for current generation and overtemperature detection. EN The current generator outputs references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination. LDO Regulation and Programmable Output Divider GND BANDGAP AND TEMPERATURE SENSOR VOLTAGE AND REFERENCE GENERATOR 1.0V 0.94V 0.9V GND Functional Description The ISL9005 contains all circuitry required to implement a high performance LDO. High performance is achieved through a circuit that delivers fast transient response to varying load conditions. In a quiescent condition, the ISL9005 adjusts its biasing to achieve the lowest standby current consumption. The device also integrates current limit protection, smart thermal shutdown protection, and soft-start. Smart Thermal shutdown protects the device against overheating. Power Control The ISL9005 has an enable pin, EN, to control power to the LDO output. When EN is low, the device is in shutdown mode. During this condition, all on-chip circuits are off, and the device draws minimum current, typically less than 0.1µA. When the enable pin is asserted, the device first polls the output of the UVLO detector to ensure that VIN voltage is at least about 2.1V. Once verified, the device initiates a start-up sequence. During the start-up sequence, trim settings are first read and latched. Then, sequentially, the bandgap, reference voltage and current generation circuitry power up. Once the references are stable, a fast-start circuit powers up the LDO. 8 The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9005 provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1µF to 10µF output capacitor that has a tolerance better than 20% and ESR less than 200mΩ. The design is performance-optimized for a 1µF capacitor. Unless limited by the application, use of an output capacitor value above 4.7µF is not recommended as LDO performance improvement is minimal. Soft-start circuitry integrated into each LDO limits the initial ramp-up rate to about 30µs/V to minimize current surge. The ISL9005 provides short-circuit protection by limiting the output current to about 425mA. The LDO uses an independently trimmed 1V reference as its input. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory. Overheat Detection The bandgap outputs a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about 140°C, if the LDO is sourcing more than 50mA it shuts down until the die cools sufficiently. Once the die temperature falls back below about 110°C, the disabled LDO is re-enabled and soft-start automatically takes place. FN9234.0 December 22, 2005 ISL9005 Dual Flat No-Lead Plastic Package (DFN) L8.2x3 2X 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE 0.15 C A A D 2X 0.15 C B E MILLIMETERS SYMBOL MIN A 0.80 A1 - 6 A3 INDEX AREA b TOP VIEW D2 // 0.10 A SIDE VIEW C SEATING PLANE D2 (DATUM B) C 0.08 C 0.20 A3 7 8 0.90 1.00 - - 0.05 - 0.25 0.32 1 5,8 1.50 1.65 1.75 7,8 3.00 BSC 1.65 e 1.80 1.90 7,8 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 8 Nd 4 D2/2 6 INDEX AREA NOTES 2.00 BSC E E2 MAX 0.20 REF D B NOMINAL 2 3 Rev. 0 6/04 2 NX k NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. (DATUM A) E2 4. All dimensions are in millimeters. Angles are in degrees. E2/2 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. NX L N N-1 NX b e 8 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 5 0.10 (Nd-1)Xe REF. M C A B 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. BOTTOM VIEW CL (A1) NX (b) L 5 SECTION "C-C" C C e TERMINAL TIP FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN9234.0 December 22, 2005