NCP1246: 65 W Fixed Frequency Current-Mode Controller, <30mW No-Load Standby

AND9170/D
Design Approach to
Light­Load Effective
Power Supply Utilizing
the NCP1244/46 PWM
Controllers
http://onsemi.com
APPLICATION NOTE
Introduction
of no-load input power. Two important components of
no-load consumption are the controller consumption and the
EMI filter X2 capacitor discharge branch.
The NCP1244/46 family of PWM controllers has
integrated advanced features which dramatically reduce
consumption in no-load mode. These are off-mode and the
X2 capacitors discharge sequences which fulfill the safety
requirements when the power supply is unplugged from the
outlet.
The power supply having no-load consumption below
30 mW can be designed using the NCP1244/46 family of
PWM controllers.
When designing power supplies, the important defining
regulations for efficiency and no-load power requirements
are the ENERGY STAR® specifications. With the release of
the EPS 2.0 standard, the light-load input power
consumption and the standby power consumption have
become more important. The new specification more
accurately reflects the actual usage of a laptop adapter which
operates a considerable amount of time in a no-load or
a minimal load operating condition (laptop in sleep mode).
The key losses need to be identified when focusing on the
light-load efficiency of the adapter design. Switching losses
play a major role in determining the light-load efficiency and
are directly linked to the control methodology. These losses
are caused by the energy stored in the sum of all the
capacitances at the drain node (MOSFET output
capacitance, stray capacitance of the transformer and other
parasitic capacitances on PCB) together with the gate charge
losses associated with driving the MOSFET. These losses
are also proportional to the switching frequency. Hence
reducing the switching frequency reduces the losses and
improves the efficiency.
The NCP1244/46 family of PWM controllers are focused
on meeting the new stringent ENERGY STAR®
requirements. A key part of this architecture is a frequency
foldback function, thereby lowering the frequency at lighter
loads and reducing the switching losses. The additional
feature helping to decrease the switching losses is a fixed
current set point under light-loading condition. This feature
increases the transferred energy in a single pulse, but also
decreases the switching frequency to deliver the required
amount of power to the load.
No-load input power of the power supply continues to be
an important requirement. This refers to when the power
supply or adapter is plugged into the wall outlet and not
plugged into the laptop. The requirements for less than
30 mW of no-load input power is quite common in such
applications like notebook, Ultrabookt or printer adapters.
Every loss component in the power supply design starts to
play a big role when trying to achieve such a small amount
© Semiconductor Components Industries, LLC, 2014
July, 2014 − Rev. 0
Application Note Contents
• The NCP1244/46 Features Brief Description
• Comparison between the Adapter Design Solution
•
•
•
•
•
•
Using NCP1236 without Off Mode with the Design
Utilizing the NCP1244/46
The Off-mode Control Detailed Description
X2 Capacitor Discharge System Description and its
Capability
The Low Power Measurement Analysis of Precision
The HV Pin Sensitivity to Noise
Summary of the Obtained Results
Reference Design
65 W ac-dc Adapter Board Specifications
The adapter was designed for the following performance
ratings:
Output Power
65 W
Output Voltage
19 Vdc
Output Current
3.42 A
Minimum Input Voltage
85 V
Maximum Input Voltage
265 V
Average Efficiency
(as per Energy Star 2.0 guidelines)
> 87%
No-Load Input Power
1
< 30 mW
Publication Order Number:
AND9170/D
AND9170/D
Features of NCP1244/46 Family
The usage of current mode PWM controllers from
NCP1244/46 family brings an advantage in decreasing the
consumption in no-load conditions by dedicated off-mode.
This mode is controlled by the FB pin and allows the remote
control (or secondary side control) of the power supply to
shut down. Most of the device’s internal circuitry is unbiased
in the low consumption off-mode. Only the FB pin control
circuitry and X2 cap discharging circuitry operates in the
low consumption off-mode. When the voltage at feedback
pin decreases below the 0.4 V, the controller enters the low
consumption off-mode. The controller starts if the FB pin
voltage increases above the 2.2 V level. Other features
include:
• X2 Capacitor Discharge: This feature saves
approximately 16 mW – 25 mW input power depending
on the EMI filter X2 capacitors volume and it saves
the external components count as well. The discharge
feature is ensured via the start-up current source with
a dedicated control circuitry for this function.
• Current-Mode Control: Cycle by cycle, primary
current sensing helps to prevent any significant
overcurrent conditions that would cause transformer
core saturation and result in power supply failure.
• Frequency Foldback: This advantage lies in decreasing
the switching frequency under light-load conditions.
This feature is called frequency foldback and
significantly helps to reduce switching losses.
• Frozen Current Setpoint under the Light-Load
Conditions: This feature increases efficiency under
the light-load conditions. The light-load condition is
detected when the FB pin voltage is below 1.5 V.
• Dynamic Self-Supply: This ensures the voltage supply
for the IC in applications where the output voltage
varies significantly during operation, e.g. during
the startup of the power supply or overload conditions.
The dynamic self-supply (DSS) also supplies the IC
during a latched state and when the switching operation
is stopped. The dynamic self-supply operates by means
of controlling the charging of the capacitor at Vcc pin
via a built-in high voltage current source. In order to
prevent any damage or overheating of the controller in
case of a short in Vcc circuitry, the high voltage startup
current is limited when the VCC is below 0.6 V.
• High Voltage Sensing: The device allows direct
high-voltage sensing up to 500 V to enable features
such as brown-out protection and input OVP without
using extra pins.
• Brown-Out Protection: This function is enabled for
the NCP1246 device only and protects the application
when the main voltage is too low. If the peak voltage at
the HV pin VHV is higher than 111 V (typical – see
VHV(start) spec in the datasheet) and if the VCC is high
enough, the device will start operating. The device runs
•
•
•
•
•
•
•
and produces the DRV pulses if the HV pin voltage is
above the VHV(stop) (brown-out protection stop level).
There is a 65 ms (typ.) timer before the brown-out
protection is activated allowing the converter to ride
through a short line drop-out.
Timer Based Overcurrent Protection: The devices
NCP1244/46 offer the overcurrent protection which is
activated when the voltage at CS pin is above the
internal threshold of 0.7 V (typ.) for a longer time than
the overcurrent fault timer duration time (typ. 128 ms).
Current Stop Protection: A special additional current
stop protection senses the voltage at the current sensing
pin. If this voltage is higher than 150% of
the maximum internal current set point, the protection
fault mode is immediately activated. This feature
protects application against the winding short-circuit or
the shorts at the output of the application.
Overpower Compensation: The primary peak current
value varies with the value of the input voltage.
The reason is the propagation delay between the
internal current set point detection and the power
MOSFET switch-off and dependence of the primary
current slope on the input voltage. In order to eliminate
this phenomenon, the peak voltage at HV pin is sensed
and converted into a current flowing out of the CS pin.
By the external resistor ROPP a voltage offset to Vsense
voltage is created providing the overpower
compensation as a result.
Built-In Internal Slope Compensation: In order to
avoid the sub-harmonic oscillations during the CCM
operation with the duty ratio D higher than 50%,
internal slope compensation is applied.
Latch Input: The LATCH pin feature allows
the additional external OVP and OTP protections.
If this pin is between 0.8 V and 2.5 V (when not
connected, it is at 1.2 V), the output drive pulses are
active. An external NTC can be used to pull it below
0.8 V for OTP and a Zener diode to the bias voltage can
be used to detect output OVP condition and shut down
the pulses. A decoupling capacitor C100 can be used to
filter an induced noise to node where the latch pin is
connected. A precharge current INTC(SSTART) is applied
to the C1 during the soft-start period to charge
the decoupling capacitor and avoid false triggering of
the OTP protection. Maximum recommended value of
C1 is 1.04 mF. It is important to note that during
soft-start period the OTP is not activated.
Skip Mode: This burst mode is used under no-load
conditions or light-load conditions to increase the total
efficiency and no-load input power.
Off-Mode: If the voltage at feedback pin decreases
below 0.4 V, the controller enters the off-mode, which
allows reaching extremely low no-load input power.
This feature enables the remote shut-down as well.
http://onsemi.com
2
AND9170/D
2
Low No-Load Mode Input Consumption
of the Adapter Utilizing NCP1236
P loss,X2 + tgdwC X2V ac,rms +
+ 1 @ 10 *3 @ 2 @ p @ 50 @ 100 @ 10 *9 @ 230 2 +
Firstly, let us analyze no-load power losses of notebook
adapter using the NCP1236 controller without any energy
saving feature. This analysis helps to understand the design
space for improvements to achieve the low no-load input
consumption. The schematic of this adapter is shown in
Figure 1. The typical no-load input power consumption is 70
to 80 mW at high input line 230 Vac,rms/50 Hz for such
a design. The following analysis will show the main losses
contributors under high line conditions 230 Vac,rms/50 Hz:
• Primary Controller Consumption: The controller
usually runs in skip mode in no-load, thus its
consumption is around 0.9 mA from the VCC supply.
Then the primary control consumption can be easily
calculated:
P PC + V CC @ I CC3 + 13.7 @ 0.9 @ 10
*6
+ 12.3 mW
+ 1.66 mW
The values of reactive current ICX2 and reactive power
Preact,X2 are also important.
I CX2 + wC X2V ac,rms + 2 @ p @ 50 @ 100 @ 10 *9 @ 230 +
(eq. 6)
+ 7.23 mW
2
P react,X2 + wC X2V ac,rms +
Loss on DC resistance RDC of the used common choke L2
type B82734W2202B030 from EPCOS are:
2
P loss,L2 + 2R DCI CX2 + 2 @ 0.24 @ 0.0723 2 +
(eq. 1)
P HVsense +
V HV,rms
R HV
+
30 @ 10 6
P HVbias + V HV,av @ I bias +
+ 1.76 mW
2 Ǹ2
@ V HV,rms @ I bias +
p
2 Ǹ2
@ 230 @ 10 @ 10 *6 + 2.1 mW
+
p
But its reactive power Preact,L2 caused by the stray
inductance is negligible:
2
P react,L2 + wL strayI CX2 +
+ 2 @ p @ 50 @ 105 @ 10 *6 @ 0.00723 2 +
V ac,rms
R var
2
+
230 2
100 @ 10 6
+ 0.53 mW
(eq. 9)
+ 1.7 mVAr
• Primary X2 Capacitor Discharge Branch
(eq. 2)
Consumption: This branch consists of the serial
resistors RD100, RD101, and RD102.
This consumption can be simply derived.
(eq. 3)
P disch +
V ac,rms
R dis
2
+
230 2
2.46 @ 10 6
+ 21.5 mW
(eq. 10)
• Leakage of the Bulk Capacitor: The dc leakage of the
The primary controller is analyzed. The following part
will examine other components of the primary no-load
consumption, this time, from the front-end side.
• Leakages: The leakage of all the branch components
(between the L and N) should not be neglected. It can
affect the no-load consumption. Let us consider the
varistor R5 leakage power loss PleakVAR . The EPCOS
type B72210P2301K101 is used and the datasheet
provides information about its isolation resistance
100 MW.
P leakVAR +
(eq. 8)
+ 0.025 mW
no-load consumption can be divided in two parts.
The first one is the high voltage sensor consumption
which has resistive character and the second one is the
bias consumption which has the character of the current
sink.
230 2
(eq. 7)
+ 2 @ p @ 50 @ 100 @ 10 *9 @ 230 2 + 1.66 VAr
• Primary HV Sensing Consumption: This part of
2
(eq. 5)
bulk capacitor on the primary side is a quite important
topic. The aluminum electrolytic capacitors are often
used as a bulk capacitor. Many vendors specifies its
maximum dc leakage current Ileak at a temperature of
20°C after 5 minutes of biasing at nominal voltage by
following formula: (it is valid for aluminum electrolytic
capacitor with maximum voltage higher than 100 V)
I leak + 0.02CV ) 15 [mA; mF, V]
(eq. 11)
The last term in the formula can differ from vendor to
vendor. The bulk capacitor CB1 value 100 mF/400 V was
designed. The selected one was the aluminum electrolytic
type EKXG401ELL101MMN3S from Nippon Chemi-Con.
The dc leakage Ileak value of this capacitor was calculated
82 mA, based on its datasheet. A similar type for
replacement B43044A9107M000 from EPCOS has
815 mA.
(eq. 4)
• Input EMI Filter Consumption: The losses in the input
EMI filter are caused by the dielectric polarization
losses in the X2 capacitors and losses caused by flow of
the X2 capacitors reactive current through their
equivalent serial resistance ESR and the dc resistances
of the common mode choke RDC . The loss in the X2
capacitor can be calculated using the dissipation factor
tgd. The EMI suppression capacitors from EPCOS
which are used are of the B32922C3104K type with
dissipation factor tgd 10-3. The loss in one X2 capacitor
is:
P leakBulk + V HVmaxI leak + Ǹ2 V HVrmsI leak +
+ Ǹ2 @ 230 @ 825 @ 10 *6 + 268mW
(eq. 12)
This calculated consumption is the worst case with a huge
margin. The real measurements show the dissipation at bulk
capacitor around 1 mW.
http://onsemi.com
3
R7
P$1
NTC10R−3A
R5
1XTSTPOINT
U$1
N
P$1
X2−1
4
1
23
WE
744 841 330
EPCOS
B82734
2n2
CY2
820k
820k
820k
2k7
R101
NTC 100n
330k
C100
DRV 5
VCC 6
HV 8
C101
NU
1n
680
R115
NCP1236B65
4 GND
3 CS
2 FB
1 LATCH
IC100
2k7
R100
C102
MMSZ15
D106
MRA4007T3G
100uF/400V
CB1
D100
+
D101
D1
1N4007
FB
22
R114
10k
R116
MMSD4148
2R2
R117 D107
2R2 MMSD4148
100n 47u/50V
C103 C1
R4
R103
R107
L2
33k
330k
R3
1R
R108
L4
R102
330k
1R
R111
CY3
2n2
MRA4007T3G
MRA4007T3G
D102
D103
MRA4007T3G
MRA4007T3G
D104
D105
5n6/500V
C2
TR1
AUX
R1
4M7
CY1
2n2
3
4
KA5038−AL
1/2 VIN
pins 2 & 3
connected on PCB
1/2 VIN
Q1
SPA10N60C3
FB
D108 D109
2R2
1R
4007 4007
F1
PC817W
2
1
OK1
15R
R6
C3
STPS30150CT
FB
D2
1.5A
COUT2
+
+
COUT1
C105
GND
1k0
R112
IC1
TL431
33n
C107
1k0
C106 1n0
R110
NU
L1
X1−1
GND
X1−2
DC OUTPUT
+ 19V/3.5A
WE
744 841 414
C104
470u/25V 470u/25V 470u/25V 33n
COUT3
L3
R105
R106
R104
R2
1R
R113
http://onsemi.com
GND GND
+
3k9
4
1
L
8k2
6k2
2k2
4
GND
23
X2−2
AND9170/D
Figure 1. The Notebook Adapter Schematic using the NCP1236 Controller
R109
100n CX1
RD102 RD101 RD100
100n CX2
B72210P2301K101
AND9170/D
• Leakage of the Primary Switch: The primary switch
Table 1. SUMMARY OF THE NO-LOAD
CONSUMPTION ANALYSIS FOR THE ADAPTER
USING NCP1236 CONTROLLER
Q1 leakage dissipation loss calculation is shown to
complete this detailed analysis. The maximum DC
leakage of the used type SPP11N60C3 from Infineon is
1 mA, so the primary switch Q1 power dissipation
caused by leakage is negligible.
Component
P leakQ1 + V HVmaxI leak + 325 @ 1 @ 10 *6 + 0.33 mW (eq. 13)
The analysis further continues with the secondary
consumption.
• Secondary Control Consumption: The first part of
the secondary consumption in no-load mode is
the secondary controller current. It is given by
the TL431 bias current and the opto-coupler LED
current needed to pull down the primary controller FB
pin. Let us assume the CTR of this opto-coupler is 50%
and typical FB pin pull-up current 250 mA, then
the needed secondary opto-coupler LED current is
0.5 mA. Consumption of secondary control is:
P 431 + V OUT @
+ 19 @
ǒ
V LED
R bias
ǒ[email protected] 10
Ǔ
) I LED @
3
V LED
R bias
+
Ǔ
(eq. 14)
V OUT
R div
2
+
Varistor
PleakVAR [mW]
0.53
EMI Filter - X2 Capacitors
2 x Ploss,X2 [mW]
3.32
EMI Filter - L2 Common Choke
Ploss,L2 [mW]
X2 Discharge Branch
Pdisch [mW]
Bulk Capacitor DC Leakage Loss
PleakBulk [mW]
Q1 Leakage Loss
PleakQ1 [mW]
0.33
Primary Controller - HV Bias
PHVbias [mW]
2.1
Primary Controller - HV Sense
PHVsense [mW]
1.76
Primary Controller - VCC
Consumption
PPC [mW]
12.3
Secondary Controller - TL431
P431 [mW]
13.88
Secondary Divider
Pdiv [mW]
21.74
Transfer Efficiency
h [%]
Transfer to Primary
Pprim [mW]
Total No-Load Input Power
Pin [mW]
) 0.5 @ 10 *3 + 13.88 mW
19 2
+ 21.74 mW
16.6 @ 10 3
(eq. 15)
NOTE: The indicating LED is not used in many
adapters due to its huge consumption if it is
supplied by the steady dc current. Let us assume
5 mA of the dc LED current.
P LED + V OUT @ I LED + 19 @ 5 @ 10 *3 + 95 mW
0.025
21.5
1
60
79.9
110.4
Having consulted Table 1, the major contributors to the
no-load input power can be identified. They are the X2
capacitor discharging resistive branch, primary controller
consumption, secondary controller consumption, and
branch current through the secondary voltage feedback
divider. The optimization for the low no-load input power
was performed at these fields:
• The X2 Capacitor Discharging resistive branch was
totally removed from application and was replaced by
the primary controller device integrated feature.
• The Primary Controller was optimized for the lowest
consumption from the VCC circuitry and the dedicated
off-mode was added.
• The Energy Saving Hiccup Mode was chosen for the
secondary control under the no-load condition to save
the input power and keep the ability to detect the load
connected to output and restart the primary controller.
• The Secondary Voltage Feedback Divider branch
current was optimized to obtain the low consumption
and still keep the reasonable transient responses and
herewith noise and EMC immunity.
The second component of the secondary consumption in
no-load mode is the branch current through the feedback
divider.
P OUTdiv +
Consumption
(eq. 16)
This is a huge number. This needs to be recalculated to
the primary side considering the efficiency of the power
supply. The additional component 158 mW of the no-load
input power consumption appears. The purpose which is to
reach the minimum no-load consumption is diminished by
the usage of such LED driving. It is possible to use dedicated
secondary controllers to drive the LED by current pulses
only, and thus significantly decrease the consumption.
ON Semiconductor offers a dedicated family of the
secondary controllers with such a built-in LED driver of the
NCP435X devices family.
The following part will provide a summary of all
previously calculated numbers and obtain the expected
no-load input power consumption.
The total no-load input power calculated value 110 mW
noticeably differs from the measured value 87.9 mW under
the same high input line conditions. The root cause of the
difference lies in the analysis approach because all
the calculations were done for the worst cases values from
datasheets (the typical values are not usually mentioned for
such parameters as leakages or isolation resistances).
http://onsemi.com
5
L
F1
X2−2
R5
1
R6
NU
WE
744 841 330
2
100n
B72210P2301K101
4
L4
3
CX2
L2
2n2
CY2
33k
1XTSTPOINT
D105
D106
D103
D104
MRA4007T3G
MRA4007T3G
D109
NTC
330k
VCC 6
DRV 5
HV 8
C102
NU
1n0
680
R123
NCP1246B65
3 CS
4 GND
1 LATCH
2 FB
C101
MMSZ15
2k7
R100
IC100
2k7
MRA4007T3G
MRA4007T3G
D107
100uF/400V
CB1
R102
100n
EPCOS
B82734
2n2
1.5A
100n
C100
R2
D100
D1
1N4007
+
22R
100n 47u/50V
C103 C1
R119
10k
R124
2R2 MMSD4148
D112
R126
2R2 MMSD4148
R103
R4
330k
R3
330k
FB
5n6/500V
TR1
AUX
4
MRA4007T3G
2
R7
C4
MMDL914
4u7/50V
C2
C107
NU
+
470u/25V
COUT2
GND
D102
GND
NU
D101
15R
1n2/500V
NTST30100SG
FB
1
PC817W
R1
4M7
CY1
2n2
3
MRA4007T3G
OK1
KA5038−BL
1/2 VIN
pins 2 & 3
connected on PCB
1/2 VIN
Q1
SPP11N60C3
FB
2R2
R108
1R
R109
1R
R113
1R
R118
1R
D114
R101
D113
CX1
X2−1
D2
GND GND
CY3
N
NU
MRA4007T3G
MRA4007T3G
U$3
P$1
P$1
L3
+
COUT1
470u/25V 470u/25V
2u2
COUT3
1k0
Q101
5k1 BC817−25LT1SMDNU
Q102
BC817−25LT1SMD
33n
C105
4
NCP431
IC1
5n6
47k
C106 180p
GND
1n5
C108
X1−1
GND
X1−2
DC OUTPUT
+ 19V/3.5A
WE
744 841 414
L1
R116 C109
1
D108
R112
R122
+
R114
+
R105
R107
R111
100k
Q100
330k
R104
33k
10k
MMDL914MMDL914
BC807−25LT1SMD
100k
D111 D110
C104
NU
R106
R110
R117R1151k0
23
100R
160k
R125
12k
6
12k
http://onsemi.com
R120 R121
C3
AND9170/D
Figure 2. Schematic of the Notebook Adapter Using NCP1246 with Optimized No-Load Input Power
AND9170/D
Description of the Design Solution Utilizing NCP1246
The Off-Mode Principle
The solution was implemented utilizing a flyback
topology, granting the advantage of a quite high density
power design. The design operates in both CCM (continuous
conduction mode) and DCM (discontinuous conduction
mode) allowing it to accept a wide universal input voltage
range.
The CCM operation provides a desired full load
performance with good efficiency and a low ripple of
primary current. The DCM operation permits an increase of
efficiency under the light-load conditions by decreasing the
switching losses. The device switches at 65 kHz, which
represents a good trade-off between switching losses,
magnetic size and the EMI.
The NCP1246 fixed frequency controller was selected to
achieve the design requirements. This device is housed in
a SOIC 7 leads that includes multiple features including
input ac line sensing. The electrical schematic of the adapter
board is shown in Figure 2.
The adapter consists of several important sections.
The first one is an input EMI filter which reduces the
conducted EMI to the ac line at the input of the adapter.
The EMI filter is formed by 2 common-mode inductors L4
and L2 and capacitors CX1, CX2. The varistor R5 is used to
protect the adapter against the line overvoltage peaks and
NTC R6 is not used to increase the full load efficiency.
The L4 inductor is used to filter the RF components of the
conducted EMI.
The next block is the rectifier with a bulk capacitor.
The HV pin of the controller NCP1244/46 is sensing the
voltage in front of the rectifier. HV pin must observe full
wave rectified ac signal to ensure the correct functionality of
built-in X2 capacitors discharge circuitry. The HV pin must
not be connected to dc voltage. It will cause activation of X2
capacitors discharge circuitry and a consequent outbreak of
the device by long term overheating.
The main power stage of the flyback converter utilizes the
SPP11N60C3 MOSFET from Infineon along with a custom
designed transformer TR1 type KA5038-BL from Coilcraft
company. Secondary rectification is provided by a low drop
Schottky diode NTST30100SG from ON Semiconductor.
A simple RC snubber across the secondary rectifier damps
any high frequency ringing caused by the unclamped
leakage inductance at secondary side of the transformer.
The
programmable
reference
NCP431
from
ON Semiconductor ensures the output voltage regulation.
The NCP431 output is coupled via the opto-coupler to the
controller of the NCP1246B 65 kHz version. The last stage
of the adapter is the output filter consisting of primary filter
capacitors COUT2 and COUT3, and secondary filter made
up of L3, and COUT1. The output common choke L1
decreases the radiated EMI by preventing the flow of
asymmetric radiating current into the floating load.
If the voltage at feedback pin decreases below 0.4 V, the
controller enters the off-mode allowing reaching extremely
low no-load input power consumption. The internal VCC is
turned-off, the IC consumes extremely low VCC current and
only the voltage at external VCC capacitor is maintained by
the Self-Supply circuit. The Self-Supply circuit keeps the
VCC voltage at the VCC(reg) level. The supply for the FB pin
watch dog circuitry and FB pin bias is provided via the low
consumption current sources from the external VCC
capacitor. The controller can start only if the FB pin voltage
increases above the 2.2 V level.
The protection timer GoToOffMode tGTOM is used to
protect the application against the false activation of the low
consumption off-mode by the fast drop outs of the FB pin
voltage below the 0.4 V level e.g. in case the high FB pin
voltage ripple is present during the skip mode.
The secondary circuitry regulates the primary controller
so that it can enter off-mode or leave this mode via the
feedback opto-coupler. The additional circuitry is needed to
detect the no-load condition and control the opto-coupler so
that the primary controller can enter off-mode or rouse the
primary controller.
The no-load condition is detected via the peak detector
formed by diode D102, capacitor C2, and the load consisting
of R111 and R112. The time constant given by the capacitor
C2, and its load R111, and R112 defines the time detection
level from which the hiccup mode starts. The voltage across
capacitor C2 is dropping while no positive voltage pulses are
present at secondary winding for a set time period. This time
period is set by the time constant of circuitry consisting of
C2, R105, R107, R111, and R112. The voltage across C2
drops and causes the closing of the switch Q100 and
consequently turning-on of the current source Q101.
The current source Q101 forces a permanent lighting of the
opto-coupler LED and consequently pulls down the FB pin.
GoToOffMode timer tGTOM (inside the primary controller)
starts to count down when the pulled-down FB voltage
crosses the 0.4 V level. The off-mode starts when this timer
elapses. The primary controller is kept off now, zero energy
is transferred via the transformer and the output voltage
starts to fall down slowly. Its decreasing is caused by the self
consumption of the secondary control circuitry.
http://onsemi.com
7
AND9170/D
2u2
1n2/500V
L1
470u/25V
COUT1
C105
470u/25V
33n
WE
744 841 414
R125
47k
C106
180p
IC1
NCP431
100R
12k
5k1 BC817−25LT1SMD
R115
1k0
R117
D110
Q101
D111
10k
R112
4u7/50V
MMDL914 MMDL914
33k
C2
R111
MMDL914
1n5
C109
5n6
12k
R116
160k
C108
PC817W
D102
+
R122
2
R121
1
3
GND
X1−1
1k0
R106
BC807−25LT1SMD
OK1
4
100k
R104
100k
Q100
330k
R107
GND
R105
AUX
KA5038−BL
X1−2
DC OUTPUT
2
470u/25V
15R
COUT3
1
COUT2
+
C4
+
R7
R120
1/2 VIN
+
pins 2 & 3
connected on PCB
3
+ 19V/3.5A
L3
4
1/2 VIN
NTST30100SG
FB
D2
TR1
Q102
BC817−25LT1SMD
GND
Figure 3. Secondary Control Circuitry
The X2 Capacitor Discharge Principle
The switch Q102 is used to decrease the opto-coupler
LED current in case it is in off-mode when the FB pin is
pulled up by 5 mA current only. More energy is saved at the
secondary side now. The circuitry created by diode D101,
capacitor C107 and resistor R114 forms the secondary
voltage regulator NCP431 dynamic biasing, but it is not used
in this design. It has to stop the biasing of the secondary
voltage regulator NCP431 under the skip mode and save the
power consumption in skip modes and off-modes.
The NCP431 has good dynamic performance so that the
additional bias at normal operation is not needed. Hence this
type of circuitry was not assembled.
The hiccup cycle ends when the output voltage is so small
that the LED current fades away. When the opto-coupler
LED current fades away the FB is no longer pulled down by
closed transistor inside the opto-coupler and FB pin voltage
starts to rise up being pulled up by the internal 5 mA current
source. When the FB pin voltage crosses the 2.2 V level, the
primary controller restarts and recharges the secondary
capacitors tank. This cycling repeats in the hiccup mode. If
any load is connected, the discharge of the output capacitors
tank is faster and after recharge of the output capacitors, the
application enters the regulated mode and keeps the output
voltage at the required level set by the voltage feedback
loop.
This feature saves approximately 16–25 mW of input
power depending on the EMI filter X2 capacitors volume
and it saves the external components count as well. The
discharge feature is ensured via the start-up current source
with a dedicated control circuitry for this function.
The dedicated structure called ac line unplug detector is
used inside the X2 capacitor discharge control circuitry. See
Figure 5 for the block diagram of this structure and Figure 6
for the timing diagram. The basic idea of ac line unplug
detector lies in comparison of the direct sample of the high
voltage obtained via the high voltage sensing structure with
the delayed sample of the high voltage. The delayed signal
is created by the sample & hold structure.
One can ask why such a complicated method is used. Why
is the regular crossing of the voltage level close to zero not
simply detected? See the following picture showing the
rectified ac signal in the power supply loaded by high
impedance.
http://onsemi.com
8
AND9170/D
The additional offset NOS can be measured as the
VHV(hyst) at the HV pin. If the comparator output produces
pulses, it means that the slope of input signal is higher than
the set resolution level and the slope is positive. If the
comparator output produces a low level, it means that the
slope of input signal is lower than the set resolution level or
the slope is negative. The detection timer is used which is
reset by any edge of the comparator output. It means that if
no edge comes before the timer elapses, there is only a dc
signal present or a signal with a small ac ripple at the HV pin.
This type of ac detector detects only the positive slope which
fulfils the requirements for the ac line presence detection.
HV
R1
Figure 4. Full Wave Rectified ac Line Voltage at
High Impedance HV Pin
+
−
Q1
The problem is that the rectified voltage at a high
impedance HV pin never reaches zero level. This situation
is even worse if a small capacitance is present at the HV pin.
The no zero reaching is caused by the floating of the primary
controller common node GND. The floating is caused by the
charging and discharging of the CY1, CY2 and CY3
capacitors. The actual status of charging and discharging
those capacitors forms the actual slope of signal at HV pin.
The comparator used for the comparison of these signals
is without a hysteresis inside. The resolution between the
slopes of the ac signal and dc signal is defined by the
sampling time TSAMPLE and additional internal offset NOS.
These parameters ensure the noise immunity as well.
The additional offset is added to the signal sampled and
divided from HV pin and its analog sum is stored in the C1
storage capacitor. If the voltage level of the HV sensing
structure output crosses this level, the comparator CMP
output signal resets the detection timer which provides the
low level of DC detect signal. It means that ac signal is
present at the HV pin and the X2 discharge sequence is
disabled.
VHV SAMPLE
CMP
Sample & Hold
R2
Nos
Detection Timer
Reset
C1
Lo frq OSC
Out sq
Figure 5. The ac Line Unplug Detector Structure
Used for X2 Capacitor Discharge System
The X2 capacitor discharge feature is enabled in any
controller operation mode to ensure the compliance with the
safety requirement. The detection timer is reused to limit the
time of the discharge phase, which protects the device
against overheating. The discharging process is cyclic and
continues until the ac line is detected again or the voltage
across the X2 capacitor is lower than VHV(min). It is
important to note that it is not allowed to connect the HV
pin to any dc voltage e.g. directly to bulk capacitor. Please
refer to the NCP1244 or NCP1246 datasheets if more details
are needed.
TSAMPLE
VHV(hyst)
time
Comparator
Output
Timer
tDET = 32 ms
Detection timer is
periodically reset
Detection timer counts
DC
Detect
Detection timer
is reset
time
Detection timer is
periodically reset
time
Figure 6. The ac Line Unplug Detector Timing Diagram
http://onsemi.com
9
AND9170/D
The X2 Capacitor Discharge System Capability
I opto +
The time needed to discharge the X2 capacitors in the EMI
filter is very important from the safety point of view.
The safety standards can vary from country to country and
one of the very common ones is to discharge the X2
capacitors bank at least to 50 Vdc in 500 ms. The X2
capacitors are discharged by the HV startup circuitry by
Istart2 current. The discharge process is periodic with the
32 ms detection period and 32 ms discharge period to
prevent the overheating of the device and a fault when the
whole application is plugged into mains again.
The time tdis needed to discharge a certain amount of
capacitance can be calculated by the following formula:
t dis +
C X2 @ DV
+
I start2 @ t dis
V out,min ) RI opto
V out ) RI opto
3
Ǔ
(eq. 20)
*6
(eq. 21)
*6
3
The required no-load power for the secondary circuitry
will be calculated by the energy law. The energy stored in the
output capacitor tank (when it is fully charged to nominal
output voltage) is:
E1 +
2
1
1
C V
+ @ 1.5 @ 10 *3 @ 19 2 + 0.270 J
2 out out
2
(eq. 22)
The rest of energy stored in the output capacitor tank
(when it is discharged to minimum output voltage) is:
E1 +
2
1
1
C V
+ @ 1.5 @ 10 *3 @ 2 2 + 0.003 J (eq. 23)
2 out out,min
2
Thus the required power for charging the output capacitor
tank is:
P sec +
E1 * E2
t hiccup
+
0.270 * 0.003
+ 2.85 mW
93.6
(eq. 24)
This amount of power contributes to input power of the
adapter. Nevertheless it appears at input increased by the
transfer losses. Let us assume the efficiency of 60% for the
transfer from the primary circuitry, thus the contribution of
the secondary circuitry to no-load consumption is 4.8 mW.
Then the estimated total no-load input power is around
19 mW.
Let us analyze the consumption of the whole adapter
again. The adapter using hiccup mode for no-load loading
condition has been analyzed. The consumption of the
secondary control circuitry can be modeled as composition
of the current sink and resistor. The current sink models
consumption of the branch with the opto-coupler LED
which is supplied by the current source formed by the Q101.
The resistor models the consumption of all the resistive
branches in the secondary control. The first branch is formed
by R112, R111, R107 and R105. The second branch is R104
because the drop across D110, D111 and Q100 is neglected
due to the simplicity. The last branch consists of the
feedback divider R120, R121, R125 and R122. All these
branches in parallel give the resistance R = 56.99 kW.
Table 2. SUMMARY OF THE NO-LOAD
CONSUMPTION ANALYSIS FOR THE ADAPTER
USING NCP1246 CONTROLLER
Component
Vout
dc output
Iopto
(eq. 19)
+ 115 mA
2 ) 56.99 @ 10 @ 115 @ 10 Ǔ
@ ln ǒ
+ 93.6 s
19 ) 56.99 @ 10 @ 115 @ 10
Estimated No-Load Mode Input Consumption
in Solution Utilizing NCP1246
Cout
+
t hiccup + * 56.99 @ 10 3 @ 1.5 @ 10 3 @
The minimum voltage to which the X2 capacitors can be
discharged is given by VHV(min) . It is the minimum level for
HV startup current source functionality.
+
1 @ 10 3 ) 5.1 @ 10 3
ǒ
(eq. 18)
DV
0.7 ) 0.7 * 0.7
t hiccup + * RC out ln
DV means the difference between the mains maximum
peak voltage and residual voltage at X2 capacitors bank
allowed by safety standard. The maximum allowed
capacitance, which could be discharged in the specified time
period, can be calculated by the following formula:
C X2 +
R 115 ) R 117
The hiccup mode period can be, this time, calculated by
the following formula:
(eq. 17)
I start2
V D111 ) V D110 * V be,Q101
Figure 7. Simplified Diagram of the Output for
the Consumption Analysis
The Iopto sink current is calculated by the following
formula:
PleakVAR [mW]
EMI Filter - X2 Capacitors
2 x Ploss,X2 [mW]
EMI Filter - L2 Common Choke
Ploss,L2 [mW]
X2 Discharge Branch
Pdisch [mW]
Bulk Capacitor DC Leakage Loss
PleakBulk [mW]
Q1 Leakage Loss
PleakQ1 [mW]
Primary Controller - HV Bias
PHVbias [mW]
Primary Controller - HV Sense
PHVsense [mW]
1.76
Primary Controller - Vcc
Consumption
PPC [mW]
5.17
Secondary Control
Psec [mW]
2.85
Transfer Efficiency
h [%]
60
Transfer to Primary
Pprim [mW]
4.8
Total No-Load Input Power
Pin [mW]
http://onsemi.com
10
Consumption
Varistor
0.53
3.32
0.025
0
1
0.33
2.1
19.0
AND9170/D
The total no-load input power calculated value is 19 mW.
The previous solution utilizing NCP1236 flyback controller
has no-load input power of 110 mW. The major power
saving contributors are:
• The X2 Discharge Resistor Branch was Removed
• The Hiccup Mode at Output Stage when the Adapter is
Unloaded was Implemented
• The Off-mode Inside Primary Controller was
Implemented
defined by the YOKOGAWA WT210 power meter
specification is ±61% when we measure no-load input
power in range of 20 mW. The results of such a direct
no-load input power measurement vary quite a lot and
provide a wrong result in the hiccup mode because the
output capacitor charging bursts are hardly measurable that
way. In addition, the measurement range of the current has
to be increased to measure the correct active power value.
A more precise method for the hiccup no-load mode uses
an integration approach. The YOKOGAWA WT210 power
meter allows measuring consumed energy in the no-load
mode using the long integration time. The usual approach is
to start the measured adapter or the power supply first, let it
warm up approximately for one hour and then start the
measurement. The set integration time is from 20 minutes to
10 hours. This method provides more repeatable results;
with the spread of measured values up to ±2 mW. This is one
of the generally used and accepted ways how to evaluate
very low value of no-load active input power. The best way
how to evaluate the no-load input power consumption in
a hiccup mode could be the dynamic and fast change of
current range. This feature can ensure that the wattmeter
measures precisely when the controller is in off-mode and
the power meter is not overloaded during the bursts.
Let us analyze the precision of power meter
YOKOGAWA WT210 specified by the manufacturer.
Power Meter YOKOGAWA WT210 Analysis of
Measurement Precision
The efficiency and no-load input power consumption
were measured by the YOKOGAWA WT210 power meter.
However, a significant error appeared during the no-load
input power measurement due to high input reactive power
of the input EMC filter (3.32 VAr). This effect can cause
a significant error at read value of no-load input power. How
significant can such an error be?
The YOKOGAWA WT210 Power Meter Specification
Declares:
Active Power Accuracy:
• ±(0.1% rdg + 0.1% rng) for 45 Hz ≤ f ≤ 66 Hz
Influence of Power Factor PF:
• ±0.2% of VA for 45 Hz ≤ f ≤ 66 Hz when PF = 0
• ±(tanF × influence when PF = 0)% rdg when
Accuracy of Integration:
• ±(power (current) accuracy + 0.1% of reading)
0 < PF < 1
Accuracy fo Timer:
• ±0.02%
Where F is the phase angle of the voltage and current.
Let us assume the voltage range setting of 300 V and the
current range setting of 20 mA. It gives the power range of
6 W. Assuming that the read value will be around 30 mW,
the error given by the reading precision is negligible.
The next analysis takes into account only the measurement
range precision and influence of the power factor.
It is necessary to increase the current range to 2 A to catch
the bursts of the input consumption when the output
capacitor tank is being recharged in the hiccup mode.
The power range increases to 600 W as well and the power
accuracy is now 600 mW. This number is 30 times higher
than the measured value, thus the measured value can be
affected by a significant error. The maximum possible value
of the error can exceed the regulators’ requirements. It
means that the measurement which was performed by the
world-wide standard and used the power meter
YOKOGAWA WT210 has only an informative value.
The results can significantly differ from one power meter to
another.
Active Power Accuracy for Given Example:
• ±6 mW for 45 Hz ≤ f ≤ 66 Hz
Influence of Power Factor PF:
• ±0.2% of 3.32 VAr means ±6.64 mW
Then, the maximum total error is 12.2 mW in a 6 W
measurement range if the no-load input power is directly
measured. The relative precision of such a measurement
http://onsemi.com
11
AND9170/D
Efficiency and No-Load Consumption
Notebook Adapter Efficiency
95.0
Table 3. EFFICIENCY VS. OUTPUT POWER
AND INPUT LINE VOLTAGE
90.0
85.0
Efficiency (%)
Vin = 115 Vac/60 Hz
80.0
Pout/Poutmax
[%]
Pout
[W]
Pin
[W]
Efficiency
[%]
100.7
65.43
73.10
89.51
70.0
75.5
49.05
54.68
89.71
65.0
50.1
32.58
36.31
89.74
60.0
25.7
16.69
18.63
89.57
10.6
6.90
7.74
89.19
5.4
3.52
4.00
89.12
1.5
0.97
1.15
83.97
0.7
0.48
0.60
80.19
0.0
Pout
[W]
Pin
[W]
Efficiency
[%]
100.7
65.43
71.20
91.89
75.4
49.04
54.17
90.53
50.1
32.57
36.14
90.13
25.7
16.69
28.58
89.81
10.6
6.91
7.75
89.11
5.4
3.54
4.02
88.03
1.5
0.97
1.16
83.12
0.7
0.49
0.63
77.44
Average Efficiency
No-Load Input Power
115 Vac/60 Hz
230 Vac/50 Hz
89.6%
90.6%
8.41 mW
16.22 mW
20.0
30.0
40.0
Efficiency @ 115 V/60 Hz
50.0
60.0
70.0
80.0
90.0
100.0
Efficiency @ 230 V/50 Hz
Figure 8. Efficiency vs. Output Power and Input
Line Voltage
The observed “waves” at the efficiency curves in the range
from 25% of loading are caused by the fact that the primary
switch is turned on in case the voltage values at the drain
node are different. If the controller switches in the valley of
the drain voltage in the DCM mode, the efficiency of the
adapter is higher. When the controller switches in the peak,
the total efficiency decreases in opposite case.
The High Voltage Pin Sensitivity to Noise
The high voltage sensing pin HV has a big internal
impedance to reach the extremely low input power
consumption while the power supply is in idle mode.
The input impedance of the HV pin is typically 30 MW and
the typical leakage current 10 mA is present as well. Such
high impedance creates a small power loss and helps to
decrease no-load input power. On the other hand, the high
impedance pin is a disadvantage. It has high sensitivity to
coupled noise. The noise can be coupled from the power
stage or from the mains. The noise from the power stage is
mainly coupled by the capacitive way. The noise from the
mains comes through the unmatched EMI filter. There is
a question, though, why the EMI filter is unmatched?
The EMI filter is usually designed/selected to decouple
the switching frequency current noise and its higher
harmonic components from the power stage to the mains.
Every filter works well if it is properly matched at its both
ports. The EMI filters in power supplies are matched well
when the supply current flows through them. These filters
are unmatched when its output connected to bridge rectifier
is unloaded, which simply means that the diodes are not
conducting any current. The noise from the mains can freely
come through the filter this time.
Table 4. AVERAGE EFFICIENCY AND NO-LOAD
INPUT POWER
Input Line
10.0
Pout/Poutmax (%)
Vin = 230 Vac/50 Hz
Pout/Poutmax
[%]
75.0
The total input power is lower than the goal 30 mW.
The difference between the calculated value and the
measured value is 2.78 mW at high line, which means 17.1%
from the measured value. The results are adequately
similar), if all effects affecting the measurement precision
are considered. The extremely low no-load input power is
obtained thanks to an output voltage hiccup mode when
there is no-load connected. The loading current borderline
values to detect the no-load condition are the following:
• 3.1 mA Going to Hiccup Mode
• 36.9 mA Leaving the Hiccup Mode
http://onsemi.com
12
AND9170/D
voltage at the HV pin. The HV pin is connected via diodes
D107, D108 to an unmatched EMC filter. It has an open
output. All impedances connected to the HV pin are high and
the amount of the coupled noise is the highest.
The comparator output in the ac line detection system goes
high and resets the peak detector when the instantaneous
voltage value at the HV pin is higher than the HV sampled
value. The watch dog signal generates the false maximum of
the mains after 2 sample clocks. Consequently, the false
overpower compensating current starts to be sourced out of
the CS pin. Its value usually drops. See Figure 12 for your
reference. The undesirable change of the overpower
compensating current greatly depends on the phase shift
between the sample clock and the HV pin voltage
ripple/noise and the amount of the coupled noise.
The easiest way to decrease the noise coupling factor to
the HV pin is to add the parallel decoupling capacitor. Such
a capacitor is also increasing the surge immunity when it is
a part of the T topology damping structure. The T topology
filter damps the surge pulse by the serial and parallel
branches and protects the HV pin structure against the high
peak current from the decoupling capacitor when the
breakdown voltage appears on it.
Overpower compensating current can decrease or even
drop during the falling slope of voltage at the HV pin when
the noise coupling is strong and the T topology filter is not
used. The application will run for short periods without
overpower compensation in such cases. The consequences
of such a false incorrect overpower compensation were
evaluated:
• The fault timer duration fluctuation was observed up to
5%
• Missing overpower compensation could cause
transformer core saturation and a primary peak current
increase in case of a tight design of the transformer.
CSstop protection should stop the application in such
a case. Please see [1], [2] for more details about CSstop
protection
• The overpower compensating current causes output
voltage overshoots/undershoots up to 50 mV. These
overshoots/undershoots are heavily dependent on the
input voltage and the transformer primary inductance
• The application always securely stops in case of
overload thanks to the implementation of CSstop
protection
The excessive noise coupled to the HV pin can cause the
overpower compensation system to partially fail. The partial
fail means that the overpower compensating current sourced
by the CS pin will not be in line with the current peak voltage
of the mains. A 3-bit A/D converter with the peak detector
senses the ac input, and its output is periodically sampled
and reset in order to follow closely the input voltage
variations. The sample and reset events are given by the
output from the ac line unplug detector. It can simply
provide the information that the peak of input voltage
passes. It will pass after the positive slope of input voltage
has ceased. The sensed HV pin voltage peak value is
validated when no HV edges from the comparator are
present after the last falling edge during 2 sample clocks.
Peak detector is reset by the first edge of the HV comparator.
See Figure 11 and device datasheet [1] for details.
Figure 9. The Noise Coupled to HV Pin when the
Diodes in Bridge Rectifier are not Conducting.
EMI Filter is Unmatched.
Attention: The effect of the noise coupled to the HV pin
described above is greatly dependant on the
NCP1244/46 application schematic,
PCB layout pattern, and overall application
configurations. This effect was observed only
in application with a stronger coupling of the
noise to the HV pin.
Figure 10. The Noise Coupled to HV Pin when
the Diodes in Bridge Rectifier are Conducting.
EMI Filter is Matched as Works Well.
The coupled noise to the HV pin can affect the overpower
compensating system when its instantaneous value is higher
than the sampled value in the ac detector system. The worst
case that creates such an effect is the falling slope of the
http://onsemi.com
13
AND9170/D
VHV SAMPLE
TSAMPLE
VHV(hyst)
1st HV edge resets
the watch dog and
starts the peak
detection of HV pin
signal
Comparator
Output
time
time
Sample
Clock
time
Watch Dog
Signal
2nd sample clock
pulse after last HV
edge initiates the
watch dog signal
2nd sample clock
pulse after last HV
edge initiates the
watch dog signal
time
Reset
Reset
Peak
Detector
Sample
Sample
time
IOPC
time
Figure 11. Overpower Compensation System Timing Diagram
http://onsemi.com
14
AND9170/D
VHV SAMPLE
Peak of the ripple
higher than
sampled value
starts incorrect
IOPC generation
TSAMPLE
VHV(hyst)
1st HV edge resets
the watch dog and
starts the peak
detection of HV pin
signal
Comparator
Output
time
time
Sample
Clock
time
Watch Dog
Signal
Peak
Detector
2nd sample clock
pulse after last HV
edge initiates the
watch dog signal
2nd sample clock
pulse after last HV
edge initiates the
watch dog signal
2nd sample clock
pulse after last HV
edge initiates the
watch dog signal
Reset
time
Reset
Reset
Sample
Sample
time
IOPC
time
Figure 12. Overpower Compensation System is Affected by the Noise Coupled to the HV Pin
http://onsemi.com
15
L
F1
X2−2
R5
1
R6
NU
WE
744 841 330
2
100n
B72210P2301K101
4
L4
3
CX2
L2
2n2
2n2
1.5A
CY2
100n
X2−1
CX1
EPCOS
B82734
CY3
U$3
R101
2k7
NTC 100n
330k
C100
D103
D104
VCC 6
DRV 5
HV 8
C102
NU
1n0
680
R123
NCP1246B65
3 CS
4 GND
1 LATCH
2 FB
IC100
100p/500V
C5
R100
2k7
C101
MMSZ15
D109
MRA4007T3G
100uF/400V
CB1
33k
MRA4007T3G
MRA4007T3G
D108
R4
D100
FB
D1
1N4007
+
22R
100n 47u/50V
C103 C1
R119
R124
10k
2R2 MMSD4148
D112
R126
2R2 MMSD4148
R103
R108
MRA4007T3G
D107
R102
330k
R3
1R
R109
5n6/500V
TR1
AUX
2
MRA4007T3G
PC817W
R1
4M7
CY1
2n2
3
1
4
C107
MMDL914
D102
GND NU
NU
D101
GND
NTST30100SG
FB
1n2/500V
C4
COUT2
R7
470u/25V
15R
MRA4007T3G
OK1
KA5038−BL
1/2 VIN
pins 2 & 3
connected on PCB
1/2 VIN
Q1
SPP11N60C3
FB
2R2
1R
D114
330k
R2
1R
R113
1R
R118
C3
4u7/50V
C2
NU
MRA4007T3G
MRA4007T3G
N
D113
L3
+
COUT1
470u/25V 470u/25V
2u2
COUT3
Q101
1k0
Q102
BC817−25LT1SMD
33n
C105
4
IC1
NCP431
5n6
47k
C106 180p
GND
1n5
C108
X1−1
GND
X1−2
DC OUTPUT
+ 19V/3.5A
WE
744 841 414
L1
R116 C109
1
D105
D106
P$1
P$1
D2
GND
GND
23
R122
R125
+
R114
+
R105
+
R107
R111
100k
Q100
330k
R104
33k
10k
MMDL914MMDL914
R112
BC807−25LT1SMD
100k
D111 D110
C104
NU
R106
R110
5k1 BC817−25LT1SMDNU
R117R1151k0
100R
160k
12k
16
12k
http://onsemi.com
R120 R121
HV Capacitor for
Surge and Noise
Immunity Increase
AND9170/D
Figure 13. Recommended Schematic of the Notebook Adapter Using NCP1246
with Optimized Surge and Noise Immunity
1XTSTPOINT
AND9170/D
Performance of the Designed 65 W Notebook Adapter
frequency foldback, pulse skipping, transient load response,
stability in CCM, frequency jitter, overload protection, X2
capacitor discharge feature, etc. under both 115 V and 230 V
input conditions as appropriate.
The following figures demonstrate the operation of the
converter under different operating conditions and highlight
various features such as a transition from CCM to DCM,
Notebook Adapter Line Regulation
19.04
19.06
19.04
19.04
19.03
VOUT (V)
VOUT (V)
Notebook Adapter Load Regulation
19.08
19.02
19.00
19.03
19.02
18.98
19.02
18.96
19.01
18.94
19.01
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
80
100
120
IOUT (A)
Vout @ 115 /60 Hz
140
160
180
200
220
240
260
280
VINAC (V)
Vout @ 230 V/50 Hz
Vout @ Iout 2.5 A
Vout @ Iout 3.0 A
Vout @ Iout 3.5 A
Figure 14. Load Regulation for Low and High
Input Line
Figure 15. Line Regulation for High Output Loads
Figure 16. CCM Operation at Full Load (3.5 A)
and 115 V/60 Hz Input
Figure 17. Ripple at Bulk Capacitor at Full Load
(3.5 A) and 115 V/60 Hz Input Supply
Figure 18. No Subharmonic Oscillations Appear
under Full Load (3.5 A) and CCM Operation,
with D > 50%, 110 V/45 Hz Input
Figure 19. The DCM Mode Starts at 2.27 A of Load
Current at 115 V/60 Hz Input
http://onsemi.com
17
AND9170/D
Figure 20. The Frequency Foldback Mode Starts at
1.60 A of Load Current at 115 V/60 Hz Input
Figure 21. The Lowest Frequency at 0.65 A of Load
Current at 115 V/60 Hz Input − Frequency Foldback
is Finished
Figure 22. The Skip Mode at 137 mA of Load
Current at 115 V/60 Hz Input
Figure 23. The Hiccup Mode and Output Voltage
Waveform without any Load at Output and
115 V/60 Hz Input
Figure 24. The Recharge Burst of DRV Pulses in
the Hiccup Mode without any Load at Output and
115 V/60 Hz Input
Figure 25. CCM/DCM Borderline Operation at Full
Load (3.5 A) and 230 V/50 Hz Input
http://onsemi.com
18
AND9170/D
Figure 26. The Frequency Foldback Mode Starts at
2.62 A of Load Current at 230 V/50 Hz Input
Figure 27. The Lowest Frequency at 0.70 A of Load
Current at 230 V/50 Hz Input − Frequency Foldback
is Finished
Figure 28. The Skip Mode at 137 mA of Load
Current at 230 V/50 Hz Input
Figure 29. The Hiccup Mode and Output Voltage
Waveform without any Load at Output and
230 V/50 Hz Input
Figure 30. The Recharge Burst of DRV Pulses in
the Hiccup Mode without any Load at Output and
230 V/50 Hz Input
Figure 31. The Load Transient Step from 20% of
Load to 100% of Load at 115 V/60 Hz Input
http://onsemi.com
19
AND9170/D
Figure 32. The Load Transient Step from 100% of
Load to 20% of Load at 115 V/60 Hz Input
Figure 33. The Overcurrent Protection Timer
Duration is 121 ms when the Adapter was
Overloaded from 3.5 A to 6 A at 115 V/60 Hz Input.
No OPP is Observable at these Conditions
Figure 34. The Overcurrent Protection Timer Duration
is 121 ms when the Adapter was Overloaded from
3.5 A to 7 A at 230 V/50 Hz Input. The OPP Current is
Observable as a Shift of Minimum Levels between the
Signal Vsense from Rsense and the Signal at the CS Pin
Figure 35. Adapter Start Up at 115 V/60 Hz Input
and 1 A Output Current Load
Figure 36. Brown-out Protection Reaction when
the rms ac Input Voltage Drops Down from 80 V to
70 V under 1 A Output Current Loading
Figure 37. The Soft Start at 115 V/60 Hz Input with
3.5 A Output Current Loading
http://onsemi.com
20
AND9170/D
Figure 39. The 2 mF X2 Capacitors Bank was
Discharged after Application Unplug from
230 V/50 Hz Mains (Extra Added X2 Capacitors to
Demonstrate System Feature)
Figure 38. The X2 Capacitors Bank was
Discharged after Application Unplug from
230 V/50 Hz Mains
Figure 40. The X2 Discharge Feature Works Properly
(is not False Activated) while the Application is
Supplied by Cheap UPS, Using Square Wave
Figure 41. Frequency Deviation of the Frequency
Jittering
Figure 43. Detail of the Output Voltage Ripple and
Voltage across Secondary Winding of Transformer
at 115 V/60 Hz Input with 3.5 A Output Current
Loading (the Ringing is Caused by the Secondary
Diode Reverse Recovery)
Figure 42. Ripple Observable at Bulk Capacitor at
85 V/50 Hz Input and 3.5 A Continuous Output
Loading Current
http://onsemi.com
21
AND9170/D
Conducted Emission Quasi
90
−peak dB
m V (Domestic)
The obtained average efficiency is 89.6% for the low line
conditions (115 V/60 Hz) and 90.6% at high line conditions
(230 V/50 Hz). This excellent result provides enough
margins to fulfill the EPS 2.0 specification of 87% for the
average efficiency. The high efficiency is obtained thanks to
the low forward drop diode NSTS30100SG from
ON Semiconductor, transformer KA5038-BL from
COILCRAFT with dedicated design for this application and
the low loss EMI filters.
LIMIT
80
RS_FSVR_Quasi Peak CISPR
Level (dB mV)
70
60
50
40
30
20
Thanks
10
100000
1000000
10000000
100000000
Thanks to the COILCRAFT Company for providing the
samples, custom design of the flyback transformer used in
this board and their support.
Another thank belongs to the EPCOS Company for
providing the samples of their components used in this
design.
Frequency (Hz)
Figure 44. Harmonic Components of the Input
Current at 230 V/50 Hz Input and 3.5 A
Continuous Output Loading Current
Results Summary
Caution
The goal of this design is to show the extremely no-load
input power solution which is cost effective and whose
measured value is always below 20 mW. The frequency
foldback and frozen current setpoint features offer the
advantage of designing power supplies whose efficiency at
light-loads are above 80%. Measured efficiency at 0.5 W of
output power is always higher than 75%. Meeting these
specs will enable our customers to meet the latest
ENERGY STAR® requirements.
The designed wide input range adapter fulfils the
requirement of having no-load input power lower than
30 mW over the wide input voltage range. While the
complete design of the adapter must focus on achieving the
low no-load input power, the controller facilitates this result
by a frequency foldback and off-mode features. The family
of controllers NCP1244/46 allows building cost effective,
easy-to-design and extremely low no-load input power
consumption power supplies.
This demo board is intended for demonstration and
evaluation purposes only.
References
[1] NCP1244A/B Datasheet
[2] NCP1246A/B Datasheet
[3] Christophe P. Basso: Switch-Mode Power Supplies,
SPICE Simulations and Practical Designs,
McGraw-Hill, new York, 2008
[4] Dr. Ray Ridley: A New Continuous-Time Model for
Current-Mode Control,
(http://www.ridleyengineering.com/books.html)
[5] Application Note AND8461/D
[6] Application Note AN1679/D
[7] Application Note AND8393/D
[8] Application Note AND8154/D
Figure 45. Photograph of the Designed Prototype (Real Dimensions are 150 y 51 mm)
http://onsemi.com
22
AND9170/D
1
12
2
Pb
2
4
1
1
12
6
7
4
4
12
3
2
1
3
Figure 46. Component Placement on the Top Side (Top View)
Pb
Figure 47. Component Placement on the Bottom Side (Bottom View)
Figure 48. Bottom Side PCB Pattern (Bottom View)
http://onsemi.com
23
3
AND9170/D
Table 5. BILL OF MATERIALS
Substitution
Allowed
Designator
Qty.
Description
Value
Tolerance
Footprint
Manufacturer
Manufacturer’s
Part Number
C1
1
Electrolytic
Capacitor
47 mF/50 V
20%
Radial
Koshin
KLH-050V470ME110
Yes
C2
1
Electrolytic
Capacitor
4.7 mF/50 V
20%
Radial
Koshin
KLH-50V4U7
Yes
C3
1
Ceramic
Capacitor
5.6 nF/630 V
5%
Radial
TDK Corporation
FK20C0G2J562J
Yes
C4
1
Ceramic
Capacitor
1.2 nF/630 V
5%
Radial
TDK Corporation
FK26C0G2J122J
Yes
C100, C103
2
Ceramic
Capacitor
100 nF
10%
0805
Kemet
C0805C104K5RAC
Yes
C101
1
Ceramic
Capacitor
1.0 nF
10%
0805
Kemet
C0805C102K5RAC
Yes
C102, C107
2
Ceramic
Capacitor
NU
−
0805
−
−
−
C105
1
Ceramic
Capacitor
33 nF
10%
0805
Kemet
C0805C333K5RAC
Yes
C106
1
Ceramic
Capacitor
180 pF
10%
0805
Kemet
C0805C181K5RAC
Yes
C109
1
Ceramic
Capacitor
5.6 nF
10%
0805
Kemet
C0805C560K5GAC
Yes
CB1
1
Bulk Capacitor
100 mF/400 V
20%
Through Hole
United Chemi-Con
EKXG401ELL101MMN3S
Yes
COUT1,
COUT2,
COUT3
3
Electrolytic
Capacitor
470 mF/25 V
20%
Radial
Panasonic − ECG
ECA-1EHG471
Yes
CX1, CX2
2
Suppression
Film
Capacitors
100 nF
10%
Through Hole
Epcos
B32922C3104K
No
CY1, CY2,
CY3
3
Ceramic
Capacitor
2.2 nF/X1/Y1
20%
Disc − Radial
Murata
DE1E3KX222MA5B
Yes
D1
1
Standard
Recovery
Rectifier
1N4007
−
DO41-10B
ON Semiconductor
1N4007G
No
D2
1
Diode
Schottky
100 V 30 A
NTST30100SG
−
TO220
ON Semiconductor
NTST30100SG
No
D100, D112
2
Diode
MMSD4148
−
SOD123
ON Semiconductor
MMSD4148T3G
No
D101
1
Diode
NU
−
SOD323-2
−
−
−
D102, D110,
D111
4
Diode
MMDL914T1G
−
SOD323-2
ON Semiconductor
MMDL914T1G
No
D103, D104,
D105, D106,
D107, D108,
D113, D114
8
Standard
Recovery
Rectifier
MRA4007T3G
−
SMA
ON Semiconductor
MRA4007T3G
No
D109
1
Zener Diode
MMSZ15
5%
SOD123
ON Semiconductor
MMSZ15T3G
No
F1
1
Fuse
(MST ser.)
1.6 A
−
Through Hole
Schurter Inc
0034.6617
Yes
IC1
1
Programmable
Precision
Reference
NCP431
−
TO-92
ON Semiconductor
NCP431AVLPRAG
No
IC100
1
SMPS
Controller
NCP1246B65
−
SOIC-08
ON Semiconductor
NCP1246B65
No
L1
1
Inductor
744 841 414
−
744 841 414
Würth Elektronik
744 841 414
No
L2
1
Inductor
B82734L
−
B82734L
Epcos
B82734W2202B030
No
L3
1
Inductor
2.2 mH
10%
RFB0807
CoilCraft
RFB0807-2R2L
No
L4
1
Inductor
744 841 330
−
744 841 330
Würth Elektronik
744 841 330
No
−
2
EMI
Suppression
Ferrite Bead
74270073
−
74270073
Würth Elektronik
74270073
Yes
http://onsemi.com
24
AND9170/D
Table 5. BILL OF MATERIALS (continued)
Substitution
Allowed
Designator
Qty.
Description
Value
Tolerance
Footprint
Manufacturer
Manufacturer’s
Part Number
NTC
1
Sensing NTC
Thermistor
330 kW
5%
Disc − Radial
Vishay
NTCLE100E3334JB0
Yes
OK1
1
Opto-coupler
PC817
−
4-DIP
Sharp
PC817X2J000F
Yes
Q1
1
N MOSFET
Transistor
SPP11N60C3
−
TO220
Infineon
SPP11N60C3
Yes
Q100
1
PNP Bipolar
Transistor
BC807-25LT1G
−
SOT-23
ON Semiconductor
BC807-25LT1G
Yes
Q101, Q102
2
NPN Bipolar
Transistor
BC817-25LT1G
−
SOT-23
ON Semiconductor
BC817-25LT1G
Yes
R1
1
Resistor
Through Hole,
High Voltage
4.7 MW
5%
Axial Lead
Welwyn
VRW37-4M7JI
Yes
R2
1
Resistor
2.2 W
1%
0207
Vishay
MBB02070C2208FRP00
Yes
R3, R4
2
Resistor
330 kW
1%
0207
Vishay
HVR2500003303FR500
Yes
R5
1
Surge
Protecting
Varistor
B72210P2301K
101
20%
Disc − Radial
Epcos
B72210P2301K101
No
R6
1
NTC
Thermistor
Wire Strap
−
Disc − Radial
−
−
Yes
R7
1
Resistor
15 W
1%
0207
Vishay
MRS25000C1509FRP00
Yes
R100, R101
2
Resistor SMD
2.7 kW
1%
1206
Rohm
MCR18EZHF2701
Yes
R102, R111
2
Resistor SMD
33 kW
1%
0805
Rohm
MCR10EZPF3302
Yes
R103, R126
2
Resistor SMD
2.2 W
1%
0805
Rohm
MCR10EZHFL2R20
Yes
R104, R105
2
Resistor SMD
100 kW
1%
0805
Rohm
MCR10EZPF1003
Yes
R106, R115
2
Resistor SMD
1.0 kW
1%
0805
Rohm
MCR10EZPF1001
Yes
R107
1
Resistor SMD
330 kW
1%
0805
Rohm
MCR10EZPF3303
Yes
R108, R109,
R113, R118
4
Resistor SMD
1.0 W
1%
1206
Rohm
MCR18EZHFL1R00
Yes
R110,
R114
2
Resistor SMD
NU
−
0805
−
−
−
R112, R124
2
Resistor SMD
10 kW
1%
0805
Rohm
MCR10EZPF1002
Yes
R116
1
Resistor SMD
5.6 kW
1%
0805
Rohm
MCR10EZPF5601
Yes
R117
1
Resistor SMD
5.1 kW
1%
0805
Rohm
MCR10EZPF5101
Yes
R119
1
Resistor SMD
22 W
1%
0805
Rohm
MCR10EZPF22R0
Yes
R120, R121
2
Resistor SMD
12 kW
1%
0805
Rohm
MCR10EZPF1202
Yes
R122
1
Resistor SMD
100 W
1%
0805
Rohm
MCR10EZPF1000
Yes
R123
1
Resistor SMD
680 W
1%
0805
Rohm
MCR10EZPF6800
Yes
R125
1
Resistor SMD
160 kW
1%
0805
Rohm
MCR10EZPF1603
Yes
TR1
1
Transformer
KA5038-AL
−
KA5038-AL
CoilCraft
KA5037-AL
No
X1
1
Terminal
Block, 2 Way
CTB5000/2
−
W237-102
Cadem El.
CTB5000/2
Yes
X2
1
Terminal
Block, 3 Way
CTB5000/3
−
W237-113
Cadem El.
CTB5000/3
Yes
http://onsemi.com
25
AND9170/D
ENERGY STAR and the ENERGY STAR mark are registered U.S. Marks.
Ultrabook is a trademark of Intel Corporation in the U.S. and/or other countries.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable
copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
http://onsemi.com
26
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
AND9170/D