Si3456BDV Vishay Siliconix N-Channel 30-V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) 30 RDS(on) (Ω) ID (A) 0.035 at VGS = 10 V 6.0 0.052 at VGS = 4.5 V 4.9 • Halogen free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • 100 % Rg Tested • Compliant to RoHS Directive 2002/95/EC TSOP-6 Top View 3 mm 1 6 2 5 3 4 (1, 2, 5, 6) D (3) G 2.85 mm (4) S Ordering Information: Si3456BDV-T1-E3 (Lead (Pb)-free) Si3456BDV-T1-GE3 (Lead (Pb)-free and Halogen-free) Marking Code: 6Bxxx N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol 5s Steady State Drain-Source Voltage VDS 30 Gate-Source Voltage VGS ± 20 Continuous Drain Current (TJ = 150 °C)a TA = 25 °C TA = 70 °C Continuous Source Current (Diode Conduction)a IS TA = 25 °C TA = 70 °C PD 6.0 4.5 3.6 ± 30 1.7 0.9 2.0 1.1 1.3 0.7 TJ, Tstg Operating Junction and Storage Temperature Range V 4.8 IDM Pulsed Drain Current Maximum Power Dissipationa ID Unit - 55 to 150 A W °C THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambienta Maximum Junction-to-Foot (Drain) Symbol t≤5s Steady State Steady State RthJA RthJF Typical Maximum 55 62.5 92 110 28 40 Unit °C/W Notes: a. Surface Mounted on 1" x 1" FR4 board. Document Number: 72544 S09-0530-Rev. D, 06-Apr-09 www.vishay.com 1 Si3456BDV Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Symbol Test Conditions Min. 1.0 Typ. Max. Unit Static VGS(th) VDS = VGS, ID = 250 µA 3.0 V Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 20 V ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 30 V, VGS = 0 V 1 VDS = 30 V, VGS = 0 V, TJ = 55 °C 5 On-State Drain Currenta ID(on) Gate Threshold Voltage Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltage a VDS ≥ 5 V, VGS = 10 V RDS(on) µA 30 A VGS = 10 V, ID = 6 A 0.028 0.035 VGS = 4.5 V, ID = 4.9 A 0.041 0.052 gfs VDS = 15 V, ID = 6 A 12 VSD IS = 1.7 A, VGS = 0 V 0.8 1.2 8.6 13 Ω S V Dynamicb Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg VDS = 15 V, VGS = 10 V, ID = 6 A 1.5 f = 1 MHz 1.4 td(on) Turn-On Delay Time VDD = 15 V, RL = 15 Ω ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω tr Rise Time td(off) Turn-Off Delay Time Fall Time tf Source-Drain Reverse Recovery Time trr nC 1.8 IF = 1.7 A, dI/dt = 100 A/µs 2.8 4.8 10 15 15 25 25 40 10 15 20 40 Ω ns Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 40 40 TC = - 55 °C VGS = 10 V thru 6 V 35 35 5V 25 °C 30 I D - Drain Current (A) I D - Drain Current (A) 30 25 20 4V 15 25 125 °C 20 15 10 10 5 5 3V 0 0 0 1 2 3 4 VDS - Drain-to-Source Voltage (V) Output Characteristics www.vishay.com 2 5 0 1 2 3 4 5 6 VGS - Gate-to-Source Voltage (V) Transfer Characteristics Document Number: 72544 S09-0530-Rev. D, 06-Apr-09 Si3456BDV Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.10 800 600 C - Capacitance (pF) R DS(on) - On-Resistance (Ω) 700 0.08 0.06 VGS = 4.5 V 0.04 VGS = 10 V Ciss 500 400 300 200 Coss 0.02 100 Crss 0.00 0 0 5 10 15 20 25 30 35 40 0 15 20 25 I D - Drain Current (A) VDS - Drain-to-Source Voltage (V) Capacitance 30 1.6 VGS = 10 V ID = 6 A VDS = 15 V ID = 6 A 1.4 8 RDS(on) - On-Resistance (Normalized) VGS - Gate-to-Source Voltage (V) 10 On-Resistance vs. Drain Current 10 6 4 1.2 1.0 0.8 2 0.6 - 50 0 0 2 4 6 8 10 - 25 0 25 50 75 100 125 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature 40 150 0.10 R DS(on) - On-Resistance (Ω) I S - Source Current (A) 5 TJ = 150 °C 10 TJ = 25 °C 1 0.08 0.06 ID = 6 A 0.04 0.02 0.00 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 2 4 6 8 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage Document Number: 72544 S09-0530-Rev. D, 06-Apr-09 10 www.vishay.com 3 Si3456BDV Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.4 50 0.2 40 0.0 Power (W) VGS(th) Variance (V) ID = 250 µA - 0.2 30 20 - 0.4 10 - 0.6 - 0.8 - 50 - 25 0 25 50 75 100 125 0 10- 3 150 10- 2 10- 1 1 10 TJ - Temperature (°C) Time (s) Threshold Voltage Single Pulse Power 100 600 100 Limited by RDS(on)* IDM Limited I D - Drain Current (A) 10 1 P(t) = 0.0001 s P(t) = 0.001 s ID(on) Limited P(t) = 0.01 s 0.1 TA = 25 °C Single Pulse BVDSS Limited 0.01 0.1 P(t) = 0.1 s P(t) = 1 s P(t) = 10 s DC 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = RthJA = 92 °C/W 3. TJM - TA = PDMZthJA(t) Single Pulse 0.01 10- 4 10- 3 4. Surface Mounted 10- 2 10- 1 1 10 100 600 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Ambient www.vishay.com 4 Document Number: 72544 S09-0530-Rev. D, 06-Apr-09 Si3456BDV Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10- 4 10- 3 10- 2 10-1 1 10 Square Wave Pulse Duration (s) Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72544. Document Number: 72544 S09-0530-Rev. D, 06-Apr-09 www.vishay.com 5 Package Information Vishay Siliconix TSOP: 5/6−LEAD JEDEC Part Number: MO-193C e1 e1 5 4 6 E1 1 2 5 4 E E1 1 3 2 3 -B- e b E -B- e 0.15 M C B A 5-LEAD TSOP b 0.15 M C B A 6-LEAD TSOP 4x 1 -A- D 0.17 Ref c R R A2 A L2 Gauge Plane Seating Plane Seating Plane 0.08 C L A1 -C- (L1) 4x 1 MILLIMETERS Dim A A1 A2 b c D E E1 e e1 L L1 L2 R Min Nom Max Min Nom Max 0.91 - 1.10 0.036 - 0.043 0.01 - 0.10 0.0004 - 0.004 0.90 - 1.00 0.035 0.038 0.039 0.30 0.32 0.45 0.012 0.013 0.018 0.10 0.15 0.20 0.004 0.006 0.008 2.95 3.05 3.10 0.116 0.120 0.122 2.70 2.85 2.98 0.106 0.112 0.117 1.55 1.65 1.70 0.061 0.065 0.067 0.95 BSC 0.0374 BSC 1.80 1.90 2.00 0.071 0.075 0.079 0.32 - 0.50 0.012 - 0.020 0.60 Ref 0.024 Ref 0.25 BSC 0.010 BSC 0.10 - - 0.004 - - 0 4 8 0 4 8 7 Nom 1 ECN: C-06593-Rev. I, 18-Dec-06 DWG: 5540 Document Number: 71200 18-Dec-06 INCHES 7 Nom www.vishay.com 1 AN823 Vishay Siliconix Mounting LITTLE FOOTR TSOP-6 Power MOSFETs Surface mounted power MOSFET packaging has been based on integrated circuit and small signal packages. Those packages have been modified to provide the improvements in heat transfer required by power MOSFETs. Leadframe materials and design, molding compounds, and die attach materials have been changed. What has remained the same is the footprint of the packages. The basis of the pad design for surface mounted power MOSFET is the basic footprint for the package. For the TSOP-6 package outline drawing see http://www.vishay.com/doc?71200 and see http://www.vishay.com/doc?72610 for the minimum pad footprint. In converting the footprint to the pad set for a power MOSFET, you must remember that not only do you want to make electrical connection to the package, but you must made thermal connection and provide a means to draw heat from the package, and move it away from the package. In the case of the TSOP-6 package, the electrical connections are very simple. Pins 1, 2, 5, and 6 are the drain of the MOSFET and are connected together. For a small signal device or integrated circuit, typical connections would be made with traces that are 0.020 inches wide. Since the drain pins serve the additional function of providing the thermal connection to the package, this level of connection is inadequate. The total cross section of the copper may be adequate to carry the current required for the application, but it presents a large thermal impedance. Also, heat spreads in a circular fashion from the heat source. In this case the drain pins are the heat sources when looking at heat spread on the PC board. Since surface mounted packages are small, and reflow soldering is the most common form of soldering for surface mount components, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low impedance path for heat to move away from the device. REFLOW SOLDERING Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a test preconditioning and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow temperature profile used, and the temperatures and time duration, are shown in Figures 2 and 3. Figure 1 shows the copper spreading recommended footprint for the TSOP-6 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlays the basic pattern on pins 1,2,5, and 6. The copper plane connects the drain pins electrically, but more importantly provides planar copper to draw heat from the drain leads and start the process of spreading the heat so it can be dissipated into the ambient air. Notice that the planar copper is shaped like a “T” to move heat away from the drain leads in all directions. This pattern uses all the available area underneath the body for this purpose. 0.167 4.25 0.074 1.875 0.014 0.35 0.122 3.1 0.026 0.65 0.049 1.25 0.049 1.25 0.010 0.25 FIGURE 1. Recommended Copper Spreading Footprint Document Number: 71743 27-Feb-04 Ramp-Up Rate +6_C/Second Maximum Temperature @ 155 " 15_C 120 Seconds Maximum Temperature Above 180_C 70 − 180 Seconds Maximum Temperature 240 +5/−0_C Time at Maximum Temperature 20 − 40 Seconds Ramp-Down Rate +6_C/Second Maximum FIGURE 2. Solder Reflow Temperature Profile www.vishay.com 1 AN823 Vishay Siliconix 10 s (max) 255 − 260_C 1X4_C/s (max) 3-6_C/s (max) 217_C 140 − 170_C 60 s (max) 60-120 s (min) Pre-Heating Zone 3_C/s (max) Reflow Zone Maximum peak temperature at 240_C is allowed. FIGURE 3. Solder Reflow Temperature and Time Durations THERMAL PERFORMANCE TABLE 1. Equivalent Steady State Performance—TSOP-6 Thermal Resistance Rqjf 30_C/W On-Resistance vs. Junction Temperature 1.6 VGS = 4.5 V ID = 6.1 A 1.4 rDS(on) − On-Resiistance (Normalized) A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rqjc, or the junction-to-foot thermal resistance, Rqjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows the thermal performance of the TSOP-6. 1.2 1.0 0.8 0.6 −50 SYSTEM AND ELECTRICAL IMPACT OF TSOP-6 −25 0 25 50 75 100 125 150 TJ − Junction Temperature (_C) FIGURE 4. Si3434DV In any design, one must take into account the change in MOSFET rDS(on) with temperature (Figure 4). www.vishay.com 2 Document Number: 71743 27-Feb-04 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR TSOP-6 0.099 0.039 0.020 0.019 (1.001) (0.508) (0.493) 0.064 (1.626) 0.028 (0.699) (3.023) 0.119 (2.510) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 26 Document Number: 72610 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000