DN05041/D 85-115 Vac Buck LED Driver Overview As LED lighting grows in the general lighting market, cost pressure increases as the volumes grow. Performance is weighted against cost especially for low power applications. LED manufacturers are developing high voltage LEDs whose voltage is more closely matched to the line voltage and thus supports high conversion efficiency with low line ripple. This makes the CrM buck topology an excellent architecture as an LED driver for the following reasons: Low RMS Current Stress on the FET and Output Diode since the Current is Much Lower for the HV LEDs and the Duty Cycle to Relatively High Low Current Stress Allows the Use of Smaller FETS and Diodes Leading to Optimum Bill-of-material (BOM) Cost Standard Mass Produced Inductors Can also be Used which Further Supports a Cost Effective Design http://onsemi.com DESIGN NOTE The key reason this controller was selected is that it has a very accurate current sense threshold of 485 mV 2% which is important to achieve good current regulation accuracy. In addition, in this design the inductor was also the focus of change from the standard implementation to eliminate the need for auxiliary winding for VCC power and ZCD (Zero Current Detector). This allows the designer to use a standard off-the-shelf inductor rather than a custom inductor. Referencing the schematic, VCC power and ZCD now come from a charge pump driven from the drain of the FET. The charge pump consists of C11, D9, and R12. When the FET turns off, drain current charges C11 providing a pulse of current into the VCC capacitor via D9. Figure 2 and 3 show some simulations of the charge pump. The 2 noteworthy items from figure 2 are that the current is limited because it is driven by the inductor. Also the drain voltage has well defined rise time which reduces EMI and reduces the trailing edge power losses. At turn on, the FET is fast but turns on into a low current. Key Features Operation of the NCL30002 CrM controller for buck operation is detailed in AND9094D. While that application note describes how the device can be used to implement a high power factor buck implementation, this design note will describe a low ripple configuration. Please note the input bulk capacitor was sized to comply with JIS61000−3−2 Class C (Japan), but the same basic design can be used for other lower voltage mains regions like US, Canada, and Latin America for example where that standard does not apply. Table 1. DEVICE DETAILS Device Application Input Voltage Output Power Topology I/O Isolation NCL30002 LED Lighting 85 to 115 Vac 3.6 W CRM Buck No Table 2. OTHER SPECIFICATIONS Output Specification Output Voltage 60 V Nominal Current 60 mA Harmonic Content JIS61000−3−2 Class C Efficiency 86.5% Typical Semiconductor Components Industries, LLC, 2013 May, 2013 − Rev. 2 1 Publication Order Number: DN05041/D 1 AC_L 1 AC_N D2 D1 Rfuse D4 D3 R2 C10 C2 R11 L1 R3 C3 2 http://onsemi.com Figure 1. Schematic C9 4 3 2 1 NCL30002 8 VCC 7 Comp Gdrv 6 Gnd CT 5 ZCD CS MFP U1 CVCC D10 Rzcd Rgd D9 Rstart R12 C11 Rsens Qfet Dout L2 Cout 1 1 LED_P 1 LED_N 1 DN05041/D DN05041/D V(vds) 140 V I(D2) 270 mA 130 V 240 mA 120 V 210 mA 110 V 180 mA 100 V 150 mA VCC 90 V 120 mA 80 V 90 mA 70 V 60 mA 60 V 30 mA 50 V 0 mA 40 V −30 mA 30 V −60 mA Drain 20 V −90 mA −120 mA 10 V −150 mA 0V −10 V 223.0 ms −180 mA 223.2 ms 223.4 ms 223.6 ms 223.8 ms 224.0 ms 224.2 ms 224.4 ms 223.1 ms 223.3 ms 223.5 ms 223.7 ms 223.9 ms 224.1 ms 224.3 ms 224.5 ms Figure 2. Simulation of Drain Voltage and Charge Current V(vds) 110 V −I(C3) 140 mA 100 V 120 mA 90 V 100 mA 80 V 80 mA FET Turn On 70 V 60 mA 60 V 40 mA 50 V 20 mA 40 V 0 mA 30 V −20 mA 20 V −40 mA Charge Pump 10 V −60 mA −80 mA 0V −10 V 185 ms 186 ms 187 ms 188 ms 189 ms 190 ms 191 ms 192 ms 193 ms 194 ms 195 ms 196 ms Figure 3. FET Drain Voltage and Charge Pump Capacitor Current http://onsemi.com 3 197 ms −100 mA 198 ms DN05041/D The turn on of the FET discharges the charge pump capacitor through R12. The on time needs to be at least 3RC time constants of C11 and R12 to ensure good discharge. R12 should be chosen to provide the lowest discharge current while still allowing for a complete discharge of C11. Since this is a CrM control, the peak to average current is 2:1. So by controlling the peak current by choice of Rsens, we can control the average current. In any open loop control, there are error sources that show up in the regulation. The two major error sources are: 1. Propagation Delay in the Sensing and Control: The delays in the current sense cause the current to overshoot the target value resulting in the output current creeping up with the line voltage. This is a relatively linear effect. Higher frequency operation will show this more than low frequency operation. 2. Charge-pump Operation: The charge pump capacitor causes a delay in rise time of the drain voltage. This effect is more prominent at higher switching frequency which is the case at higher line voltages. Start-up The start-up resistor (Rstart) connects to the output. This type of connection has three key advantages: 1. Fast Start-up: The start-up resistor precharges the output capacitor while also charging the VCC capacitor. 2. Low dissipation: In operation, the output voltage is much lower than the HVDC bulk voltage. 3. Inherent open circuit protection: If the load is open, there is no current available to start switching. Conclusion The charge pump buck LED driver is best used in a single line range configuration. The charge pump current increases with frequency and voltage. The nature of CrM operation causes both frequency and voltage to increase together. The charge pump capacitor is sized by the lowest operating voltage (which is also the lowest frequency). As the line voltage increases, excess charge pump current is dissipated in D10. The effect of this is seen in the efficiency curves. The effect on efficiency is most noticed in low power applications. While 3% regulation is very good over the extremes of a single line range, the addition of feed forward into the current sense node can further improve the line regulation. This requires the addition of 2 resistors R13 and R14 shown in the following schematic. Regulation The NCL30002 controller operates as a peak current limit controller with no feedback. The internal error amplifier is bias by R2 and R3 to saturate the error amplifier output high. The error amplifier input cannot be left open as this is detected as an open feedback divider and the controller will shutdown. The value of the timing capacitor (C9) is chosen to be long enough not to limit the on time. DI + (V in * V LED) V @ t on + LED @ t off + I peak L L I LED + I peak 2 http://onsemi.com 4 DN05041/D Table 3. BILL OF MATERIALS Item Qty Reference Part Manufacturer Part Number Substitution RoHS 1 1 2 1 CVCC 1.0 mF Cout 470 nF Panasonic ECE-A1HKK010 Yes Yes TDK C2012X7S2A474M/SOFT Yes Yes 3 4 2 C2, C3 1 C9 4.7 mF 200 V Rubycon 200LLE4R7MEFC6.3X11 Yes Yes 10 nF Kemet C0402C103K3GACTU Yes Yes 5 1 6 1 C10 1 nF Kemet C0402C102K3GACTU Yes Yes C11 470 pF Kemet C0805C4712GACTU Yes Yes 7 1 Dout UFM13PL−TP MCC UFM13PL−TP Yes Yes 8 1 D4 MB6S MCC MB6S Yes Yes 9 1 D9 BAS21DW5T1G ON Semiconductor BAS21DW5T1G No Yes 10 1 D10 NZ9F18VT5G ON Semiconductor NZ9F18VT5G No Yes 11 1 F1 FUSE Littelfuse 0263.500WRT1L Yes Yes 15 1 L1 100 mH Wurth 7447462101 Yes Yes 16 1 L2 2.2 mH Bourns RL875S−222K Yes Yes 17 1 Qfet BSS131 Infineon BSS131 H6327 Yes Yes 18 1 Rgd 10 W Yageo RC0402FR−0710RL Yes Yes 19 1 Rsens 2W Yageo RC0603JR−072R0L Yes Yes 20 1 Rstart 1.0 MW Yageo RC0805FR−071ML Yes Yes 21 1 Rzcd 24.9 kW Yageo RC0402FR−0724k9L Yes Yes 22 1 R2 100 kW Yageo RC0402FR−07100kL Yes Yes 23 1 R3 681 kW Yageo RC0402FR−07681kL Yes Yes 24 1 R12 2 kW Stackpole RNCP1206FTD2K32 Yes Yes 25 1 U1 NCL30002 ON Semiconductor NCL30002 No Yes L1 Rstart R11 D9 D10 C3 R3 C11 Dout R12 CVCC R14 1 2 3 4 R2 U1 MFP VCC Comp Gdrv CT Gnd CS ZCD 8 7 6 5 Rgd Qfet Rzcd NCL30002 C10 C9 R13 Rsens Figure 4. Proposed Line Regulation Feed Forward Improvement http://onsemi.com 5 DN05041/D RESULTS 63.0 62.5 62.0 Output Current (mA) 61.5 61.0 60.5 60.0 59.5 59.0 58.5 58.0 57.5 57.0 85 90 95 100 105 110 115 Input Line Voltage (Vac) Figure 5. Output Current across Input Line Voltage 90% 89% Efficiency (%) 88% 87% 86% 85% 84% 83% 85 90 95 100 105 110 Line Voltage (Vac) Figure 6. Output Efficiency across Line (Vf = 60 Vdc Nominal) http://onsemi.com 6 115 DN05041/D 5.0% 4.0% Normalized Current Regulation (%) 3.0% 2.0% 1.0% 0.0% −1.0% −2.0% −3.0% −4.0% −5.0% 85 90 95 100 105 110 115 Line Voltage (Vac) Figure 7. Normalized Output Current across Input Line Voltage (Vf = 60 Vdc Nominal) ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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