AK4346VF

ASAHI KASEI
[AK4346]
AK4346
3.3V 192kHz 24-Bit 6-Channel DAC
GENERAL DESCRIPTION
The AK4346 is an 6-channel 24bit DAC operating off of a single +3.3V power supply. The outputs are
single-ended, and it samples at rates from 8kHz to 192kHz. It uses AKM’s advanced multi-bit architecture
for the modulator to achieve a wide dynamic range while preserving linearity for improved THD+N
performance. The output circuit includes a switched-cap filter and a second-order analog low pass filter,
minimizing the need for external filtering.
FEATURES
† Sampling Rate: 8kHz to 192kHz
† 24-Bit 8 times Digital Filter with Slow Roll-Off Option
† DR, S/N: 104dB
† THD+N: -90dB
† High Tolerance to Clock Jitter
† Single Ended Output Buffer with Second Order Analog LPF
† Digital De-emphasis for 32, 44.1 & 48kHz sampling
† Zero Detect Function
† Channel Independent Digital Attenuator (Linear 256 steps)
† 3-wire Serial or I2C Control
† I/F format: MSB justified, LSB justified (16-, 20-, 24-bit), I2S, TDM
† Master clock: 256fs, 384fs, 512fs or 768fs or 1152fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs or 192fs (Quad Speed Mode)
† Power Supply: 2.7V to 3.6V
† Ta = −20 ∼ 85°C (EF), −40 ∼ 85°C (VF)
† Package: 30-pin VSOP
DZF
Audio
I/F
LOUT1
LPF
SCF
DAC
DATT
ROUT1
LPF
SCF
DAC
DATT
LOUT2
LPF
SCF
DAC
DATT
ROUT2
LPF
SCF
DAC
DATT
LOUT3
LPF
SCF
DAC
DATT
ROUT3
LPF
SCF
DAC
DATT
MCLK
LRCK
BICK
SDTI1
SDTI2
SDTI3
PCM
Control
Register
3-wire
or I2C
AK4346
MS0531-E-00
2006/07
-1-
ASAHI KASEI
[AK4346]
„ Ordering Guide
AK4346EF
AK4346VF
AKD4346
-20 ∼ +85°C
30pin VSOP
-40 ∼ +85°C
30pin VSOP
Evaluation Board for AK4346
„ Pin Layout
MCLK
1
30
DZF1
BICK
2
29
TDM0/DZF2
SDTI1
3
28
AVDD
LRCK
4
27
AVSS
RSTB
5
26
VCOM
SMUTE/CSN/CAD0
6
25
LOUT1
ACKS/CCLK/SCL
7
24
ROUT1
DIF0/CDTI/SDA
8
23
P/S
SDTI2
9
22
LOUT2
SDTI3
10
21
ROUT2
TST1
11
20
LOUT3
DIF1
12
19
ROUT3
DEM0/CAD1
13
18
TST3
DVDD
14
17
TST2
DVSS
15
16
DEM1/I2C
AK4346
Top
View
MS0531-E-00
2006/07
-2-
ASAHI KASEI
[AK4346]
PIN/FUNCTION
No.
1
Pin Name
MCLK
I/O
I
Function
Master Clock Input
An external TTL clock should be input on this pin.
2
BICK
I
Audio Serial Data Clock
3
SDTI1
I
DAC1 Audio Serial Data Input
4
LRCK
I
L/R Clock
5
RSTB
I
Reset Mode
When at “L”, the AK4346 is in reset mode.
The AK4346 must be reset once upon power-up.
6
SMUTE
I
Soft Mute in parallel control mode
“H”: Enable, “L”: Disable
CSN
I
Chip Select in serial 3-wire mode
CAD0
I
Chip Address in serial I2C mode
7
ACKS
I
Auto Setting Mode in parallel control mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
CCLK
I
Control Data Clock in serial 3-wire control mode
SCL
Control Data Clock in serial I2C control mode
8
DIF0
I
Audio Data Interface Format in parallel control mode
CDTI
I
Control Data Input in serial 3-wire control mode
SDA
I/O
Control Data in serial I2C control mode
9
SDTI2
I
DAC2 Audio Serial Data Input
10
SDTI3
I
DAC3 Audio Serial Data Input
11
TST1
I
Test pin – connect to ground.
12
DIF1
I
Audio Data Interface Format
13
CAD1
I
Chip Address in serial control mode
DEM0
I
De-emphasis Filter Enable
14
DVDD
Digital Power Supply, +2.7∼+3.6V
15
DVSS
Digital Ground
16
I2C
I
µP I/F Mode Select in serial control mode
“L”: 3-wire Serial, “H”: I2 C Bus
DEM1
I
De-emphasis Filter Enable in parallel control mode
17
TST2
Test pin – leave this pin floating.
18
TST3
Test pin – leave this pin floating.
19
ROUT3
O
DAC3 Right Channel Analog Output
20
LOUT3
O
DAC3 Left Channel Analog Output
21
ROUT2
O
DAC2 Right Channel Analog Output
22
LOUT2
O
DAC2 Left Channel Analog Output
23
P/S
I
Parallel/Serial Control Mode Select
(Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
24
ROUT1
O
DAC1 Right Channel Analog Output
25
LOUT1
O
DAC1 Left Channel Analog Output
26
VCOM
O
Common Voltage, AVDD/2
Normally connected to AVSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
27
AVSS
Analog Ground
28
AVDD
Analog Power Supply, +2.7∼+3.6V
29
TDM0
I
TDM I/F Format Mode in parallel control mode (Internal pull-down pin)
“L”: Normal mode, “H”: TDM 256 mode
DZF2
O
Data Zero Input Detect in serial control mode
30
DZF1
O
Data Zero Input Detect
Note: All input pins except P/S and TDM0 pins should not be left floating.
MS0531-E-00
2006/07
-3-
ASAHI KASEI
[AK4346]
„ Handling of Unused Pins
Unused I/O pins should be resolved as shown in this table.
Classificatio
n
Analog
Digital
Setting
Pin Name
LOUT3-1, ROUT3-1
DZF2-1
SDTI3-1
SMUTE (Parallel control mode)
DEM0, DIF1 (Serial control mode)
Leave open.
Leave open.
Connect to DVSS.
Connect to DVDD or DVSS.
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 1)
Parameter
Symbol
Min
Power Supplies
Analog
AVDD
-0.3
Digital
DVDD
-0.3
|AVSS-DVSS|
(Note 2)
∆GND
Input Current (any pins except for supplies)
IIN
Analog Input Voltage
VINA
-0.3
Digital Input Voltage
VIND
-0.3
Ambient Operating Temperature
AK4346EF
Ta
-20
AK4346VF
Ta
-40
Storage Temperature
Tstg
-65
Max
4.6
4.6
0.3
±10
AVDD+0.3
DVDD+0.3
85
85
150
Units
V
V
V
mA
V
V
°C
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AVSS and DVSS must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 1)
Parameter
Symbol
Min
Typ
Power Supplies
Analog
AVDD
2.7
3.3
(Note 1)
Digital
DVDD
2.7
3.3
Max
3.6
3.6
Units
V
V
Note 3. The power up sequence between AVDD and DVDD is not critical.
*AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0531-E-00
2006/07
-4-
ASAHI KASEI
[AK4346]
ANALOG CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=3.3V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Input Data;
Measurement frequency=20Hz ∼ 20kHz; RL ≥5kΩ; unless otherwise specified)
Parameter
Min
Typ
Max
Resolution
24
Dynamic Characteristics
(Note 4)
THD+N
Fs=44.1kHz
0dBFS
-90
-80
BW=20kHz
-60dBFS
-40
fs=96kHz
0dBFS
-86
BW=40kHz
-60dBFS
-37
fs=192kHz
0dBFS
-86
BW=40kHz
-60dBFS
-37
Dynamic Range (-60dBFS with A-weighted)
(Note 5)
96
104
S/N
(A-weighted)
(Note 6)
96
104
Interchannel Isolation (1kHz)
80
100
Interchannel Gain Mismatch
0.2
0.5
DC Accuracy
Gain Drift
100
Output Voltage
(Note 7)
2.09
2.24
2.39
Load Resistance
(Note 8)
5
Load Capacitance
25
Power Supplies
Power Supply Current (AVDD+DVDD)
37
60
Normal Operation (RSTB pin = “H”, fs≤96kHz)
44
66
Normal Operation (RSTB pin = “H”, fs=192kHz)
33
133
Reset Mode (RSTB pin = “L”)
(Note 9)
Units
Bits
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ppm/°C
Vpp
kΩ
pF
mA
mA
µA
Note 4. Measured by Audio Precision System Two. Refer to the evaluation board manual.
Note 5. 100dB when using 16bit data.
Note 6. S/N does not depend on input data resolution.
Note 7. Full scale voltage (0dB). Output voltage scales with the voltage of AVDD pin. AOUT (typ. @0dB) =
2.24Vpp×AVDD/3.3
Note 8. For AC-load.
Note 9 P/S pin is tied to DVDD and the other all digital input pins including clock pins (MCLK, BICK, LRCK) are tied
to DVSS.
MS0531-E-00
2006/07
-5-
ASAHI KASEI
[AK4346]
SHARP ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 2.7 ∼ 3.6V; fs = 44.1kHz; DEM = OFF; SLOW = “0”)
Parameter
Symbol
Min
Typ
Digital filter
PB
0
Passband
(Note 10)
±0.05dB
22.05
-6.0dB
Stopband
(Note 10)
SB
24.1
Passband Ripple
PR
Stopband Attenuation
SA
54
Group Delay
(Note 11)
GD
19.3
Digital Filter + SCF
Frequency Response 20.0kHz Fs=44.1kHz
FR
+ 0.06/-0.10
40.0kHz Fs=96kHz
FR
+ 0.06/-0.13
80.0kHz Fs=192kHz
FR
+ 0.06/-0.51
Max
Units
20.0
-
-
kHz
kHz
kHz
dB
dB
1/fs
-
dB
dB
dB
± 0.02
Note 10. The passband and stopband frequencies scale with fs(system sampling rate). For example, PB=0.4535×fs
(@±0.05dB), SB=0.546×fs.
Note 11. Calculated delay time caused by the digital filter. This time is measured from when the serial data of both
channels is in the input register to the output of the analog signal.
SLOW ROLL-OFF FILTER CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 2.7~3.6V; fs = 44.1kHz; DEM = OFF; SLOW = “1”)
Parameter
Digital Filter
Passband
±0.04dB
-3.0dB
Stopband
Passband Ripple
Stopband Attenuation
Group Delay
Symbol
Min
(Note 12)
PB
(Note 12)
SB
PR
SA
GD
0
39.2
(Note 11)
Typ
Max
Units
18.2
8.1
-
72
-
19.3
-
kHz
kHz
kHz
dB
dB
1/fs
-
+0.1/-4.3
+0.1/-3.3
+0.1/-3.7
-
dB
dB
dB
± 0.005
Digital Filter + SCF
Frequency Response
20.0kHz
40.0kHz
80.0kHz
fs=44.kHz
fs=96kHz
fs=192kHz
FR
FR
FR
Note 12. The passband and stopband frequencies scale with fs. For example, PB = 0.185×fs (@±0.04dB), SB = 0.888×fs.
DC CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 2.7 ∼ 3.6V)
Parameter
Symbol
Min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
High-Level Output Voltage (Iout = -80µA)
VOH
DVDD-0.4
Low-Level Output Voltage
(Iout = 80µA)
VOL
Input Leakage Current
(Note 13)
Iin
-
Typ
-
Max
30%DVDD
0.4
± 10
Units
V
V
V
V
µA
Note 13. P/S pin has an internal pull-up device and TDM0 pin has an internal pull-down device, nominally 100kΩ.
MS0531-E-00
2006/07
-6-
ASAHI KASEI
[AK4346]
SWITCHING CHARACTERISTICS
(Ta = 25°C; AVDD, DVDD = 2.7 ∼ 3.6V; CL = 20pF)
Parameter
Symbol
Min
fCLK
2.048
Master Clock Frequency
Duty Cycle
dCLK
40
LRCK Frequency
Normal Mode (TDM0= “0”, TDM1= “0”)
Normal Speed Mode
fsn
8
Double Speed Mode
fsd
60
Quad Speed Mode
fsq
120
Duty Cycle
Duty
45
TDM256 mode (TDM0= “1”, TDM1= “0”)
Normal Speed Mode
fsn
8
High time
tLRH
1/256fs
Low time
tLRL
1/256fs
TDM128 mode (TDM0= “1”, TDM1= “1”)
Normal Speed Mode
fsn
8
Double Speed Mode
60
fsd
High time
1/128fs
tLRH
Low time
1/128fs
tLRL
Audio Interface Timing
BICK Period
tBCK
81
BICK Pulse Width Low
tBCKL
30
Pulse Width High
tBCKH
30
tBLR
20
BICK “↑” to LRCK Edge
(Note 14)
tLRB
20
LRCK Edge to BICK “↑”
(Note 14)
tSDH
10
SDTI Hold Time
tSDS
10
SDTI Setup Time
Control Interface Timing (3-wire Serial mode):
CCLK Period
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN High Time
tCSW
150
tCSS
50
CSN “↓” to CCLK “↑”
tCSH
50
CCLK “↑” to CSN “↑”
Control Interface Timing (I2C Bus mode):
fSCL
SCL Clock Frequency
1.3
tBUF
Bus Free Time Between Transmissions
0.6
tHD:STA
Start Condition Hold Time (prior to first clock pulse)
1.3
tLOW
Clock Low Time
0.6
tHIGH
Clock High Time
0.6
tSU:STA
Setup Time for Repeated Start Condition
0
tHD:DAT
SDA Hold Time from SCL Falling
(Note 15)
0.1
tSU:DAT
SDA Setup Time from SCL Rising
tR
Rise Time of Both SDA and SCL Lines
tF
Fall Time of Both SDA and SCL Lines
0.6
tSU:STO
Setup Time for Stop Condition
0
tSP
Pulse Width of Spike Noise Suppressed by Input Filter
Cb
Capacitive load on bus
Reset Timing
RSTB Pulse Width
(Note 16)
tRST
150
MS0531-E-00
Typ
11.2896
Max
36.864
60
Units
MHz
%
48
96
192
55
kHz
kHz
kHz
%
48
kHz
ns
ns
48
96
kHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
400
0.3
0.3
50
400
kHz
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
pF
ns
2006/07
-7-
ASAHI KASEI
[AK4346]
Note 14. BICK rising edge must not occur at the same time as LRCK edge.
Note 15. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 16. The AK4346 can be reset by bringing RSTB pin = “L”.
Note 17. I2C is a registered trademark of Philips Semiconductors.
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
VIH
LRCK
VIL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Clock Timing
VIH
LRCK
VIL
tBLR
tLRB
VIH
BICK
VIL
tSDH
tSDS
VIH
SDTI
VIL
Audio Serial Interface Timing
MS0531-E-00
2006/07
-8-
ASAHI KASEI
[AK4346]
VIH
CSN
VIL
tCSS
tCCKL tCCKH
VIH
CCLK
VIL
tCDS
C1
CDTI
tCDH
C0
R/W
VIH
A4
VIL
WRITE Command Input Timing
tCSW
VIH
CSN
VIL
tCSH
VIH
CCLK
VIL
VIH
CDTI
D3
D2
D1
D0
VIL
WRITE Data Input Timing
VIH
SDA
VIL
tLOW
tBUF
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
tHD:DAT
tSU:DAT
tSU:STA
tSU:STO
Start
Stop
Start
I2C Bus mode Timing
tRST
RSTB
VIL
Reset Timing
MS0531-E-00
2006/07
-9-
ASAHI KASEI
[AK4346]
OPERATION OVERVIEW
„ System Clock
The external clocks required to operate the AK4346 are MCLK, LRCK and BICK. The master clock (MCLK) should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS bit = “0”:
Register 00H), the sampling speed is set by DFS0-1 bits (Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2~Table 4) In Auto Setting Mode (ACKS bit = “1”: Default), the MCLK frequency is detected
automatically (Table 5), and the internal master clock is set to the appropriate frequency (Table 6) and it is not necessary
to set DFS0-1.
In parallel control mode, the sampling speed can be set by only the ACKS pin. When ACKS pin = “L”, the AK4346
operates by normal speed mode. When ACKS pin = “H”, auto setting mode is enabled. The parallel control mode does not
support 128fs and 192fs of double speed mode.
All external clocks (MCLK, BICK and LRCK) should be present whenever the AK4346 is in normal operation mode
(RSTB pin = “H”). If these clocks are not provided, the AK4346 may draw excess current and will not operate properly
because it utilizes these clocks for internal dynamic refresh of registers. The AK4346 should be reset by setting RSTB pin
= “L” after threse clocks are provided. If the external clocks are not present, the AK4346 should be in the power-down
mode (RSTB pin = ”L”). After exiting reset(RSTB = “↑”) at power-up, the AK4346 is in the power-down mode until
MCLK is input.
DFS1
DFS0
Sampling Rate (fs)
0
0
Normal Speed Mode
8kHz~48kHz
0
1
Double Speed Mode
60kHz~96kHz
1
0
Quad Speed Mode
Default
120kHz~192kHz
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
384fs
12.2880MHz
16.9344MHz
18.4320MHz
MCLK
512fs
16.3840MHz
22.5792MHz
24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
1152fs
36.8640MHz
N/A
N/A
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
fs
88.2kHz
96.0kHz
128fs
106896MHz
12.2880MHz
MCLK
192fs
256fs
16.9344MHz 22.5792MHz
18.4320MHz 24.5760MHz
384fs
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK
fs
176.4kHz
192.0kHz
MCLK
128fs
192fs
22.5792MHz 33.8688MHz
24.5760MHz 36.8640MHz
BICK
64fs
106896MHz
12.2880MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MS0531-E-00
2006/07
- 10 -
ASAHI KASEI
[AK4346]
MCLK
1152fs
512fs
256fs
128fs
Sampling Speed
Normal (fs≤32kHz)
Normal
Double
Quad
768fs
384fs
192fs
Table 5. Sampling Speed (Auto Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
128fs
22.5792
24.5760
192fs
33.8688
36.8640
256fs
22.5792
24.5760
-
MCLK (MHz)
384fs
512fs
16.3840
22.5792
24.5760
33.8688
36.8640
-
768fs
24.5760
33.8688
36.8640
-
1152fs
36.8640
-
Sampling
Speed
Normal
Double
Quad
Table 6. System Clock Example (Auto Setting Mode)
MS0531-E-00
2006/07
- 11 -
ASAHI KASEI
[AK4346]
„ Audio Serial Interface Format
In parallel control mode, the DIF0-1 and TDM0 pins can select eight serial data modes (Table 7). The register value of
DIF0-1 and TDM0bits are ignored. In serial control mode, the DIF0-2 and TDM0-1 bits shown in Table 8 can select 11
serial data modes. The default format is Mode 2 (24-bit MSB justified format in normal mode). The setting of DIF1 pin
is ignored. In all modes the audio data is MSB-first, 2’s complement format and is latched on the rising edge of BICK.
Mode 2 can be used for 16/20-bit MSB justified formats by zeroing the unused LSB’s.
In parallel control mode, when the TDM0 pin = “H”, the audio interface format is TDM256 mode (Table 7). The audio
data of all DACs (six channels) is input to the SDTI1 pin. The input data to SDTI2-3 pins is ignored. BICK should be
fixed to 256fs. “H” time and “L” time of LRCK should be at least 1/256fs. The audio data is MSB-first, 2’s complement
format. The input data to SDTI1 pin is latched on the rising edge of BICK.
In serial control mode, when the TDM0 bit = “1” and the TDM1 bit = “0”, the audio interface format is TDM256 mode
(Table 8), and the audio data of all DACs (six channels) is input to the SDTI1 pin. The input data to SDTI2-3 pins is
ignored. BICK should be fixed to 256fs. “H” time and “L” time of LRCK should be at least 1/256fs. The audio data is
MSB-first, 2’s complement format. The input data to SDTI1 pin is latched on the rising edge of BICK. In TDM128 mode
(TDM0 bit = “1” and TDM1 bit = “1”, Table 8), the audio data of DACs (four channels; L1, R1, L2, R2) is input to the
SDTI1 pin. The other two data (L3, R3) is input to the SDTI2 pin. The input data to SDTI3 pins is ignored. BICK should
be fixed to 128fs. The audio data is MSB-first, 2’s complement format. The input data to SDTI1-2 pins is latched on the
rising edge of BICK.
Mode
Normal
TDM256
0
1
2
3
5
6
TDM0
L
L
L
L
H
H
H
H
DIF1
L
L
H
H
L
L
H
H
DIF0
L
H
L
H
L
H
L
H
SDTI Format
16-bit LSB Justified
20-bit LSB Justified
24-bit MSB Justified
24-bit I2S Compatible
N/A
N/A
24-bit MSB Justified
24-bit I2S Compatible
LRCK
H/L
H/L
H/L
L/H
BICK
≥32fs
≥40fs
≥48fs
≥48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
↑
↓
256fs
256fs
Figure 5
Figure 6
Table 7. Audio Data Formats (Parallel control mode)
Mode
Normal
0
1
2
3
4
TDM256
5
6
7
TDM128
8
9
10
TDM1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
TDM0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
DIF2
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
DIF1
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
DIF0
0
1
0
1
0
0
1
0
1
0
0
1
0
1
0
SDTI Format
16-bit LSB Justified
20-bit LSB Justified
24-bit MSB Justified
24-bit I2 S Compatible
24-bit LSB Justified
N/A
N/A
24-bit MSB Justified
24-bit I2 S Compatible
24-bit LSB Justified
N/A
N/A
24-bit MSB Justified
24-bit I2 S Compatible
24-bit LSB Justified
LRCK
H/L
H/L
H/L
L/H
H/L
BICK
≥32fs
≥40fs
≥48fs
≥48fs
≥48fs
Figure
Figure 1
Figure 2
Figure 3
Figure 4
Figure 2
↑
↓
↑
256fs
256fs
256fs
Figure 5
Figure 6
Figure 7
↑
↓
↑
128fs
128fs
128fs
Figure 8
Figure 9
Figure 10
Table 8. Audio Data Formats (Serial control mode, Default: Mode 2)
MS0531-E-00
2006/07
- 12 -
ASAHI KASEI
[AK4346]
LRCK
0
1
10
11
12
13
14
15
0
1
10
11
12
13
14
15
0
1
BICK
(32fs)
SDTI
Mode 0
15
14
6
1
0
5
14
4
15
3
2
16
1
17
0
31
15
0
14
6
5
14
1
4
15
3
16
2
1
17
0
31
15
14
0
1
0
1
0
1
BICK
(64fs)
SDTI
Mode 0
Don’t care
15
14
0
Don’t care
15
14
0
15:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0
1
8
9
10
11
12
31
0
1
8
9
10
11
12
31
BICK
(64fs)
SDTI
Mode 1
Don’t care
19
0
Don’t care
19
0
Don’t care
19
0
19
0
19:MSB, 0:LSB
SDTI
Mode 4
Don’t care
23
22
21
20
23
22
21
20
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1,4 Timing
LRCK
0
1
2
22
23
24
30
31
0
1
2
22
23
24
30
31
BICK
(64fs)
SDTI
23 22
1
0
Don’t care
23 22
1
0
Don’t care
23
22
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 3. Mode 2 Timing
MS0531-E-00
2006/07
- 13 -
ASAHI KASEI
[AK4346]
LRCK
0
1
2
3
23
24
25
31
0
1
2
3
23
24
25
31
0
1
BICK
(64fs)
SDTI
0
1
23 22
Don’t care
23 22
1
0
Don’t care
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 4. Mode 3 Timing
256 BICK
LRCK
BICK(256fs)
SDTI1(i)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
L3
R3
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
Figure 5. Mode 5 Timing
256 BICK
LRCK
BICK(256fs)
SDTI1(i)
23
0
23
0
23
0
23
0
23
0
23
0
L1
R1
L2
R2
L3
R3
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
23
32 BICK
32 BICK
Figure 6. Mode 6 Timing
256 BICK
LRCK
BICK(256fs)
SDTI1(i)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
R1
L2
R2
L3
R3
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
32 BICK
0
23
32 BICK
32 BICK
Figure 7. Mode 7 Timing
MS0531-E-00
2006/07
- 14 -
ASAHI KASEI
[AK4346]
128 BICK
LRCK
BICK(128fs)
SDTI1(i)
SDTI2(i)
23 22
23 22
0
0
23 22
23 22
0
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
23 22
0
23 22
0
L3
R3
32 BICK
32 BICK
23 22
32 BICK
32 BICK
Figure 8. Mode 8 Timing
128 BICK
LRCK
BICK(128fs)
SDTI1(i)
SDTI2(i)
23 22
0
23 22
0
0
23 22
23 22
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
23
0
0
L3
R3
32 BICK
32 BICK
23
32 BICK
32 BICK
Figure 9. Mode 9 Timing
128 BICK
LRCK
BICK(128fs)
SDTI1(i)
SDTI2(i)
23 22
0
23 22
0
23 22
0
23 22
0
L1
R1
L2
R2
32 BICK
32 BICK
32 BICK
32 BICK
23 22
0
23 22
0
L3
R3
32 BICK
32 BICK
19
19
32 BICK
32 BICK
Figure 10. Mode 10 Timing
MS0531-E-00
2006/07
- 15 -
ASAHI KASEI
[AK4346]
„ De-emphasis Filter
A digital de-emphasis filter is available for 32, 44.1 or 48kHz sampling rates (tc = 50/15µs). The digital de-emphasis
filter is always off when the AK4346 is operated in double or quad speed modes. In serial control mode, the DEM0-1 bits
are valid for the DAC enabled by the DEMA-C bits. In parallel control mode, the DEM0-1 pins are valid.
DEM1
DEM0
Mode
0
0
1
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
Table 9. De-emphasis Filter Control (Normal Speed Mode)
„ Output Volume
The AK4346 includes channel independent digital volume controls (ATT) with 256 linear steps, including MUTE. The
volume controls are in front of the DAC and can attenuate the input data from 0dB to –48dB, and mute. When changing
levels, transitions are executed via soft changes; thus no switching noise occurs during these transitions. The transition
time of 1 level and all 256 levels is shown in Table 10. The attenuation level is calculated by ATT = 20 log10
(ATT_DATA / 255) [dB] and MUTE at ATT_DATA = “0”.
Sampling Speed
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
Transition Time
1 Level
255 to 0
4LRCK
1020LRCK
8LRCK
2040LRCK
16LRCK
4080LRCK
Table 10. ATT Transition time
„ Zero Detection
When the input data at all channels are continuously zeros for 8192 LRCK cycles, the AK4346 has a Zero Detect function
detailed in Table 11. The DZF pin immediately goes to “L” if the input data for each channel is not zero after the DZF pin
is “H”. If the RSTN bit is “0”, the DZF pin goes to “H”. The DZF pin goes to “L” after 4 to 5LRCK cycles if the input data
of each channel is not zero after the RSTN bit returns to “1”. The Zero Detect function can be disabled by the DZFE bit.
In this case, both DZF pins are always “L”. When one of the PW1-3 bits is set to “0”, the input data of the DAC for which
the PW bit is set to “0” should be zero in order to enable zero detection of the other channels. When all PW1-3 bits are set
to “0”, both DZF pins are fixed to “L”. The DZFB bit can invert the polarity of the DZF pin. In parallel control mode, the
zero detect function is disabled and the DZF1 pin is fixed to “L”.
DZF Pin
DZF1
DZF2
Operations
AND’ed output of zero detection flag of each channel set to “1” in 0CH register
AND’ed output of zero detection flag of each channel set to “1” in 0DH register
Table 11. DZF pins Operation
MS0531-E-00
2006/07
- 16 -
ASAHI KASEI
[AK4346]
„ Soft Mute Operation
Soft mute operation is performed in the digital domain. When the SMUTE bit goes to “1”, the output signal is attenuated
by -∞ during the ATT_DATA×ATT transition time (Table 10) from the current ATT level. When the SMUTE bit is
returned to “0”, the mute is cancelled and the output attenuation gradually changes to the ATT level during the
ATT_DATA×ATT transition time. If the soft mute is cancelled before attenuating to -∞ after starting the operation, the
attenuation is discontinued and returned to ATT level by the same cycle. The soft mute is effective when changing the
signal source without stopping the signal transmission.
SMUTE
ATT Level
(1)
(1)
(3)
Attenuation
-∞
GD
(2)
GD
AOUT
DZF pin
(4)
8192/fs
Notes:
(1) ATT_DATA×ATT transition time (Table 10). For example, in Normal Speed Mode, this time is 1020LRCK cycles
(1020/fs) at ATT_DATA=255.
(2) The analog output corresponding to the digital input has a group delay, GD.
(3) If the soft mute is cancelled before attenuating to -∞ after starting the operation, the attenuation is discontinued and
returned to ATT level by the same cycle.
(4) When the input data at each channel is continuously zero for 8192 LRCK cycles, the DZF pin of each channel goes
to “H”. The DZF pin immediately goes to “L” if input data are not zero after going DZF “H”. In parallel control
mode, the DZF pin is fixed to “L” regardless of the state of SMUTE pin.
Figure 11. Soft Mute and Zero Detection (DZFB bit = “0”)
MS0531-E-00
2006/07
- 17 -
ASAHI KASEI
[AK4346]
„ System Reset
The AK4346 should be reset once by bringing RSTB pin = ”L” upon power-up. The AK4346 is powered up and the
internal timing starts clocking by LRCK “↑” after exiting reset and power down state by MCLK. The AK4346 is in the
power-down mode until MCLK and LRCK are input.
„ Power ON/OFF timing
All DACs are placed in the power-down mode by bringing RSTB pin “L” and the registers are initialized. The analog
outputs go to VCOM. Since some click noise occurs at the edge of the RSTB signal, the analog output should be muted
externally if the click noise influences system application.
Each DAC can be powered down by setting each power-down bit (PW1-3 bits) to “0”. In this case, the registers are not
initialized and the corresponding analog outputs go to VCOM. Since some click noise occurs at the edge of the RSTB
signal, the analog output should be muted externally if the click noise influences system application.
Power
RSTB pin
Internal
State
DAC In
(Digital)
Normal Operation
(2)
“0”data
(2)
“0”data
GD
(1)
(3)
DAC Out
(Analog)
Reset
GD
(3)
(4)
Clock In
Don’t care
Don’t care
MCLK,LRCK,BICK
(6)
DZF1/DZF2
External
Mute
(5)
Mute ON
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are VCOM at the power-down mode.
(3) Click noise occurs at the edge of RSTB signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (RSTB pin = “L”).
(5) Mute the analog output externally if the click noise (3) influences the system application.
The timing example is shown in this figure.
(6) DZF pins are “L” in the power-down mode (RSTB pin = “L”). (DZFB bit = “0”)
Figure 12. Power-down/up Sequence Example
MS0531-E-00
2006/07
- 18 -
ASAHI KASEI
[AK4346]
„ Reset Function (RSTN bit)
When the RSTN bit = “0”, the internal circuit of the DAC is powered down but the registers are not initialized. The
analog outputs go to VCOM voltage and the DZF pins go to “H” when the DZFB bit = “0”. Figure 13 shows the example
of reset by the RSTN bit. When the RSTN bit = “0”, click noise is decreased at no clock state.
RSTN bit
3~4/fs (6)
2~3/fs (6)
Internal
RSTN bit
Internal
State
Normal Operation
D/A In
(Digital)
“0” data
(1)
D/A Out
(Analog)
Normal Operation
Digital Block Power-down
GD
GD
(3)
(2)
(3)
(1)
(4)
Clock In
Don’t care
MCLK,LRCK,BICK
2/fs(5)
DZF
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs go to VCOM voltage.
(3) Small click noise occurs at the edges(“↑ ↓”) of the internal timing of RSTN bit. This noise is output even if “0”
data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the reset mode (RSTN bit = “0”).
(5) DZF pins go to “H” when the RSTN bit becomes “0”, and go to “L” at 2/fs after RSTN bit becomes “1”.
(6) There is a delay, 3~4/fs from RSTN bit “0” to the internal RSTN bit “0”, and 2~3/fs from RSTN bit “1” to the
internal RSTN bit “1”.
Figure 13. Reset Sequence Example (DZFB bit = “0”)
MS0531-E-00
2006/07
- 19 -
ASAHI KASEI
[AK4346]
„ Register Control Interface
The AK4346 controls its functions via registers. Two types of control mode can be used to write to the internal registers.
In I2C-bus mode, the chip address is determined by the state of the CAD0-1 pins. In 3-wire mode, the chip address can
be selected by the state of the CAD1 pin. RSTB pin = “L” initializes the registers to their default values. Writing “0” to
the RSTN bit resets the internal timing circuit, but the registers are not initialized.
* The AK4346 does not support the read command.
* When the AK4346 is in the power down mode (RSTB bit = “L”) or the MCLK is not provided, writing to control
registers is prohibited.
* When the state of P/S pin is changed, the AK4346 should be reset by RSTB bit = “L”.
* In serial control mode, the setting of parallel pins is invalid.
Function
Parallel control mode
Serial control mode
O
O
O
-
O
O
O
O
O
O
O
Double sampling mode at 128/192fs
De-emphasis
SMUTE
Zero Detection
24-bit LSB justified format
TDM256 mode
TDM128 mode
Table 12. Function Table (O: Supported, -: Not supported)
(1) 3-wire Serial Control Mode (I2C pin = “L”)
Internal registers may be written to via the 3-wire µP interface pins (CSN, CCLK and CDTI). The data on this interface
consists of Chip Address (2-bits, C1/0; C1=CAD1 and C0 is fixed to “1”), Read/Write (1-bit; fixed to “1”, Write only),
Register Address (MSB first, 5-bits) and Control Data (MSB first, 8-bits). The AK4346 latches the data on the rising edge
of CCLK, so data should clocked in on the falling edge. The writing of data becomes valid by the rising edge of CSN. The
clock speed of CCLK is 5MHz (max).
CSN
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14 15
CCLK
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1=CAD1, C0=“1”)
READ/WRITE (Fixed to “1”, Write only)
Register Address
Control Data
Figure 14. Control I/F Timing
MS0531-E-00
2006/07
- 20 -
ASAHI KASEI
[AK4346]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4346 supports fast-mode I2C-bus system (max: 400kHz).
Figure 15 shows the data transfer sequence at the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 19). After the
START condition, a slave address is sent. This address is 7 bits long followed by an eighth bit which is a data direction
bit (R/W) (Figure 16). The most significant five bits of the slave address are fixed as “00100”. The next two bits are
CAD1 and CAD0 (chip address bits). The bits identify the specific device on the bus. The hard-wired input pins (CAD1
and CAD0 pins) set them. If the slave address match that of the AK4346 and R/W bit is “0”, the AK4346 generates the
acknowledge and the write operation is executed. If R/W bit is “1”, the AK4346 generates the not acknowledge since the
AK4346 can be only a slave-receiver. The master must generate the acknowledge-related clock pulse and release the
SDA line (HIGH) during the acknowledge clock pulse (Figure 20).
The second byte consists of the address for control registers of the AK4346. The format is MSB first, and those most
significant 3-bits are fixed to zeros (Figure 17). Those data after the second byte contain control data. The format is MSB
first, 8bits (Figure 18). The AK4346 generates an acknowledge after each byte has been received. A data transfer is
always terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL
is HIGH defines a STOP condition (Figure 19).
The AK4346 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the
AK4346 generates an acknowledge, and awaits the next data again. The master can transmit more than one byte instead
of terminating the write cycle after the first data byte is transferred. After the receipt of each data, the internal 5bits
address counter is incremented by one, and the next data is taken into next address automatically. If the addresses exceed
1FH prior to generating the stop condition, the address counter will “roll over” to 00H and the previous data will be
overwritten.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line
can only change when the clock signal on the SCL line is LOW (Figure 21) except for the START and the STOP
condition.
S
T
A
R
T
SDA
S
S
T
O
P
R/W
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+x)
Data(n+1)
A
C
K
A
C
K
A
C
K
A
C
K
P
A
C
K
Figure 15. Data transfer sequence at the I2C-bus mode
0
0
1
0
0
CAD1
CAD0
R/W
(Those CAD1/0 should match with CAD1/0 pins)
Figure 16. The first byte
0
0
0
A4
A3
A2
A1
A0
D2
D1
D0
Figure 17. The second byte
D7
D6
D5
D4
D3
Figure 18. Byte structure after the second byte
MS0531-E-00
2006/07
- 21 -
ASAHI KASEI
[AK4346]
SDA
SCL
S
P
start condition
stop condition
Figure 19. START and STOP conditions
DATA
OUTPUT BY
MASTER
not acknowledge
DATA
OUTPUT BY
SLAVE(AK4359)
acknowledge
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
acknowledgement
START
CONDITION
Figure 20. Acknowledge on the I2 C-bus
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 21. Bit transfer on the I2C-bus
MS0531-E-00
2006/07
- 22 -
ASAHI KASEI
[AK4346]
„ Register Map
Addr
Register Name
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
Control 1
Control 2
Control 3
LOUT1 ATT Control
ROUT1 ATT Control
LOUT2 ATT Control
ROUT2 ATT Control
LOUT3 ATT Control
ROUT3 ATT Control
Reserved
Reserved
Invert Output Signal
DZF1 Control
DZF2 Control
DEM Control
D7
D6
D5
D4
D3
D2
D1
D0
ACKS
0
0
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
1
1
INVL1
L1
L1
0
TDM1
0
PW3
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
1
1
INVR1
R1
R1
0
TDM0
SLOW
PW2
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
1
1
INVL2
L2
L2
0
DIF2
DFS1
0
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
1
1
INVR2
R2
R2
0
DIF1
DFS0
0
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
1
1
INVL3
L3
L3
DEMA
DIF0
DEM1
DZFB
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
1
1
INVR3
R3
R3
DEMB
PW1
DEM0
PW1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
1
1
0
0
0
DEMC
RSTN
SMUTE
0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
1
1
0
0
0
0
Note: For addresses from 0FH to 1FH, data must not be written.
When RSTB pin goes to “L”, the registers are initialized to their default values.
When RSTN bit goes to “0”, the only internal timing is reset, and the registers are not initialized to their default
values. All data can be written to the registers even if PW1-3 bits or RSTN bit is “0”.
„ Register Definitions
Addr
00H
Register Name
Control 1
Default
D7
ACKS
D6
TDM1
D5
TDM0
D4
DIF2
D3
DIF1
D2
DIF0
D1
PW1
D0
RSTN
1
0
0
0
1
0
1
1
RSTN: Internal timing reset
0: Reset. All DZF pins go to “H” and any registers are not initialized.
1: Normal operation
When MCLK frequency or DFS changes, the click noise can be reduced by RSTN bit.
PW1: Power-down control (0: Power-down, 1: Power-up)
PW1: Power down control of DAC1
This bit is duplicated into D1 of 02H.
DIF2-0: Audio data interface modes (See Table 7, Table 8)
Initial: “010”, Mode 2
TDM0-1: TDM Mode Select
Mode
Normal
TDM256
TDM128
TDM1
0
0
1
TDM0
0
1
1
BICK
32fs∼
256fs fixed
128fs fixed
SDTI
1-3
1
1-2
Sampling Speed
Normal, Double, Quad Speed
Normal Speed
Normal, Double Speed
ACKS: Master Clock Frequency Auto Setting Mode Enable
0: Disable, Manual Setting Mode
1: Enable, Auto Setting Mode
Master clock frequency is detected automatically when the ACKS bit = “1”. In this case, the setting of
DFS1-0 bits is ignored. When this bit is “0”, DFS1-0 bits set the sampling speed mode.
MS0531-E-00
2006/07
- 23 -
ASAHI KASEI
Addr
01H
[AK4346]
Register Name
Control 2
D7
0
0
Default
D6
0
0
D5
SLOW
D4
DFS1
D3
DFS0
D2
DEM1
D1
DEM0
D0
SMUTE
0
0
0
0
1
0
SMUTE: Soft Mute Enable
0: Normal operation
1: DAC outputs soft-muted
DEM1-0: De-emphasis Response (See Table 9)
Initial: “01”, OFF
DFS1-0: Sampling speed control (See Table 1)
00: Normal speed
01: Double speed
10: Quad speed
When changing between Normal/Double Speed Mode and Quad Speed Mode, some click noise occurs.
SLOW: Slow Roll-off Filter Enable
0: Sharp Roll-off Filter
1: Slow Roll-off Filter
Adr
Register Name
02H
Speed &
Control
Power
Default
Down
D7
D6
D5
D4
D3
D2
D1
D0
0
PW3
PW2
0
0
DZFB
PW1
0
0
1
1
0
0
0
1
0
PW1: Power-down control (0: Power-down, 1: Power-up)
PW1: Power down control of DAC1
This bit is duplicated into D1 of 00H.
DZFB: Inverting Enable of DZF
0: DZF goes “H” at Zero Detection
1: DZF goes “L” at Zero Detection
PW3-2: Power-down control (0: Power-down, 1: Power-up)
PW2: Power down control of DAC2
PW3: Power down control of DAC3
All sections are powered-down by PW1=PW2=PW3=0.
MS0531-E-00
2006/07
- 24 -
ASAHI KASEI
Addr
03H
04H
05H
06H
07H
08H
Register Name
LOUT1 ATT Control
ROUT1 ATT Control
LOUT2 ATT Control
ROUT2 ATT Control
LOUT3 ATT Control
ROUT3 ATT Control
Default
[AK4346]
D7
ATT7
ATT7
ATT7
ATT7
ATT7
ATT7
1
D6
ATT6
ATT6
ATT6
ATT6
ATT6
ATT6
1
D5
ATT5
ATT5
ATT5
ATT5
ATT5
ATT5
1
D4
ATT4
ATT4
ATT4
ATT4
ATT4
ATT4
1
D3
ATT3
ATT3
ATT3
ATT3
ATT3
ATT3
1
D2
ATT2
ATT2
ATT2
ATT2
ATT2
ATT2
1
D1
ATT1
ATT1
ATT1
ATT1
ATT1
ATT1
1
D0
ATT0
ATT0
ATT0
ATT0
ATT0
ATT0
1
D6
INVR1
0
D5
INVL2
0
D4
INVR2
0
D3
INVL3
0
D2
INVR3
0
D1
0
0
D0
0
0
D5
L2
L2
0
D4
R2
R2
0
D3
L3
L3
0
D2
R3
R3
0
D1
0
0
0
D0
0
0
0
D5
0
0
D4
0
0
D3
DEMA
0
D2
DEMB
0
D1
DEMC
0
D0
0
0
ATT = 20 log10 (ATT_DATA / 255) [dB]
00H: Mute
Addr
0BH
Register Name
Invert Output Signal
Default
D7
INVL1
0
INVL1-3, INVR1-3: Inverting Output Polarity
0: Normal Output
1: Inverted Output
Addr
0CH
0DH
Register Name
DZF1 Control
DZF2 Control
Default
D7
L1
L1
0
D6
R1
R1
0
L1-3, R1-3: Zero Detect Flag Enable for DZF1/2 pins
0: Disable
1: Enable
Addr
0EH
Register Name
DEM Control
Default
D7
0
0
D6
0
0
DEMA-C: De-emphasis Enable of DAC1/2/3
0: Disable
1: Enable
MS0531-E-00
2006/07
- 25 -
ASAHI KASEI
[AK4346]
SYSTEM DESIGN
Figure 22 and 23 shows the system connection diagram. An evaluation board (AKD4346) is available which
demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
Master Clock
1
MCLK
DZF1
30
64fs
2
BICK
TDM0
29
24bit Audio Data
3
SDTI1
AVDD
28
fs
4
LRCK
AVSS
27
Reset
5
RSTB
VCOM
26
6
SMUTE
7
ACKS
8
DIF0
24bit Audio Data
9
24bit Audio Data
10
Microcontroller
Mute Signal
TDM Mode
0.1u 10u
Analog 3.3V
+
+
0.1u 10u
LOUT1
25
MUTE
L1ch Out
ROUT1
24
MUTE
R1ch Out
P/S
23
SDTI2
LOUT2
22
MUTE
L2ch Out
SDTI3
ROUT2
21
MUTE
R2ch Out
AK4346
11
TST1
LOUT3
20
MUTE
L3ch Out
Micro-
12
DIF1
ROUT3
19
MUTE
R3ch Out
controller
13
DEM0
TST3
18
14
DVDD
TST2
17
15
DVSS
DEM1
16
10u
+
Micro-controller
0.1u
Digital 3.3V
Digital Ground
Analog Ground
Figure 22. Typical Connection Diagram (Parallel Control Mode)
Notes:
- LRCK = fs, BICK = 64fs.
- When LOUT/ROUT drives some capacitive load, some resistor should be added in series between LOUT/ROUT
and capacitive load.
- All input pins except P/S and TDM0 pins should not be left floating.
MS0531-E-00
2006/07
- 26 -
ASAHI KASEI
[AK4346]
Master Clock
1
MCLK
DZF1
30
64fs
2
BICK
DZF2
29
24bit Audio Data
3
SDTI1
AVDD
28
fs
4
LRCK
AVSS
27
Reset
5
RSTB
VCOM
26
6
CSN
LOUT1
25
MUTE
L1ch Out
7
CCLK
ROUT1
24
MUTE
R1ch Out
8
CDTI
24bit Audio Data
9
24bit Audio Data
Microcontroller
AK4346
0.1u 10u
Analog 3.3V
+
+
0.1u 10u
P/S
23
SDTI2
LOUT2
22
MUTE
L2ch Out
10
SDTI3
ROUT2
21
MUTE
R2ch Out
11
TST1
LOUT3
20
MUTE
L3ch Out
Micro-
12
DIF1
ROUT3
19
MUTE
R3ch Out
controller
13
CAD0
TST3
18
14
DVDD
TST2
17
15
DVSS
I2C
16
10u
+
0.1u
Digital 3.3V
Digital Ground
Analog Ground
Figure 23. Typical Connection Diagram (3-wire Serial Control Mode)
Notes:
- LRCK = fs, BICK = 64fs.
- When LOUT/ROUT drives some capacitive load, some resistor should be added in series between LOUT/ROUT
and capacitive load.
- All input pins except P/S pin should not be left floating.
- DZF1 control bits must be set to “1” in order to enable the DZF function.
MS0531-E-00
2006/07
- 27 -
ASAHI KASEI
[AK4346]
Analog Ground
Digital Ground
System
Controller
1
MCLK
2
BICK
3
SDTI1
4
DZF1
30
TDM0/DZF2
29
AK4346
AVDD
28
LRCK
AVSS
27
5
PDN
VCOM
26
6
SMUTE/CSN/CAD0
LOUT1
25
7
ACKS/CCLK/CSL
ROUT1
24
8
DFS0/CDT/SDA
P/S
23
9
SDTI2
LOUT2
22
10
SDTI3
ROUT2
21
11
TST1
LOUT3
20
12
DIF1
ROUT3
19
13
DEM0/CAD1
TST3
18
14
DVDD
TST2
17
15
DVSS
DEM1/I2
16
Figure 24. Ground Layout
AVSS and DVSS must be connected to the same analog ground plane.
1. Grounding and Power Supply Decoupling
AVDD and DVDD are usually supplied from the analog supply in the system and it should be separated from system
digital supply. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS
and DVSS of the AK4346 must be connected to the analog ground plane. System analog ground and digital ground
should be connected together close to where the supplies are brought onto the printed circuit board. A decoupling
capacitor, typically a 0.1µF ceramic capacitor for high frequency bypass, should be placed as near to AVDD and DVDD
as possible.
2. Analog Outputs
The analog outputs are single-ended and centered around the VCOM voltage. The output signal range is typically
2.24Vpp (when AVDD=3.3V). The phase of the analog outputs can be inverted channel independently by the
INVL/INVR bits. The internal switched-capacitor filter and continuous-time filter attenuate the noise generated by the
delta-sigma modulator beyond the audio passband. The input data format is 2’s complement. The output voltage is a
positive full scale for 7FFFFFH (@24-bit) and a negative full scale for 800000H (@24-bit). The ideal output is VCOM
voltage for 000000H (@24-bit).
DC offsets on the analog outputs are eliminated by AC coupling since the analog outputs have DC offsets of VCOM + a
few mV.
MS0531-E-00
2006/07
- 28 -
ASAHI KASEI
[AK4346]
PACKAGE
30pin VSOP (Unit: mm)
*9.7±0.1
0.3
30
1.5MAX
16
7.6±0.2
5.6±0.1
A
15
1
0.22±0.1
0.15 +0.10
-0.05
0.65
0.12 M
0.45±0.2
+0.10
0.08
0.10 -0.05
1.2±0.10
Detail A
NOTE: Dimension "*" does not include mold flash.
„ Package & Lead frame material
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0531-E-00
2006/07
- 29 -
ASAHI KASEI
[AK4346]
MARKING (AK4346EF)
AKM
AK4346EF
XXXBYYYYC
XXXBYYYYC
Date code identifier
XXXB: Lot number (X: Digit number, B: Alpha character)
YYYYC: Assembly date (Y: Digit number, C: Alpha character)
MS0531-E-00
2006/07
- 30 -
ASAHI KASEI
[AK4346]
MARKING (AK4346VF)
AKM
AK4346VF
XXXBYYYYC
XXXBYYYYC
Date code identifier
XXXB: Lot number (X: Digit number, B: Alpha character)
YYYYC: Assembly date (Y: Digit number, C: Alpha character)
Date (YY/MM/DD)
06/07/28
Revision
00
Reason
First edition
Page
Contents
IMPORTANT NOTICE
• These products and their specif ications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales off ice or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to
customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of lif e or in
significant injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the saf ety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0531-E-00
2006/07
- 31 -