CD40181BMS CMOS 4 Bit Arithmetic Logic Unit December 1992 Features Description • High Voltage Type (20V Rating) • Full Look Ahead Carry for Speed Operations on Long Words • Generates 16 Logic Functions of Two Boolean Variables • Generates 16 Arithmetic Functions of Two 4 Bit Binary Words • A = B comparator Output Available • Ripple Carry Input and Output Available • Typical Addition Time 200ns at VDD = 10V • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Standardized Symmetrical Output Characteristics • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” The CD40181BMS is a low power four bit parallel arithmetic logic unit (ALU) capable of providing 16 binary arithmetic operations on two four-bit words and 16 logical functions of two Boolean variables. The mode control input M selects logical (M = High) or arithmetic (M = Low) operation. The four select inputs (S0, S1, S2, and S3) select the desired logical or arithmetic functions, which include AND, OR, NAND, NOR and exclusive-OR and-NOR in the logic mode, and addition, subtraction, decrement, left-shift and straight transfer in the arithmetic mode, according to the truth table. The CD40181BMS operation may be interpreted with either active-low or active-high data at the A and B word inputs and the function outputs F, by using the appropriate truth table. Applications • Parallel Arithmetic Units • Process Controllers • Low Power Minicomputers The CD40181BMS contains logic for full look ahead carry operation for fast carry generation using the carry-generate and carry-propagate outputs G and P for the four bits of the CD40181BMS. Use of the CD40182BMS look-ahead carry generator in conjunction with multiple CD40181BMS’s permits high speed arithmetic operations on long words. A ripple carry output Cn+4 is available for use in systems where speed is not of primary importance. Also included in the CD40181BMS is a comparator output A = B, which assumes a high level whenever the two four-bit input words A and B are equal and the device is in the subtract mode. In addition, relative magnitude information may be derived from the carry-in input Cn and ripple carryout output Cn+4 by placing the unit in the subtract mode and externally decoding using the information in Table B. The CD40181BMS is similar to industry types MC14581 and 74181. Pinout CD40181BMS ACTIVE-LOW DATA TOP VIEW B0 1 24 VDD A0 2 23 A1 S3 3 22 B1 S2 4 21 A2 S1 5 20 B2 S0 6 19 A3 Cn 7 18 B3 M 8 17 G F0 9 16 Cn+4 F1 10 15 P F2 11 14 A = B VSS 12 The CD40181BMS is supplied in these 24-lead outline packages: Braze Seal DIP Ceramic Flatpack HNZ H4P 13 F3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1400 File Number 3361 CD40181BMS Functional Diagrams FUNCTION SELECT INPUTS S0 S1 S2 S3 6 WORD A 5 4 3 A0 2 9 F0 A1 23 10 F1 A2 21 11 F2 A3 19 13 F3 14 A = B COMPARE OUT B0 1 B1 22 B2 20 B3 18 Cn CARRY IN MODE M CONTROL 7 17 G 8 15 P WORD B OUTPUT FUNCTION 16 Cn+4 RIPPLE CARRY OUT LOOK AHEAD CARRY OUTPUTS VDD = 24 VSS = 12 ACTIVE-LOW DATA FUNCTION SELECT INPUTS S0 S1 S2 S3 6 WORD A 5 4 3 A0 2 9 F0 A1 23 10 F1 A2 21 11 F2 A3 19 13 F3 14 A = B COMPARE OUT B0 1 B1 22 B2 20 B3 18 Cn CARRY IN MODE M CONTROL 7 17 G 8 15 P WORD B OUTPUT FUNCTION 16 Cn+4 RIPPLE CARRY OUT VDD = 24 VSS = 12 ACTIVE-HIGH DATA 7-1401 LOOK AHEAD CARRY OUTPUTS Specifications CD40181BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage VOL15 VOH15 VDD = 15V, No Load VDD = 15V, No Load (Note 3) LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA 2 +125oC - 1000 µA 3 -55oC - 10 µA 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA Output Current (Sink) Output Current (Source) IOL15 IOH5A VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH15 VNTH VPTH F VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1402 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD40181BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Propagation Delay A or B to F (Logic Mode), A or B to G or P TPHL1 TPLH1 VDD = 5V, VIN = VDD or GND Propagation Delay A or B to F, Cn+4, or A = B TPHL2 TPLH2 VDD = 5V, VIN = VDD or GND Propagation Delay Cn to F TPHL3 TPLH3 VDD = 5V, VIN = VDD or GND Propagation Delay Cn to Cn+4 TPHL4 TPLH4 VDD = 5V, VIN = VDD or GND Transition Time TTHL TTLH CONDITIONS (NOTE 1, 2) GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 +125oC, -55oC +25oC o o MIN MAX UNITS - 800 ns - 1080 ns - 1000 ns 10, 11 +125 C, -55 C - 1350 ns 9 +25oC - 640 ns - 864 ns - 400 ns - 540 ns - 200 ns - 270 ns 10, 11 9 10, 11 VDD = 5V, VIN = VDD or GND +25oC LIMITS 9 10, 11 +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA +125 C - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA -55oC, +25oC - 10 µA +125oC - 600 µA o VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND 1, 2 1, 2 o o Output Voltage VOL VDD = 5V, No Load 1, 2 +25 C, +125 C, -55oC - 50 mV Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V VDD =15V, VOUT = 13.5V 7-1403 1, 2 1, 2 +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA Specifications CD40181BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V 1, 2, 3 +25oC - 320 ns Propagation Delay A or B to F (Logic Mode) A or B to G or P TPHL1 TPLH1 Propagation Delay A or B to F, Cn+4 or A = B VDD = 10V o VDD = 15V 1, 2, 3 +25 C - 240 ns TPHL2 TPLH2 VDD = 10V 1, 2, 3 +25oC - 400 ns VDD = 15V 1, 2, 3 +25oC - 280 ns Propagation Delay Cn to F TPHL3 TPLH3 VDD = 10V 1, 2, 3 +25oC - 270 ns VDD = 15V 1, 2, 3 +25 C - 200 ns Propagation Delay Cn to Cn+4 TPHL4 TPLH4 VDD = 10V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25oC - 140 ns Transition Time Input Capacitance TTHL TTLH CIN o o VDD = 10V 1, 2, 3 +25 C - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns - 7.5 pF Any Input o 1, 2 +25 C NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTND P Threshold Voltage VTP P Threshold Voltage Delta ∆VTPD Functional F CONDITIONS NOTES TEMPERATURE UNITS 1, 4 +25 C - 25 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25 C - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND TPHL TPLH MAX VDD = 10V, ISS = -10µA o 1, 4 +25 C - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns o VDD = 3V, VIN = VDD or GND Propagation Delay Time MIN VDD = 20V, VIN = VDD or GND o VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) 7-1404 Specifications CD40181BMS TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 (Note 1) 9-11, 13-17 1-8, 12, 18-23 24 Static Burn-In 2 (Note 1) 9-11, 13-17 12 1-8, 18-24 Dynamic BurnIn (Note 1) - 4-6, 8, 12 3, 24 9-11, 13-17 12 1-8, 18-24 Irradiation (Note 2) 9V ± -0.5V 50kHz 25kHz 9-11, 13-17 1, 2, 18-23 7 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-1405 CD40181BMS Logic Diagram S3 S2 S1 S0 B3 3* 4* 5* 6* 17 16 15 A3 B2 A2 B1 19* 13 11 F3 F2 22* A=B 23* F1 1* 9 A0 P 21* 10 B0 Cn+4 20* 14 A1 G 18* 2* F0 VDD M n * 8* ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK 7* VSS FIGURE 1. ACTIVE LOW DATA 7-1406 CD40181BMS TRUTH TABLE INPUTS/OUTPUTS ACTIVE LOW FUNCTION SELECT S3 S2 S1 S0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ARITHMETIC* FUNCTION M = L LOGIC FUNCTION M=H A AB A+B Logic 1 A+B B A⊕B A+B AB A⊕B B A+B Logic 0 AB AB A INPUTS/OUTPUTS ACTIVE HIGH FUNCTION SELECT Cn = L Cn = H S3 S2 S1 S0 A minus 1 AB minus 1 AB minus 1 minus 1 A plus (A + B) AB plus (A + B) A minus B minus 1 A+B A plus (A + B) A plus B AB plus (A + B) A+B A plus A AB plus A AB plus A A A AB AB Zero A plus (A + B) plus 1 AB plus (A + B) plus 1 A minus B (A + B) plus 1 A plus (A + B) plus 1 A plus B plus 1 AB plus (A + B) plus 1 A + B plus 1 A plus A plus 1 AB plus A plus 1 AB plus A plus 1 A plus 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ARITHMETIC* FUNCTION M = L LOGIC FUNCTION M=H A A+B AB Logic 0 AB B A⊕B AB A+B A⊕B B AB Logic 1 A+B A+B A Cn = H Cn = L A A+B A+B minus 1 A plus AB (A + B) plus AB A minus B minus 1 AB minus 1 A plus AB A plus B (A + B) plus AB AB minus 1 A plus A (A + B) plus A (A+ B) plus A A minus 1 A plus 1 (A + B) plus 1 (A + B) plus 1 Zero A plus AB plus 1 (A + B) plus AB plus 1 A minus B AB A plus AB plus 1 A plus B plus 1 (A + B) plus AB plus 1 AB A plus A plus 1 (A + B) plus A plus 1 (A + B) plus A plus 1 A * Expressed as two’s complement 1 = High level 0 = Low level AMBIENT TEMPERATURE (TA) = +25oC 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 1407 CD40181BMS 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 0 -5 -10 -15 -10V -20 -25 -15V -30 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -10 -15V FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS -15 FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 800 AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC TRANSITION TIME (tTHL, tTLH) (ns) PROPAGATION DELAY TIME (tPHL, tPLH) (ns) 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 (Continued) OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) Typical Performance Characteristics 600 SUPPLY VOLTAGE (VDD) = 5V 400 200 10V 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 15V 50 15V 0 0 20 60 80 40 LOAD CAPACITANCE (CL) (pF) 0 0 100 FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (FOR A OR B TO F, LOGIC MODE POWER DISSIPATION PER (PD) (µW) 106 8 6 4 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE AMBIENT TEMPERATURE (TA) = +25oC 2 105 SUPPLY VOLTAGE (VDD) = 15V 8 6 4 5V 2 104 10V 8 6 4 2 103 8 6 4 LOAD CAPACITANCE CL = 50pF CL = 15pF 2 102 2 1 4 68 10 2 4 68 2 4 68 2 4 68 102 103 104 INPUT FREQUENCY (fIN) (kHz) 2 4 68 105 FIGURE 8. TYPICAL DYNAMIC DISSIPATION AS A FUNCTION OF INPUT FREQUENCY 7-1408 CD40181BMS TABLE A. AC TEST SETUP REFERENCE (ACTIVE LOW DATA) AC PATHS TEST DELAY TIMES INPUTS DC DATA INPUTS OUTPUTS TO VSS TO VDD MODE* SUMIN to SUMOUT B0 Any F B1, B2, B3, M, Cn All A’s Add SUMIN to P A0 P A1, A2, A3, M, Cn All B’s Add SUMIN to G B0 G All A’s, M, Cn B1, B2, B3 Add SUMIN to Cn+4 B0 Cn+4 All A’s, M, Cn B1, B2, B3 Add Cn to SUMOUT Cn Any F All A’s, M All B’s Add Cn to Cn+4 Cn Cn+4 All A’s, M All B’s Add SUMIN to A = B B0 A=B All A’s, B1, B2, B3, M Cn Subtract SUMIN to SUMOUT (Logic Mode) All B’s Any F All A’s, Cn M Exclusive OR * Add Mode: S0, S3 = VDD; S1, S2 = VSS. Subtract Mode: S0, S3 = VSS; S1, S2 = VDD. TABLE B. MAGNITUDE COMPARISON ACTIVE HIGH DATA ACTIVE LOW DATA INPUT Cn OUTPUT Cn+4 MAGNITUDE INPUT Cn OUTPUT Cn+4 MAGNITUDE 1 1 A≤B 0 0 A≤B 0 1 A<B 1 0 A<B 1 0 A>B 0 1 A>B 0 A≥B 1 1 A≥B 0 1 = High level 0 = Low level Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kÅ − 14kÅ, PASSIVATION: BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 7-1409 AL. 10.4kÅ - 15.6kÅ, Silane 0.0198 inches - 0.0218 inches