INTERSIL CD4070

CD4070BMS
CD4077BMS
CMOS Quad Exclusive OR and
Exclusive NOR Gates
December 1992
Features
Pinouts
CD4070BMS
TOP VIEW
• High Voltage Types (20V Rating)
A 1
14 VDD
B 2
13 H
J = A⊕B 3
12 G
K = C⊕D 4
11 M = G⊕H
• CD4070BMS - Quad Exclusive OR Gate
• CD4077BMS - Quad Exclusive NOR Gate
• Medium Speed Operation
- tPHL, tPLH = 65ns (Typ.) at VDD = 10V, CL = 50pF
• 5V, 10V and 15V Parametric Ratings
• Standardized, Symmetrical Output Characteristics
C 5
10 L = E⊕F
D 6
9 F
VSS 7
8 E
• 100% Tested for Quiescent Current at 20V
CD4077BMS
TOP VIEW
• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
A 1
14 VDD
B 2
13 H
J = A⊕B 3
12 G
K = C⊕D 4
11 M = G⊕H
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
C 5
10 L = E⊕F
D 6
9 F
VSS 7
8 E
Functional Diagram
• Logical Comparators
A
• Parity Generators and Checkers
J = A⊕B
• Adders/Subtractors
K = C⊕D
Description
M = G⊕H
L = E⊕F
CD4070BMS contains four independent Exclusive OR gates.
The CD4077BMS contains four independent Exclusive NOR
gates.
VSS = 7
VDD = 14
B
C
D
E
F
G
H
The CD4070BMS and CD4077BMS provide the system
designer with a means for direct implementation of the
Exclusive OR and Exclusive NOR functions, respectively.
A
B
J = A⊕B
H4Q
Frit Seal DIP
H1B
Ceramic Flatpack
*H4F
*CD4070B Only
†CD4077B Only
†H3W
3
2
5
4
6
8
9
12
13
10
11
J
K
L
M
CD4070BMS
The CD4070BMS and CD4077BMS are supplied in these 14
lead outline packages:
Braze Seal DIP
1
K = C⊕D
C
M = G⊕H
E
L = E⊕F
F
D
G
H
1
3
2
5
4
6
8
9
12
13
10
11
J
K
L
M
CD4077BMS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-455
File Number
3322
Specifications CD4070BMS, CD4077BMS
Absolute Maximum Ratings
Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . .
θja
θjc
Ceramic DIP and FRIT Package . . . . . 80oC/W
20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W
20oC/W
o
Maximum Package Power Dissipation (PD) at +125 C
For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Supply Current
SYMBOL
IDD
CONDITIONS (NOTE 1)
VDD = 20V, VIN = VDD or GND
VDD = 18V, VIN = VDD or GND
Input Leakage Current
IIL
VIN = VDD or GND
VDD = 20
VDD = 18V
Input Leakage Current
IIH
VIN = VDD or GND
VDD = 20
GROUP A
SUBGROUPS
LIMITS
TEMPERATURE
MIN
+25
-
2
µA
+125oC
-
200
µA
3
-55oC
-
2
µA
1
+25o
C
-100
-
nA
2
+125oC
-1000
-
nA
3
-55oC
-100
-
nA
1
+25oC
-
100
nA
2
+125oC
-
1000
nA
-
100
nA
-
50
mV
-
V
3
Output Voltage
VOL15
VDD = 15V, No Load
1, 2, 3
+25oC, +125oC, -55oC
Output Voltage
VOH15
VDD = 15V, No Load (Note 3)
1, 2, 3
+25oC, +125oC, -55oC 14.95
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
UNITS
1
-55oC
VDD = 18V
MAX
2
oC
1
+25oC
0.53
-
mA
Output Current (Sink)
IOL10
VDD = 10V, VOUT = 0.5V
1
+25oC
1.4
-
mA
Output Current (Sink)
IOL15
VDD = 15V, VOUT = 1.5V
1
+25oC
3.5
-
mA
1
+25oC
-
-0.53
mA
1
+25oC
-
-1.8
mA
Output Current (Source)
Output Current (Source)
IOH5A
IOH5B
VDD = 5V, VOUT = 4.6V
VDD = 5V, VOUT = 2.5V
Output Current (Source)
IOH10
VDD = 10V, VOUT = 9.5V
1
+25oC
-
-1.4
mA
Output Current (Source)
IOH15
VDD = 15V, VOUT = 13.5V
1
+25oC
-
-3.5
mA
1
+25oC
-2.8
-0.7
V
1
+25oC
0.7
2.8
V
N Threshold Voltage
P Threshold Voltage
Functional
VNTH
VPTH
F
VDD = 10V, ISS = -10µA
VSS = 0V, IDD = 10µA
VDD = 2.8V, VIN = VDD or GND
7
+25oC
VDD = 20V, VIN = VDD or GND
7
+25oC
VDD = 18V, VIN = VDD or GND
8A
+125oC
VDD = 3V, VIN = VDD or GND
8B
-55oC
VOH > VOL <
VDD/2 VDD/2
V
Input Voltage Low
(Note 2)
VIL
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
-
1.5
V
Input Voltage High
(Note 2)
VIH
VDD = 5V, VOH > 4.5V, VOL < 0.5V
1, 2, 3
+25oC, +125oC, -55oC
3.5
-
V
Input Voltage Low
(Note 2)
VIL
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
-
4
V
Input Voltage High
(Note 2)
VIH
VDD = 15V, VOH > 13.5V,
VOL < 1.5V
1, 2, 3
+25oC, +125oC, -55oC
11
-
V
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
7-456
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
Specifications CD4070BMS, CD4077BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER
Propagation Delay
Transition Time
SYMBOL
TPHL
TPLH
CONDITIONS (NOTES 1, 2)
GROUP A
SUBGROUPS TEMPERATURE
VDD = 5V, VIN = VDD or GND
9
10, 11
TTHL
TTLH
VDD = 5V, VIN = VDD or GND
9
10, 11
+25oC
+125oC,
-55oC
+25oC
+125oC,
-55oC
LIMITS
MIN
MAX
UNITS
-
280
ns
-
378
ns
-
200
ns
-
270
ns
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
Supply Current
SYMBOL
CONDITIONS
NOTES
TEMPERATURE
MIN
MAX
UNITS
IDD
VDD = 5V, VIN = VDD or GND
1, 2
-55oC, +25oC
-
1
µA
+125oC
-
30
µA
µA
VDD = 10V, VIN = VDD or GND
VDD = 15V, VIN = VDD or GND
Output Voltage
VOL
VDD = 5V, No Load
1, 2
1, 2
1, 2
-55oC,
+25oC
-
2
+125oC
-
60
µA
-55oC, +25oC
-
2
µA
+125oC
-
120
µA
+25oC, +125oC,
-
50
mV
-55oC
Output Voltage
VOL
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
-
50
mV
Output Voltage
VOH
VDD = 5V, No Load
1, 2
+25oC, +125oC,
-55oC
4.95
-
V
Output Voltage
VOH
VDD = 10V, No Load
1, 2
+25oC, +125oC,
-55oC
9.95
-
V
Output Current (Sink)
IOL5
VDD = 5V, VOUT = 0.4V
1, 2
+125oC
0.36
-
mA
-55oC
0.64
-
mA
+125oC
0.9
-
mA
-55oC
1.6
-
mA
+125oC
2.4
-
mA
-55oC
4.2
-
mA
+125oC
-
-0.36
mA
-55oC
-
-0.64
mA
+125oC
-
-1.15
mA
-55oC
-
-2.0
mA
+125oC
-
-0.9
mA
-55oC
-
-2.6
mA
+125oC
-
-2.4
mA
-55oC
Output Current (Sink)
Output Current (Sink)
Output Current (Source)
Output Current (Source)
Output Current (Source)
Output Current (Source)
IOL10
IOL15
IOH5A
IOH5B
IOH10
IOH15
VDD = 10V, VOUT = 0.5V
1, 2
VDD = 15V, VOUT = 1.5V
1, 2
VDD = 5V, VOUT = 4.6V
1, 2
VDD = 5V, VOUT = 2.5V
1, 2
VDD = 10V, VOUT = 9.5V
1, 2
VDD =15V, VOUT = 13.5V
1, 2
-
-4.2
mA
Input Voltage Low
VIL
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
-
3
V
Input Voltage High
VIH
VDD = 10V, VOH > 9V, VOL < 1V
1, 2
+25oC, +125oC,
-55oC
7
-
V
7-457
Specifications CD4070BMS, CD4077BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
LIMITS
PARAMETER
SYMBOL
Propagation Delay
TPHL
TPLH
Transition Time
VDD = 15V
TTHL
TTLH
Input Capacitance
CONDITIONS
VDD = 10V
VDD = 10V
VDD = 15V
CIN
Any Input
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 2, 3
+25oC
-
130
ns
1, 2, 3
+25oC
-
100
ns
1, 2, 3
+25oC
-
100
ns
1, 2, 3
+25oC
-
80
ns
1, 2
+25oC
-
7.5
pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
SYMBOL
Supply Current
IDD
CONDITIONS
VDD = 20V, VIN = VDD or GND
NOTES
TEMPERATURE
MIN
MAX
UNITS
1, 4
+25oC
-
7.5
µA
N Threshold Voltage
VNTH
VDD = 10V, ISS = -10µA
1, 4
+25oC
-2.8
-0.2
V
N Threshold Voltage
Delta
∆VTN
VDD = 10V, ISS = -10µA
1, 4
+25oC
-
±1
V
P Threshold Voltage
VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
0.2
2.8
V
P Threshold Voltage
Delta
∆VTP
VSS = 0V, IDD = 10µA
1, 4
+25oC
-
±1
V
1
+25oC
VOH >
VDD/2
VOL <
VDD/2
V
1, 2, 3, 4
+25oC
-
1.35 x
+25oC
Limit
ns
Functional
F
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
Propagation Delay Time
TPHL
TPLH
VDD = 5V
3. See Table 2 for +25oC limit.
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-1
IDD
± 0.2µA
Output Current (Sink)
IOL5
± 20% x Pre-Test Reading
IOH5A
± 20% x Pre-Test Reading
Output Current (Source)
TABLE 6. APPLICABLE SUBGROUPS
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
IDD, IOL5, IOH5A
100% 5004
1, 7, 9, Deltas
100% 5004
1, 7, 9
CONFORMANCE GROUP
PDA (Note 1)
Interim Test 3 (Post Burn-In)
7-458
READ AND RECORD
IDD, IOL5, IOH5A
Specifications CD4070BMS, CD4077BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued)
CONFORMANCE GROUP
PDA (Note 1)
Final Test
Group A
Group B
MIL-STD-883
METHOD
GROUP A SUBGROUPS
100% 5004
1, 7, 9, Deltas
100% 5004
2, 3, 8A, 8B, 10, 11
READ AND RECORD
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Sample 5005
1, 2, 3, 8A, 8B, 9
Group D
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS
TEST
READ AND RECORD
MIL-STD-883
METHOD
PRE-IRRAD
POST-IRRAD
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
1, 9
Table 4
Group E Subgroup 2
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
FUNCTION
OPEN
GROUND
VDD
Static Burn-In 1
Note 1
3, 4, 10, 11
1, 2, 5-9, 12, 13
14
Static Burn-In 2
Note 1
3, 4, 10, 11
7
1, 2, 5, 6, 8,
9, 12-14
Dynamic BurnIn Note 1
-
7
14
3, 4, 10, 11
7
1, 2, 5, 6, 8,
9, 12-14
Irradiation
Note 2
9V ± -0.5V
50kHz
25kHz
3, 4, 10, 11
1, 5, 8, 12
2, 6, 9, 13
NOTE:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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P. O. Box 883, Mail Stop 53-204
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459
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CD4070BMS, CD4077BMS
Schematics
VDD
p
VDD
B*
2 (5, 9, 12)
n
p
n
TRUTH TABLE CD4070BMS
1 OF 4 GATES
p
VSS
p
p
VDD
n
p
A*
J
3 (4, 10, 11)
n
1 (6, 8, 13)
B
J
0
0
0
1
0
1
0
1
1
1
1
0
1 = High Level
0 = Low Level
J = A⊕B
n
VDD
VSS
*
A
VSS
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VSS
FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070BMS (1 OF 4 IDENTICAL GATES)
VDD
VDD
p
p
B*
2 (5, 9, 12)
n
n
n
TRUTH TABLE CD4077BMS
1 OF 4 GATES
p
VSS
p
VDD
J
3 (4, 10, 11)
n
n
p
A*
1 (6, 8, 13)
B
J
0
0
1
1
0
0
0
1
0
1
1
1
1 = High Level
0 = Low Level
J = A⊕B
n
VDD
VSS
*
A
VSS
ALL INPUTS PROTECTED BY
CMOS PROTECTION NETWORK
VSS
FIGURE 2. SCHEMATIC DIAGRAM FOR CD4077BMS (1 OF 4 IDENTICAL GATES)
7-460
CD4070BMS, CD4077BMS
30
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25
20
15
10V
10
5
5V
0
5
10
15
AMBIENT TEMPERATURE (TA) = +25oC
15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
12.5
10.0
10V
7.5
5.0
2.5
5V
0
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
5
10
15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
DRAIN-TO-SOURCE VOLTAGE (VDS) (V)
-15
-10
-5
AMBIENT TEMPERATURE (TA) = +25oC
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
0
-5
-10
-15
-10V
-20
-25
-15V
-30
-5
-10V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
TRANSITION TIME (tTHL, tTLH) (ns)
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
20
-15
FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
200
0
0
-10
-15V
AMBIENT TEMPERATURE (TA) = +25oC
50
0
GATE-TO-SOURCE VOLTAGE (VGS) = -5V
FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
150
0
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
0
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) = +25oC
300
200
SUPPLY VOLTAGE (VDD) = 5V
100
10V
15V
0
40
60
80
100
LOAD CAPACITANCE (CL) (pF)
20
40
60
80
LOAD CAPACITANCE (CL) (pF)
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
FIGURE 8. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
7-461
100
CD4070BMS, CD4077BMS
(Continued)
105
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50pF
POWER DISSIPATION PER GATE (PD) (µW)
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
Typical Performance Characteristics
300
200
100
104
103
5
10
15
AMBIENT TEMPERATURE (TA) = +25oC
6
4
2
SUPPLY VOLTAGE
(VDD) = 15V
6
4
2
102 6
10V
4
2
10V
5V
10
6
4
2
LOAD CAPACITANCE
1 6
10-1
0
6
4
2
20
CL = 50pF
4
2
CL = 15pF
2
10-1
SUPPLY VOLTAGE (VDD) (V)
FIGURE 9. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF SUPPLY VOLTAGE
4 68
2
4 6 8
4 6 8
103
2
4 6 8
104
FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION AS A
FUNCTION OF INPUT FREQUENCY
CD4077BMSH
Dimensions and pad layout for CD4070BMSH are
identical
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
PASSIVATION:
2
1
10
102
INPUT FREQUENCY (fI) (kHz)
Chip Dimensions and Pad Layout
METALLIZATION:
4 6 8
2
Thickness: 11kÅ − 14kÅ,
AL.
10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-462