[AK8160BV2] AK8160BV2 Low Power & Low Jitter Clock Generator for PCI Express 1. General Description The AK8160BV2 is a member of AKM’s low power and low jitter clock generator family designed for PCI Express generation 2.0. This device has one PLL with spread spectrum (SS) function and enables to output high quality differential 100MHz as PCI Express clock and 25MHz as reference simultaneously. 2. Features Low Current Consumption 31mA Typ. (Full function, 25MHz output and 100MHz output) 25MHz Crystal Input or External Clock Input One single-end 25MHz-Reference Output without Spread Spectrum Two differential 100MHz Clock Outputs with Spread Spectrum Selectable Spread Spectrum ON / OFF Spread Spectrum Modulation ratio 0% (Off), -0.5% Spread Spectrum Modulation frequency 30kHz to 33kHz Low Jitter Performance of 100MHz Output Clock RMS Jitter: 2.6ps Max. (PCIE0p-1p/0n-1n pin, BW=10kHz – 1.5MHz) 2.6ps Max. (PCIE0p-1p/0n-1n pin, BW=1.5MHz – 50MHz) Cycle to Cycle Jitter: 125ps Max. (PCIE0p-1p/0n-1n pin) 23ps Typ. (1σ), (REFOUT pin) Supply Voltage 3.0V – 3.6V Operating Temperature Range -40C to +105C Package 0.5mm pitch 4mm x 4mm 20-pin QFN (Lead free) Application - Automotive Infotainment - DSLR : Digital Single-Lens Reflex camera - Network apparatus, Server, Datacenter - MFP : Multi-Function Printer - Game 014003471-E-00 2014/06 -1- [AK8160BV2] 3. Table of Contents 1. General Description........................................................................................................................................1 2. Features ..........................................................................................................................................................1 3. Table of Contents ...........................................................................................................................................2 4. Block Diagram and Functions ........................................................................................................................3 5. Pin Configurations and Functions ..................................................................................................................4 6. Absolute Maximum Ratings ...........................................................................................................................6 7. Recommended Operating Conditions ............................................................................................................6 8. Electrical Characteristics ................................................................................................................................7 9. Recommended External Circuits ..................................................................................................................13 10. Package .......................................................................................................................................................14 11. Important Notice.........................................................................................................................................16 014003471-E-00 2014/06 -2- [AK8160BV2] 4. Block Diagram and Functions VDD1-4 Input : 25[MHz] Crystal or External Clock XIN Crystal OSC REFOUT XOUT 25[MHz] Refout Clock VREF PLL1 (SS) Output Divider REFOUT_OE PCIE0p PCIE0n PCIE1p PCIE1n 100[MHz] PCIe Gen2 PCIE0_OE PCIE1_OE SS_SEL VSS1-4 Figure 1. AK8160BV2 Block Diagram 014003471-E-00 2014/06 -3- [AK8160BV2] 5. Pin Configurations and Functions XOUT VSS2 VDD2 PCIE0_OE PCIE1_OE 15 14 13 12 11 XIN 16 10 PCIE0n VSS1 17 9 PCIE0p VDD1 18 8 PCIE1n REFOUT 19 7 PCIE1p REFOUT_OE 20 6 VSS4 1 2 3 4 5 SS_SEL VSS3 VDD3 VREF VDD4 Figure 2. AK8160BV2 Package: 20-Pin QFN (Top View) Pin No. Pin Name Pin Type 1 SS_SEL DI 2 3 VSS3 VDD3 PWR PWR 4 VREF AO 5 6 VDD4 VSS4 PWR PWR 7 PCIE1p DO 8 PCIE1n DO 9 PCIE0p DO 10 PCIE0n DO Description SS Modulation Control Pin This pin must be connected to “H” or “L”. (1) SS_SEL = “L” : Modulation ratio is 0[%] (Off) SS_SEL = “H” : Modulation ratio is -0.5 [%] Ground pin 3 Power Supply Pin 3 Reference Voltage Generation Pin This pin must be connected to 1F capacitor. This pin goes to Hi-Z when power down. Power Supply Pin 4 Ground Pin 4 PCI Express Gen2 Clock Output pin 1 (Positive) This pin outputs 100MHz. PCI Express Gen2 Clock Output pin 1 (Negative) This pin outputs 100MHz. PCI Express Gen2 Clock Output pin 0 (Positive) This pin outputs 100MHz. PCI Express Gen2 Clock Output pin 0 (Negative) This pin outputs 100MHz. 014003471-E-00 2014/06 -4- [AK8160BV2] 11 PCIE1_OE DI 12 PCIE0_OE DI 13 14 VDD2 VSS2 PWR PWR 15 XOUT AO 16 17 18 19 XIN VSS1 VDD1 REFOUT AI PWR PWR DO 20 REFOUT_OE DI Exposed Pad --- PCIE1p/n Output Control Pin This pin must be connected to “H” or “L”. (1). PCIE1_OE = “L” : PCIE1p/n outputs “L”. PCIE1_OE = “H” : PCIE1p/n outputs 100MHz. PCIE0p/n Output Control Pin This pin must be connected to “H” or “L”. (1) PCIE0_OE = “L” : PCIE0p/n outputs “L”. PCIE0_OE = “H” : PCIE0p/n outputs 100MHz. Power Supply Pin 2 Ground Pin 2 25MHz Crystal Connection Pin OPEN when an External Clock Input is used 25MHz Crystal Connection Pin or External Clock Input Pin Ground Pin 1 Power Supply Pin 1 25MHz Output Pin 25MHz Output Control Pin This pin must be connected to “H” or “L”. (1) REFOUT_OE = “L” : REFOUT outputs “L”. REFOUT_OE = “H” : REFOUT outputs 25MHz. Connecting exposed pad of package to board ground must be required. Note: (1) This pin is recommended to connect with more than 10[k] resistor as pull-up or pull-down. If the device is mounted with wrong angle on the PCB, the resistor can prevent the device from overcurrent. (2) AI : Analog input pin AO : Analog output pin DI : Digital input pin DO : Digital output pin PWR : Power supply and Ground pin 014003471-E-00 2014/06 -5- [AK8160BV2] 6. Absolute Maximum Ratings Over operating free-air temperature range unless otherwise noted (1) Items Symbol Ratings Unit Supply voltage VDD -0.3 to 4.6 V Input voltage Vin VSS-0.3 to VDD+0.3 V Input current (any pins except supplies) IIN ±10 mA Storage temperature Tstg -65 to 150 C Note (1) Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to absolute-maximum-rating conditions for extended periods may affect device reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. This device is manufactured on a CMOS process, therefore, generically susceptible to damage by excessive static voltage. Failure to observe proper handling and installation procedures can cause damage. AKM recommends that this device is handled with appropriate precautions. ESD Sensitive Device 7. Recommended Operating Conditions Parameter Symbol Conditions Min Typ Max Unit Operating temperature Ta -40 105 C (1) Supply voltage VDD Pin: VDD1 - 4 3.0 3.3 3.6 V Output Load Capacitance Cpl Pin: REFOUT 25 pF Note: (1) Power to VDD1 – VDD4 requires to be supplied from a single source. A decoupling capacitor of 0.1μF for power supply line should be connected close to each VDD pin. 014003471-E-00 2014/06 -6- [AK8160BV2] 8. Electrical Characteristics Current Consumption All specifications at VDD: 3.0V to 3.6V, Ta: -40 to +105C, 25MHz Crystal, unless otherwise noted Parameter Symbol Conditions Min Typ Max Unit Current Consumption 1 IDD1 (1), (2) Current Consumption 2 IDD2 (1), (3) Current Consumption 3 IDD3 (1), (4) Note: (1) REFOUT : No load, PCIE0p/n, PCIE1p/n : CL=2[pF] (2) Full function REFOUT output, 100MHz output *REFOUT_OE = PCIE0_OE = PCIE1_OE = SS_SEL = “H” (3) REFOUT output off, 100MHz output *REFOUT_OE = “L”, PCIE0_OE = PCIE1_OE = SS_SEL = “H” (4) Full power down * REFOUT_OE = PCIE0_OE = PCIE1_OE = “L” 31 30 0 38 37 100 mA mA A DC Characteristics All specifications at VDD: 3.0V to 3.6V, Ta: -40 to +105C, 25MHz Crystal, unless otherwise noted Parameter Symbol Conditions Min Typ Max REFOUT_OE pin PCIE0_OE pin High Level Input Voltage VIH 0.7*VDD PCIE1_OE pin SS_SEL pin REFOUT_OE pin PCIE0_OE pin Low Level Input Voltage VIL 0.3*VDD PCIE1_OE pin SS_SEL pin REFOUT_OE pin PCIE0_OE pin Input Leakage Current IL -1 +1 PCIE1_OE pin SS_SEL pin VREF pin VREF Output Voltage VREF 0.72 0.8 0.88 CVREF = 1F REFOUT pin High Level Output Voltage VOH 0.8*VDD IOH = -4mA REFOUT pin Low level Output Voltage VOL 0.2*VDD IOL = 4mA 014003471-E-00 Unit V V A V V V 2014/06 -7- [AK8160BV2] AC Characteristics (except Differential Output) All specifications at VDD: 3.0V to 3.6V, Ta: -40 to +105C, 25MHz Crystal, unless otherwise noted Parameter Symbol Conditions Min Typ Max Crystal Clock Frequency Oscillation Accuracy External Clock Frequency Input Clock Voltage Swing Input Clock Duty Cycle Output Frequency Output Rising and Falling Output Clock Duty Cycle Fin_xo XIN pin XOUT pin Faccuracy Fin_ext Vswing_ext Textindc Fosc TRF Toutdc_xtal (4) Toutdc_ext (5) Jitc2c Tlock REFOUT pin (1) XIN pin (2) XIN pin (2) XIN pin (2) REFOUT pin REFOUT pin (3) REFOUT pin REFOUT pin REFOUT pin (6) REFOUT pin (7) 25.000 -30 0 25.000 1 45 40 MHz +30 VDD 50 25.000 1.8 50 50 23 0.5 Unit 5.0 55 60 48 2 ppm MHz Vpp % MHz ns % % ps ms Cycle to Cycle Jitter Output Lock Time Note: (1) Specification of Frequency Accuracy is measured by connecting the standard 25MHz crystal unit for part number XRCGB25M000F3M00R0 of Murata Manufacturing Co., Ltd. on page 11. This Output Clock Frequency Accuracy does not include accuracy of crystal unit. Total output clock frequency accuracy could be up to “Output Clock Frequency Accuracy” + “Crystal unit accuracy”. (2) Use Case of External Clock Input (3) Transition time between 0.2VDD and 0.8VDD (4) When the standard 25MHz Crystal Unit is connected. (5) When the Duty Cycle of External Clock Input is 50%. (6) 1σ in 10000 sampling or more (7) Transition time to settle output into ±0.1% of specified frequency after escaping power down mode. (REFOUT_OE pin = PCIE0_OE pin = PCIE1_OE pin = ‘L’). 014003471-E-00 2014/06 -8- [AK8160BV2] AC Characteristics (Differential Output pin : PCIE0p-1p/0n-1n pin) All specifications at VDD: 3.0V to 3.6V, Ta: -40 to +105C, 25MHz Crystal, unless otherwise noted Parameter Symbol Conditions Min Typ Max Average Output Frequency Fin SS Off (1) SS On (1) 99.97 99.47 100.000 100.03 100.03 250 MHz MHz ps 2.5 4.0 8.0 V/ns -150 550 mV mV mV 140 mV 100 mV Output Skew Tslew Slew Rate of Output Rising and Falling Tslew Differential Figure 6 High Level Output Voltage Low Level Output Voltage Output Cross Point Voltage VIH VIL Vcross Differential Differential Figure 4 Output Cross Point Voltage Deviation Vcross_delta Figure 5 Output Ring Back Voltage Margin Vrb Figure 9 -100 Tstable Figure 10 500 Output Ring Back Time 150 250 Average Clock Period Accuracy Tperiod_avg Absolute Period Tperiod_abs Figure 8 Maximum Output Voltage Vmax Single End Figure 4 Minimum Output Voltage Vmin Single End Figure 4 -0.3 Output Duty Cycle Toutdc Figure 8 45 Tslew_delta Figure 7 Time Matching of Output Rising and Falling Parameter PCI Express Gen2 RMS Jitter Symbol JitRMS Unit Conditions BW= 10kHz - 1.5MHz (2) BW= 1.5MHz - 50MHz (2) (3) SS Off (4) ps -300 2800 ppm 9.847 10.203 ns 1.15 V Min V 50 55 % 20 % Typ Max Unit 0.5 2.6 ps 1.2 2.6 ps Cycle to Cycle Jitter (p-p) Jitc2c 60 125 ps Output Lock Time Tlock 0.5 2 ms Note: (1) Specification of Frequency Accuracy is measured by connecting the standard 25MHz crystal unit for part number XRCGB25M000F3M00R0 of Murata Manufacturing Co., Ltd. on page 11. This Output Clock Frequency Accuracy does not include accuracy of crystal unit. Total output clock frequency accuracy could be up to “Output Clock Frequency Accuracy” + “Crystal unit accuracy”. (2) The specifications are values applied the jitter filter function specified PCI Express standard. (3) ±7σ in 10000 sampling or more (4) Transition time to settle output into ±0.1% of specified frequency after escaping power down mode. (PCIE0_OE pin = PCIE1_OE pin = ‘L’). 014003471-E-00 2014/06 -9- [AK8160BV2] Differential Output Measurement Circuit Each Characteristic is measured at the point of “Measure point” in Figure 3 3.3V Measure point < 5inch PLL Core 2pF Vref 1F 2pF Z=100 Differential Traces Figure 3. Differential Output Measurement Circuit Definition of Differential Output AC Characteristics Voh_max=1.15V PCIE0/1p Voh Vcross_max=550mV Vcross Vol Vcross_min=250mV PCIE0/1n Vol_min=-0.3V Figure 4. Definition of High / Low Level Voltage, Output Cross Point Voltage PCIE0/1p Vcross_delta_max=140mV Vcross_delta PCIE0/1n Figure 5. Definition of Output Cross Point Voltage Deviation Rer +150mV -150mV Differential (PCIE0/1p)-(PCIE0/1n) Fer Figure 6. Definition of Output Slew Rate 014003471-E-00 2014/06 - 10 - [AK8160BV2] PCIE0/1p Vcross_median +75mV Vcross_median Vcross_median Tr Tf -75mV PCIE0/1n Tslew_delta (%) = 100 * 2 * (Tr - Tf) / (Tr + Tf) Figure 7. Definition of Time Matching of Output Rising and Falling Tperiod Thigh 0.0V Differential (PCIE0/1p)-(PCIE0/1n) Toutdc (%) = 100 * Thigh / Tperiod Figure 8. Definition of Output Duty Cycle Ring Back Vrb_max=100mV Vrb_min=-100mV Prohibited Ring Back Voltage Range Ring Back Differential (PCIE0/1p)-(PCIE0/1n) Figure 9. Definition of Output Ring Back Voltage Margin Tstable +150mV -150mV Differential (PCIE0/1p)-(PCIE0/1n) Tstable Figure 10. Definition of Output Ring Back Time 014003471-E-00 2014/06 - 11 - [AK8160BV2] Crystal Specification Murata Manufacturing Co.,Ltd, XRCGB25M000F3M00R0 Parameter Crystal Clock Frequency Series Resistance Shunt Capacitance Motional Capacitance Motional Inductance Power level Symbol f0 R1 C0 C1 L1 Conditions CL=6[pF] Min Typ 25.000 56.9 0.59 1.29 31.52 Max 150 300 L1 R1 Unit MHz Ω pF fF mH W C1 Crystal C0 Load Capacitance CL CL Figure 11. Equivalent parameters of crystal and load capacitance 014003471-E-00 2014/06 - 12 - [AK8160BV2] 9. Recommended External Circuits C1 : 0.1F 3.3V (TYP) L C2, C3 : 1F L : Bead Cext1, Cext2: Depends on crystal characteristic Refer the specification of the crystal. C3 Cext2 14 PCIE1_OE VSS2 15 VDD2 XOUT Crystal 25MHz PCIE0_OE C1 13 12 11 Cext1 XIN 16 10 PCIE0n VSS1 17 9 PCIE0p VDD1 18 8 PCIE1n REFOUT 19 7 PCIE1p REFOUT_OE 20 6 VSS4 C1 Digital Input 1 2 3 4 PCI Express Device SS_SEL VSS3 VDD3 VREF Reference Output 25MHz 5 VDD4 C1 C2 C1 Figure 12. Recommended External Circuits PCB Layout Consideration The AK8160BV2 is a high-accuracy and low-jitter clock generator. For proper performances specified in this datasheet, careful PCB layout should be taken. The followings are layout guidelines based on the typical connection diagram shown in Figure 12. Power supply line & Ground pin connection AK8160BV2 has four power supply pins (VDD1-4) which deliver power to internal circuitry segments. And AK8160BV2 has four ground pins (VSS1-4). These pins require connecting to plane ground which will eliminate any common impedance with other critical switching signal return. 0.1F decoupling capacitors placed at VDD1, VDD2, VDD3 and VDD4 should be grounded at close to the VSS1pin, the VSS2 pin, VSS3 pin and the VSS4 pin, respectively. Crystal connection Proper oscillation performance are susceptible to stray or parasitic capacitors around crystal. The wiring traces to a crystal form XIN (Pin 16) and XOUT (Pin 15) have equal lengths with no via and as short in length as possible. These traces should be also located away from any traces with switching signal. 014003471-E-00 2014/06 - 13 - [AK8160BV2] 10. Package Outline Dimensions 0.5mm pitch 4mm x 4mm 20-pin QFN (Unit: mm) 0.75±0.05 2.10±0.10 B 16 20 C0.35 15 5 11 10 6 0.55±0.10 4.00±0.10 2.10±0.10 1 A 0.10 M C A B 0.05MAX 4.00±0.10 0.25±0.05 0.08 C 0.50TYP Ｃ Package & Lead Frame Material Package molding compound : Epoxy Resin (Green Compound) Lead frame material : Cu Lead frame surface treatment : 100% Sn 014003471-E-00 2014/06 - 14 - [AK8160BV2] Marking a: #1 Pin Index : Circle b: Part number : 160BV2 c: Date code : 4 digits b 15 14 13 12 11 16 10 17 9 160BV2 xxxx 18 19 8 7 6 20 1 a 2 3 4 5 C Revision History Date Revision Reason 14/06/24 00 Initial Release. Page/Line 014003471-E-00 Contents 2014/06 - 15 - [AK8160BV2] 11. Important Notice IMPORTANT NOTICE 0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information contained in this document without notice. When you consider any use or application of AKM product stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized distributors as to current status of the Products. 1. All information included in this document are provided only to illustrate the operation and application examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of AKM or any third party with respect to the information in this document. You are fully responsible for use of such information contained in this document in your product design or applications. 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This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of AKM. 014003471-E-00 2014/06 - 16 -