CY24293
Two Outputs PCI-Express Clock Generator
Two Outputs PCI-Express Clock Generator
Features
Functional Description
■
25 MHz crystal or clock input
CY24293 is a two output PCI-Express clock generator device
intended for networking applications. The device takes 25 MHz
crystal or clock input and provides two pairs of differential outputs
at 25 MHz, 100 MHz, 125 MHz, or 200 MHz for HCSL signaling
standard.
■
Two sets of differential PCI-Express clocks
■
Pin selectable output frequencies
■
Supports HCSL compatible output levels
■
Spread Spectrum capability on all output clocks with pin
selectable spread range
The device incorporates Lexmark Spread Spectrum profile for
maximum electromagnetic interference (EMI) reduction. The
spread type and amount can be selected using select pins.
■
16-pin TSSOP package
For a complete list of related documentation, click here.
■
Operating voltage 3.3 V
■
Commercial, Industrial operating temperature range
Logic Block Diagram
VDDX
XIN/EXCLKIN
Clock Buffer/
Crystal
Oscillator
(25 MHz)
XOUT
VDDO
PCIE0P
PCIE0N
PLL Clock
Synthesizer
SS0
PCIE1P
SS1
PCIE1N
Control
Logic
S0
S1
I REF
OE
GNDX
Cypress Semiconductor Corporation
Document Number: 001-46117 Rev. *I
•
198 Champion Court
GNDO
•
R REF= 475 Ohms 1%
San Jose, CA 95134-1709
•
408-943-2600
Revised May 23, 2016
CY24293
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Output Frequency Selection Table ................................. 4
Spread Selection Table .................................................... 4
Application Information ................................................... 5
Crystal Recommendations .......................................... 5
Crystal Loading ........................................................... 5
Calculating Load Capacitors ....................................... 5
Current Source (Iref) Reference Resistor .................... 5
Output Termination ...................................................... 6
Decoupling Capacitors ................................................ 6
PCI-Express (HCSL compatible) Layout Guidelines ..... 6
Absolute Maximum Ratings ............................................ 7
Recommended Operation Conditions ............................ 7
DC Electrical Characteristics .......................................... 7
Thermal Resistance .......................................................... 8
AC Electrical Characteristics .......................................... 8
Document Number: 001-46117 Rev. *I
AC Electrical Characteristics .......................................... 9
Test and Measurement Setup .......................................... 9
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagram ............................................................ 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC®Solutions ....................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Page 2 of 15
CY24293
Pinouts
Figure 1. 16-pin TSSOP pinout
S0
S1
1
16
VDDX
2
15
PCIE0P
SS0
XIN/EXCLKIN
3
4
14
13
PCIE0N
GNDO
XOUT
5
12
VDDO
OE
6
11
PCIE1P
GNDX
7
10
SS1
8
9
TSSOP
PCIE1N
IREF
Pin Definitions
16-pin TSSOP
Pin Number
1
2
3
Pin Name
Pin Type
Description
S0
Input
Frequency select pin. Has internal weak pull-up. Refer to Output Frequency Selection
Table on page 4.
S1
Input
Frequency select pin. Has internal weak pull-up. Refer to Output Frequency Selection
Table on page 4.
SS0[1]
Input
Spread spectrum select pin 0. Has internal weak pull-up. Refer to Spread Selection Table
on page 4.
4
XIN/EXCLKIN Input
Crystal or clock input. 25 MHz fundamental mode crystal or clock input.
5
XOUT
Output
Crystal output. 25 MHz fundamental mode crystal input. Float for clock input.
OE
Input
High true output enable pin. When set low, PCI-E outputs are tri-stated. Has internal weak
pull-up.
GNDX
Power
Ground
SS1[1]
Input
Spread spectrum select pin 1. has internal weak pull-up. Refer to Spread Selection Table
on page 4.
6
7
8
9
IREF
Output
Current set for all differential clock drivers. Connect 475 resistor to ground.
10
PCIE1N
Output
Differential PCI-Express complementary clock output. Tristated when disabled.
Output
Differential PCI-Express true clock output. Tristated when disabled.
11
PCIE1P
12
VDDO[2]
Input
3.3 V Power supply for output driver and analog circuits.
13
GNDO
Power
Ground
14
PCIE0N
Output
Differential PCI-Express complementary clock output. Tristated when disabled.
15
PCIE0P
Output
Differential PCI-Express true clock output. Tristated when disabled.
16
VDDX[2]
Input
3.3 V Power supply for oscillator and digital circuits.
Notes
1. Once powered up, state of SS1/SS0 pins should be held constant at the desired state.
2. VDDX must be supplied faster or equal to VDDO.
Document Number: 001-46117 Rev. *I
Page 3 of 15
CY24293
Output Frequency Selection Table
S1
S0
PCIE0[N,P], PCIE1[N,P]
0
0
25 MHz
0
1
100 MHz
1
0
125 MHz
1
1
200 MHz
Spread Selection Table
SS1 [3]
SS0 [3]
Spread%
0
0
No Spread
0
1
–0.5%
1
0
–0.75%
1
1
No Spread
Note
3. Once powered up, state of SS1/SS0 pins should be held constant at the desired state.
Document Number: 001-46117 Rev. *I
Page 4 of 15
CY24293
Application Information
Crystal Recommendations
CY24293 requires a parallel resonance crystal. Substituting a series resonance crystal causes the CY24293 to operate at the wrong
frequency and violate the ppm specification. For most applications, there is a 300 ppm frequency shift between series and parallel
crystals due to incorrect loading.
Table 1. Crystal Recommendations
Frequency
Cut
Load Cap
Eff Series Rest
(max)
25.00 MHz
Parallel
16 pF
30
Crystal Loading
Crystal loading plays a critical role in achieving low ppm
performance. To realize low ppm performance, consider the total
capacitance the crystal sees to calculate the appropriate
capacitive loading (CL).
Figure 2 shows a typical crystal configuration using two trim
capacitors. It is important to note that the trim capacitors in series
with the crystal are not parallel. It is a common misconception
that load capacitors are in parallel with the crystal and must be
approximately equal to the load capacitance of the crystal. This
is not true.
Figure 2. Crystal Loading Example
C lock C hip
Drive (max) Tolerance (max) Stability (max) Aging (max)
1.0 mW
30 ppm
10 ppm
5 ppm/yr.
Use the following formulas to calculate the trim capacitor values
for Ce1 and Ce2:
Load capacitance (each side)
Ce = 2 * CL – (Cs + Ci)
Total capacitance (as seen by the crystal)
CLe
=
1
( Ce1 + Cs1
+ Ci1
1
+
1
Ce2 + Cs2 + Ci2
)
CL .................................................. Crystal load capacitance
CLe ........................................ Actual loading seen by crystal
using standard value trim capacitors
Ce .................................................... External trim capacitors
Cs .............................................Stray capacitance (terraced)
Ci2
Ci .......................................................... Internal capacitance
Pin
3 to 6p
X2
X1
C s1
C s2
T race
2.8 pF
XTAL
Ce1
C e2
T rim
26 pF
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading.
As mentioned in the previous section, the capacitance on each
side of the crystal is in series with the crystal. This means the
total capacitance on each side of the crystal must be twice the
specified crystal load capacitance (CL). While the capacitance
on each side of the crystal is in series with the crystal, trim
capacitors (Ce1, Ce2) must be calculated to provide equal
capacitive loading on both sides.
Document Number: 001-46117 Rev. *I
Current Source (IREF) Reference Resistor
If the board target trace impedance (Z) is 50 , then for
RREF = 475 (1%, provides IREF of 2.32 mA. The output
current (IOH) is equal to 6*IREF. For other values of RREF, the
following graph can be referred. It demonstrates the relationship
of variation of IREF w.r.t. rise time /fall time (TR/TF).
Figure 3. IREF vs. TR/TF relationship (Typical)
Rise Time (single ended waveform,
measured from 0.175V to 0.525V)
C i1
240
220
200
180
160
140
120
100
420
440
460
min
480
typ
500
520
max
IREF Resistor value ()
Page 5 of 15
CY24293
3. The PCB trace to the VDD pin and the ground via must be kept
as short as possible. Distance of the ferrite bead and bulk
decoupling from the device is less critical.
4. An optimum layout is one with all components on the same
side of the board, minimizing vias through other signal layers
(any ferrite beads and bulk decoupling capacitors can be
mounted on the back). Other signal traces must be routed
away from the CY24293. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
Output Termination
The PCI-Express differential clock outputs of the CY24293 are
open source drivers and require an external series resistor and
a resistor to ground. These resistor values and their allowable
locations are explained in Figure 4.
PCB Layout Recommendations
For optimum device performance and the lowest phase noise,
the following guidelines must be observed:
1. Each 0.01 µF decoupling capacitor must be mounted on the
component side of the board as close to the VDD pin as
possible.
2. No vias must be used between the decoupling capacitor and
the VDD pin.
Decoupling Capacitors
The decoupling capacitors of 0.01 µF must be connected
between VDD and GND as close to the device as possible. Do
not share ground vias between components. Route power from
the power source through the capacitor pad and then into the
CY24293 pin.
PCI-Express (HCSL compatible) Layout Guidelines
Table 2. Common Recommendations for Differential Routing
Differential Routing
Dimension or Value
Unit
L1 length, route as non-coupled 50 trace
0.5 max
inch
L2 length, route as non-coupled 50 trace
0.2 max
inch
L3 length, route as non-coupled 50 trace
0.2 max
inch
RS
33
RT
49.9
Dimension or Value
Unit
Table 3. Differential Routing for PCI-Express Load or Connector
Differential Routing
L4 length, route as coupled microstrip 100 differential trace
L4 length, route as coupled stripline 100 differential trace
2 to 32
inch
1.8 to 30
inch
Figure 4. PCI-Express Differential Routing
Rs
L1
L2
L4
L2
L4
RS
L1
RT
Output Buffer
Document Number: 001-46117 Rev. *I
L3
RT
L3
PCI Express Load or
Connector
Page 6 of 15
CY24293
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Parameter
Description
Condition
Min
Max
Unit
–0.5
4.6
V
–0.5
VDD + 0.5
V
VDD
Supply voltage
VIN
Input voltage
TS
Temperature, Storage
Non Functional
–65
+150
°C
TJ
Temperature, Junction
Non Functional
–65
+150
°C
2000
–
V
Relative to VSS
ESDHBM
ESD Protection (Human Body Model)
JEDEC EIA/JESD22-A114-E
UL-94
Flammability rating
–
V-0 at 1/8 in.
MSL
Moisture sensitivity level
–
3
Recommended Operation Conditions
Parameter
Description
Min
Typ
Max
Unit
3.0
–
3.6
V
0
–
+70
°C
VDD
Supply voltage
TAC
Commercial ambient temperature
TAI/AA
Industrial ambient temperature
–40
–
+85
°C
tPU
Power up time for all VDD to reach minimum specified voltage (power
ramps must be monotonic)
0.05
–
500
ms
DC Electrical Characteristics
Unless otherwise stated, VDD = 3.3 V ± 0.3 V, ambient temperature = –40 °C to +85 °C Industrial, 0 °C to +70 °C Commercial
Parameter [4]
Description
VIL
Input low voltage
Condition
–
Min
Typ
Max
Unit
–0.3
–
0.8
V
VIH
Input high voltage
–
2.0
–
VDD + 0.3
V
VOL
Output low voltage of PCIE0[P/N],
PCIE1[P/N]
HCSL termination (RS = 33
RT = 49.9 ). See note
19.
–0.2
0
0.05
V
VOH
Output high voltage of PCIE0[P/N],
PCIE1[P/N]
HCSL termination (RS = 33
RT = 49.9 ). See note
19.
0.65
0.71
0.95
V
IDD
Operating supply current
No load, OE = 1
–
45
60
mA
IDDOD
Output disabled current
OE = 0
–
–
50
mA
CIN
Input capacitance
All input pins
–
5
–
pF
RPU
Pull-up resistance
S0, S1, SS0, SS1, OE
–
70k
–
Note
4. Parameters are guaranteed by design and characterization. Not 100% tested in production.
Document Number: 001-46117 Rev. *I
Page 7 of 15
CY24293
Thermal Resistance
Parameter [5]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
16-pin TSSOP Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
89
°C/W
12
°C/W
AC Electrical Characteristics
Unless otherwise stated: VDD = 3.3 V ± 0.3 V, ambient temperature = –40 °C to +85 °C Industrial, 0 °C to +70 °C Commercial, Outputs
HCSL terminated.
Parameter [6]
Min
Typ
Max
Unit
FIN
Input clock frequency (crystal or
external clock)
Description
–
Condition
–
25
–
MHz
FOUT
Output frequency
HCSL termination
–
–
200
MHz
FERR
Frequency synthesis error
–
–
0
–
ppm
TCCJ
Cycle-to-cycle jitter
See notes 7, 8
–
–
75
ps
SPPROFILE
Spread modulation profile
–
–
Lexmark
type
SPMOD
Spread modulation frequency
30
32
33
kHz
Output clock duty cycle
See notes: 7, 9
45
50
55
%
TOEH
Output enable time
OE going high to differential
outputs becoming valid
–
–
200
ns
TOEL
Output disable time
OE going low to differential outputs
becoming invalid
–
–
200
ns
TLOCK
Clock stabilization from power up
Measured from 90% of the applied
power supply level
–
1
2
ms
TR
Output rise time
Measured from 0.175 V to 0.525 V.
See notes: 7, 10
130
–
700
ps
TF
Output fall time
Measured from 0.525 V to 0.175 V.
See notes: 7, 10
130
–
700
ps
DTR
Rise time variation
For a given frequency,
Max (TR) – Min (TR)
–
–
125
ps
DTF
Fall time variation
For a given frequency,
Max (TF) – Min (TF)
–
–
125
ps
TOSKEW
Output skew
Measured at VCROSS point.
See note: 11
–
–
50
ps
VCROSS
Absolute crossing point voltage
See notes: 9, 10, 12
0.25
0.35
0.55
V
VXdelta
Variation of VCROSS over all rising
clock edges
See notes: 9, 10, 13
–
–
140
mV
TDC
Notes
5. These parameters are guaranteed by design and are not tested.
6. Parameters are guaranteed by design and characterization. Not 100% tested in production.
7. Measured with Cload = 4 pF max. (scope probe + trace load).
8. Measurement taken from differential waveform (PCIEP minus PCIEN). Either single ended probes with math or a differential probe can be used.
9. Measured at crossing point where the instantaneous voltage value of the rising edge of PCIEP equals the falling edge of PCIEN.
10. Measurement taken from single ended waveform.
11. Measured at the rising 0V point of the differential signal. Skew is the time difference of the rising 0V point between any two differential signal pairs. The measurement
is taken over 1000 samples, and the average value is used.
12. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement.
13. Defined as the total variation of all crossing voltages of Rising PCIEP and Falling PCIEN. This is the maximum allowed variance in VCROSS for any particular system.
Document Number: 001-46117 Rev. *I
Page 8 of 15
CY24293
AC Electrical Characteristics
Differential 100 MHz, HCSL Terminated Outputs (Parameters for the PCI Express Specification. Use above AC Characteristics
parameter where it is not listed in this section)
Parameter
FOUT
Description
Test Conditions
Min
Output frequency
Typ
Max
Units
–
–
100
MHz
–
30
86
ps
TPHJ
Peak-to-peak phase jitter
10-6 BER. Note: 14
ERR
Rising edge rate
See notes: 15, 16
0.6
1.3
4.0
V/ns
ERF
Falling edge rate
See notes: 15, 16
0.6
1.3
4.0
V/ns
TPERIOD AVG
Average clock period accuracy
See notes: 15, 17
–300
–
2800
ppm
TPERIOD ABS
Absolute clock period
See notes: 15, 18
9.847
–
10.203
ns
RFMATCHING
Rising edge rate to falling edge
rate matching
See note: 19, 20
–
–
20
%
Test and Measurement Setup
Figure 5. Test Load Configuration for Differential Output Signals
33 Ohm
PCIEP
CLoad
50 Ohm
CLoad
50 Ohm
33 Ohm
PCIEN
475
Ohm
Notes
14. Phase jitter is determined using data captured on an oscilloscope at a sample rate of 20 GS/sec, for a minimum 100,000 continuous clock periods. This data is then
processed using the ClockJitter 1.3.0 software from PCISIG, using the PCI_E_1_1 template.
15. Measurement taken from differential waveform (PCIEP minus PCIEN). Either single ended probes with math or a differential probe can be used.
16. Measured from -150 mV to +150 mV on the differential waveform (derived from PCIEP minus PCIEN). The signal must be monotonic through the measurement region
for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
17. PPM refers to parts per million and is a DC absolute period accuracy specification. The period is to be measured with a frequency counter with measurement window
set to 100 ms or greater. The ±300 PPM applies to systems that do not employ Spread Spectrum or that use common clock source. For systems employing Spread
Spectrum, there is an additional 2500 PPM nominal shift in maximum period resulting from the 0.5% down spread, resulting in a maximum average period specification
of +2800 PPM.
18. Defined as the absolute minimum or maximum instantaneous period. This includes cycle-to-cycle jitter, relative PPM tolerance, and spread spectrum modulation.
19. Measurement taken from single ended waveform.
20. Matching applies to rising edge rate for PCIEP and falling edge for PCIEN. It is measured using a ± 75mV window centered on the median cross point where PCIEP
rising meets PCIEN falling.
Document Number: 001-46117 Rev. *I
Page 9 of 15
CY24293
Ordering Information
Part Number
Type
Production Flow
Pb-free
CY24293ZXC
16-pin TSSOP
Commercial, 0 °C to 70 °C
CY24293ZXCT
16-pin TSSOP – Tape and Reel
Commercial, 0 °C to 70 °C
CY24293ZXI
16-pin TSSOP
Industrial, –40 °C to 85 °C
CY24293ZXIT
16-pin TSSOP – Tape and Reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 24293
Z
X
X
X
X = T or blank
T = Tape and Reel; blank = Tube
Temperature Range: X = C or I
C = Commercial, I = Industrial
Pb-free
Package Type:
Z = 16-pin TSSOP
Base Device Part Number
Company ID: CY = Cypress
Document Number: 001-46117 Rev. *I
Page 10 of 15
CY24293
Package Diagram
Figure 6. 16-pin TSSOP 4.40 mm Body Z16.173/ZZ16.173 Package Outline, 51-85091
51-85091 *E
Document Number: 001-46117 Rev. *I
Page 11 of 15
CY24293
Acronyms
Acronym
Document Conventions
Description
Units of Measure
EIA
electronic industries alliance
EMI
electromagnetic interference
°C
degree Celsius
ESD
electrostatic discharge
kHz
kilohertz
HCSL
high speed current steering logic
MHz
megahertz
JEDEC
joint electron devices engineering council
µF
microfarad
PCB
printed circuit board
mA
milliampere
PCI
peripheral component interconnect
ms
millisecond
PLL
phase-locked loop
mV
millivolt
TSSOP
thin shrunk small outline package
mW
milliwatt
Document Number: 001-46117 Rev. *I
Symbol
Unit of Measure
ns
nanosecond
ohm
ppm
parts per million
%
percent
pF
picofarad
ps
picosecond
V
volt
Page 12 of 15
CY24293
Document History Page
Document Title: CY24293, Two Outputs PCI-Express Clock Generator
Document Number: 001-46117
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
2490167
PYG / DPF
/ AESA
See ECN
*A
2507681
DPF /
AESA
05/23/2008
Added Note 1: Parameters are guaranteed by design and characterization. Not
100% tested in production.
Added Note 2 for Duty cycle spec in the AC Elect. Characteristics.
Added HCSL termination in Condition for VOL, VOH DC Elect. Char.
Added VXdelta value of 140 mV in the Differential 100 MHz HCSL output.
Changed Cload from 2 pF to 4 pF in Note 2.
Added internal weak Pull-ups for S0, S1, SS0, SS1 and OE pins.
Updated TOEH and TOEL to 200 ns (max.).
Updated to new template.
*B
2621901
CXQ /
AESA
12/19/2008
Updated IDD spec in DC Electrical Characteristics.
Added max spec for IDDOD DC Electrical Characteristics.
Added RPU in DC Electrical Characteristics.
Replaced TRFVAR with DTR and DTF in AC Electrical Characteristics.
Added definitions for rise and fall time variation, crossing point variation in AC
Electrical Characteristics.
Reduced cycle-to-cycle jitter spec to 75ps in AC Electrical Characteristics.
*C
2683343
CXQ /
PYRA
04/03/2009
Changed status from Preliminary to Final.
Added “max” to crystal ESR spec.
Changed “LVDS Down Device” to “LVDS Device” in Table 8 and Figure 4.
*D
3289802
BASH
06/27/2011
Added Ordering Code Definitions.
Updated Package Diagram.
Added Acronyms and Units of Measure.
Updated to new template.
*E
3395894
PURU
10/05/2011
Updated Features (Removed LVDS related information).
Updated Functional Description (Removed LVDS related information).
Updated Output Termination under Application Information (Removed LVDS
related information).
Removed the section LVDS Compatible Layout Guidelines under the main
section PCI-Express (HCSL compatible) Layout Guidelines.
Updated AC Electrical Characteristics (Removed LVDS related information).
Updated Package Diagram.
Updated to new template.
*F
4467398
XHT
08/08/2014
Updated DC Electrical Characteristics:
Changed maximum value of VOH parameter from 0.85 V to 0.95 V.
*G
4581659
TAVA
11/28/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagram.
Document Number: 001-46117 Rev. *I
Description of Change
New data sheet.
Page 13 of 15
CY24293
Document History Page (continued)
Document Title: CY24293, Two Outputs PCI-Express Clock Generator
Document Number: 001-46117
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
*H
4817220
XHT
07/25/2015
Updated Pin Definitions:
Added Note 1 and referred the same note in SS0 and SS1 pins.
Added Note 2 and referred the same note in VDDO and VDDX pins.
Updated Spread Selection Table:
Added Note 3 and referred the same note in “SS1” and “SS0” columns.
Updated Application Information:
Updated Current Source (Iref) Reference Resistor:
Updated description.
Added Figure 3.
Updated AC Electrical Characteristics:
Added SPPROFILE parameter and its details.
Added minimum value of SPMOD parameter (30 kHz).
Added maximum value of SPMOD parameter (33 kHz).
Updated Note 10 (Replaced differential with single ended).
Added AC Electrical Characteristics (to specify PCIe parameter specifications).
Updated to new template.
Completing Sunset Review.
*I
5281627
PSR
05/23/2016
Added Thermal Resistance.
Updated to new template.
Document Number: 001-46117 Rev. *I
Page 14 of 15
CY24293
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
cypress.com/clocks
Interface
Lighting & Power Control
cypress.com/interface
cypress.com/powerpsoc
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
cypress.com/memory
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2008-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-46117 Rev. *I
Revised May 23, 2016
Page 15 of 15