ASAHI KASEI [AKD4388A-SA] AKD4388A-SA AK4388A Evaluation board Rev.0 General Description The AKD4388A-SA is an evaluation board for AK4388A, which is 192kHz sampling 24Bit ΔΣ DAC. The AKD4388A-SA includes a LPF which can add differential analog outputs from the AK4388A and also has a digital interface. Therefore, it is easy to evaluate the AK4388A. Ordering Guide AKD4388A-SA --- Evaluation board for AK4388A Function On-board Analog output buffer circuit On-board digital audio interface. (AK4113) +15V +5V +3.3V GND -15V +5V Reg Reg DIR Lch COAX In 2nd Order AK4113 Opt In AK4388A LPF PORT1 Control Data Rch PORT2 EXT Figure 1. AKD4388A-SA Block diagram * Circuit diagram are attached at the end of this manual. COAX is recommended for an evaluation of the Sound quality. <KM095600> 1 2008/06 ASAHI KASEI [AKD4388A-SA] Operation sequence 1) Set up the power supply lines. (See “Other jumpers set-up”.) Name Color Voltage Comments For regulator and op-amps. +15V Green +12∼+15V -15V Blue -12∼-15V For op-amps. +5V Red +4.75∼+5.25V For AK4388A. AGND Black 0V GND Attention This jack should be always connected to power supply. This jack should be always connected to power supply. This jack should be always connected to power supply. This jack should be always connected to power supply. Table 1. Set up of power supply lines Each supply line should be distributed from the power supply unit. 2) Set-up the jumper pins 3) Set-up the DIP switches. (See the followings.) 4) Power on The AK4388A should be reset once by bringing SW4 (PDN) “L” upon power-up. <KM095600> 2 2008/06 ASAHI KASEI [AKD4388A-SA] Evaluation mode 1. DIR (COAX) (default) It is possible to evaluate the AK4388A by using CD disk. The DIR generates MCLK, BICK, LRCK and SDATA from the received data through RCA connector (J3). Setting of jumper is shown below. COAX is recommended for an evaluation of the Sound quality. JP1 COAX OPT RX (Default) Figure 2. Jumper setting, when using DIR 2. DIR (Optical Link) It is possible to evaluate the AK4388A by using CD disk. The DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical connector (PORT3: TORX173). Setting of jumper is shown below. JP1 COAX OPT RX Figure 3. Jumper setting, when using DIR 3. All clocks are fed through the PORT2. R1, R2, R3, R4 R26, R27, R28, R30 <KM095600> : open : 100Ω or short (0Ω) 3 2008/06 ASAHI KASEI [AKD4388A-SA] DIP Switch setting [SW1]: AK4388A setting No. Pin SW1 OFF SW1 ON Default 1 SMUTE Soft Mute : “Disable” Soft Mute : “Enable” OFF 2 P/S 3 ACKS 4 DIF0 Always ON for Parallel Control mode only Manual setting mode ON Auto setting mode ON Audio Data Formats Refer to Table7 Table 2. SW1 setting OFF [SW2]: AK4388A setting No. Pin 1 - Default NC OFF 2 - NC OFF 3 DEM De-emphasis Control setting Refer to Table6 OFF 4 DIF1 Audio Data Formats Refer to Table7 ON Table 3. SW2 setting [SW3]: AK4113 setting No. Pin 1 2 OCKS1 OCKS0 OFF ON Default ON OFF AK4113 Master Clock setting Refer to Table 5. Table 4. SW3 setting The frequency of the master clock output is set by OCKS0 and OCKS1 as shown in Table 5. OCKS1 0 1 1 OCKS0 0 0 1 MCLK Frequency 256fs @fs=88.2/96kHz 512fs @32/44.1/48kHz 128fs @176.4/192kHz Table 5. MCLK Clock Default The digital de-emphasis filter is set by DEM pin as follows. DEM SW DEM pin state De-emphasis Filter OFF 1 ON 0 OFF ON Default Table 6. De-emphasis Filter Control Data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF0-1 as shown in Table 7 can select four serial data modes. Mode 0 DIF1 SW ON DIF0 SW ON DIF1 pin state 0 DIF0 pin state 0 1 2 3 ON OFF OFF OFF ON OFF 0 1 1 1 0 1 SDTI Format 16bit LSB justified 24bit LSB justified 24bit MSB justified 16/24bit I2S Compatible BICK ≥32fs ≥48fs ≥48fs ≥48fs or 32fs Default Table 7. Audio Data Formats <KM095600> 4 2008/06 ASAHI KASEI [AKD4388A-SA] Toggle switch setting [SW4](PDN): Reset of AK4388A. Select “H” during operation. <KM095600> 5 2008/06 ASAHI KASEI [AKD4388A-SA] External Analog Circuit The 2nd order LPF (fc=125.6kHz, Q=0.753) which adds differential outputs of the AK4388A is implemented on the board. When the further attenuation of the out-band noise is needed, some additional LPF is required. Analog signal is output through BNC connectors on the board. And the output level of the AK4388A is 5.67Vpp@5V. C1 R4 R3 +Vop R0 22u R1 Analog Out R2 AOUT 22K C2 -Vop fc=125.6kHz, Q=0.753, g=0.060dB at 40kHz Figure 4. External Analog Filter R0 910 R1 1.8k R2 3.9k R3 3.3k R4 3.9k C1 390p C2 390p Table 8. The value of R,C on this board fin 20kHz 40kHz Frequency Response 0.023dB 0.060dB Table 9. Frequency Response of LPF 80kHz -0.288dB <Calculation> K Amplitude = 20 log K= R3+R4 , R4 fc= ω0 , 2π ω0= 1 C1C2R1R2 Q = 2πfc <KM095600> 2 2 [1-(f/fc) ] +[(1/Q)(f/fc)] 2 [dB], , 1 1 1 1− k + + C1 R1 C1 R2 C 2 R2 6 2008/06 ASAHI KASEI [AKD4388A-SA] REVISION HISTORY Date (YY/MM/DD) 08/06/20 Manual Revision KM095600 Board Revision 0 Reason Page Contents First Edition IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification. <KM095600> 7 2008/06 1 -15V +15V +5V VOP- VOP+ + C1 C2 + 470u R61 0 470u T1 NJM78M05FA R62 NC NC 1 NC R28 NC IN OUT AVDD 2 R27 3 GND R26 R29 D3V 10k MCLK BICK LRCK SDATA 1 2 3 4 5 PORT2 10 9 8 7 6 R5,R8,R9,R10,C9 Setting for AK4384/4387/4388/4388A # 15 DIF1 DEM AK4387 NC AK4384 P/S AK4388, AK4388A EXT R30 #9 R5 NC C9 R10 R8 R9 NC 0-ohm NC 0-ohm DVDD 0-ohm 0.1u NC NC NC DZFR NC NC NC 0-ohm NC NC AVDD U1 R5 R6 A 4113_BICK 4113_SDTO 4113_LRCK R1 5.1 MCLK 1 MCLK DZF 16 R2 100 BICK 2 BICK DEM 15 R3 100 SDTI1 3 SDTI VDD 14 R4 100 LRCK 4 LRCK VSS 13 RSTN 5 RSTN VCOM 12 C8 6 SMUTE AOUTL 11 R57 7 ACKS AOUTR 10 8 DIF0 RSTN NC A + C6 0.1u 10u + 4113_MCLK 0 C7 C20 R7 C9 10u NC NC NC NC 9 DIF1 AOUTL AK4388A C4 C5 10p NC AOUTR SMUTE D3V R11 10 8 6 4 2 PORT1 9 7 5 3 1 10k R12 10k CSN CCLK CDTI uP-I/F ACKS DIF0 P/S R13 C36 0.1u 10k R14 R15 470 470 R16 470 U4 2 3 5 6 11 10 14 13 1A 1B 2A 2B 3A 3B 4A 4B 1 15 A/B G 1Y 4 2Y 7 3Y 9 4Y 12 VCC GND 16 8 R25 AVDD R8 NC R9 0 R10 0 5.1 SW2 SW1 SMUTE P/S ACKS DIF0 1 2 3 4 8 7 6 5 DEM DIF1 1 2 3 4 8 7 6 5 SW DIP-4 SW DIP-4 74LVC157 SMUTE P/S ACKS DIF0 R17 R18 R19 R20 10k 10k 10k 10k R21 R22 R23 R24 10k 10k 10k 10k Title Size A3 Date: 1 AKD4388A-SA Document Number Rev 0 AK4388A Friday, June 20, 2008 Sheet 1 of 3 1 C14 390p R47 C22 C24 100p NC R39 R41 3.9k 3.3k 0 VOP- 4 C45 NC C10 R35 R37 C16 910 22u 1.8k 3.9k NC 2 3 R33 22k C18 C12 8 + AOUTL 390p 100p R45 1 U3A NJM4580 C26 10u J1 MR-552LS 220 + R31 + 10u C29 + C28 0.1u - R58 NC 2 3 1 R43 20k R48 0 VOP+ R59 NC C30 0.1u C31 10u + C46 NC C15 390p A A C25 100p NC R40 R42 3.9k 3.3k 4 C23 R38 C17 1.8k 3.9k NC 6 5 8 + AOUTR C19 390p R34 22k R46 7 U3B NJM4580 C27 10u J2 MR-552LS 220 + R36 22u + C11 910 - R32 R44 2 3 1 20k C13 100p Title Size A3 Date: 1 AKD4388A-SA Document Number Rev 0 Analog Friday, June 20, 2008 Sheet 2 of 3 1 S3 T2 uPC3533HF C32 47u + GND R56 1 VOP+ IN C33 0.1u OUT 0 3 Master Clock OCKS1 OCKS0 H L 512fs@fs=32k/44.1k/48kHz L L 256fs@fs=88.2k/96kHz H H 128fs@fs=176.4k/192kHz D3V C34 0.1u 2 SW3 1 2 AVDD SW4 RSTN 3 L 2 1 D1 HSU119 2 OCKS1 OCKS0 R55 R54 10k 10k OCKS U2 R50 5.1 1 H C37 0.1u 4 3 R49 10k C38 10u + 1 DVDD CM0/CDTO/CAD1 30 2 DVSS CM1/CDTI/SDA 29 3 TVDD OCKS1/CCLK/SCL 28 4 V/TX OCKS0/CSN/CAD0 27 5 XTI MCKO1 26 6 XTO MCKO2 25 7 PDN DAUX 24 8 R BICK 23 4113_BICK 9 AVDD SDTO 22 4113_SDTO 10 AVSS LRCK 21 C39 0.1u C40 0.1u U5 1 2 3 4 5 6 7 1A 1Y 2A 2Y 3A 3Y GND VCC 6A 6Y 5A 5Y 4A 4Y 14 13 12 11 10 9 8 C35 0.1u 4113_MCLK 74HC14 A A R51 15k RSTN C47 NC R60 NC C41 10u + C42 0.1u 4113_LRCK INT0 J3 MR-552LS COAX C43 0.1u 2 3 1 11 RX1 INT0 20 12 RX2/DIF0 FS96/I2C 19 13 RX3/DIF1 P/SN 18 14 RX4/DIF2 INT1 17 15 RX5 RX6/IPS 16 COAX R52 75 JP1 RX OPT AK4113 PORT3 6 5 6 5 GND VCC GND OUT 4 3 2 1 C44 L1 0 0.1u 1 2 R53 100 TORX173 Title Size A3 Date: 1 AKD4388A-SA Document Number Rev 0 DIR Friday, June 20, 2008 Sheet 3 of 3