XC83x Series User's Manual

8-Bit
XC83x
8-Bit Single-Chip Microcontroller
User’s Manual
V1.1 2010-09
Microcontrollers
Edition 2010-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2010 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
8-Bit
XC83x
8-Bit Single-Chip Microcontroller
User’s Manual
V1.1 2010-09
Microcontrollers
XC83x
XC83x User’s Manual
Revision History: V1.1 2010-09
Previous Versions: V1.0
Page
Subjects (major changes since last revision)
1-4
The pin configuration and package information of XC83x have been
removed. This information can be found in the Data Sheet.
3-7
The storage field is renamed from STx to MOD_STx.
5-4, 7-11
1 or 0 wait state for Flash read access based on CPU clock.
22-2,
22-45
The value of setup time between conversion modes has been removed
in User’s Manual. Refer to Data Sheet for timing information.
22-21
Description of bit ENGT in ADC_CMR1 register is added.
24-26,
24-27
The LPF Gain is added in Figure 24-6 and 24-7.
24-40
Figure 24-10 is updated with the Subtraction m (offset).
24-28,
24-37,
24-28
The “value (subtraction m)” is renamed to “offset value (subtraction m)”.
24-47
EEPROM emulated ROM library is written on KEIL C51 toolchain.
We Listen to Your Comments
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Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
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User’s Manual
V1.1, 2010-09
XC83x
1
1.1
1.2
1.3
1.4
1.5
1.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 [1]
XC83x Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 [1]
Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 [1]
Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 [1]
Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 [1]
Reserved, Undefined and Unimplemented Terminology . . . . . . . . . . 1-14 [1]
Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 [1]
2
2.1
2.2
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.4
2.4.1
2.4.2
2.5
XC800 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XC800 Core Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFRs of the CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack Pointer (SP, 81H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Pointer (DPTR, 82-3H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Accumulator (ACC, E0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B Register (F0H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Status Word (PSW, D0H) . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Operation Register (EO, A2H) . . . . . . . . . . . . . . . . . . . . .
Power Control Register (PCON, 87H) . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SFRs of The Core Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3.1
3.2
3.2.1
3.2.2
3.3
3.4
3.4.1
3.4.1.1
3.4.2
3.4.2.1
3.4.3
3.4.4
3.4.5
3.4.5.1
3.4.5.2
3.4.5.3
3.4.5.4
3.4.5.5
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 [1]
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 [1]
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 [1]
Internal Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 [1]
External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 [1]
Memory Protection Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1]
Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1]
Address Extension by Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 [1]
System Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 [1]
Address Extension by Paging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 [1]
Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 [1]
Bit-Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 [1]
Bit Protection Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 [1]
XC83x Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 [1]
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 [1]
MDU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 [1]
CORDIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15 [1]
System Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 [1]
Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 [1]
User’s Manual
1-1
2-1 [1]
2-1 [1]
2-1 [1]
2-3 [1]
2-3 [1]
2-3 [1]
2-3 [1]
2-3 [1]
2-3 [1]
2-5 [1]
2-6 [1]
2-6 [1]
2-7 [1]
2-7 [1]
2-7 [1]
2-8 [1]
V1.1, 2010-09
XC83x
3.4.5.6
3.4.5.7
3.4.5.8
3.4.5.9
3.4.5.10
3.4.5.11
3.4.5.12
3.4.5.13
ADC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LEDTSCU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RTC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CCU6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SSC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IIC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCDS Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-20 [1]
3-24 [1]
3-25 [1]
3-27 [1]
3-27 [1]
3-32 [1]
3-32 [1]
3-33 [1]
4
4.1
4.2
4.3
4.4
4.5
4.5.1
4.6
4.7
4.7.1
4.7.1.1
4.7.1.2
4.7.2
4.7.2.1
4.7.2.2
4.7.3
4.7.4
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 [1]
Flash Memory Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 [1]
Flash Bank Sectorization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 [1]
Wordline Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 [1]
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 [1]
Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 [1]
Flash Error Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 [1]
In-System Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 [1]
In-Application Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 [1]
Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 [1]
Non-background Flash Program Subroutine . . . . . . . . . . . . . . . 4-15 [1]
Background Flash Program Subroutine . . . . . . . . . . . . . . . . . . . 4-15 [1]
Flash Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 [1]
Non-background Flash Erase Subroutine . . . . . . . . . . . . . . . . . 4-16 [1]
Background Flash Erase Subroutine . . . . . . . . . . . . . . . . . . . . . 4-16 [1]
Aborting Background Flash Erase . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 [1]
Flash Read Mode Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 [1]
5
5.1
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.4.1
Boot and Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot ROM Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Mode (Productive) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User Mode (Diagnostic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Boot-Loader Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCDS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternate User BSL Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1 [1]
5-2 [1]
5-4 [1]
5-4 [1]
5-4 [1]
5-4 [1]
5-4 [1]
5-5 [1]
6
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.1.1
6.2.1.2
UART Boot-Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phase I: Automatic Serial Synchronization to the Host . . . . . . . . . . . .
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Calculation of BG and PRE values . . . . . . . . . . . . . . . . . . . . . . . . .
Phase II: Serial Communication Protocol and the Modes . . . . . . . . . .
Serial Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Block Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Block Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6-1 [1]
6-2 [1]
6-2 [1]
6-3 [1]
6-4 [1]
6-4 [1]
6-4 [1]
6-5 [1]
User’s Manual
1-2
V1.1, 2010-09
XC83x
6.2.1.3
6.2.2
6.2.2.1
6.2.2.2
6.2.2.3
6.2.2.4
6.2.2.5
6.2.2.6
6.2.2.7
6.2.2.8
Response codes to the host . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6 [1]
The Selection of Working Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 [1]
Receiving the Header Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 [1]
Mode0: Program customer code to XRAM . . . . . . . . . . . . . . . . . 6-9 [1]
Mode1: Execute customer code in XRAM . . . . . . . . . . . . . . . . . 6-11 [1]
Mode2: Program customer code to FLASH . . . . . . . . . . . . . . . . 6-11 [1]
Mode3: Execute customer code in FLASH . . . . . . . . . . . . . . . . 6-13 [1]
Mode4: Erase customer code in FLASH sector(s) . . . . . . . . . . 6-13 [1]
Mode6: Program 4 bytes of USER_ID . . . . . . . . . . . . . . . . . . . . 6-14 [1]
ModeA: Get 4 bytes Information . . . . . . . . . . . . . . . . . . . . . . . . 6-15 [1]
7
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.1.4
7.2.1.5
7.2.2
7.2.3
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
7.4.1
7.4.1.1
7.4.1.2
7.4.1.3
7.4.2
7.5
System Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 [1]
Power Supply System with Embedded Voltage Regulator . . . . . . . . . 7-1 [1]
Reduced Voltage Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3 [1]
EVR Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 [1]
Reset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 [1]
Types of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 [1]
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 [1]
Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 [1]
Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 [1]
Power-Down Wake-Up Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 [1]
Brownout Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 [1]
Module Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 [1]
Reset Control Register Description . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 [1]
Clock System and Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 [1]
Oscillator Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12 [1]
Loss of Clock Detection and Recovery . . . . . . . . . . . . . . . . . . . . . 7-13 [1]
Startup Control for 32.768 kHz Oscillator Clock . . . . . . . . . . . . . . 7-13 [1]
CCU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15 [1]
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17 [1]
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 [1]
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 [1]
Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-18 [1]
Peripheral Clock Management . . . . . . . . . . . . . . . . . . . . . . . . . 7-23 [1]
Power Management Register Description . . . . . . . . . . . . . . . . . . . 7-25 [1]
SCU Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-27 [1]
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reset effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . .
Module Suspend Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User’s Manual
1-3
8-1 [1]
8-1 [1]
8-2 [1]
8-2 [1]
8-2 [1]
8-2 [1]
8-3 [1]
V1.1, 2010-09
XC83x
8.3
8.4
8.4.1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 [1]
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 [1]
Watchdog Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6 [1]
9
9.1
9.1.1
9.1.2
9.2
9.2.1
9.2.2
9.3
9.4
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.6
Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1]
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 [1]
Interrupt Source and Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 [1]
Interrupt Source and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-9 [1]
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 [1]
Interrupt Structure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 [1]
Interrupt Structure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 [1]
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 [1]
Interrupt Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 [1]
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 [1]
Interrupt Node Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 [1]
External Interrupt Control Registers . . . . . . . . . . . . . . . . . . . . . . . 9-20 [1]
Interrupt Flag Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-25 [1]
Interrupt Priority Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-31 [1]
Interrupt Flag Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-33 [1]
10
10.1
10.1.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.3
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.4
10.4.1
10.4.1.1
10.4.1.2
10.4.1.3
10.4.2
10.4.3
10.5
Debug System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 [1]
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 [1]
Components of the Debug System . . . . . . . . . . . . . . . . . . . . . . . . 10-1 [1]
Product Specific Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1]
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1]
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1]
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 [1]
Debug Suspend Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 [1]
JTAG ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 [1]
Functional Overview of the Debug System . . . . . . . . . . . . . . . . . . . . 10-5 [1]
Recognizing Debug-events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 [1]
Activating the Monitor Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 [1]
Debug Suspend Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 [1]
Running the Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 [1]
Returning to the User Program . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 [1]
Single Step Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-8 [1]
Breakpoint Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9 [1]
Generating Hardware Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . 10-9 [1]
Breakpoints on Instruction Address . . . . . . . . . . . . . . . . . . . . . . 10-9 [1]
Breakpoints on Internal RAM Address . . . . . . . . . . . . . . . . . . . 10-10 [1]
Tracing changes in Break Address . . . . . . . . . . . . . . . . . . . . . 10-11 [1]
Processing External Breaks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 [1]
Processing Software Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . 10-11 [1]
Reactions on Breakpoints without Monitor Entry . . . . . . . . . . . . . . . 10-12 [1]
User’s Manual
1-4
V1.1, 2010-09
XC83x
10.5.1
10.6
10.6.1
10.6.2
10.6.3
10.7
10.8
10.8.1
10.8.2
10.8.3
Triggering a NMI request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NMI Request and Control by OCDS . . . . . . . . . . . . . . . . . . . . . . . .
NMI request from OCDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCDS NMI Service Routine Handling . . . . . . . . . . . . . . . . . . . . .
General NMI control by OCDS . . . . . . . . . . . . . . . . . . . . . . . . . .
NMI-mode priority over Debug-mode . . . . . . . . . . . . . . . . . . . . . . .
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Breakpoint Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Work Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11
11.1
11.1.1
11.1.1.1
11.1.1.2
11.2
11.2.1
11.2.2
11.3
11.3.1
11.3.2
11.4
11.4.1
11.4.2
11.5
11.5.1
11.5.2
Parallel Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 [1]
General Port Operation Description . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 [1]
General Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 [1]
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8 [1]
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-10 [1]
Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 [1]
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-18 [1]
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-24 [1]
Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-28 [1]
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-29 [1]
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 [1]
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 [1]
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-38 [1]
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-41 [1]
Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 [1]
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-44 [1]
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-46 [1]
12
12.1
12.2
12.2.1
12.2.2
12.3
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.3.7
12.4
12.5
Multiplication/Division Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Normalize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiplication with Single Left Shift . . . . . . . . . . . . . . . . . . . . . . . .
Division with Single Right Shift . . . . . . . . . . . . . . . . . . . . . . . . . . .
Busy Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User’s Manual
1-5
10-12 [1]
10-13 [1]
10-13 [1]
10-14 [1]
10-14 [1]
10-15 [1]
10-15 [1]
10-16 [1]
10-18 [1]
10-21 [1]
12-1 [1]
12-1 [1]
12-2 [1]
12-2 [1]
12-3 [1]
12-3 [1]
12-4 [1]
12-5 [1]
12-5 [1]
12-5 [1]
12-6 [1]
12-6 [1]
12-6 [1]
12-7 [1]
12-8 [1]
V1.1, 2010-09
XC83x
12.5.1
12.5.2
12.5.3
Operand and Result Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 [1]
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-12 [1]
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-14 [1]
13
13.1
13.2
13.2.1
13.2.1.1
13.2.2
13.3
13.3.1
13.3.2
13.3.3
13.3.3.1
13.3.3.2
13.3.4
13.3.5
13.3.6
13.4
13.5
13.5.1
13.5.2
13.6
13.6.1
13.6.2
13.6.3
CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1]
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 [1]
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 [1]
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 [1]
Peripheral Management Control Register 1 . . . . . . . . . . . . . . . 13-3 [1]
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 [1]
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 [1]
Operation of the CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . 13-4 [1]
Normalized Result Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-5 [1]
CORDIC Coprocessor Operating Modes . . . . . . . . . . . . . . . . . . . . 13-5 [1]
Domains of Convergence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 [1]
Overflow Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 [1]
CORDIC Coprocessor Data Format . . . . . . . . . . . . . . . . . . . . . . . 13-9 [1]
Accuracy of CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . . . . 13-10 [1]
Performance of CORDIC Coprocessor . . . . . . . . . . . . . . . . . . . . 13-12 [1]
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 [1]
CORDIC Coprocessor Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13 [1]
Arctangent and Hyperbolic Arctangent Look-Up Tables . . . . . . . 13-13 [1]
Linear Function Emulated Look-Up Table . . . . . . . . . . . . . . . . . . 13-14 [1]
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 [1]
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15 [1]
Status and Data Control Register . . . . . . . . . . . . . . . . . . . . . . . . 13-18 [1]
Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-19 [1]
14
14.1
14.2
14.2.1
14.2.2
14.2.3
14.3
14.4
14.4.1
14.4.2
14.4.3
14.4.4
14.5
14.5.1
Timer 0 and Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .
Basic Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer 0 and Timer 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Timer 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [1]
User’s Manual
1-6
14-1 [1]
14-1 [1]
14-1 [1]
14-1 [1]
14-2 [1]
14-2 [1]
14-3 [1]
14-4 [1]
14-5 [1]
14-6 [1]
14-7 [1]
14-8 [1]
14-9 [1]
14-9 [1]
V1.1, 2010-09
XC83x
15.1
15.2
15.2.1
15.2.2
15.2.3
15.2.4
15.2.5
15.3
15.4
15.4.1
15.4.2
15.5
15.6
15.7
15.8
15.8.1
15.8.2
15.8.3
15.8.4
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [1]
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [1]
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 [1]
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 [1]
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 [1]
IP interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 [1]
Module Suspend Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-5 [1]
Basic Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 [1]
Auto-Reload Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 [1]
Up/Down Count Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-6 [1]
Up/Down Count Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-7 [1]
Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 [1]
Count Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 [1]
External Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 [1]
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 [1]
Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 [1]
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-14 [1]
Timer 2 Reload/Capture Register . . . . . . . . . . . . . . . . . . . . . . . . 15-15 [1]
Timer 2 Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 [1]
16
16.1
16.2
16.2.1
16.2.2
16.2.3
16.3
16.4
16.5
16.5.1
16.5.2
16.5.3
16.5.4
16.6
16.7
16.7.1
16.7.2
Real-Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [1]
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [1]
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [1]
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [1]
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 [1]
Module Suspend Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 [1]
Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 [1]
Basic Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [1]
Real-Time Clock Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-3 [1]
Mode 0: Time Keeping Mode with 32.768 kHz Crystal Clock . . . . 16-3 [1]
Mode 1: Periodic Wake-up Mode with 75 kHz Oscillator Clock . . . 16-5 [1]
Mode 2: Time Keeping Mode with 1 Hz External Clock . . . . . . . . . 16-7 [1]
Mode 3: Timer Mode with External Clock . . . . . . . . . . . . . . . . . . . 16-7 [1]
Power Saving Mode Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-8 [1]
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-9 [1]
Real-Time Clock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 [1]
Oscillator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-22 [1]
17
17.1
17.2
17.2.1
17.2.2
17.2.3
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .
User’s Manual
1-7
17-1 [1]
17-1 [1]
17-1 [1]
17-1 [1]
17-3 [1]
17-3 [1]
V1.1, 2010-09
XC83x
17.3
17.3.1
17.3.2
17.3.3
17.3.4
17.4
17.5
17.5.1
17.5.2
17.5.3
17.6
17.6.1
17.6.2
17.6.2.1
17.6.2.2
17.6.2.3
17.6.2.4
17.7
17.7.1
17.7.2
17.7.3
UART Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 [1]
Mode 0, 8-Bit Shift Register, Fixed Baud Rate . . . . . . . . . . . . . . . 17-4 [1]
Mode 1, 8-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . 17-4 [1]
Mode 2, 9-Bit UART, Fixed Baud Rate . . . . . . . . . . . . . . . . . . . . . 17-7 [1]
Mode 3, 9-Bit UART, Variable Baud Rate . . . . . . . . . . . . . . . . . . . 17-7 [1]
Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 [1]
Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 [1]
Fixed Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 [1]
UART Baud-rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 [1]
Timer 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 [1]
LIN Support in UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 [1]
LIN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-14 [1]
LIN Header Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 [1]
Automatic Synchronization to the Host . . . . . . . . . . . . . . . . . . 17-16 [1]
Initialization of Break/Synch Field Detection Logic . . . . . . . . . 17-17 [1]
Baud Rate Range Selection . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17 [1]
LIN Baud Rate Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 [1]
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-20 [1]
UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-21 [1]
Baud-rate Generator Control and Status Registers . . . . . . . . . . . 17-23 [1]
Baud-rate Generator Timer/Reload Registers . . . . . . . . . . . . . . . 17-25 [1]
18
18.1
18.2
18.2.1
18.2.1.1
18.2.2
18.2.3
18.3
18.4
18.5
18.6
18.7
18.8
18.8.1
18.8.2
18.8.3
18.8.4
18.9
18.9.1
18.9.2
18.9.3
Inter-IC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 [1]
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 [1]
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 [1]
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 [1]
Output Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 [1]
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 [1]
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 [1]
Status Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-4 [1]
Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 [1]
Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 [1]
Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-6 [1]
Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 [1]
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 [1]
Master Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-7 [1]
Master Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-10 [1]
Slave Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-12 [1]
Slave Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-13 [1]
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-15 [1]
Slave Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-16 [1]
Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-17 [1]
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-18 [1]
User’s Manual
1-8
V1.1, 2010-09
XC83x
18.9.4
18.9.5
18.9.6
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-20 [1]
Baud Rate Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21 [1]
Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-21 [1]
19
19.1
19.2
19.2.1
19.2.2
19.2.3
19.3
19.3.1
19.3.2
19.3.3
19.3.4
19.3.5
19.3.6
19.4
19.5
19.5.1
19.5.2
19.5.3
19.5.4
High-Speed Synchronous Serial Interface . . . . . . . . . . . . . . . . . . 19-1 [1]
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 [1]
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 [1]
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 [1]
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 [1]
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 [1]
General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 [1]
Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-8 [1]
Full-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-10 [1]
Half-Duplex Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-13 [1]
Continuous Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-14 [1]
Baud Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-15 [1]
Error Detection Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-16 [1]
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-19 [1]
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-20 [1]
Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-21 [1]
Baud Rate Timer Reload Register . . . . . . . . . . . . . . . . . . . . . . . . 19-26 [1]
Transmitter Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-26 [1]
Receiver Buffer Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-27 [1]
20
20.1
20.2
20.2.1
20.2.2
20.2.3
20.2.4
20.2.5
20.3
20.4
20.4.1
20.5
20.5.1
20.6
20.7
20.8
20.9
20.10
20.11
20.11.1
LED and Touch-Sense Controller . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [1]
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 [1]
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 [1]
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 [1]
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 [1]
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 [1]
IP Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 [1]
Debug Suspend Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-5 [1]
Time-Multiplexed LED & Touch-Sense Functions On Pin . . . . . . . . . 20-5 [1]
LED Driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-8 [1]
LED Pin Assignment and Current Capability . . . . . . . . . . . . . . . . 20-10 [1]
Touchpad Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-11 [1]
Finger Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 [1]
Time-Multiplexed LED and Touch-Sense Function on Pin . . . . . . . 20-14 [1]
Function Enabling and Control Hints . . . . . . . . . . . . . . . . . . . . . . . . 20-15 [1]
LEDTSCU Timing Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 [1]
LEDTSCU Pin Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 [1]
Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 [1]
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-20 [1]
Global Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 [1]
User’s Manual
1-9
V1.1, 2010-09
XC83x
20.11.2
Function Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-24 [1]
21
21.1
21.1.1
21.1.2
21.1.3
21.2
21.2.1
21.2.2
21.2.3
21.2.4
21.2.5
21.3
21.3.1
21.3.2
21.3.2.1
21.3.2.2
21.3.2.3
21.3.3
21.3.3.1
21.3.3.2
21.3.3.3
21.3.4
21.3.4.1
21.3.4.2
21.3.4.3
21.3.5
21.3.6
21.3.7
21.3.8
21.3.8.1
21.3.8.2
21.3.8.3
21.3.8.4
21.3.8.5
21.3.9
21.3.9.1
21.3.9.2
21.3.9.3
21.4
21.4.1
21.4.2
Capture/Compare Unit 6 (CCU6) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [1]
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 [1]
Feature Set Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 [1]
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 [1]
Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 [1]
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 [1]
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 [1]
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-12 [1]
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . 21-13 [1]
IP Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-15 [1]
Module Suspend Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17 [1]
Operating Timer T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-17 [1]
T12 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-19 [1]
T12 Counting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 [1]
Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-21 [1]
Edge-Aligned / Center-Aligned Mode . . . . . . . . . . . . . . . . . . . 21-21 [1]
Single-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-24 [1]
T12 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-25 [1]
Compare Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-25 [1]
Channel State Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-26 [1]
Hysteresis-Like Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . 21-31 [1]
Compare Mode Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 [1]
Dead-Time Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-32 [1]
State Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-34 [1]
Output Modulation and Level Selection . . . . . . . . . . . . . . . . . . 21-35 [1]
T12 Capture Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-37 [1]
T12 Shadow Register Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 21-41 [1]
Timer T12 Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . 21-42 [1]
T12 related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43 [1]
T12 Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-43 [1]
Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-44 [1]
Capture/Compare Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 21-46 [1]
Capture/Compare Shadow Registers . . . . . . . . . . . . . . . . . . . 21-47 [1]
Dead-time Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-49 [1]
Capture/Compare Control Registers . . . . . . . . . . . . . . . . . . . . . . 21-51 [1]
Channel State Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-51 [1]
T12 Mode Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-55 [1]
Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-57 [1]
Operating Timer T13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-67 [1]
T13 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-67 [1]
T13 Counting Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-70 [1]
User’s Manual
1-10
V1.1, 2010-09
XC83x
21.4.2.1
T13 Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-70 [1]
21.4.2.2
Single-Shot Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-71 [1]
21.4.2.3
Synchronization to T12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-72 [1]
21.4.3
T13 Compare Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-74 [1]
21.4.4
Compare Mode Output Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-76 [1]
21.4.5
T13 Shadow Register Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 21-77 [1]
21.4.6
T13 related Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-79 [1]
21.4.6.1
T13 Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-79 [1]
21.4.6.2
Period Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-81 [1]
21.4.6.3
Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-83 [1]
21.4.6.4
Compare Shadow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-83 [1]
21.5
Trap Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-85 [1]
21.6
Multi-Channel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-87 [1]
21.7
Hall Sensor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-90 [1]
21.7.1
Hall Pattern Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-91 [1]
21.7.2
Hall Pattern Compare Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-93 [1]
21.7.3
Hall Mode Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-94 [1]
21.7.4
Hall Mode for Brushless DC-Motor Control . . . . . . . . . . . . . . . . . 21-96 [1]
21.8
Modulation Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-98 [1]
21.8.1
Modulation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-98 [1]
21.8.2
Trap Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-100 [1]
21.8.3
Passive State Level Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-103 [1]
21.8.4
Multi-Channel Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . 21-104 [1]
21.9
Interrupt Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-110 [1]
21.9.1
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-110 [1]
21.9.2
Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-112 [1]
21.9.2.1
Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-112 [1]
21.9.2.2
Interrupt Status Set Register . . . . . . . . . . . . . . . . . . . . . . . . . 21-116 [1]
21.9.2.3
Status Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-118 [1]
21.9.2.4
Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-120 [1]
21.9.2.5
Interrupt Node Pointer Register . . . . . . . . . . . . . . . . . . . . . . . 21-124 [1]
21.10
General Module Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-126 [1]
21.10.1
Input Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-126 [1]
21.10.2
General Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-127 [1]
21.10.2.1
Port Input Select Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 21-127 [1]
21.11
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-130 [1]
22
22.1
22.1.1
22.1.2
22.1.3
22.1.4
Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clocking Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Events and Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .
IP Interconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User’s Manual
1-11
22-1 [1]
22-3 [1]
22-3 [1]
22-3 [1]
22-4 [1]
22-4 [1]
V1.1, 2010-09
XC83x
22.2
22.3
22.4
22.5
22.5.1
22.6
22.6.1
22.6.2
22.6.3
22.7
22.7.1
22.7.2
22.8
22.8.1
22.8.2
22.8.3
22.8.4
22.8.5
22.8.6
22.8.7
22.9
22.9.1
22.10
22.10.1
22.10.2
22.11
22.12
Introduction and Basic Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 [1]
Electrical Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-10 [1]
Transfer Characteristics and Error Definitions . . . . . . . . . . . . . . . . . 22-12 [1]
Configuration of General Functions . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 [1]
General Clocking Scheme and Control . . . . . . . . . . . . . . . . . . . . 22-13 [1]
Conversion Request Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-17 [1]
Channel Scan Request Source Handling . . . . . . . . . . . . . . . . . . 22-19 [1]
Queued Request Source Handling . . . . . . . . . . . . . . . . . . . . . . . 22-25 [1]
Hardware Trigger Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-37 [1]
Request Source Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-38 [1]
Arbiter Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-40 [1]
Request Source Priority and Conversion Start Mode . . . . . . . . . 22-41 [1]
Analog Input Channel Configuration . . . . . . . . . . . . . . . . . . . . . . . . 22-45 [1]
Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-45 [1]
Channel Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-48 [1]
Limit Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-52 [1]
Alias Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-54 [1]
Out of Range Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-57 [1]
Conversion Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-61 [1]
Channel Events and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 22-63 [1]
Conversion Result Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-64 [1]
Storage of Conversion Results . . . . . . . . . . . . . . . . . . . . . . . . . . 22-64 [1]
Wait-for-Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-79 [1]
Result Events and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-80 [1]
Data Reduction and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-80 [1]
Interrupt Request Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-83 [1]
Register Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-90 [1]
23
23.1
23.2
23.3
23.4
23.5
23.6
23.7
23.8
Boot ROM User Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 [1]
Flash Bank Read Mode Status Subroutine . . . . . . . . . . . . . . . . . . . . 23-2 [1]
Get 4 Bytes Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 [1]
Feature Setting Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 [1]
UART Auto Baud Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 [1]
UART BSL Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-7 [1]
Flash Program Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 [1]
Flash Erase Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-10 [1]
Abort Flash Erase Subroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13 [1]
24
24.1
24.1.1
24.1.2
24.1.3
24.1.4
ROM Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fixed Point ROM Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
P Controller Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PI Controller Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PT1_24 Controller Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PT1_32 Controller Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
User’s Manual
1-12
24-1 [1]
24-2 [1]
24-2 [1]
24-3 [1]
24-5 [1]
24-6 [1]
V1.1, 2010-09
XC83x
24.1.5
Cartesian-Polar Transform Routine . . . . . . . . . . . . . . . . . . . . . . . . 24-7 [1]
24.1.6
Clarke Transform Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 [1]
24.1.7
Vector Rotation (Park Transform) Routine . . . . . . . . . . . . . . . . . 24-10 [1]
24.1.8
Inverse Vector Rotation (Inverse Park Transform) Routine . . . . . 24-11 [1]
24.1.9
Sine/Cosine Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 [1]
24.2
LED and Touch-Sense Controller ROM Library . . . . . . . . . . . . . . . 24-15 [1]
24.2.1
SET_LDLINE_CMP Function (LED and Touch-Sense) . . . . . . . . 24-16 [1]
24.2.1.1
Inputs for SET_LDLINE_CMP Function (LED only) . . . . . . . . 24-18 [1]
24.2.1.2
Inputs for SET_LDLINE_CMP Function (Touch-sense only) . . 24-20 [1]
24.2.1.3
Inputs for SET_LDLINE_CMP Function (LED and Touch-Sense) . . . . . .
24-22 [1]
24.2.2
FINDTOUCHEDPAD Function (Touch-Sense) . . . . . . . . . . . . . . 24-26 [1]
24.2.2.1
Inputs of FINDTOUCHEDPAD Function . . . . . . . . . . . . . . . . . 24-28 [1]
24.2.2.2
Outputs of FINDTOUCHEDPAD Function . . . . . . . . . . . . . . . . 24-31 [1]
24.2.2.3
XRAM Parameters of FINDTOUCHEDPAD Function . . . . . . . 24-35 [1]
24.2.2.4
Implementation Details of Function . . . . . . . . . . . . . . . . . . . . . 24-37 [1]
24.2.3
Use of the functions in Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . 24-45 [1]
24.3
EEPROM Emulation ROM Library . . . . . . . . . . . . . . . . . . . . . . . . . . 24-47 [1]
24.3.1
Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-47 [1]
24.3.2
System requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-47 [1]
24.3.3
Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-47 [1]
24.3.4
API description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-49 [1]
24.3.4.1
Constant definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-49 [1]
24.3.4.2
EEPROMInfo data structure . . . . . . . . . . . . . . . . . . . . . . . . . . 24-49 [1]
24.3.4.3
Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-50 [1]
24.3.4.4
Example of API usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-53 [1]
User’s Manual
1-13
V1.1, 2010-09
XC83x
Introduction
1
Introduction
The XC83x is a member of the high-performance XC800 family of 8-bit microcontrollers.
It is based on the XC800 Core that is compatible with the industry standard 8051
processor. The XC83x features a great number of enhancements to enable new
application technologies through its highly integrated on-chip components, such as
on-chip oscillator or an integrated voltage regulator, allowing a range of voltage supply
of 2.5 V to 5.5 V. In addition, the XC83x is equipped with embedded Flash memory to
offer high flexibility in development and ramp-up. The XC83x memory protection strategy
features read-out protection of user intellectual property (IP).
The multi-bank Flash architecture supports In-Application Programming (IAP), allowing
user program to run from one bank, while programming or erasing another bank.
In-System Programming (ISP) is available through the Boot ROM-based Boot-Loader
(BSL), enabling convenient programming and erasing of the embedded Flash via an
external host (e.g., personal computer).
Other key features include a Capture/Compare Unit 6 (CCU6) for the generation of pulse
width modulated signal with special modes for motor control; a 10-bit Analog-to-Digital
Converter (ADC) with out of range comparator that has differential input channels and
extended functionalities such as autoscan and result accumulation for anti-aliasing
filtering or for averaging; a Multiplication/Division Unit (MDU) to support the XC800 Core
in math-intensive computations in advanced motor control like Field Oriented Control; a
a CORDIC (COrdinate Rotation DIgital Computer) Coprocessor performing high-speed
computation of trigonometric, linear or hyperbolic functions for vector rotation and
transformations; LED and Touch-sense Controller (LEDTSCU) for driving 7 segment
displays in a LED matrix and supporting touch-sense function concurrently ; a Real Time
Clock (RTC) to support time keeping or periodic wake-up in low power application and
an On-Chip Debug Support (OCDS) unit for software development and debugging of
XC800-based systems. Local Interconnect Network (LIN) applications are also
supported through extended UART features and the provision of LIN low level drivers for
most devices. For low power applications, various power saving modes are available for
selection by the user. Control of the numerous on-chip peripheral functionalities is
achieved by extending the Special Function Register (SFR) address range with an
intelligent paging mechanism optimized for interrupt handling.
Figure 1-1 shows the functional units of the XC83x.
User’s Manual
System Architecture, V1.0
1-1
V1.1, 2010-09
XC83x
Introduction
8/4K Bytes
Flash
On-Chip Debug Support
IIC
Boot ROM
8K Bytes
UART
SSC
Port 0
8-bit Digital I/O
Capture/Compare Unit
16-bit
Port 1
6-bit Digital I/O
Compare Unit
16-bit
Port 2
8-bit Digital/Analog Input
ADC
10-bit
8-channel
Port 3
3-bit Digital I/O
XC800 Core
XRAM
256 Bytes
RAM
256 Bytes
MDU
Figure 1-1
LED and Touch Sense Controller
CORDIC
Timer 0
16-bit
Timer 1
16-bit
Timer 2
16-bit
Real-Time
Clock
Watchdog
Timer
XC83x Functional Units
User’s Manual
System Architecture, V1.0
1-2
V1.1, 2010-09
XC83x
Introduction
1.1
XC83x Feature List
The following list summarizes the main features of the XC83x:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High performance XC800 Core
– compatible to standard 8051 Core
– two clocks per machine cycle architecture (for memory access without wait state)
– two data pointers
On-chip Memory
– 8-KByte Boot ROM for startup firmware, Flash and User routines and ROM library
– 256-byte RAM; plus 64-byte Monitor RAM
– 256-byte XRAM
– 4/8-KByte Flash for program code and data; (includes memory protection strategy)
I/O port supply at 2.5 - 5.5V and core logic supply at 2.5V (generated by embedded
voltage regulator)
Power-on reset generation
Brown-out detection for IO supply and core logic supply
On-chip OSC for clock generation
– Loss-of-clock detection
Power saving modes
– idle mode
– power-down mode with wake-up capability via real-time clock interrupt
– clock gating control to each peripheral
Watchdog Timer (WDT) with programmable window feature for refresh operation and
warning prior to overflow
Three general purpose I/O ports
– 4 high current I/O
– 2 high sink I/O
– Up to 25 pins as digital I/O
– Up to 8 pins as digital/analog input
16-bit Vector Computer for Field-Oriented Control (FOC)
– Multiplication/Division Unit (MDU) for arithmetic calculation
– CORDIC Unit for trigonometric calculation
Software libraries to support fixed-point control and EEPROM emulation
Up to 8 channels, 10-bit A/D Converter
– support up to 7 differential input channel
Up to 8 channels, Out of range comparator
Three 16-bit timers - Timer 0, Timer 1, Timer2
Real-time clock with 32.768 kHz crystal pad
Capture/compare unit for PWM signal generation (CCU6)
Full duplex serial interface (UART)
Synchronous serial channel (SSC)
Inter-IC (IIC) serial interface
LED and Touch-sense Controller (LEDTSCU)
User’s Manual
System Architecture, V1.0
1-3
V1.1, 2010-09
XC83x
Introduction
•
On-chip Debug Support via single pin DAP interface (SPD)
– 1-KByte monitor ROM (part of the Boot ROM)
– 64-byte monitor RAM
The block diagram of the XC83x is shown in Figure 1-2.
XC83x
T0 & T1
UART
Port 0
256-byte RAM
+
64-byte monitor
RAM
P0.0 - P0.7
Port 1
XC800 Core
P1.0 - P1.5
Port 2
Internal Bus
8-Kbyte
Boot ROM 1)
P2.0 – P2.7
Vector Computer
VDDP
256-byte XRAM
VSSP
VSSC
4/8-Kbyte
Flash
CORDIC
MDU
RTC
IIC
WDT
SSC
Timer 2
CCU6
ADC
48 MHz
On-chip OSC
OCDS
75 KHz
On-chip OSC
EVR
Port 3
XTAL
Clock Generator
P3.0 - P3.2
SCU
LED and Touch
Sense Controller
1) Includes 1-Kbyte monitor ROM
Figure 1-2
1.2
XC83x Block Diagram
Pin Definitions and Functions
After reset, all pins are configured as input with one of the following:
•
•
•
Pull-up device enabled only (PU)
Pull-down device enabled only (PD)
High impedance with both pull-up and pull-down devices disabled (Hi-Z)
The functions and default states of the XC83x external pins are provided in Table 1-1.
User’s Manual
System Architecture, V1.0
1-4
V1.1, 2010-09
XC83x
Introduction
Table 1-1
Pin Definitions and Functions for XC83x
Symbol
Type
P0
I/O
P0.0
P0.1
P0.2
Reset
State
Function
Port 0
Port 0 is a bidirectional general purpose I/O port. It can
be used as alternate functions for LEDTSCU, Timer 0,
1 and 2, SSC, CCU6, IIC, SPD and UART.
Hi-Z
Hi-Z
Hi-Z
User’s Manual
System Architecture, V1.0
T2_0
Timer 2 Input
T13HR_1
CCU6 Timer 13 Hardware Run Input
MTSR_2
SSC Master Transmit Output/
Slave Receive Input
MRST_3
SSC Master Receive Input
T12HR_0
CCU6 Timer 12 Hardware Run Input
CCPOS0_0
CCU6 Hall Input 0
TSIN0
Touch-sense Input 0
LINE0
LED Line 0
COUT61_1
Output of Capture/Compare Channel 1
T0_0
Timer 0 Input
CC61_1
Input/Output of Capture/Compare
channel 1
MTSR_3
SSC Slave Receive Input
MRST_2
SSC Master Receive Input/
Slave Transmit Output
T13HR_0
CCU6 Timer 13 Hardware Run Input
CCPOS1_0
CCU6 Hall Input 1
TSIN1
Touch-sense Input 1
LINE1
LED Line 1
T1_0
Timer 1 Input
CC62_1
Input/Output of Capture/Compare
channel 2
SCL_1
IIC Clock Line
CCPOS2_0
CCU6 Hall Input 2
TSIN2
Touch-sense Input 2
LINE2
LED Line 2
1-5
V1.1, 2010-09
XC83x
Introduction
Table 1-1
Symbol
P0.3
P0.4
P0.5
Pin Definitions and Functions for XC83x (cont’d)
Type
Reset
State
Function
Hi-Z
CC60_1
Input/Output of Capture/Compare
channel 0
SDA_1
IIC Data Line
CTRAP_0
CCU6 Trap Input
TSIN3
Touch-sense Input 3
LINE3
LED Line 3
PD
Hi-Z
User’s Manual
System Architecture, V1.0
T2EX_1
Timer 2 External Trigger Input
SCK_0
SSC Clock Input/Output
SCL_0
IIC Clock Line
CTRAP_1
CCU6 Trap Input
EXINT1_0
External Interrupt Input 1
TSIN4
Touch-sense Input 4
LINE4
LED Line 4
EXF2_0
Timer 2 Overflow Flag
COL0_1
LED Column 0
COL3_2
LED Column 3
COLA_4
LED Column A
RXD_0
UART Receive Input
MTSR_0
SSC Master Transmit Output/
Slave Receive Input
MRST_1
SSC Master Receive Input
EXINT0_0
External Interrupt Input 0
TSIN5
Touch-sense Input 5
LINE5
LED Line 5
COUT62_1
Output of Capture/Compare Channel 2
TXD_4
UART Transmit Output
COL1_1
LED Column 1
EXF2_3
Timer 2 Overflow Flag
1-6
V1.1, 2010-09
XC83x
Introduction
Table 1-1
Symbol
Pin Definitions and Functions for XC83x (cont’d)
Type
P0.6
P0.7
P1
Reset
State
Function
PU
SPD_1
SPD Input/Output
RXD_1
UART Receive Input
SDA_0
IIC Data Line
MTSR_1
SSC Slave Receive Input
MRST_0
SSC Master Receive Input/
Slave Transmit Output
EXINT0_1
External Interrupt Input 0
T2EX_0
Timer 2 External Trigger Input
TSIN6
Touch-sense Input 6
Hi-Z
I/O
User’s Manual
System Architecture, V1.0
LINE6
LED Line 6
TXD_0
UART Transmit Output
COL2_1
LED Column 2
COLA_2
LED Column A
SCL_3
IIC Clock Line
TSIN7
Touch-sense Input 7
LINE7
LED Line 7
TXD_5
UART Transmit Output/
2-wire UART BSL Transmit Output
COUT63_0
Output of Capture/Compare Channel 3
COL3_1
LED Column 3
COLA_3
LED Column A
Port 1
Port 1 is a bidirectional general purpose I/O port. It can
be used as alternate functions for CCU6, LEDTSCU,
SPD, UART and Timer 2
1-7
V1.1, 2010-09
XC83x
Introduction
Table 1-1
Symbol
Pin Definitions and Functions for XC83x (cont’d)
Type
P1.0
Hi-Z
P1.1
Hi-Z
P1.2
Hi-Z
P1.3
Hi-Z
P1.4
Hi-Z
P1.5
P2
Reset
State
Hi-Z
I
User’s Manual
System Architecture, V1.0
Function
SPD_2
SPD Input/Output
RXD_2
UART Receive Input
T2EX_2
Timer 2 External Trigger Input
EXINT0_2
External Interrupt Input 0
COL0_0
LED Column 0
COUT60_0
Output of Capture/Compare Channel 0
TXD_1
UART Transmit Output
CC60_0
Input/Output of Capture/Compare
channel 0
COL1_0
LED Column 1
TXD_2
UART Transmit Output
EXINT4
External Interrupt Input 4
COL2_0
LED Column 2
COUT61_0
Output of Capture/Compare channel 1
COUT63_1
Output of Capture/Compare channel 3
CC61_0
Input/Output of Capture/Compare
channel 1
COL3_0
LED Column 3
EXF2_2
Timer 2 Overflow Flag
EXINT5
External Interrupt Input 5
COL4
LED Column 4
COUT62_0
Output of Capture/Compare channel 2
COUT63_2
Output of Capture/Compare channel 3
CC62_0
Input/Output of Capture/Compare
channel 2
COL5
LED Column 5
COLA_1
LED Column A
Port 2
Port 2 is a general purpose input-only port. It can be
used as inputs for A/D Converter and out of range
comparator, CCU6, Timer 2, SSC and UART.
1-8
V1.1, 2010-09
XC83x
Introduction
Table 1-1
Symbol
P2.0
P2.1
P2.2
P2.3
Pin Definitions and Functions for XC83x (cont’d)
Type
Reset
State
Function
Hi-Z
CCPOS0_1
CCU6 Hall Input 0
T12HR_2
CCU6 Timer 12 Hardware Run Input
T13HR_2
CCU6 Timer 13 Hardware Run Input
Hi-Z
Hi-Z
Hi-Z
User’s Manual
System Architecture, V1.0
T2EX_3
Timer 2 External Trigger Input
T2_1
Timer 2 Input
EXINT0_3
External Interrupt Input 0
AN0
Analog Input 0 /
Out of range comparator channel 0
CCPOS1_1
CCU6 Hall Input 1
RXD_5
UART Receive Input
MTSR_6
SSC Slave Receive Input
T0_1
Timer 0 Input
EXINT1_1
External Interrupt Input 1
AN1
Analog Input 1 /
Out of range comparator channel 1
CCPOS2_1
CCU6 Hall Input 2
T12HR_3
CCU6 Timer 12 Hardware Run Input
T13HR_3
CCU6 Timer 13 Hardware Run Input
SCK_3
SSC Clock Input/Output
T1_1
Timer 1 Input
EXINT2_0
External Interrupt Input 2
AN2
Analog Input 2 /
Out of range comparator channel 2
CCPOS0_2
CCU6 Hall Input 0
CTRAP_2
CCU6 Trap Input
T2_2
Timer 2 Input
EXINT3
External Interrupt Input 3
AN3
Analog Input 3 /
Out of range comparator channel 3
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V1.1, 2010-09
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Introduction
Table 1-1
Symbol
Pin Definitions and Functions for XC83x (cont’d)
Type
P2.4
P2.5
Hi-Z
T12HR_5
CCU6 Timer 12 Hardware Run Input
T13HR_5
CCU6 Timer 13 Hardware Run Input
T2_3
Timer 2 Input
AN4
Analog Input 4 /
Out of range comparator channel 4
T12HR_7
CCU6 Timer 12 Hardware Run Input
Hi-Z
P2.7
P3.0
Function
Hi-Z
P2.6
P3
Reset
State
Hi-Z
I/O
T13HR_7
CCU6 Timer 13 Hardware Run Input
AN5
Analog Input 5 /
Out of range comparator channel 5
SCK_2
SSC Clock Input/Output
EXINT6
External Interrupt Input 6
AN6
Analog Input 6 /
Out of range comparator channel 6
RXD_6
UART Receive Input
T2EX_6
Timer 2 External Trigger Input
MTSR_7
SSC Slave Receive Input
EXINT0_4
External Interrupt Input 0
AN7
Analog Input 7 /
Out of range comparator channel 7
Port 3
Port 3 is a bidirectional general purpose I/O port. It can
be used as alternate functions for IIC, LEDTSCU,
UART, Timer 2, SSC, SPD and 32.768 kHz crystal pad.
PU
User’s Manual
System Architecture, V1.0
SCL_2
IIC Clock Line
SCK_1
SSC Clock Input/Output
EXINT2_1
External Interrupt Input 2
COL6
LED Column 6
XTAL4
32.768 kHz External Oscillator Output
1-10
V1.1, 2010-09
XC83x
Introduction
Table 1-1
Symbol
Pin Definitions and Functions for XC83x (cont’d)
Type
P3.1
P3.2
Reset
State
Function
PU
RXD_4
UART Receive Input
RTCCLK
RTC External Clock Input
MTSR_4
SSC Master Transmit Output/
Slave Receive Input
MRST_4
SSC Master Receive Input
EXINT0_5
External Interrupt Input 0
COLA_0
LED Column A
XTAL3
32.768 kHz External oscillator Input
EXF2_1
Timer 2 Overflow Flag
SPD_0
SPD Input/Output
RXD_3
UART Receive Input/
UART BSL Receive Input
PU
SDA_2
IIC Data Line
MTSR_5
SSC Slave Receive Input
MRST_5
SSC Master Receive Input/
Slave Transmit Output
EXINT0_6
External Interrupt Input 0
T2EX_7
Timer 2 External Trigger Input
TXD_3
UART Transmit Output/
1-wire UART BSL Transmit Output
VDDP
–
–
I/O Port Supply (2.5 V - 5.5 V)
VDDC
–
–
Core Supply Monitor (2.5 V)
VSSP/
VSSC
–
–
I/O Port Ground/
Core Supply Ground
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XC83x
Introduction
1.3
Chip Identification Number
Each device variant of XC83x is assigned an unique chip identification number to allow
easy identification of one device variant from the others. The differentiation is based on
the product, variant type and device step information.
Two methods are provided to read a device variant’s chip identification number:
•
•
In-application subroutine, see Chapter 23.2;
Boot-loader (BSL) mode A, see Chapter 6.2.2.8.
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XC83x
Introduction
1.4
Text Conventions
This document uses the following text conventions for named components of the XC83x:
•
•
•
•
•
•
•
•
Functional units of the XC83x are shown in upper case. For example: “The SSC can
be used to communicate with shift registers.”
Pins using negative logic are indicated by an overbar. For example: “A reset input pin
RESET is provided for the hardware reset.”
Bit fields and bits in registers are generally referenced as “Register name.Bit field” or
“Register name.Bit”. Most of the register names contain a module name prefix,
separated by an underscore character “_” from the actual register name. In the
example of “SSC_CON”, “SSC” is the module name prefix, and “CON” is the actual
register name).
Variables that are used to represent sets of processing units or registers appear in
mixed-case type. For example, the register name “CC6xR” refers to multiple
“CC6xR” registers with the variable x (x = 0, 1, 2). The bounds of the variables are
always specified where the register expression is first used (e.g., “x = 0 - 2”), and is
repeated as needed.
The default radix is decimal. Hexadecimal constants have a suffix with the subscript
letter “H” (e.g., C0H). Binary constants have a suffix with the subscript letter “B”
(e.g., 11B).
When the extents of register fields, groups of signals, or groups of pins are
collectively named in the body of the document, they are represented as
“NAME[A:B]”, which defines a range, from B to A, for the named group. Individual
bits, signals, or pins are represented as “NAME[C]”, with the range of the variable C
provided in the text (e.g., CFG[2:0] and TOS[0]).
Units are abbreviated as follows:
– MHz = Megahertz
– µs = Microseconds
– kBaud, kbit = 1000 characters/bits per second
– MBaud, Mbit = 1,000,000 characters/bits per second
– Kbyte = 1024 bytes of memory
– Mbyte = 1,048,576 bytes of memory
In general, the k prefix scales a unit by 1000 whereas the K prefix scales a unit by
1024. Hence, the Kbyte unit scales the expression preceding it by 1024. The
kBaud unit scales the expression preceding it by 1000. The M prefix scales by
1,000,000 or 1048576, and µ scales by 0.000001. For example, 1 Kbyte is
1024 bytes, 1 Mbyte is 1024 × 1024 bytes, 1 kBaud/kbit are 1000 characters/bits
per second, 1 MBaud/Mbit are 1,000,000 characters/bits per second, and 1 MHz
is 1,000,000 Hz.
Data format quantities are defined as follows:
– Byte = 8-bit quantity
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XC83x
Introduction
1.5
Reserved, Undefined and Unimplemented Terminology
In tables where register bit fields are defined, the following conventions are used to
indicate undefined and unimplemented function. Further, types of bits and bit fields are
defined using the abbreviations shown in Table 1-2.
Table 1-2
Bit Function Terminology
Function of Bits
Description
Unimplemented
Register bit fields named “0” indicate unimplemented functions
with the following behavior.
Reading these bit fields returns 0.
Writing to these bit fields has no effect.
These bit fields are reserved. When writing, software should
always set such bit fields to 0 in order to preserve compatibility
with future products. Setting the bit fields to 1 may lead to
unpredictable results.
Undefined
Certain bit combinations in a bit field can be labeled “Reserved”,
indicating that the behavior of the XC83x is undefined for that
combination of bits. Setting the register to undefined bit
combinations may lead to unpredictable results. Such bit
combinations are reserved. When writing, software must always
set such bit fields to legal values as provided in the bit field
description tables.
rw
The bit or bit field can be read and written.
r
The bit or bit field can only be read (read-only).
w
The bit or bit field can only be written (write-only). Reading
always return 0.
h
The bit or bit field can also be modified by hardware (such as a
status bit). This attribute can be combined with ‘rw’ or ‘r’ bits to
‘rwh’ and ‘rh’ bits, respectively.
1.6
Acronyms
Table 1-3 lists the acronyms used in this document.
Table 1-3
Acronyms
Acronym
Description
ADC
Analog-to-Digital Converter
ALU
Arithmetic/Logic Unit
BSL
Boot-Loader
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Introduction
Table 1-3
Acronyms (cont’d)
Acronym
Description
CAN
Controller Area Network
CCU6
Capture/Compare Unit 6
CGU
Clock Generation Unit
CORDIC
Cordinate Rotation Digital Computer
CPU
Central Processing Unit
DAP
Device Access Port
DNL
Differential Non-Linearity error
ECC
Error Correction Code
EVR
Embedded Voltage Regulator
FDR
Fractional Divider
FIFO
First-In-First-Out data buffer mechanism
GPIO
General Purpose I/O
HCPADA
High Current Bidirectional Pad Type A
HCPADB
High Current Bidirectional Pad Type B
IAP
In-Application Programming
IIC
Inter-IC Bus
I/O
Input/Output
INL
Integral Non-Linearity error
ISP
In-System Programming
JTAG
Joint Test Action Group
LEDTSCU
LED and Touch-Sense Controller Unit
LIN
Local Interconnect Network
LSBn
Least Significant Bit: finest granularity of the analog value in digital
format, represented by one least significant bit of the conversion result
with n bits resolution (measurement range divided in 2n equally
distributed steps)
MDU
Multiplication/Division Unit
NMI
Non-Maskable Interrupt
OCDS
On-Chip Debug Support
ORC
Out of Range Comparator
PC
Program Counter
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Introduction
Table 1-3
Acronyms (cont’d)
Acronym
Description
POR
Power-On Reset
PLL
Phase-Locked Loop
PSW
Program Status Word
PWM
Pulse Width Modulation
RAM
Random Access Memory
ROM
Read-Only Memory
RTC
Real-Time Clock
SCU
System Control Unit of the device
SFR
Special Function Register
SPD
Single Pin DAP
SPI
Serial Peripheral Interface
SSC
Synchronous Serial Channel
TUE
Total Unadjusted Error
UART
Universal Asynchronous Receiver/Transmitter
WDT
Watchdog Timer
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XC83x
XC800 Core
2
XC800 Core
This chapter describes the XC800 Core.
2.1
Overview
The XC800 Core is a complete, high performance CPU core that is functionally upward
compatible to the 8051. While the standard 8051 core is designed around a 12-clock
machine cycle, the XC800 Core uses a two-clock period machine cycle.
The instruction set consists of 45% one-byte, 41% two-byte and 14% three-byte
instructions. Each instruction takes 1, 2 or 4 machine cycles to execute. In case of
access to slower memory, the access time may be extended by wait cycles (one wait
cycle lasts one machine cycle, which is equivalent to two wait states).
The XC800 Core support a range of debugging features including basic stop/start,
single-step execution, breakpoint support and read/write access to the data memory,
program memory and special function registers.
Features
The key features of the XC800 Core implemented are listed below.
•
•
•
•
•
•
•
•
•
•
•
•
Two clocks per machine cycle
On-chip XRAM in external data space
256 bytes IRAM in internal data space
Up to 64 kByte of code space (not fully assigned to implemented memory)
Support for synchronous or asynchronous program and data memory
Wait state support for slow memory
15-source, 4-level interrupt controller
2 data pointers
Power saving modes
Dedicated debug mode
Two 16-bit timers (Timer 0 and Timer 1)
Full duplex serial port (UART)
2.2
XC800 Core Functional Blocks
Figure 2-1 shows the functional blocks of the XC800 Core. The XC800 Core consists
mainly of the instruction decoder, the arithmetic section, the program control section, the
access control section, and the interrupt controller.
The instruction decoder decodes each instruction and accordingly generates the internal
signals required to control the functions of the individual units within the core. These
internal signals have an effect on the source and destination of data transfers and control
the ALU processing.
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XC800 Core
Internal Data
Memory
Core SFRs
Register Interface
External SFRs
External Data
Memory
Program Memory
Clocks
Memory Wait
Reset
Legacy External Interrupts (IEN0, IEN1)
External Interrupts
Non-Maskable Interrupt
16-bit Registers &
Memory Interface
ALU
Opcode &
Immediate
Registers
Multiplier / Divider
Opcode Decoder
Timer 0 / Timer 1
State Machine &
Power Saving
UART
Interrupt
Controller
Core Block Diagram
Figure 2-1
XC800 Core Block Diagram
The arithmetic section of the processor performs extensive data manipulation and
consists of the arithmetic/logic unit (ALU), A register, B register and PSW register. The
ALU accepts 8-bit data words from one or two sources and generates an 8-bit result
under the control of the instruction decoder. The ALU performs both arithmetic and logic
operations. Arithmetic operations include add, substract, multiply, divide, increment,
decrement, BCD-decimal-add-adjust and compare. Logic operations include AND, OR,
Exclusive OR, complement and rotate (right, left or swap nibble (left four)). Also included
is a Boolean unit performing the bit operations as set, clear, complement, jump-if-set,
jump-if-not-set, jump-if-set-and-clear and move to/from carry. The ALU can perform the
bit operations of logical AND or logical OR between any addressable bit (or its
complement) and the carry flag, and place the new result in the carry flag.
The program control section controls the sequence in which the instructions stored in
program memory are executed. The 16-bit program counter (PC) holds the address of
the next instruction to be executed. The conditional branch logic enables internal and
external events to the processor to cause a change in the program execution sequence.
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XC800 Core
The access control unit is responsible for the selection of the on-chip memory resources.
The interrupt requests from the peripheral units are handled by the interrupt controller
unit.
2.3
SFRs of the CPU
The XC800 Core registers occupy direct Internal Data Memory space locations in the
range 80H to FFH.
2.3.1
Stack Pointer (SP, 81H)
The SP register contains the Stack Pointer. The Stack Pointer is used to load the
program counter into internal data memory during LCALL and ACALL instructions and
to retrieve the program counter from memory during RET and RETI instructions. Data
may also be saved on or retrieved from the stack using PUSH and POP instructions.
Instructions that use the stack automatically pre-increment or post-decrement the stack
pointer so that the stack pointer always points to the last byte written to the stack, i.e. the
top of the stack. On reset, the Stack Pointer is reset to 07H. This causes the stack to
begin at a location = 08H above register bank zero. The SP can be read or written under
software control. The programmer must ensure that the location and size of the stack in
internal data memory do not overlap with other application data.
2.3.2
Data Pointer (DPTR, 82-3H)
The Data Pointer (DPTR) is stored in registers DPL (Data Pointer Low byte) and DPH
(Data Pointer High byte) to form 16-bit addresses for External Data Memory accesses
(MOVX A,@DPTR and MOVX @DPTR,A), for program byte moves (MOVC
A,@A+DPTR) and for indirect program jumps (JMP @A+DPTR).
Two true 16-bit operations are allowed on the Data Pointer: load immediate
(MOV DPTR,#data) and increment (INC DPTR).
2.3.3
Accumulator (ACC, E0H)
This register provides one of the operands for most ALU operations. ACC is the symbol
for the accumulator register. The mnemonics for accumulator-specific instructions,
however, refer to the accumulator simply as “A”.
2.3.4
B Register (F0H)
The B register is used during multiply and divide operations to provide the second
operand. For other instructions, it can be treated as another scratch pad register.
2.3.5
Program Status Word (PSW, D0H)
The PSW contains several status bits that reflect the current state of the core.
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XC800 Core
PSW
Program Status Word Register
RMAP: X, PAGE: X
(D0H)
Reset Value: 00H
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS0
OV
F1
P
rwh
rwh
rw
rw
rw
rwh
rw
rh
Field
Bits
Type Description
P
0
rh
Parity Flag
Set/cleared by hardware after each instruction to
indicate an odd/even number of “one” bits in the
accumulator, i.e. even parity.
F1
1
rw
General Purpose Flag
OV
2
rwh
Overflow Flag
Used by arithmetic instructions.
RS0,
RS1
3,
4
rw
Register Bank Select
These bits are used to select one of the four register
banks.
00B Bank 0 selected, data address 00H - 07H
01B Bank 1 selected, data address 08H - 0FH
10B Bank 2 selected, data address 10H - 17H
11B Bank 3 selected, data address 18H - 1FH
F0
5
rw
General Purpose Flag
AC
6
rwh
Auxiliary Carry Flag
Used by instructions which execute BCD operations.
CY
7
rwh
Carry Flag
Used by arithmetic instructions.
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2.3.6
Extended Operation Register (EO, A2H)
The instruction set includes an additional instruction MOVC @(DPTR++),A which writes
to program memory implemented as RAM. This instruction may be used both to
download code into the program memory when the CPU is initialized and subsequently,
to provide software updates. The instruction copies the contents of the accumulator to
the code memory at the location pointed to by the current data pointer, then increments
the data pointer.
The instruction uses the opcode A5H, which is the same as the software break instruction
TRAP (see Table 2-1). Bit TRAP_EN in the Extended Operation (EO) register is used to
select the instruction executed by the opcode A5H. When bit TRAP_EN is 0 (default), the
A5H opcode executes the MOVC instruction. When bit TRAP_EN is 1, the A5H opcode
executes the software break instruction TRAP, which switches the CPU to debug mode
for breakpoint processing.
Register EO is also used to select the current data pointer.
EO
Extended Operation Register
RMAP: X, PAGE: X
7
6
5
(A2H)
Reset Value: 00H
4
3
2
1
0
0
TRAP_EN
0
DPSEL2
DPSEL1
DPSEL0
r
rw
r
rw
rw
rw
Field
Bits
Type Description
DPSEL0,
DPSEL1,
DPSEL2
0,
1,
2
rw
Data Pointer Select
These bits are used to select the current data
pointer.
000B DPTR0 selected
001B DPTR1 selected
others: Reserved
TRAP_EN
4
rw
TRAP Enable
0B
Select MOVC @(DPTR++),A
1B
Select software TRAP instruction
0
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
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XC800 Core
2.3.7
Power Control Register (PCON, 87H)
The PCON register provides control for entering idle mode, baud rate control for UART
in mode 2, as well as two general purpose flags.
The XC800 Core has two power-saving modes: idle mode and power-down mode. The
idle mode can be entered via the PCON register. In idle mode, the clock to the core is
disabled while the timers, serial port and interrupt controller continue to run. In powerdown mode 1, the clock to the entire core is stopped.
PCON
Power Control Register
RMAP: X, PAGE: X
7
6
(87H)
5
4
Reset Value: 00H
3
2
1
0
SMOD
0
GF1
GF0
0
IDLE
rw
r
rw
rw
r
rw
Field
Bits
Type Description
IDLE
0
rw
Idle Mode Enable
0B
Do not enter idle mode
1B
Enter idle mode
GF0
2
rw
General Purpose Flag Bit 0
GF1
3
rw
General Purpose Flag Bit 1
SMOD
7
rw
Double Baud Rate Enable
This bit controls the baud rate generation for UART
in mode 2.
0B
Do not double the baud rate
1B
Double the baud rate
0,
0
1,
[6:4]
r
Reserved
Returns 0 if read; should be written with 0.
2.3.8
Interrupt Registers
One non-maskable and fourteen maskable interrupt nodes are available.
Refer to Interrupt chapter for details of the interrupt registers.
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2.4
SFRs of The Core Peripherals
2.4.1
Timer Registers
Two 16-bit timers are provided - Timer 0 (T0) and Timer 1 (T1).
Refer to Timer 0 and Timer 1 chapter for details of the timer registers.
2.4.2
UART Registers
The UART uses three SFRs - PCON, SCON and SBUF.
Refer to Section 2.3.7 and UART chapter for details of the UART registers.
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2.5
Instruction Timing
A CPU machine cycle comprises two input clock periods, referred to as Phase 1 (P1)
and Phase 2 (P2), that correspond to two different CPU states. A CPU state within an
instruction is referenced by the machine cycle and state number, e.g., C2P1 means the
first clock period within machine cycle 2. Memory access takes place during one or both
phases of the machine cycle. SFR writes occur only at the end of P2. Instructions are 1,
2, or 3 bytes long and can take 1, 2 or 4 machine cycles to execute. Registers are
generally updated and the next opcode pre-fetched at the end of P2 of the last machine
cycle for the current instruction.
The XC800 Core supports access to slow memory by using wait cycle(s). Each wait
cycle lasts one machine cycle, i.e. two clock periods. For example, in case of a memory
requiring one/two wait state(s), the access time is increased by one machine cycle for
every byte of opcode/operand fetched.
Figure 2-2 shows the fetch/execute timing related to the internal states and phases.
Execution of an instruction occurs at C1P1. For a 2-byte instruction, the second reading
starts at C1P1.
Figure 2-2 (a) shows two timing diagrams for a 1-byte, 1-cycle (1 × machine cycle)
instruction. The first diagram shows the instruction being executed within one machine
cycle since the opcode (C1P2) is fetched from a memory without wait state. The second
diagram shows the corresponding states of the same instruction being executed over
two machine cycles (instruction time extended), with one wait cycle inserted for opcode
fetching from the flash memory.
Figure 2-2 (b) shows two timing diagrams for a 2-byte, 1-cycle (1 × machine cycle)
instruction. The first diagram shows the instruction being executed within one machine
cycle since the second byte (C1P1) and the opcode (C1P2) are fetched from a memory
without wait state. The second diagram shows the corresponding states of the same
instruction being executed over three machine cycles (instruction time extended), with
one wait cycle inserted for each access to the flash memory. In this case, two wait cycles
are inserted in total.
Figure 2-2 (c) shows two timing diagrams of a 1-byte, 2-cycle (2 × machine cycle)
instruction. The first diagram shows the instruction being executed over two machine
cycles with the opcode (C2P2) fetched from a memory without wait state. The second
diagram shows the corresponding states of the same instruction being executed over
three machine cycles (instruction time extended), with one wait cycle inserted for opcode
fetching from the slow memory requiring one/two wait state(s).
Note: For instructions that are executed over two or more machine cycles, execution
cycle may or may not be extended in case of access to slow memory with one/two
wait states. The execution cycle is, nonetheless, guaranteed consistent for each
instruction when accessed from slow memory with defined wait state(s).
Reference: Table 2-1.
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XC800 Core
Instruction Timing Examples
fCCLK
Read next opcode
(without wait state)
C1P1
C1P2
next instruction
Read next opcode
(one wait cycle)
C1P1
C1P2
WAIT
WAIT
next instruction
(a) 1-byte, 1-cycle instruction, e.g. INC A
Read 2nd byte
(without wait state)
C1P1
Read next opcode
(without wait state)
C1P2
next instruction
Read 2nd byte
Read next opcode
(one wait cycle)
(one wait cycle)
C1P1
WAIT
WAIT
C1P2
WAIT
WAIT
next instruction
(b) 2-byte, 1-cycle instruction, e.g. ADD A, #data
Read next opcode
(without wait state)
C1P1
C1P2
C2P1
C2P2
next instruction
Read next opcode
(one wait cycle)
C1P1
C1P2
C2P1
C2P2
WAIT
WAIT
next instruction
(c) 1-byte, 2-cycle instruction, e.g. MOVX
Figure 2-2
CPU Instruction Timing
The time taken for each instruction includes:
•
•
•
decoding/executing the fetched opcode
fetching the operand/s (for instructions > 1 byte)
fetching the first byte (opcode) of the next instruction (due to CPU pipeline)
Note: The XC800 Core fetches the opcode of the next instruction while executing the
current instruction.
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XC800 Core
Table 2-1 lists all the instructions supported by the XC800 Core. Instructions are 1, 2 or
3 bytes long as indicted in the ‘Bytes’ column. Each instruction takes 1, 2 or 4 machine
cycles to execute (with no wait cycle). The table gives two values for the number of
machine cycles required by each instruction. The first value applies to fetching operand/s
and opcode from fast memory (e.g. Boot ROM and XRAM) without wait state. The
second value applies to fetching operand/s and opcode (and in some cases accessing
data) from slow memory (e.g. Flash) with wait cycles inserted due to memory requiring
one/two wait state(s). One machine cycle comprises two CCLK clock cycles.
Table 2-1
Instruction Table
Mnemonic
Hex Code Bytes
Machine
Machine Cycles
(one wait state1))
Cycles
(no wait state)
ADD A,Rn
28-2F
1
1
2
ADD A,dir
25
2
1
3
ADD A,@Ri
26-27
1
1
2
ADD A,#data
24
2
1
3
ADDC A,Rn
38-3F
1
1
2
ADDC A,dir
35
2
1
3
ADDC A,@Ri
36-37
1
1
2
ADDC A,#data
34
2
1
3
SUBB A,Rn
98-9F
1
1
2
SUBB A,dir
95
2
1
3
SUBB A,@Ri
96-97
1
1
2
SUBB A,#data
94
2
1
3
INC A
04
1
1
2
INC Rn
08-0F
1
1
2
INC dir
05
2
1
3
INC @Ri
06-07
1
1
2
DEC A
14
1
1
2
DEC Rn
18-1F
1
1
2
DEC dir
15
2
1
3
DEC @Ri
16-17
1
1
2
INC DPTR
A3
1
2
2
ARITHMETIC
User’s Manual
XC800 Core, V 1.0.2
2-10
V1.1, 2010-09
XC83x
XC800 Core
Table 2-1
Instruction Table (cont’d)
Mnemonic
Hex Code Bytes
Machine
Machine Cycles
Cycles
(one wait state1))
(no wait state)
MUL AB
A4
1
4
4
DIV AB
84
1
4
4
DA A
D4
1
1
2
ANL A,Rn
58-5F
1
1
2
ANL A,dir
55
2
1
3
ANL A,@Ri
56-57
1
1
2
ANL A,#data
54
2
1
3
ANL dir,A
52
2
1
3
ANL dir,#data
53
3
2
5
ORL A,Rn
48-4F
1
1
2
ORL A,dir
45
2
1
3
ORL A,@Ri
46-47
1
1
2
ORL A,#data
44
2
1
3
ORL dir,A
42
2
1
3
ORL dir,#data
43
3
2
5
XRL A,Rn
68-6F
1
1
2
XRL A,dir
65
2
1
3
XRL A,@Ri
66-67
1
1
2
XRL A,#data
64
2
1
3
XRL dir,A
62
2
1
3
XRL dir,#data
63
3
2
5
CLR A
E4
1
1
2
CPL A
F4
1
1
2
SWAP A
C4
1
1
2
RL A
23
1
1
2
RLC A
33
1
1
2
RR A
03
1
1
2
RRC A
13
1
1
2
LOGICAL
User’s Manual
XC800 Core, V 1.0.2
2-11
V1.1, 2010-09
XC83x
XC800 Core
Table 2-1
Instruction Table (cont’d)
Mnemonic
Hex Code Bytes
Machine
Machine Cycles
Cycles
(one wait state1))
(no wait state)
MOV A,Rn
E8-EF
1
1
2
MOV A,dir
E5
2
1
3
MOV A,@Ri
E6-E7
1
1
2
MOV A,#data
74
2
1
3
MOV Rn,A
F8-FF
1
1
2
MOV Rn,dir
A8-AF
2
2
4
MOV Rn,#data
78-7F
2
1
3
MOV dir,A
F5
2
1
3
MOV dir,Rn
88-8F
2
2
4
MOV dir,dir
85
3
2
5
MOV dir,@Ri
86-87
2
2
4
MOV dir,#data
75
3
2
5
MOV @Ri,A
F6-F7
1
1
2
MOV @Ri,dir
A6-A7
2
2
4
MOV @Ri,#data
76-77
2
1
3
MOV DPTR,#data
90
3
2
5
MOVC A,@A+DPTR
93
1
2
3 or 42)
MOVC A,@A+PC
83
1
2
3 or 42)
MOVX A,@Ri
E2-E3
1
2
3
MOVX A,@DPTR
E0
1
2
3
MOVX @Ri,A
F2-F3
1
2
3
MOVX @DPTR,A
F0
1
2
3
PUSH dir
C0
2
2
4
POP dir
D0
2
2
4
XCH A,Rn
C8-CF
1
1
2
XCH A,dir
C5
2
1
3
XCH A,@Ri
C6-C7
1
1
2
XCHD A,@Ri
D6-D7
1
1
2
DATA TRANSFER
User’s Manual
XC800 Core, V 1.0.2
2-12
V1.1, 2010-09
XC83x
XC800 Core
Table 2-1
Instruction Table (cont’d)
Mnemonic
Hex Code Bytes
Machine
Machine Cycles
Cycles
(one wait state1))
(no wait state)
CLR C
C3
1
1
2
CLR bit
C2
2
1
3
SETB C
D3
1
1
2
SETB bit
D2
2
1
3
CPL C
B3
1
1
2
CPL bit
B2
2
1
3
ANL C,bit
82
2
2
4
ANL C,/bit
B0
2
2
4
ORL C,bit
72
2
2
4
ORL C,/bit
A0
2
2
4
MOV C,bit
A2
2
1
3
92
2
2
4
ACALL addr11
11->F1
2
2
4
LCALL addr16
12
3
2
5
RET
22
1
2
2 or 32)
RETI
32
1
2
2 or 32)
AJMP addr 11
01->E1
2
2
4
LJMP addr 16
02
3
2
5
SJMP rel
80
2
2
4
JC rel
40
2
2
4
JNC rel
50
2
2
4
JB bit,rel
20
3
2
5
JNB bit,rel
30
3
2
5
JBC bit,rel
10
3
2
5
JMP @A+DPTR
73
1
2
2 or 32)
JZ rel
60
2
2
4
JNZ rel
70
2
2
4
BOOLEAN
MOV bit,C
BRANCHING
3)
User’s Manual
XC800 Core, V 1.0.2
2-13
V1.1, 2010-09
XC83x
XC800 Core
Table 2-1
Instruction Table (cont’d)
Mnemonic
Hex Code Bytes
Machine
Machine Cycles
Cycles
(one wait state1))
(no wait state)
CJNE A,dir,rel
B5
3
2
5
CJNE A,#d,rel
B4
3
2
5
CJNE Rn,#d,rel
B8-BF
3
2
5
CJNE @Ri,#d,rel
B6-B7
3
2
5
DJNZ Rn,rel
D8-DF
2
2
4
DJNZ dir,rel
D5
3
2
5
00
1
1
2
MISCELLANEOUS
NOP
ADDITIONAL INSTRUCTIONS
MOVC @(DPTR++),A
A5
1
2
2 or 32)
TRAP
A5
1
1
–
1) In case of fetch from slow memory requiring only 1 wait state, no wait cycle may be required per the instruction
fetched (normally for opcodes that do not require fetch in the next cycle).
2) Depending on whether the operation is accessing memory with zero or one/two wait state.
3) For branch instructions, the instruction time may vary depending on jump destination.
User’s Manual
XC800 Core, V 1.0.2
2-14
V1.1, 2010-09
XC83x
Memory Organization
3
Memory Organization
The XC83x CPU operates in the following five address spaces:
•
•
•
8 Kbytes of Boot ROM program memory
256 bytes of internal RAM data memory
256 bytes of XRAM memory
(XRAM can be read/written as program memory or external data memory)
a 128-byte Special Function Register area
4 or 8 Kbytes of Flash program memory
(The 8 Kbytes variant contains an additional 64 bytes user BSL Flash sector)
•
•
Figure 3-1 illustrates the memory address spaces of the 8-Kbyte Flash device.
FFFF H
User BSL Flash Sector
64 Bytes2)
XRAM
256 Bytes
FFFF H
FF80H
FF40H
F100H
F000H
XRAM
256 Bytes
F100H
F000H
E000H
Boot ROM
8 KBytes
C000H
B000H
Flash Bank 1
4 KBytes 1)
A000H
Indirect
Address
Direct
Address
Internal RAM
Special Function
Registers
FFH
2000H
Flash Bank 1
4 KBytes 1)
80H
1000H
7FH
Flash Bank 0
4 KBytes
40H
0000H
Code Space
0000H
Internal RAM
In Debug Mode, this 64-byte address area
is replaced by a 64-byte Monitor RAM.
00H
External Data Space
Internal Data Space
1)
Physically one 4-Kbyte Flash bank, mapped to both address range . Flash Bank 1 is only available in 8-Kbyte Flash Variant.
2)
User BSL Flash sector is only available in 8-Kbyte Flash Variant .
Figure 3-1
Memory Map User Mode
Memory Map of 8-Kbyte Flash Device
User’s Manual
Memory Organization, V 1.0
3-1
V1.1, 2010-09
XC83x
Memory Organization
Figure 3-2 illustrates the memory address spaces of the 4-Kbyte Flash device.
FFFF H
FFFF H
F100H
XRAM
256 Bytes
XRAM
256 Bytes
F000H
F100H
F000H
E000H
Boot ROM
8 KBytes
C000H
B000H
Flash Bank 0
4 KBytes 1)
A000H
Indirect
Address
Direct
Address
Internal RAM
Special Function
Registers
FFH
80H
1000H
7FH
Flash Bank 0
4 KBytes
40H
0000H
Code Space
1)
0000H
3.1
In Debug Mode, this 64-byte address area
is replaced by a 64-byte Monitor RAM.
00H
External Data Space
Internal Data Space
Physically one 4-Kbyte Flash bank, mapped to both address range .
Figure 3-2
Internal RAM
Memory Map User Mode
Memory Map of 4-Kbyte Flash Device
Program Memory
The code space is theorectically 64 KBytes. However, only access to defined program
memory (as shown in memory map figure) is supported. For XC83x, defined code space
is occupied by on-chip memories.
3.2
Data Memory
The data space consists of an internal and external data space. Access to internal and
external data space are distinguished by different sets of instruction opcodes. In XC83x,
on-chip XRAM is located in external data space and accessed by MOVX instructions.
XC83x does not support access to external (off-chip) memory. Internal data space is
User’s Manual
Memory Organization, V 1.0
3-2
V1.1, 2010-09
XC83x
Memory Organization
occupied by Internal RAM (IRAM) and Special Function Registers (SFRs), distinguished
by direct or indirect addressing.
3.2.1
Internal Data Memory
The internal data memory is divided into two physically separate and distinct blocks: the
256-byte RAM and the 128-byte Special Function Register (SFR) area. While the upper
128 bytes of RAM and the SFR area share the same address locations, they are
accessed through different addressing modes. The lower 128 bytes of RAM can be
accessed through either direct or register indirect addressing, while the upper 128 bytes
of RAM can be accessed through register indirect addressing only. The SFRs are
accessible through direct addressing.
The 16 bytes of RAM that occupy addresses from 20H to 2FH are bitaddressable. RAM
occupying direct addresses from 30H to 7FH can be used as scratch pad registers or
used for the stack.
3.2.2
External Data Memory
The 256-byte XRAM is mapped to both the external data memory area and the program
memory area. It can be accessed using both ‘MOVX’ and ‘MOVC’ instructions.
The ‘MOVX’ instructions for XRAM access use either 8-bit or 16-bit indirect addresses.
While the DPTR register is used for 16-bit addressing, either register R0 or R1 is used
to form the 8-bit address. The upper byte of the XRAM address during execution of the
8-bit accesses is defined by the value stored in register XADDRH. Hence, the write
instruction for setting the higher order XRAM address in register XADDRH must precede
the ‘MOVX’ instruction.
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
XADDRH register.
XADDRH
On-Chip XRAM Address Higher Order (F2H)
RMAP: 0, PAGE: 3
7
6
5
4
Reset Value: F0H
3
2
1
0
ADDRH
rw
Field
Bits
Type Description
ADDRH
[7:0]
rw
User’s Manual
Memory Organization, V 1.0
Higher Order of On-chip XRAM Address
The value for XC83x is F0H.
3-3
V1.1, 2010-09
XC83x
Memory Organization
3.3
Memory Protection Strategy
The memory protection strategy in XC83x prevents unauthorized read out of critical data
and user IP from Flash memory by blocking all external access to the device.
This is achieved by using the Boot Mode Index (BMI) to control the boot options such
that once the BMI is programmed to enter user mode (productive), it is not allowed to
enter the other boot modes without an erase of the BMI by the user code.
Therefore, boot options that load and execute external code will be blocked and only
user code starting from address 0000H can be executed.
3.4
Special Function Registers
The Special Function Registers (SFRs) occupy direct internal data memory space in the
range 80H to FFH. All registers, except the program counter, reside in the SFR area. The
SFRs include pointers and registers that provide an interface between the CPU and the
on-chip peripherals. As the 128-SFR range is less than the total number of registers
required, address extension mechanisms are required to increase the number of
addressable SFRs. The address extension mechanisms include:
•
•
Mapping
Paging
3.4.1
Address Extension by Mapping
Address extension is performed at the system level by mapping. The SFR area is
extended into two portions: the standard (non-mapped) SFR area and the mapped SFR
area. Each portion supports the same address range 80H to FFH, bringing the number of
addressable SFRs to 256. The extended address range is not directly controlled by the
CPU instruction itself, but is derived from bit RMAP in the system control register
SYSCON0 at address 8FH. To access SFRs in the mapped area, bit RMAP in SFR
SYSCON0 must be set. However, the SFRs in the standard area can be accessed by
clearing bit RMAP. Figure 3-3 shows how the SFR area can be selected.
As long as bit RMAP is set, the mapped SFR area can be accessed. This bit is not
cleared automatically by hardware. Thus, before standard/mapped registers are
accessed, bit RMAP must be cleared/set, respectively, by software.
User’s Manual
Memory Organization, V 1.0
3-4
V1.1, 2010-09
XC83x
Memory Organization
Standard Area (RMAP = 0)
FFH
Module 1 SFRs
SYSCON0.RMAP
Module 2 SFRs
rw
…...
Module n SFRs
80H
SFR Data
(to/from CPU)
Mapped Area (RMAP = 1)
FFH
Module (n+1) SFRs
Module (n+2) SFRs
…...
Module m SFRs
80H
Direct
Internal Data
Memory Address
Figure 3-3
Address Extension by Mapping
User’s Manual
Memory Organization, V 1.0
3-5
V1.1, 2010-09
XC83x
Memory Organization
3.4.1.1
System Control Register 0
The SYSCON0 register contains the bit to select the SFR mapping.
SYSCON0
System control Register 0
RMAP: X, PAGE: X
7
6
5
(8FH)
4
Reset Value: 00H
3
2
1
0
0
RMAP
r
rw
Field
Bits
Type Description
RMAP
0
rw
Special Function Register Map Control
0
Accessed to non-mapped (standard) special
function register area.
1
Accessed to mapped special function register
area.
0
[7:1]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Memory Organization, V 1.0
3-6
V1.1, 2010-09
XC83x
Memory Organization
3.4.2
Address Extension by Paging
Address extension is further performed at the module level by paging. With the address
extension by mapping, the XC83x has a 256-SFR address range. However, this is still
less than the total number of SFRs needed by the on-chip peripherals. To meet this
requirement, some peripherals have a built-in local address extension mechanism for
increasing the number of addressable SFRs. The extended address range is not directly
controlled by the CPU instruction itself, but is derived from bit field PAGE in the module
page register MOD_PAGE. Hence, the bit field PAGE must be programmed before
accessing the SFRs of the target module. Each module may contain a different number
of pages and a different number of SFRs per page, depending on the specific
requirement. Besides setting the correct RMAP bit value to select the SFR area, the user
must also ensure that a valid PAGE is selected to target the desired SFRs. Figure 3-4
shows how a page inside the extended address range can be selected.
SFR Address
(from CPU)
PAGE 0
MOD_PAGE.PAGE
SFR0
rw
SFR1
…...
SFRx
PAGE 1
SFR0
SFR Data
(to/from CPU)
SFR1
…...
SFRy
…...
PAGE q
SFR0
SFR1
…...
SFRz
Module
Figure 3-4
Address Extension by Paging
User’s Manual
Memory Organization, V 1.0
3-7
V1.1, 2010-09
XC83x
Memory Organization
In order to access a register located in a page other than the current one, the current
page must be exited. This is done by reprogramming the bit field PAGE in the page
register. Only then can the desired access be performed.
If an interrupt routine is initiated between the page register access and the module
register access, and the interrupt needs to access a register located in another page, the
current page setting can be saved, the new one programmed, and the old page setting
restored. This is possible with the storage fields MOD_STx (x = 0 - 3) for the save and
restore action of the current page setting. Each peripheral that supports this local
address extension mechanism has its own set of storage fields. For example, the
storage fields of the ADC will be ADC_STx. By indicating which storage bit field should
be used in parallel with the new page value, a single write operation can:
•
•
Save the contents of PAGE in MOD_STx before overwriting with the new value
(this is done at the beginning of the interrupt routine to save the current page setting
and program the new page number); or
Overwrite the contents of PAGE with the contents of MOD_STx, ignoring the value
written to the bit positions of PAGE
(this is done at the end of the interrupt routine to restore the previous page setting
before the interrupt occurred)
MOD_ST3
MOD_ST2
MOD_ST1
MOD_ST0
STNR
PAGE
value update
from CPU
Figure 3-5
Storage Elements for Paging
With this mechanism, a certain number of interrupt routines (or other routines) can
perform page changes without reading and storing the previously used page information.
The use of only write operations makes the system simpler and faster. Consequently,
this mechanism significantly improves the performance of short interrupt routines.
The XC83x supports local address extension for:
•
•
•
•
Parallel Ports
Analog-to-Digital Converter (ADC)
Capture/Compare Unit 6 (CCU6)
System Control Registers
User’s Manual
Memory Organization, V 1.0
3-8
V1.1, 2010-09
XC83x
Memory Organization
3.4.2.1
Page Register
The page register has the following definition:
MOD_PAGE
Page Register for module MOD
7
6
Reset Value: 00H
5
4
3
2
1
OP
STNR
0
PAGE
w
w
r
rw
0
Field
Bits
Type Description
PAGE
[2:0]
rw
Page Bits
When written, the value indicates the new page.
When read, the value indicates the currently active
page.
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit field OP.
If OP = 10B,
the contents of PAGE are saved in MOD_STx before
being overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contents of MOD_STx. The value written to the bit
positions of PAGE is ignored.
00
01
10
11
User’s Manual
Memory Organization, V 1.0
MOD_ST0 is selected.
MOD_ST1 is selected.
MOD_ST2 is selected.
MOD_ST3 is selected.
3-9
V1.1, 2010-09
XC83x
Memory Organization
Field
Bits
Type Description
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the previous
contents of PAGE are saved in the storage bit
field MOD_STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field MOD_STx
indicated by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
3.4.3
Bit-Addressing
SFRs that have addresses in the form of 1XXXX000B (e.g., 80H, 88H, 90H, ..., F0H, F8H)
are bitaddressable.
User’s Manual
Memory Organization, V 1.0
3-10
V1.1, 2010-09
XC83x
Memory Organization
3.4.4
Bit Protection Scheme
The bit protection scheme prevents direct software writing of selected bits (i.e., protected
bits) using the PASSWD register. When the bit field MODE is 11B, writing 10011B to the
bit field PASS opens access to writing of all protected bits, and writing 10101B to the bit
field PASS closes access to writing of all protected bits. In both cases, the value of the
bit field MODE is not changed even if PASSWD register is written with 98H or A8H. It can
only be changed when bit field PASS is written with 11000B, for example, writing D0H to
PASSWD register disables the bit protection scheme.
Note that access is opened for maximum 32 CCLKs if the “close access” password is not
written. If “open access” password is written again before the end of 32 CCLK cycles,
there will be a recount of 32 CCLK cycles. The protected bits are: include the soft reset
request bit, SWRQ; the Watchdog Timer enable bit, WDTEN; the RTC clock count
registers, CNT0 - 5; and the power-down enable bit, PD.
•
•
•
•
RSTCON.SWRQ: soft reset request bit
PMCON0.PD: power-down enable bit
WDTCON.WDTEN: WDT enable bit
RTC_CNTx (x = 0 - 5): all bits of RTC clock count registers
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
PASSWD register.
PASSWD
Password Register
RMAP: 0, PAGE: 1
7
Reset Value: 07H
6
5
4
3
2
1
0
PASS
PROTECT
_S
MODE
wh
rh
rw
User’s Manual
Memory Organization, V 1.0
3-11
V1.1, 2010-09
XC83x
Memory Organization
Field
Bits
Type Description
MODE
[1:0]
rw
Bit Protection Scheme Control bits
00
Scheme disabled - direct access to the
protected bits is allowed.
11
Scheme enabled - the bit field PASS has to be
written with the passwords to open and close
the access to protected bits. (default)
Others: Scheme enabled
These two bits cannot be written directly. To change
the value between 11B and 00B, the bit field PASS
must be written with 11000B; only then, will the
MODE[1:0] be registered.
PROTECT_S
2
rh
Bit Protection Signal Status bit
This bit shows the status of the protection.
0
Software is able to write to all protected bits.
1
Software is unable to write to any protected
bits.
PASS
[7:3]
wh
Password bits
The Bit Protection Scheme only recognizes three
patterns.
11000BEnables writing of the bit field MODE.
10011BOpens access to writing of all protected bits.
10101BCloses access to writing of all protected bits.
User’s Manual
Memory Organization, V 1.0
3-12
V1.1, 2010-09
XC83x
Memory Organization
3.4.5
XC83x Register Overview
The SFRs of the XC83x are organized into groups according to their functional units. The
contents (bits) of the SFRs are summarized in Section 3.4.5.1 to Section 3.4.5.13.
Note: The addresses of the bit addressable SFRs appear in bold typeface.
3.4.5.1
CPU Registers
The CPU SFRs can be accessed in both the standard and mapped memory areas
(RMAP = 0 or 1).
Table 3-1
CPU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
DPL0
RMAP = 0 or 1
81H
SP
Reset: 07H
Stack Pointer Register
Bit Field
DPL
Reset: 00H
Data Pointer Register Low
Bit Field
83H
DPH
Reset: 00H
Data Pointer Register High
Bit Field
87H
PCON
Reset: 00H
Power Control Register
Bit Field
88H
TCON
Reset: 00H
Timer Control Register
Bit Field
89H
TMOD
Reset: 00H
Timer Mode Register
Bit Field
8AH
TL0
Reset: 00H
Timer 0 Register Low
Bit Field
Type
rwh
8BH
TL1
Reset: 00H
Timer 1 Register Low
Bit Field
VAL
Type
rwh
8CH
TH0
Reset: 00H
Timer 0 Register High
Bit Field
VAL
Type
rwh
8DH
TH1
Reset: 00H
Timer 1 Register High
Bit Field
VAL
98H
SCON
Reset: 00H
Serial Channel Control Register
Bit Field
SBUF
Reset: 00H
Serial Data Buffer Register
Bit Field
EO
Reset: 00H
Extended Operation Register
Bit Field
0
Type
r
82H
Type
Type
Type
Type
Type
99H
A2H
User’s Manual
Memory Organization, V 1.0
SP
Type
rw
DPL7
DPL6
DPL5
DPL4
DPL3
DPL2
DPL1
rw
rw
rw
rw
rw
rw
rw
rw
DPH7
DPH6
DPH5
DPH4
DPH3
DPH2
DPH1
DPH0
rw
rw
rw
rw
rw
rw
rw
rw
GF1
GF0
0
IDLE
SMOD
0
rw
TF1
r
TR1
TF0
rwh
TR0
rwh
rw
GATE
1
T1S
T1M
rw
rw
rw
rw
rw
r
rw
IT1
IE0
IT0
rwh
rwh
rw
GATE
0
T0S
T0M
rw
rw
rw
rw
VAL
Type
Type
rw
IE1
rwh
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
rw
rw
rw
rw
rw
rwh
rwh
rwh
TRAP_
EN
0
DPSE
L2
DPSE
L1
DPSE
L0
rw
r
rw
rw
rw
VAL
Type
rwh
3-13
V1.1, 2010-09
XC83x
Memory Organization
Table 3-1
CPU Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
A8H
IEN0
Reset: 00H
Interrupt Enable Register 0
Bit Field
EA
0
ET2
ES
ET1
EX1
ET0
EX0
Type
rw
B8H
IP
Reset: 00H
Interrupt Priority Register
Bit Field
Type
r
rw
rw
rw
rw
rw
rw
B9H
IPH
Reset: 00H
Interrupt Priority High Register
Bit Field
0
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
rw
rw
rw
rw
rw
rw
D0H
PSW
Reset: 00H
Program Status Word Register
Bit Field
CY
AC
F0
RS1
RS0
OV
F1
P
Type
rwh
rwh
rw
rw
rw
rwh
rw
rh
ACC
Reset: 00H
Accumulator Register
Bit Field
ACC7
ACC6
ACC5
ACC4
ACC3
ACC2
ACC1
ACC0
rw
rw
rw
rw
rw
rw
rw
rw
E8H
IEN1
Reset: 00H
Interrupt Enable Register 1
Bit Field
ECCIP
3
ECCIP
2
ECCIP
1
ECCIP
0
EXM
EX2
ESSC
EADC
Type
rw
rw
rw
rw
rw
rw
rw
rw
F0H
B
B Register
Reset: 00H
Bit Field
B7
B6
B5
B4
B3
B2
B1
B0
F8H
IP1
Reset: 00H
Interrupt Priority 1 Register
Bit Field
F9H
IPH1
Reset: 00H
Interrupt Priority 1 High Register
Bit Field
E0H
Type
Type
Type
Type
Type
3.4.5.2
r
0
r
rw
rw
rw
rw
rw
rw
PT2
PS
PT1
PX1
PT0
PX0
rw
rw
rw
rw
rw
rw
rw
rw
PCCIP
3
PCCIP
2
PCCIP
1
PCCIP
0
PXM
PX2
PSSC
PADC
rw
rw
rw
rw
rw
rw
rw
rw
PCCIP
3H
PCCIP
2H
PCCIP
1H
PCCIP
0H
PXMH
PX2H
PSSC
H
PADC
H
rw
rw
rw
rw
rw
rw
rw
rw
2
1
0
MDU Registers
The MDU SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-2
MDU Register Overview
Addr Register Name
Bit
7
6
5
4
3
RMAP = 0
B0H
MDUSTAT
Reset: 00H
MDU Status Register
Bit Field
0
BSY
IERR
IRDY
Type
r
rh
rwh
rwh
B1H
MDUCON
Reset: 00H
MDU Control Register
Bit Field
IE
IR
RSEL
STAR
T
OPCODE
Type
rw
rw
rw
rwh
rw
B2H
MD0
Reset: 00H
MDU Operand Register 0
Bit Field
B2H
MR0
Reset: 00H
MDU Result Register 0
Bit Field
B3H
MD1
Reset: 00H
MDU Operand Register 1
Bit Field
User’s Manual
Memory Organization, V 1.0
DATA
Type
rw
DATA
Type
rh
DATA
Type
rw
3-14
V1.1, 2010-09
XC83x
Memory Organization
Table 3-2
MDU Register Overview (cont’d)
Addr Register Name
Bit
B3H
MR1
Reset: 00H
MDU Result Register 1
Bit Field
B4H
MD2
Reset: 00H
MDU Operand Register 2
Bit Field
B4H
MR2
Reset: 00H
MDU Result Register 2
Bit Field
B5H
MD3
Reset: 00H
MDU Operand Register 3
Bit Field
B5H
MR3
Reset: 00H
MDU Result Register 3
Bit Field
B6H
MD4
Reset: 00H
MDU Operand Register 4
Bit Field
B6H
MR4
Reset: 00H
MDU Result Register 4
Bit Field
B7H
MD5
Reset: 00H
MDU Operand Register 5
Bit Field
B7H
MR5
Reset: 00H
MDU Result Register 5
Bit Field
3.4.5.3
7
6
5
4
3
2
1
0
DATA
Type
rh
DATA
Type
rw
DATA
Type
rh
DATA
Type
rw
DATA
Type
rh
DATA
Type
rw
DATA
Type
rh
DATA
Type
rw
DATA
Type
rh
CORDIC Registers
The CORDIC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-3
CORDIC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
BAH
CD_CORDXL
Reset: 00H
CORDIC X Data Low Byte
Bit Field
BBH
CD_CORDXH
Reset: 00H
CORDIC X Data High Byte
Bit Field
BCH
CD_CORDYL
Reset: 00H
CORDIC Y Data Low Byte
Bit Field
BDH
CD_CORDYH
Reset: 00H
CORDIC Y Data High Byte
Bit Field
BEH
CD_CORDZL
Reset: 00H
CORDIC Z Data Low Byte
Bit Field
BFH
CD_CORDZH
Reset: 00H
CORDIC Z Data High Byte
Bit Field
User’s Manual
Memory Organization, V 1.0
DATAL
Type
rw
DATAH
Type
rw
DATAL
Type
rw
DATAH
Type
rw
DATAL
Type
rw
DATAH
Type
rw
3-15
V1.1, 2010-09
XC83x
Memory Organization
Table 3-3
CORDIC Register Overview (cont’d)
Addr Register Name
Bit
A0H
CD_STATC
Reset: 00H
CORDIC Status and Data
Control Register
Bit Field
A1H
CD_CON
Reset: 00H
CORDIC Control Register
Bit Field
Type
7
6
5
4
3
2
1
0
KEEP
Z
KEEP
Y
KEEP
X
DMAP
INT_E
N
EOC
ERRO
R
BSY
rw
rw
rwh
rh
rw
rw
rw
MPS
X_USI
GN
ST_M
ODE
ROTV
EC
MODE
ST
rw
rw
rw
rw
rw
rwh
Type
3.4.5.4
rh
System Control Registers
The system control SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-4
SCU Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0 or 1
8FH
SYSCON0
Reset: 04H
System Control Register 0
Bit Field
0
RMAP
Type
r
rw
RMAP = 0
F1H
SCU_PAGE
Page Register
Reset: 00H
Bit Field
Type
OP
STNR
0
PAGE
w
w
r
rw
RMAP = 0, PAGE 0
EEH
NMICON
Reset: 00H
NMI Control Register
Bit Field
EFH
EXICON0
Reset: F0H
External Interrupt Control
Register 0
Bit Field
F2H
IRCON0
Reset: 00H
Interrupt Request Register 0
Bit Field
0
EXINT
6
EXINT
5
Type
r
rwh
rwh
F3H
IRCON1
Reset: 00H
Interrupt Request Register 1
Bit Field
F4H
EXICON1
Reset: 3FH
External Interrupt Control
Register 1
Bit Field
0
EXINT6
EXINT5
EXINT4
Type
r
rw
rw
rw
F5H
IRCON2
Reset: 00H
Interrupt Request Register 2
Bit Field
F6H
IRCON3
Reset: 00H
Interrupt Request Register 3
Type
NMI
XTAL
CLK
NMI
ECC
NMI
VDDP
NMI
VDDC
NMI
OCDS
NMI
FLASH
NMI
OSC
CLK
NMI
WDT
rw
rw
rw
rw
rw
rw
rw
rw
EXINT3
Type
rw
EXINT1
EXINT0
rw
rw
rw
EXINT
4
0
Type
User’s Manual
Memory Organization, V 1.0
EXINT2
r
0
EXINT
3
EXINT
2
0
rwh
rwh
rwh
ADCS
R1
ADCS
R0
RIR
TIR
EIR
rwh
rwh
rwh
rwh
rwh
CCU6
SR1
0
r
CCU6
SR0
Type
r
rwh
r
rwh
Bit Field
0
CCU6
SR3
0
CCU6
SR2
Type
r
rwh
r
rwh
3-16
V1.1, 2010-09
XC83x
Memory Organization
Table 3-4
SCU Register Overview (cont’d)
Addr Register Name
Bit
F7H
Bit Field
NMISR
Reset: 00H
NMI Status Register
Type
7
6
5
4
3
2
1
0
FNMI
XTAL
CLK
FNMI
ECC
FNMI
VDDP
FNMI
VDDC
FNMI
OCDS
FNMI
FLASH
FNMI
OSC
CLK
FNMI
WDT
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
VDDP
TH
VDDC
TH
VDDP
BOBP
VDDP
BOA
VDDP
PW
VDDC
PW
RMAP = 0, PAGE 1
EEH
SDCON
Reset: 34H
Supply Detection Control
Register
Bit Field
0
EFH
PMCON1
Reset: 00H
Power Mode Control Register 1
Bit Field
F2H
PASSWD
Reset: 07H
Password Register
Bit Field
F3H
PMCON0
Reset: 01H
Power Mode Control Register 0
Bit Field
F4H
OSC_CON
Reset: 30H
OSC Control Register
Bit Field
0
INT
OSC_
ST
Type
r
rh
F5H
ID
Identity Register
F6H
WDTCON
Reset: 00H
Watchdog Timer Control
Register
Bit Field
F7H
RSTCON
Reset: 00H
Reset Control Register
Bit Field
Type
Type
r
IIC_
DIS
LTS_
DIS
rw
rw
rw
rw
rw
rw
T2_
DIS
CCU_
DIS
SSC_
DIS
ADC_
DIS
rw
rw
rw
rw
rw
rw
PROT
ECT_S
wh
WK
SEL
r
PDMODE
rw
rw
XPD
XTAL
2L
XTAL
OWD
RST
75K
OSC
2L
rw
rh
rwh
rh
PRODID
Bit Field
Type
Type
WINB
EN
r
rw
rw
PD
EWS
rwh
rw
48M
OSC
2L
RC
OWD
RST
rh
rwh
VERID
r
0
MODE
rh
0
Type
Type
rh
MDU_
DIS
PASS
Type
Reset: UUH
rh
CDC_
DIS
r
WDT
PR
0
rh
r
WDT
EN
WDT
RS
0
rw
rwh
r
SWRQ
0
SOFT
RS
WDT
RST
WKRS
rwh
r
rwh
rwh
rwh
RMAP = 0, PAGE 3
MODPISEL3
Reset: 00H
Peripheral Input Select Register
3
Bit Field
XADDRH
Reset: F0H
On-chip XRAM Address Higher
Order
Bit Field
MODPISEL
Reset: 00H
Peripheral Input Select Register
Bit Field
CIS
SIS
Type
rw
rw
rw
F4H
MODPISEL1
Reset: 00H
Peripheral Input Select Register
1
Bit Field
EXINT0IS
URRIS
Type
rw
rw
F5H
MODPISEL2
Reset: 00H
Peripheral Input Select Register
2
Bit Field
0
T0IS
T1IS
T2IS
T2EXIS
Type
r
rw
rw
rw
rw
EEH
F2H
F3H
User’s Manual
Memory Organization, V 1.0
IST13HR1
IST12HR1
CTRAPIS
rw
rw
rw
Type
ADDRH
Type
rw
EXINT
2IS
EXINT
1IS
3-17
MIS
rw
rw
V1.1, 2010-09
XC83x
Memory Organization
Table 3-4
SCU Register Overview (cont’d)
Addr Register Name
Bit
F6H
MODSUSP
Reset: 01H
Module Suspend Control
Register
Bit Field
F7H
MODIEN
Reset: 07H
Peripheral Interrupt Enable
Register
7
6
0
Type
Bit Field
Type
r
5
4
3
2
1
0
LTS
SUSP
RTC
SUSP
T2SUS
P
T13SU
SP
T12SU
SP
WDTS
USP
rw
rw
rw
rw
rw
rw
CCU6
SR3
EN
CCU6
SR2
EN
0
RIREN
TIREN
EIREN
rw
rw
r
rw
rw
rw
RMAP = 0, PAGE 4
F3H
F4H
F5H
F6H
WDTREL
Reset: 00H
Watchdog Timer Reload
Register
Bit Field
WDTWINB
Reset: 00H
Watchdog Window-Boundary
Count Register
Bit Field
WDTL
Reset: 00H
Watchdog Timer Register Low
WDTH
Reset: 00H
Watchdog Timer Register High
WDTREL
Type
rw
WDTWINB
Type
rw
Bit Field
WDT
Type
rh
Bit Field
WDT
Type
rh
RMAP = 0, PAGE 5
F2H
BCON
Reset: 00H
Baud Rate Control Register
Bit Field
BGSEL
0
BRDIS
BRPRE
R
Type
rw
r
rw
rw
rw
BGL
Reset: 00H
Baud Rate Timer/Reload
Register, Low Byte
Bit Field
BR_VALUE
BGH
Reset: 00H
Baud Rate Timer/Reload
Register, High Byte
Bit Field
F5H
LINST
Reset: 00H
LIN Status Register
Bit Field
F6H
FEAL
Reset: 00H
Flash Error Address Register
Low
Bit Field
F7H
FEAH
Reset: 00H
Flash Error Address Register
High
Bit Field
F3H
F4H
Type
rw
BR_VALUE
Type
Type
3.4.5.5
FDSEL
rwh
rwh
BGS
SYNE
N
ERRS
YN
rw
rw
rwh
EOFS
YN
BRK
0
rwh
rwh
r
ECCERRADDR
Type
rh
ECCERRADDR
Type
rh
Port Registers
The Port SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-5
Port Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
User’s Manual
Memory Organization, V 1.0
3-18
V1.1, 2010-09
XC83x
Memory Organization
Table 3-5
Port Register Overview (cont’d)
Addr Register Name
Bit
8EH
Bit Field
PORT_PAGE
Page Register
Reset: 00H
7
Type
6
5
4
3
2
1
OP
STNR
0
PAGE
w
w
r
rw
0
RMAP = 0, PAGE 0
P0_DATAOUT
Reset: FFH
P0 Data Output Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
Type
rw
rw
rw
rw
rw
rw
rw
rw
86H
P0_DATAIN
Reset: UUH
P0 Data In Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rh
90H
P1_DATA
Reset: 3FH
P1 Data Register
Bit Field
Type
r
rw
rw
rw
rw
rw
rw
91H
P1_DATAIN
Reset: UUH
P1 Data In Register
Bit Field
0
P5
P4
P3
P2
P1
P0
92H
P1_OCD
Reset: 00H
P1 Overcurrent Detect Register
Bit Field
Type
rw
rw
94H
P2_DATAIN
Reset: UUH
P2 Data In Register
Bit Field
P7
P6
Type
rh
rh
rh
C8H
P3_DATAOUT
Reset: 07H
P3 Data Out Register
Bit Field
Type
r
rh
rh
rh
C9H
P3_DATAIN
Reset: UUH
P3 Data In Register
Bit Field
0
P2
P1
P0
Type
r
rw
rw
rw
80H
rh
0
Type
r
P3_O
CEN
P2_O
CEN
P0
rh
rh
rh
rh
rh
rh
P5
P4
P3
P2
P1
P0
rh
rh
rh
rh
rh
rh
P1_O
CEN
P0_O
CEN
P3_O
CF
P2_O
CF
P1_O
CF
P0_O
CF
rw
rw
rwh
rwh
rwh
rwh
P5
P4
P3
P2
P1
P0
rh
rh
rh
rh
rh
P2
P1
P0
0
RMAP = 0, PAGE 1
80H
P0_PUDSEL
Reset: EFH
P0 Pull-Up/Pull-Down Select
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P0_PUDEN
Reset: C4H
P0 Pull-Up/Pull-Down Enable
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P1_PUDSEL
Reset: 3FH
P1 Pull-Up/Pull-Down Select
Register
Bit Field
0
P5
P4
P3
P2
P1
P0
Type
r
rw
rw
rw
rw
rw
rw
P1_PUDEN
Reset: 00H
P1 Pull-Up/Pull-Down Enable
Register
Bit Field
0
P5
P4
P3
P2
P1
P0
Type
r
rw
rw
rw
rw
rw
rw
92H
P1_OCPEN
Reset: 00H
P1 Overcurrent Proctection
Enable Register
Bit Field
P3
P2
P1
P0
rw
rw
rw
rw
93H
P2_PUDSEL
Reset: FFH
P2 Pull-Up/Pull-Down Select
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P2_PUDEN
Reset: 00H
P2 Pull-Up/Pull-Down Enable
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P3_PUDSEL
Reset: BFH
P3 Pull-Up/Pull-Down Select
Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
86H
90H
91H
94H
C8H
User’s Manual
Memory Organization, V 1.0
0
Type
r
3-19
V1.1, 2010-09
XC83x
Memory Organization
Table 3-5
Port Register Overview (cont’d)
Addr Register Name
Bit
7
6
5
4
3
2
1
0
C9H
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
P0_ALTSEL0
Reset: 00H
P0 Alternate Select 0 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
85H
P0_ALTSEL2
Reset: 00H
P0 Alternate Select 2 Register
Bit Field
P7
P6
P5
P4
Type
rw
rw
rw
rw
86H
P0_ALTSEL1
Reset: 00H
P0 Alternate Select 1 Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
90H
P1_ALTSEL0
Reset: 00H
P1 Alternate Select 0 Register
Bit Field
P5
P4
P3
P2
P1
P0
Type
r
rw
rw
rw
rw
rw
rw
91H
P1_ALTSEL1
Reset: 00H
P1 Alternate Select 1 Register
Bit Field
0
P5
P4
P3
P2
P1
P0
Type
r
rw
rw
rw
C8H
P3_ALTSEL0
Reset: 00H
P3 Alternate Select 0 Register
Bit Field
Type
r
rw
rw
rw
C9H
P3_ALTSEL1
Reset: 00H
P3 Alternate Select 1 Register
Bit Field
0
P2
P1
P0
Type
r
rw
rw
rw
P0
P3_PUDEN
Reset: 40H
P3 Pull-Up/Pull-Down Enable
Register
RMAP = 0, PAGE 2
80H
0
0
r
0
rw
rw
rw
P2
P1
P0
RMAP = 0, PAGE 3
80H
P0_OD
Reset: FFH
P0 Open Drain Control Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
Type
rw
rw
rw
rw
rw
rw
rw
rw
90H
P1_OD
Reset: 3FH
P1 Open Drain Control Register
Bit Field
0
P5
P4
P3
P2
P1
P0
Type
r
rw
rw
92H
P1_SLEW
Reset: 00H
P1 Slew Register
Bit Field
rw
rw
rw
rw
94H
P2_EN
Reset: 00H
P2 Enable Register
Bit Field
P7
P6
P5
P4
P3
P2
P1
P0
Type
rw
rw
rw
rw
rw
rw
rw
rw
C8H
P3_OD
Reset: 07H
P3 Open Drain Control Register
Bit Field
0
P2
P1
P0
Type
r
rw
rw
rw
1
0
3.4.5.6
0
Type
r
rw
rw
rw
rw
P3
P2
P1
P0
ADC Registers
The ADC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-6
ADC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
RMAP = 0
D1H
ADC_PAGE
Page Register
Reset: 00H
Bit Field
Type
OP
STNR
0
PAGE
w
w
r
rw
RMAP = 0, PAGE 0
User’s Manual
Memory Organization, V 1.0
3-20
V1.1, 2010-09
XC83x
Memory Organization
Table 3-6
ADC Register Overview (cont’d)
Addr Register Name
Bit
CAH
ADC_GLOBCTR Reset: 30H
Global Control Register
Bit Field
CBH
ADC_GLOBSTR Reset: 00H
Global Status Register
Bit Field
CCH
ADC_PRAR
Reset: 00H
Priority and Arbitration Register
Bit Field
CDH
ADC_LCBR0
Reset: 70H
Limit Check Boundary Register 0
Bit Field
CEH
ADC_INPCR0
Reset: 00H
Input Class 0 Register
Bit Field
0
Type
r
CFH
ADC_LCBR1
Reset: B0H
Limit Check Boundary Register 1
Bit Field
D2H
ADC_LORE
Reset: 00H
Latched Out of Range Event
Register
Bit Field
D3H
ADC_ENORC
Reset: 00H
Enable Out of Range
Comparator Register
Bit Field
Type
7
6
3
2
ANON
DW
CTC
ORCIE
N
CLCIE
N
rw
rw
rw
rw
rw
4
0
Type
Type
5
CHNR
r
SAMP
LE
BUSY
r
rh
rh
ASEN
0
0
ARBM
CSM1
PRIO1
CSM0
PRIO0
rw
rw
r
rw
rw
rw
rw
rw
LORE
1
LORE
0
BOUND0
rw
STC
rw
BOUND1
Type
Type
r
0
rh
0
0
ASEN
1
Type
Type
1
rw
LORE
7
LORE
6
LORE
5
LORE
4
LORE
3
LORE
2
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
ENOR
C7
ENOR
C6
ENOR
C5
ENOR
C4
ENOR
C3
ENOR
C2
ENOR
C1
ENOR
C0
rw
rw
rw
rw
rw
rw
rw
rw
RMAP = 0, PAGE 1
CAH
ADC_CHCTR0
Reset: 00H
Channel Control Register 0
Bit Field
CBH
ADC_CHCTR1
Reset: 00H
Channel Control Register 1
Bit Field
CCH
ADC_CHCTR2
Reset: 00H
Channel Control Register 2
Bit Field
Type
rw
rw
rw
rw
CDH
ADC_CHCTR3
Reset: 00H
Channel Control Register 3
Bit Field
0
LCC
REFSEL
RESRSEL
Type
r
rw
rw
rw
CEH
ADC_CHCTR4
Reset: 00H
Channel Control Register 4
Bit Field
0
LCC
REFSEL
RESRSEL
Type
r
rw
rw
rw
CFH
ADC_CHCTR5
Reset: 00H
Channel Control Register 5
Bit Field
0
LCC
REFSEL
RESRSEL
Type
r
rw
rw
rw
D2H
ADC_CHCTR6
Reset: 00H
Channel Control Register 6
Bit Field
0
LCC
REFSEL
RESRSEL
Type
r
rw
rw
rw
D3H
ADC_CHCTR7
Reset: 00H
Channel Control Register 7
Bit Field
0
LCC
REFSEL
RESRSEL
Type
r
rw
rw
rw
Type
Type
BFEN
LCC
REFSEL
rw
rw
rw
RESRSEL
rw
BFEN
LCC
REFSEL
RESRSEL
rw
rw
rw
rw
BFEN
LCC
REFSEL
RESRSEL
RMAP = 0, PAGE 2
User’s Manual
Memory Organization, V 1.0
3-21
V1.1, 2010-09
XC83x
Memory Organization
Table 3-6
ADC Register Overview (cont’d)
Addr Register Name
Bit
CAH
ADC_RESR0L
Reset: 00H
Result Register 0 Low
Bit Field
CBH
ADC_RESR0H
Reset: 00H
Result Register 0 High
Bit Field
CCH
ADC_RESR1L
Reset: 00H
Result Register 1 Low
Bit Field
CDH
ADC_RESR1H
Reset: 00H
Result Register 1 High
Bit Field
CEH
ADC_RESR2L
Reset: 00H
Result Register 2 Low
Bit Field
CFH
ADC_RESR2H
Reset: 00H
Result Register 2 High
Bit Field
D2H
ADC_RESR3L
Reset: 00H
Result Register 3 Low
Bit Field
ADC_RESR3H
Reset: 00H
Result Register 3 High
Bit Field
D3H
7
4
3
RESULT
6
VF
DRC
CHNR
rh
rh
rh
rh
Type
5
2
1
0
RESULT
Type
rh
RESULT
VF
DRC
CHNR
rh
rh
rh
rh
Type
RESULT
Type
rh
RESULT
VF
DRC
CHNR
rh
rh
rh
rh
Type
RESULT
Type
rh
RESULT
VF
DRC
CHNR
rh
rh
rh
rh
Type
RESULT
Type
rh
RMAP = 0, PAGE 4
CAH
ADC_RCR0
Reset: 00H
Result Control Register 0
Bit Field
CBH
ADC_RCR1
Reset: 00H
Result Control Register 1
Bit Field
CCH
ADC_RCR2
Reset: 00H
Result Control Register 2
Bit Field
CDH
ADC_RCR3
Reset: 00H
Result Control Register 3
Bit Field
CEH
ADC_VFCR
Reset: 00H
Valid Flag Clear Register
Bit Field
0
Type
r
CFH
ADC_ALR0
Alias Register 0
Reset: 00H
Bit Field
D2H
ADC_CNF
Reset: 00H
Configure Out of Range
Comparator Register
Bit Field
Type
Type
Type
Type
D3H
ADC_ETRCR
Reset: 00H
External Trigger Control
Register
VFCT
R
WFR
IEN
0
DLPF
0
DRCT
R
rw
rw
r
rw
r
rw
r
rw
VFCT
R
WFR
0
IEN
0
DLPF
0
DRCT
R
rw
rw
r
rw
r
rw
r
rw
VFCT
R
WFR
0
IEN
0
DLPF
0
DRCT
R
rw
rw
r
rw
r
rw
r
rw
VFCT
R
WFR
0
IEN
0
DLPF
0
DRCT
R
rw
rw
r
rw
r
rw
r
rw
VFC3
VFC2
VFC1
VFC0
w
w
w
w
0
Type
Type
0
ALIAS0
r
rw
CNF7
CNF6
CNF5
CNF4
CNF3
CNF2
CNF1
CNF0
rw
rw
rw
rw
rw
rw
rw
rw
Bit Field
0
ETRSEL1
ETRSEL0
Type
r
rw
rw
RMAP = 0, PAGE 5
User’s Manual
Memory Organization, V 1.0
3-22
V1.1, 2010-09
XC83x
Memory Organization
Table 3-6
ADC Register Overview (cont’d)
Addr Register Name
Bit
CAH
ADC_CHINFR
Reset: 00H
Channel Interrupt Flag Register
Bit Field
CBH
ADC_CHINCR
Reset: 00H
Channel Interrupt Clear Register
Bit Field
CCH
ADC_CHINSR
Reset: 00H
Channel Interrupt Set Register
Bit Field
CEH
ADC_EVINFR
Reset: 00H
Event Interrupt Flag Register
CFH
ADC_EVINCR
Reset: 00H
Event Interrupt Clear Flag
Register
Bit Field
D2H
ADC_EVINSR
Reset: 00H
Event Interrupt Set Flag Register
Bit Field
Type
Type
Type
Bit Field
Type
Type
Type
7
6
5
4
3
2
1
0
CHINF
7
CHINF
6
CHINF
5
CHINF
4
CHINF
3
CHINF
2
CHINF
1
CHINF
0
rh
rh
rh
rh
rh
rh
rh
rh
CHINC
7
CHINC
6
CHINC
5
CHINC
4
CHINC
3
CHINC
2
CHINC
1
CHINC
0
w
w
w
w
w
w
w
w
CHINS
7
CHINS
6
CHINS
5
CHINS
4
CHINS
3
CHINS
2
CHINS
1
CHINS
0
w
w
w
w
w
EVINF
7
EVINF
6
EVINF
5
EVINF
4
w
0
w
w
EVINF
1
EVINF
0
rh
rh
rh
rh
r
rh
rh
EVINC
7
EVINC
6
EVINC
5
EVINC
4
0
EVINC
1
EVINC
0
w
w
w
w
r
w
w
EVINS
7
EVINS
6
EVINS
5
EVINS
4
0
EVINS
1
EVINS
0
w
w
w
w
r
w
w
RMAP = 0, PAGE 6
CAH
ADC_CRCR1
Reset: 00H
Conversion Request Control
Register 1
Bit Field
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
Type
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
ADC_CRPR1
Reset: 00H
Conversion Request Pending
Register 1
Bit Field
CHP7
CHP6
CHP5
CHP4
CHP3
CHP2
CHP1
CHP0
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
CCH
ADC_CRMR1
Reset: 00H
Conversion Request Mode
Register 1
Bit Field
0
LDEV
CLRP
ND
SCAN
ENSI
ENTR
0
ENGT
CDH
ADC_QMR0
Reset: 00H
Queue Mode Register 0
Bit Field
CEH
ADC_QSR0
Reset: 20H
Queue Status Register 0
Bit Field
CFH
ADC_Q0R0
Reset: 00H
Queue 0 Register 0
Bit Field
D2H
ADC_QBUR0
Reset: 00H
Queue Backup Register 0
Bit Field
D2H
ADC_QINR0
Reset: 00H
Queue Input Register 0
Bit Field
CBH
Type
Type
Type
r
w
w
rw
rw
rw
r
rw
CEV
TREV
FLUS
H
CLRV
0
ENTR
0
ENGT
r
rw
r
w
Type
User’s Manual
Memory Organization, V 1.0
Type
Type
Type
w
0
r
EXTR
ENSI
w
w
EMPT
Y
EV
rh
rh
RF
V
0
r
0
rw
FILL
rh
REQCHNR
rh
rh
rh
rh
r
rh
EXTR
ENSI
RF
V
0
REQCHNR
rh
rh
rh
rh
EXTR
ENSI
RF
0
REQCHNR
w
w
w
r
w
3-23
r
rh
V1.1, 2010-09
XC83x
Memory Organization
3.4.5.7
LEDTSCU Registers
The LEDTSCU SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-7
LEDTSCU Register Overview
Addr Register Name
Bit
7
6
LD_EN
TS_EN
rw
rw
5
4
3
2
1
0
RMAP = 0
LTS_GLOBCTL0 Reset: 00H
Global Control Register 0
Bit Field
D4H
LTS_COMPARE Reset: 00H
Time Slice Compare Shadow
Register
Bit Field
D5H
LTS_LDLINE
Reset: 00H
LED Line Pattern Shadow
Register
Bit Field
D6H
LTS_LDTSCTL Reset: 00H
LED and Touch-sense Control
Register
Bit Field
D7H
LTS_TSCTL
Reset: 00H
Touch-sense Control Register
D8H
LTS_GLOBCTL1 Reset: 00H
Global Control Register 1
D9H
LTS_TSVAL
Reset: 00H
Touch-sense Counter Value
Register
97H
Type
rw
SHD_CMP
Type
rw
SHD_LINE
Type
rw
NR_LEDCOL
Type
Bit Field
Type
User’s Manual
Memory Organization, V 1.0
CLK_PS
COL
LEV
rw
TS
CTR
OVL
TS
CTRR
NR_PADT
rw
TS
CTR
SAT
E
PULL
TSO
EXT
rw
PADT
SW
rw
PADT
rw
rw
rw
rw
rw
rwh
Bit Field
TSF
ITS
_EN
TFF
ITF
_EN
CLK
SEL
FNCOL
Type
rwh
rw
rwh
rw
rw
rh
Bit Field
TSCTRVAL
Type
rwh
3-24
V1.1, 2010-09
XC83x
Memory Organization
3.4.5.8
RTC Registers
The RTC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-8
RTC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
SFRT
C
CRFT
C
ESRT
C
ECRT
C
RTCC
T
RTM
rwh
rwh
rw
rw
rwh
rw
0
RMAP = 0
95H
RTC_RTCON
Reset: 00H
Real-Time Clock Control
Register
Bit Field
96H
RTC_RTCON1
Reset: 02H
Real-Time Clock Control
Register 1
Bit Field
0
RTYR
Type
r
rw
RTC_CNT0
Reset: 00H
Clock Count Register 0
Mode 0
Bit Field
0
Type
r
RTC_CNT0
Reset: 00H
Clock Count Register 0
Modes 1 and 3
Bit Field
RTC_CNT1
Reset: 00H
Clock Count Register 1
Modes 0 and 2
Bit Field
0
SECONDS
Type
r
rwh
RTC_CNT1
Reset: 00H
Clock Count Register 1
Modes 1 and 3
Bit Field
RTC_CNT2
Reset: 00H
Clock Count Register 2
Modes 0 and 2
Bit Field
0
MINUTES
Type
r
rwh
RTC_CNT2
Reset: 00H
Clock Count Register 2
Modes 1 and 3
Bit Field
RTC_CNT3
Reset: 00H
Clock Count Register 3
Modes 0 and 2
Bit Field
0
Type
r
RTC_CNT3
Reset: 00H
Clock Count Register 3
Modes 1 and 3
Bit Field
RTC_CNT4
Reset: 00H
Clock Count Register 4
Modes 0 and 2
Bit Field
RTC_CNT5
Reset: 00H
Clock Count Register 5
Modes 0 and 2
Bit Field
0
DAYS
Type
r
rw
RTC_RTCCR0
Reset: 00H
Real-Time Clock
Compare/Capture Register 0
Mode 0
Bit Field
0
CC_MSECS
Type
r
rwh
RTC_RTCCR0
Reset: 00H
Real-Time Clock
Compare/Capture Register 0
Modes 1 and 3
Bit Field
E1H
E1H
E2H
E2H
E3H
E3H
E4H
E4H
E5H
E6H
E7H
E7H
User’s Manual
Memory Organization, V 1.0
Type
RTCC
rw
MILLISECONDS
rwh
CNT_VAL
Type
rwh
CNT_VAL
Type
rwh
CNT_VAL
Type
rwh
HOURS
rwh
CNT_VAL
Type
rwh
DAYS
Type
rwh
CC_VAL
Type
rwh
3-25
V1.1, 2010-09
XC83x
Memory Organization
Table 3-8
RTC Register Overview (cont’d)
Addr Register Name
Bit
E9H
RTC_RTCCR1
Reset: 00H
Real-Time Clock
Compare/Capture Register 1
Modes 0 and 2
Bit Field
0
CC_SECONDS
Type
r
rwh
RTC_RTCCR1
Reset: 00H
Real-Time Clock
Compare/Capture Register 1
Modes 1 and 3
Bit Field
RTC_RTCCR2
Reset: 00H
Real-Time Clock
Compare/Capture Register 2
Modes 0 and 2
Bit Field
0
CC_MINUTES
Type
r
rwh
RTC_RTCCR2
Reset: 00H
Real-Time Clock
Compare/Capture Register 2
Modes 1 and 3
Bit Field
RTC_RTCCR3
Reset: 00H
Real-Time Clock
Compare/Capture Register 3
Modes 0 and 2
Bit Field
0
CC_HOURS
Type
r
rwh
RTC_RTCCR3
Reset: 00H
Real-Time Clock
Compare/Capture Register 3
Modes 1 and 3
Bit Field
RTC_RTCCR4
Reset: 00H
Real-Time Clock
Compare/Capture Register 4
Modes 0 and 2
Bit Field
RTC_RTCCR5
Reset: 00H
Real-Time Clock
Compare/Capture Register 5
Modes 0 and 2
Bit Field
0
CC_D
AYS
Type
r
rw
E9H
EAH
EAH
EBH
EBH
ECH
EDH
User’s Manual
Memory Organization, V 1.0
7
6
5
4
3
2
1
0
CC_VAL
Type
rwh
CC_VAL
Type
rwh
CC_VAL
Type
rwh
CC_DAYS
Type
rwh
3-26
V1.1, 2010-09
XC83x
Memory Organization
3.4.5.9
Timer 2 Registers
The Timer 2 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-9
T2 Register Overview
Addr Register Name
Bit
7
6
5
TF2
EXF2
4
3
2
1
0
EXEN
2
TR2
C_T2
CP_RL
2
rwh
rw
RMAP = 0
C0H
T2_T2CON
Reset: 00H
Timer 2 Control Register
Bit Field
C1H
T2_T2MOD
Reset: 00H
Timer 2 Mode Register
Bit Field
C2H
T2_RC2L
Reset: 00H
Timer 2 Reload/Capture
Register Low
Bit Field
Type
rwh
C3H
T2_RC2H
Reset: 00H
Timer 2 Reload/Capture
Register High
Bit Field
RC2
Type
rwh
T2_T2L
Reset: 00H
Timer 2 Register Low
Bit Field
C5H
T2_T2H
Reset: 00H
Timer 2 Register High
Bit Field
C6H
T2_T2CON1
Reset: 03H
Timer 2 Control Register 1
Bit Field
Type
Type
rwh
rwh
T2RE
GS
T2RH
EN
EDGE
SEL
PREN
rw
rw
rw
rw
Type
C4H
0
r
rw
T2PRE
rw
rw
rw
DCEN
rw
rw
0
TF2EN
EXF2E
N
r
rw
rw
RC2
THL2
Type
rwh
THL2
Type
rwh
3.4.5.10 CCU6 Registers
The CCU6 SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-10
CCU6 Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
RMAP = 0
A3H
CCU6_PAGE
Page Register
Reset: 00H
Bit Field
Type
OP
STNR
0
PAGE
w
w
r
rw
RMAP = 0, PAGE 0
9AH
9BH
9CH
CCU6_CC63SRL
Reset: 00H
Capture/Compare Shadow Register
for Channel CC63 Low
Bit Field
CCU6_CC63SRH
Reset: 00H
Capture/Compare Shadow Register
for Channel CC63 High
Bit Field
CCU6_TCTR4L
Reset: 00H
Timer Control Register 4 Low
Bit Field
rw
CC63SH
Type
Type
User’s Manual
Memory Organization, V 1.0
CC63SL
Type
rw
T12
STD
T12
STR
0
DT
RES
T12
RES
T12R
S
T12R
R
w
w
r
w
w
w
w
3-27
V1.1, 2010-09
XC83x
Memory Organization
Table 3-10
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
9DH
CCU6_TCTR4H
Reset: 00H
Timer Control Register 4 High
Bit Field
9EH
CCU6_MCMOUTSL
Reset: 00H
Multi-Channel Mode Output Shadow
Register Low
Bit Field
9FH
CCU6_MCMOUTSH
Reset: 00H
Multi-Channel Mode Output Shadow
Register High
Bit Field
A4H
CCU6_ISRL
Reset: 00H
Capture/Compare Interrupt Status
Reset Register Low
Bit Field
A5H
CCU6_ISRH
Reset: 00H
Capture/Compare Interrupt Status
Reset Register High
Bit Field
Type
A6H
CCU6_CMPMODIFL
Reset: 00H
Compare State Modification Register
Low
Bit Field
Type
r
w
r
w
w
w
A7H
CCU6_CMPMODIFH Reset: 00H
Compare State Modification Register
High
Bit Field
0
MCC6
3R
0
MCC6
2R
MCC6
1R
MCC6
0R
Type
r
w
r
w
w
w
FAH
CCU6_CC60SRL
Reset: 00H
Capture/Compare Shadow Register
for Channel CC60 Low
Bit Field
FBH
CCU6_CC60SRH
Reset: 00H
Capture/Compare Shadow Register
for Channel CC60 High
Bit Field
CCU6_CC61SRL
Reset: 00H
Capture/Compare Shadow Register
for Channel CC61 Low
Bit Field
CCU6_CC61SRH
Reset: 00H
Capture/Compare Shadow Register
for Channel CC61 High
Bit Field
CCU6_CC62SRL
Reset: 00H
Capture/Compare Shadow Register
for Channel CC62 Low
Bit Field
CCU6_CC62SRH
Reset: 00H
Capture/Compare Shadow Register
for Channel CC62 High
Bit Field
Type
FCH
FDH
FEH
FFH
Type
Type
Type
7
6
T13
STD
T13
STR
0
w
w
r
STRM
CM
0
w
r
STRH
P
0
w
r
RT12
PM
RT12
OM
5
4
3
2
1
0
T13
RES
T13R
S
T13R
R
w
w
w
MCMPS
rw
CURHS
EXPHS
rw
RCC6
2F
rw
RCC6
2R
RCC6
1F
RCC6
1R
RCC6
0F
RCC6
0R
w
w
w
w
w
w
w
w
RSTR
RIDLE
RWH
E
RCHE
0
RTRP
F
RT13
PM
RT13
CM
w
w
w
w
r
0
MCC6
3S
0
w
w
w
MCC6
2S
MCC6
1S
MCC6
0S
CC60SL
Type
rwh
CC60SH
Type
rwh
CC61SL
Type
rwh
CC61SH
Type
rwh
CC62SL
Type
rwh
CC62SH
Type
rwh
RMAP = 0, PAGE 1
9AH
9BH
9CH
CCU6_CC63RL
Reset: 00H
Capture/Compare Register for
Channel CC63 Low
Bit Field
CCU6_CC63RH
Reset: 00H
Capture/Compare Register for
Channel CC63 High
Bit Field
CCU6_T12PRL
Reset: 00H
Timer T12 Period Register Low
Bit Field
User’s Manual
Memory Organization, V 1.0
CC63VL
Type
rh
CC63VH
Type
rh
T12PVL
Type
rwh
3-28
V1.1, 2010-09
XC83x
Memory Organization
Table 3-10
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
9DH
CCU6_T12PRH
Reset: 00H
Timer T12 Period Register High
Bit Field
9EH
CCU6_T13PRL
Reset: 00H
Timer T13 Period Register Low
Bit Field
9FH
CCU6_T13PRH
Reset: 00H
Timer T13 Period Register High
Bit Field
Type
rwh
A4H
CCU6_T12DTCL
Reset: 00H
Dead-Time Control Register for
Timer T12 Low
Bit Field
DTM
A5H
7
6
5
4
3
2
1
0
T12PVH
Type
rwh
T13PVL
Type
rwh
T13PVH
Type
rw
CCU6_T12DTCH
Reset: 00H
Dead-Time Control Register for
Timer T12 High
Bit Field
0
DTR2
DTR1
DTR0
0
DTE2
DTE1
DTE0
Type
r
rh
rh
rh
r
rw
rw
rw
A6H
CCU6_TCTR0L
Reset: 00H
Timer Control Register 0 Low
Bit Field
CTM
CDIR
STE1
2
T12R
T12
PRE
A7H
CCU6_TCTR0H
Reset: 00H
Timer Control Register 0 High
FAH
CCU6_CC60RL
Reset: 00H
Capture/Compare Register for
Channel CC60 Low
Bit Field
CCU6_CC60RH
Reset: 00H
Capture/Compare Register for
Channel CC60 High
Bit Field
FCH
CCU6_CC61RL
Reset: 00H
Capture/Compare Register for
Channel CC61 Low
Bit Field
FDH
CCU6_CC61RH
Reset: 00H
Capture/Compare Register for
Channel CC61 High
Bit Field
CCU6_CC62RL
Reset: 00H
Capture/Compare Register for
Channel CC62 Low
Bit Field
CCU6_CC62RH
Reset: 00H
Capture/Compare Register for
Channel CC62 High
Bit Field
Type
FBH
FEH
FFH
rw
rh
T12CLK
rh
rh
rw
rw
Bit Field
0
STE1
3
T13R
T13
PRE
T13CLK
Type
r
rh
rh
rw
rw
CC60VL
Type
rh
CC60VH
Type
rh
CC61VL
Type
rh
CC61VH
Type
rh
CC62VL
Type
rh
CC62VH
Type
rh
RMAP = 0, PAGE 2
9AH
9BH
9CH
CCU6_T12MSELL
Reset: 00H
T12 Capture/Compare Mode Select
Register Low
Bit Field
CCU6_T12MSELH
Reset: 00H
T12 Capture/Compare Mode Select
Register High
Bit Field
CCU6_IENL
Reset: 00H
Capture/Compare Interrupt Enable
Register Low
Bit Field
Type
Type
User’s Manual
Memory Organization, V 1.0
MSEL61
MSEL60
rw
rw
Type
DBYP
HSYNC
rw
rw
MSEL62
rw
ENT1
2
PM
ENT1
2
OM
ENCC
62F
ENCC
62R
ENCC
61F
ENCC
61R
ENCC
60F
ENCC
60R
rw
rw
rw
rw
rw
rw
rw
rw
3-29
V1.1, 2010-09
XC83x
Memory Organization
Table 3-10
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
9DH
CCU6_IENH
Reset: 00H
Capture/Compare Interrupt Enable
Register High
Bit Field
9EH
CCU6_INPL
Reset: 40H
Capture/Compare Interrupt Node
Pointer Register Low
Bit Field
Type
rw
rw
rw
rw
9FH
CCU6_INPH
Reset: 39H
Capture/Compare Interrupt Node
Pointer Register High
Bit Field
0
INPT13
INPT12
INPERR
Type
r
rw
rw
rw
A4H
CCU6_ISSL
Reset: 00H
Capture/Compare Interrupt Status
Set Register Low
Bit Field
A5H
CCU6_ISSH
Reset: 00H
Capture/Compare Interrupt Status
Set Register High
Bit Field
A6H
CCU6_PSLR
Reset: 00H
Passive State Level Register
Bit Field
A7H
CCU6_MCMCTR
Reset: 00H
Multi-Channel Mode Control Register
Bit Field
0
SWSYN
0
Type
r
rw
r
rw
FAH
CCU6_TCTR2L
Reset: 00H
Timer Control Register 2 Low
Bit Field
0
T13TED
T13TEC
T13
SSC
T12
SSC
Type
r
rw
rw
rw
rw
FBH
CCU6_TCTR2H
Reset: 00H
Timer Control Register 2 High
Bit Field
FCH
CCU6_MODCTRL
Reset: 00H
Modulation Control Register Low
Bit Field
FDH
CCU6_MODCTRH
Reset: 00H
Modulation Control Register High
Bit Field
FEH
CCU6_TRPCTRL
Reset: 00H
Trap Control Register Low
Bit Field
FFH
CCU6_TRPCTRH
Reset: 00H
Trap Control Register High
Bit Field
Type
Type
Type
Type
7
6
5
4
3
2
1
0
EN
STR
EN
IDLE
EN
WHE
EN
CHE
0
EN
TRPF
ENT1
3PM
ENT1
3CM
rw
rw
rw
rw
r
rw
rw
rw
INPCHE
ST12
PM
INPCC62
ST12
OM
Type
SCC6
2R
SCC6
1F
SCC6
1R
INPCC60
SCC6
0F
SCC6
0R
w
w
w
w
w
w
w
w
SSTR
SIDLE
SWHE
SCHE
SWH
C
STRP
F
ST13
PM
ST13
CM
w
w
w
w
w
w
w
w
PSL63
0
rwh
PSL
r
rwh
0
Type
Type
SCC6
2F
INPCC61
r
MCM
EN
0
SWSEL
T13RSEL
T12RSEL
rw
rw
T12MODEN
rw
r
rw
ECT1
3O
0
T13MODEN
rw
r
rw
0
Type
r
TRPM
2
TRPM
1
TRPM
0
rw
rw
rw
TRPP
EN
TRPE
N13
TRPEN
Type
rw
rw
rw
Bit Field
0
R
MCMP
Type
r
rh
rh
RMAP = 0, PAGE 3
9AH
9BH
CCU6_MCMOUTL
Reset: 00H
Multi-Channel Mode Output Register
Low
CCU6_MCMOUTH
Reset: 00H
Multi-Channel Mode Output Register
High
User’s Manual
Memory Organization, V 1.0
Bit Field
0
CURH
EXPH
Type
r
rh
rh
3-30
V1.1, 2010-09
XC83x
Memory Organization
Table 3-10
CCU6 Register Overview (cont’d)
Addr Register Name
Bit
9CH
CCU6_ISL
Reset: 00H
Capture/Compare Interrupt Status
Register Low
Bit Field
9DH
CCU6_ISH
Reset: 00H
Capture/Compare Interrupt Status
Register High
Bit Field
9EH
CCU6_PISEL0L
Reset: 00H
Port Input Select Register 0 Low
Bit Field
9FH
CCU6_PISEL0H
Reset: 00H
Port Input Select Register 0 High
Bit Field
A4H
CCU6_PISEL2
Reset: 00H
Port Input Select Register 2
Bit Field
0
Type
r
FAH
CCU6_T12L
Reset: 00H
Timer T12 Counter Register Low
Bit Field
FBH
CCU6_T12H
Reset: 00H
Timer T12 Counter Register High
Bit Field
FCH
CCU6_T13L
Reset: 00H
Timer T13 Counter Register Low
Bit Field
FDH
CCU6_T13H
Reset: 00H
Timer T13 Counter Register High
Bit Field
FEH
CCU6_CMPSTATL
Reset: 00H
Compare State Register Low
Bit Field
FFH
CCU6_CMPSTATH
Reset: 00H
Compare State Register High
Bit Field
Type
Type
6
5
4
3
2
1
0
T12
OM
ICC62
F
ICC62
R
ICC61
F
ICC61
R
ICC60
F
ICC60
R
rh
rh
rh
rh
rh
rh
rh
rh
STR
IDLE
WHE
CHE
TRPS
TRPF
T13
PM
T13
CM
rh
rh
rh
rh
rh
rh
rh
rh
ISTRP
Type
ISCC62
ISCC61
rw
rw
rw
rw
ISPOS2
ISPOS1
ISPOS0
rw
rw
rw
rw
IST13HR
rw
T12CVL
Type
rwh
T12CVH
Type
rwh
T13CVL
Type
rwh
T13CVH
Type
Type
ISCC60
IST12HR
Type
Type
User’s Manual
Memory Organization, V 1.0
7
T12
PM
rwh
0
CC63
ST
CC
POS2
CC
POS1
CC
POS0
CC62
ST
CC61
ST
CC60
ST
r
rh
rh
rh
rh
rh
rh
rh
T13IM
COUT
63PS
COUT
62PS
CC62
PS
COUT
61PS
CC61
PS
COUT
60PS
CC60
PS
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
3-31
V1.1, 2010-09
XC83x
Memory Organization
3.4.5.11 SSC Registers
The SSC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-11
SSC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
SSC_CONL
Reset: 00H
Control Register Low
Programming Mode
Bit Field
LB
PO
PH
HB
Type
rw
rw
rw
rw
SSC_CONL
Reset: 00H
Control Register Low
Operating Mode
Bit Field
0
BC
Type
r
rh
SSC_CONH
Reset: 00H
Control Register High
Programming Mode
Bit Field
EN
MS
0
AREN
BEN
Type
rw
rw
r
rw
rw
PEN
REN
TEN
rw
rw
ABH
SSC_CONH
Reset: 00H
Control Register High
Operating Mode
Bit Field
EN
MS
0
BSY
rw
BE
PE
RE
TE
Type
rw
rw
r
rh
ACH
SSC_TBL
Reset: 00H
Transmitter Buffer Register Low
Bit Field
rwh
rwh
rwh
rwh
ADH
SSC_RBL
Reset: 00H
Receiver Buffer Register Low
Bit Field
AEH
SSC_BRL
Reset: 00H
Baud Rate Timer Reload
Register Low
Bit Field
AFH
SSC_BRH
Reset: 00H
Baud Rate Timer Reload
Register High
Bit Field
1
0
RMAP = 0
AAH
AAH
ABH
BM
rw
TB_VALUE
Type
rw
RB_VALUE
Type
rh
BR_VALUE
Type
rw
BR_VALUE
Type
rw
3.4.5.12 IIC Registers
The IIC SFRs can be accessed in the standard memory area (RMAP = 0).
Table 3-12
IIC Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
RMAP = 0
DAH
IIC_ADDR
Reset: 00H
Slave Address Register
Bit Field
DBH
IIC_DATA
Reset: 00H
Data Byte Register
Bit Field
DCH
IIC_CNTR
Control Register
Reset: 00H
Bit Field
IIC_STAT
Status Register
Reset: F8H
DDH
Type
GCE
rw
rw
DATA
Type
Type
User’s Manual
Memory Organization, V 1.0
SLA
rw
IEN
ENAB
STA
STP
IFLG
AAK
rw
rw
rwh
rwh
rwh
rw
Bit Field
Type
3-32
0
r
STAT
0
rh
r
V1.1, 2010-09
XC83x
Memory Organization
Table 3-12
IIC Register Overview (cont’d)
Addr Register Name
Bit
7
DDH
IIC_BRCR
Reset: 00H
Baud Rate Control Register
Bit Field
0
6
5
BRP
4
Type
w
w
DEH
IIC_ADDRX
Reset: 00H
Extended Slave Address
Register
Bit Field
DFH
IIC_SRST
Reset: UUH
Software Reset Register
Bit Field
3
2
1
0
PREDIV
w
SLAX
Type
rw
SRST
Type
w
3.4.5.13 OCDS Registers
The OCDS SFRs can be accessed in the mapped memory area (RMAP = 1).
Table 3-13
OCDS Register Overview
Addr Register Name
Bit
7
6
5
4
3
2
1
0
STMO
DE
0
DSUS
P
MBCO
N
ALTDI
MMEP
MMOD
E
JENA
RMAP = 1
E9H
MMCR2
Reset: 1UH
Monitor Mode Control 2
Register
Bit Field
F1H
MMCR
Reset: 00H
Monitor Mode Control Register
Bit Field
F2H
MMSR
Reset: 00H
Monitor Mode Status Register
Bit Field
F3H
MMBPCR
Reset: 00H
Breakpoints Control Register
Bit Field
F4H
MMICR
Reset: 00H
Monitor Mode Interrupt Control
Register
Bit Field
F5H
MMDR
Reset: 00H
Monitor Mode Data Transfer
Register
Receive
Bit Field
MMDR
Reset: 00H
Monitor Mode Data Transfer
Register
Transmit
Bit Field
F6H
HWBPSR
Reset: 00H
Hardware Breakpoints Select
Register
Bit Field
0
BPSEL
_P
BPSEL
Type
r
w
rw
F7H
HWBPDR
Reset: 00H
Hardware Breakpoints Data
Register
Bit Field
Type
Type
rw
rw
rw
rwh
rw
rwh
rh
rh
MEXIT
_P
MEXIT
MMNM
IE
MSTE
P
MRAM
S_P
MRAM
S
TRF
RRF
w
Type
Type
F5H
User’s Manual
Memory Organization, V 1.0
Type
rwh
0
rw
SWBC
rw
rw
w
rwh
rh
rh
EXBF
SWBF
HWB3
F
HWB2
F
HWB1
F
HWB0
F
rwh
rwh
rwh
rwh
rwh
rwh
HWB3C
rw
HWB2C
rw
rw
HWB1
C
HWB0C
rw
rw
DVEC
T
DRET
R
COMR
ST
MSTS
EL
FMIR
W
FNMIR
R
NMIR
WE
NMIR
RE
rwh
rwh
rwh
rh
rwh
rwh
rw
rw
MMRR
Type
rh
MMTR
Type
w
HWBPxx
Type
rw
3-33
V1.1, 2010-09
XC83x
Memory Organization
Table 3-13
OCDS Register Overview (cont’d)
Addr Register Name
Bit
EBH
MMWR1
Reset: 00H
Monitor Work Register 1
Bit Field
ECH
MMWR2
Reset: 00H
Monitor Work Register 2
Bit Field
User’s Manual
Memory Organization, V 1.0
7
6
5
4
3
2
1
0
MMWR1
Type
rw
MMWR2
Type
rw
3-34
V1.1, 2010-09
XC83x
Flash Memory
4
Flash Memory
The XC83x has an embedded user-programmable non-volatile Flash memory that
allows for fast and reliable storage of user code and data. It is operated with a single
2.5 V supply from the Embedded Voltage Regulator (EVR) and does not require
additional programming or erasing voltage. The sectorization of the Flash memory
allows each sector to be erased independently.
Features
•
•
•
•
•
•
•
•
•
•
In-System Programming (ISP) via UART
In-Application Programming (IAP)
Error Correction Code (ECC) for dynamic correction of single-bit errors
Background program and erase operations for CPU load minimization
Support for aborting erase operation
32-byte minimum program width
1-sector minimum erase width
1-byte read access
1 or 3 × CCLK period read access time (depending on zero or one wait state)1)
Flash is delivered in erased state (read all zeros)
1) There is one wait state inserted when CPU clock is running at 24 MHz. No wait state will be inserted when
CPU is running at 8 MHz
User’s Manual
Flash Memory, V 1.0
4-1
V1.1, 2010-09
XC83x
Flash Memory
4.1
Flash Memory Address Mapping
XC83x comes in two Flash size variants, 4-Kbyte or 8-Kbyte. The program memory map
for the two Flash sizes is shown in Figure 4-1.
FF80H
User BSL
Flash Sector
64 Bytes
FF40H
B000H
Flash Bank 0
4 Kbytes
Flash Bank 1
4 Kbytes
A000H
2000H
Flash Bank 1
4 Kbytes
1000H
Flash Bank 0
4 Kbytes
Flash Bank 0
4 Kbytes
4 Kbytes
8 Kbytes
0000H
Figure 4-1
Flash Memory Map
For the 8-Kbyte Flash variant, two 4-Kbyte Flash banks, Bank 0 and Bank 1, are
available. Bank 0 is mapped to program memory address space 0000H - 0FFFH while
Bank 1 is mapped to two program memory address spaces 1000H - 1FFFH and A000H AFFFH. This means that two different program memory accesses, for example one to
address 1000H and the other to address A000H, will point to the same physical location.
Note: In the 8-Kbyte Flash variant, a separate 64-byte User BSL Flash sector, consisting
of two wordlines, is included to support the Alternate User BSL mode entry during
boot-up. If this feature is not used, the sector can be used also for code or data
storage.
For the 4-Kbyte Flash variant, only a single 4-Kbyte Flash bank, Bank 0, is available. The
Flash bank is mapped to two program memory address spaces 0000H - 0FFFH and
A000H - AFFFH.
User’s Manual
Flash Memory, V 1.0
4-2
V1.1, 2010-09
XC83x
Flash Memory
The double-mapping of the Flash banks (Bank 1 in the 8-Kbyte Flash variant and Bank
0 in the 4-Kbyte Flash variant) is intended to facilitate software coding. As a general
guideline, the lower address spaces (0000H - 0FFFH and 1000H - 1FFFH) should be used
for Flash contents that are intended to be used as program code. Whereas the higher
address space (A000H – AFFFH) should be used for Flash contents that are intended to
be used as data.
4.2
Flash Bank Sectorization
The XC83x Flash devices consist of one or two 4-Kbyte Flash banks with the
sectorization shown in Figure 4-2. Each Flash bank can be used for code and data
storage.
Sector 9: 128-byte
Sector 8: 128-byte
Sector 7: 128-byte
Sector 6: 128-byte
Sector 5: 256-byte
Sector 4: 256-byte
Sector 3: 512-byte
Sector 2: 512-byte
Sector 1: 1-Kbyte
Sector 0: 1-Kbyte
1x Flash Bank
Figure 4-2
Flash Bank Sectorization
Sector Partitioning in each 4-Kbyte Flash bank:
•
•
•
•
Two 1-Kbyte sectors
Two 512-byte sectors
Two 256-byte sectors
Four 128-byte sectors
The internal structure of each Flash bank represents a sector architecture for flexible
erase capability. The minimum erase width is always a complete sector, and sectors can
User’s Manual
Flash Memory, V 1.0
4-3
V1.1, 2010-09
XC83x
Flash Memory
be erased separately or in parallel. Contrary to standard EEPROMs, erased Flash
memory cells contain 0s.
The Flash bank is divided into more physical sectors for extended erasing and
reprogramming capability; even numbers for each sector size are provided to allow
greater flexibility and the ability to adapt to a wide range of application requirements.
For example, the user’s program can implement a buffer mechanism for each sector.
Double copies of each data set can be stored in separate sectors of similar size to ensure
that a backup copy of the data set is available in the event the actual data set is corrupted
or erased.
Alternatively, the user can implement an algorithm for EEPROM emulation, which uses
the Flash bank like a circular stack memory; the latest data updates are always
programmed on top of the actual region. When the top of the sector is reached, all actual
data (representing the EEPROM data) is copied to the bottom area of the next sector
and the last sector is then erased. This round robin procedure, using multifold
replications of the emulated EEPROM size, significantly increases the Flash endurance.
To speed up data search, the RAM can be used to contain the pointer to the valid data
set.
User’s Manual
Flash Memory, V 1.0
4-4
V1.1, 2010-09
XC83x
Flash Memory
4.3
Wordline Address
The wordline (WL) addresses of Flash Bank 0 and Bank 1 in the 8-Kbyte Flash variant
are given in Figure 4-3 and Figure 4-4, while those of Flash Bank 0 in the 4-Kbyte Flash
variant are given in Figure 4-5.
……
0F01H
0F00H
0EE2H
0EE1H 0EE0H
……
……
……
0E9FH
……………………………..
0E82H
0E81H
0E80H
0E7FH
……………………………..
0E62H
0E61H
0E60H
……
0E00H
0DE1H 0DE0H
0D1FH
……………………………..
0D02H
0D01H 0D00H
0CFFH
……………………………..
0CE2H
0CE1H 0CE0H
0C1FH
……………………………..
0C02H
0C01H 0C00H
0BFFH
……………………………..
0BE2H
0BE1H 0BE0H
…...
…...
…...
0A3FH
……………………………..
0A22H
0A21H
0A20H
0A1FH
……………………………..
0A02H
0A01H
0A00H
09FFH
……………………………..
09E2H
09E1H
09E0H
…...
…...
…...
083FH
……………………………..
0822H
0821H
0820H
081FH
……………………………..
0802H
0801H
0800H
07FFH
……………………………..
07E2H
07E1H
07E0H
…...
…...
…...
045FH
……………………………..
0442H
0441H
0440H
043FH
……………………………..
0422H
0421H
0420H
041FH
……………………………..
0402H
0401H
0400H
03FFH
……………………………..
03E2H
03E1H
03E0H
…...
…...
…...
005FH
……………………………..
0042H
0041H
0040H
003FH
……………………………..
0022H
0021H
0020H
001FH
……………………………..
0002H
0001H
0000H
……..
……..
……..
……..
Flash Bank 0
……..
……..
……..
……
0E01H
0DE2H
……..
……
0E02H
……………………………..
……
……………………………..
0DFFH
……
0E1FH
Se ctor 8
WL 120 - 123
1 28-byte
……
0F02H
……………………………..
……
……………………………..
……
0F1FH
0EFFH
Se ctor 7
WL 116 - 119
1 28-byte
0F60H
Se ctor 6
WL 112 - 115
1 28-byte
0F80H
0F61H
Se ctor 5
WL 104 - 111
2 56-byte
0F81H
0F62H
Se ctor 4
WL 96 - 1 03
2 56-byte
0F82H
……………………………..
…...
Se ctor 3
WL 80 - 95
5 12-byte
……………………………..
0F7FH
…...
Se ctor 2
WL 64 - 79
5 12-byte
……
0FE1H 0FE0H
…...
Se ctor 1
WL 32 - 63
1-KB yte
……
0F9FH
……
0FE2H
Se ctor 9
WL 124 - 127
1 28-byte
Byte 2 Byte 1 Byte 0
……………………………..
……
0FFFH
…...
Se ctor 0
WL 0 - 3 1
1-KB yte
Byte 31
WL
Address
Figure 4-3
8-Kbyte Flash Variant Bank 0 Wordline Addresses
User’s Manual
Flash Memory, V 1.0
4-5
V1.1, 2010-09
XC83x
Flash Memory
19E0H
…...
…...
…...
183FH
……………………………..
1822H
1821H
1820H
181FH
……………………………..
1802H
1801H
1800H
17FFH
……………………………..
17E2H
17E1H
17E0H
…...
…...
…...
145FH
……………………………..
1442H
1441H
1440H
143FH
……………………………..
1422H
1421H
1420H
141FH
……………………………..
1402H
1401H
13FFH
……………………………..
13E2H
13E1H
…...
…...
…...
105FH
……………………………..
1042H
1041H
1040H
103FH
……………………………..
1022H
1021H
1020H
101FH
……………………………..
1002H
1001H
1000H
……..
A9E2H A9E1H A9E0H
…...
…...
…...
A83FH
……………………………..
A822H
A821H
A820H
A81FH
……………………………..
A802H
A801H
A800H
A7FFH
……………………………..
A7E2H A7E1H A7E0H
…...
…...
…...
A45FH
……………………………..
A442H
A441H
A440H
A43FH
……………………………..
A422H
A421H
A420H
1400H
A41FH
……………………………..
A402H
A401H
A400H
13E0H
A3FFH
……………………………..
A3E2H A3E1H A3E0H
…...
…...
…...
A05FH
……………………………..
A042H
A041H
A040H
A03FH
……………………………..
A022H
A021H
A020H
A01FH
……………………………..
A002H
A001H
A000H
Se ctor 1
WL 32 - 63
1-KB yte
Se ctor 2
WL 64 - 79
5 12-byte
Se ctor 3
WL 80 - 95
5 12-byte
……………………………..
WL
Address
Figure 4-4
…...
AA02H AA01H AA00H
A9FFH
…...
AA22H AA21H AA20H
……………………………..
…...
……………………………..
AA1FH
…...
…...
AA3FH
…...
…...
ABE2H ABE1H ABE0H
…...
…...
AC02H AC01H AC00H
……………………………..
…...
…...
……………………………..
ABFFH
Se ctor 0
WL 0 - 3 1
1-KB yte
……..
……..
……..
Flash Bank 1
……..
……..
AC1FH
Se ctor 9
WL 124 - 127
Se ctor 8
WL 120 - 123
Se ctor 7
WL 116 - 119
Se ctor 6
WL 112 - 115
19E1H
ACE2H ACE1H ACE0H
Se ctor 5
WL 104 - 111
19E2H
AD02H AD01H AD00H
……………………………..
Se ctor 4
WL 96 - 1 03
……………………………..
Flash Bank 1 (Alternate Address Mapping)
19FFH
Se ctor 5
WL 104 - 111
2 56-byte
1A00H
Se ctor 4
WL 96 - 1 03
2 56-byte
1A20H
1A01H
……………………………..
ACFFH
……..
1A21H
1A02H
……..
…...
1A22H
……………………………..
……
…...
……………………………..
1A1FH
……
…...
1A3FH
AD1FH
……..
1BE2H 1BE1H 1BE0H
ADE2H ADE1H ADE0H
……..
1C02H 1C01H 1C00H
……………………………..
……
……………………………..
1BFFH
AE02H AE01H AE00H
……………………………..
……..
1C1FH
……………………………..
……..
1CE2H 1CE1H 1CE0H
……
1D02H 1D01H 1D00H
……………………………..
AE1FH
ADFFH
……..
……………………………..
1CFFH
AE62H AE61H AE60H
……..
1D1FH
AE82H AE81H AE80H
……………………………..
……
……
1E00H
……..
……
1E01H
1DE2H 1DE1H 1DE0H
……..
……
1E02H
……………………………..
……
……………………………..
1DFFH
……………………………..
AE7FH
……
……
1E1FH
AE9FH
……
1E60H
……
1E80H
1E61H
AEE2H AEE1H AEE0H
……
1E81H
1E62H
AF02H AF01H AF00H
……………………………..
……
……
1E82H
……………………………..
……………………………..
……
……
……………………………..
1E7FH
AF1FH
AEFFH
……
……
1E9FH
AF62H AF61H AF60H
……
……
1F00H
AF82H AF81H AF80H
……………………………..
……
……
1F01H
1EE2H 1EE1H 1EE0H
……………………………..
……
……
1F02H
……………………………..
……
……………………………..
AF7FH
……
……
1F1FH
1EFFH
AF9FH
Se ctor 3
WL 80 - 95
1F60H
Se ctor 2
WL 64 - 79
1F80H
1F61H
AFE2H AFE1H AFE0H
Se ctor 1
WL 32 - 63
1F81H
1F62H
……………………………..
Se ctor 0
WL 0 - 3 1
1F82H
……………………………..
Se ctor 9
WL 124 - 127
1 28-byte
……
……………………………..
1F7FH
Se ctor 8
WL 120 - 123
1 28-byte
……
1F9FH
Byte 2 Byte 1 Byte 0
AFFFH
Se ctor 7
WL 116 - 119
1 28-byte
Byte 31
1FE2H 1FE1H 1FE0H
1FFFH
Se ctor 6
WL 112 - 115
1 28-byte
Byte 2 Byte 1 Byte 0
……………………………..
……
Byte 31
WL
Address
8-Kbyte Flash Variant Bank 1 Wordline Addresses
User’s Manual
Flash Memory, V 1.0
4-6
V1.1, 2010-09
XC83x
Flash Memory
09E0H
…...
…...
…...
083FH
……………………………..
0822H
0821H
0820H
081FH
……………………………..
0802H
0801H
0800H
07FFH
……………………………..
07E2H
07E1H
07E0H
…...
…...
…...
045FH
……………………………..
0442H
0441H
0440H
043FH
……………………………..
0422H
0421H
0420H
041FH
……………………………..
0402H
0401H
03FFH
……………………………..
03E2H
03E1H
…...
…...
…...
005FH
……………………………..
0042H
0041H
0040H
003FH
……………………………..
0022H
0021H
0020H
001FH
……………………………..
0002H
0001H
0000H
……..
A9E2H A9E1H A9E0H
…...
…...
…...
A83FH
……………………………..
A822H
A821H
A820H
A81FH
……………………………..
A802H
A801H
A800H
A7FFH
……………………………..
A7E2H A7E1H A7E0H
…...
…...
…...
A45FH
……………………………..
A442H
A441H
A440H
A43FH
……………………………..
A422H
A421H
A420H
0400H
A41FH
……………………………..
A402H
A401H
A400H
03E0H
A3FFH
……………………………..
A3E2H A3E1H A3E0H
…...
…...
…...
A05FH
……………………………..
A042H
A041H
A040H
A03FH
……………………………..
A022H
A021H
A020H
A01FH
……………………………..
A002H
A001H
A000H
Se ctor 1
WL 32 - 63
1-KB yte
Se ctor 2
WL 64 - 79
5 12-byte
Se ctor 3
WL 80 - 95
5 12-byte
……………………………..
WL
Address
Figure 4-5
…...
AA02H AA01H AA00H
A9FFH
…...
AA22H AA21H AA20H
……………………………..
…...
……………………………..
AA1FH
…...
…...
AA3FH
…...
…...
ABE2H ABE1H ABE0H
…...
…...
AC02H AC01H AC00H
……………………………..
…...
…...
……………………………..
ABFFH
Se ctor 0
WL 0 - 3 1
1-KB yte
……..
……..
……..
Flash Bank 0
……..
……..
AC1FH
Se ctor 9
WL 124 - 127
Se ctor 8
WL 120 - 123
Se ctor 7
WL 116 - 119
Se ctor 6
WL 112 - 115
09E1H
ACE2H ACE1H ACE0H
Se ctor 5
WL 104 - 111
09E2H
AD02H AD01H AD00H
……………………………..
Se ctor 4
WL 96 - 1 03
……………………………..
Flash Bank 0 (Alternate Address Mapping)
09FFH
Se ctor 5
WL 104 - 111
2 56-byte
0A00H
Se ctor 4
WL 96 - 1 03
2 56-byte
0A20H
0A01H
……………………………..
ACFFH
……..
0A21H
0A02H
……..
…...
0A22H
……………………………..
……
…...
……………………………..
0A1FH
……
…...
0A3FH
AD1FH
……..
0BE2H 0BE1H 0BE0H
ADE2H ADE1H ADE0H
……..
0C02H 0C01H 0C00H
……………………………..
……
……………………………..
0BFFH
AE02H AE01H AE00H
……………………………..
……..
0C1FH
……………………………..
……..
0CE2H 0CE1H 0CE0H
……
0D02H 0D01H 0D00H
……………………………..
AE1FH
ADFFH
……..
……………………………..
0CFFH
AE62H AE61H AE60H
……..
0D1FH
AE82H AE81H AE80H
……………………………..
……
……
0E00H
……..
……
0E01H
0DE2H 0DE1H 0DE0H
……..
……
0E02H
……………………………..
……
……………………………..
0DFFH
……………………………..
AE7FH
……
……
0E1FH
AE9FH
……
0E60H
……
0E80H
0E61H
AEE2H AEE1H AEE0H
……
0E81H
0E62H
AF02H AF01H AF00H
……………………………..
……
……
0E82H
……………………………..
……………………………..
……
……
……………………………..
0E7FH
AF1FH
AEFFH
……
……
0E9FH
AF62H AF61H AF60H
……
……
0F00H
AF82H AF81H AF80H
……………………………..
……
……
0F01H
0EE2H 0EE1H 0EE0H
……………………………..
……
……
0F02H
……………………………..
……
……………………………..
AF7FH
……
……
0F1FH
0EFFH
AF9FH
Se ctor 3
WL 80 - 95
0F60H
Se ctor 2
WL 64 - 79
0F80H
0F61H
AFE2H AFE1H AFE0H
Se ctor 1
WL 32 - 63
0F81H
0F62H
……………………………..
Se ctor 0
WL 0 - 3 1
0F82H
……………………………..
Se ctor 9
WL 124 - 127
1 28-byte
……
……………………………..
0F7FH
Se ctor 8
WL 120 - 123
1 28-byte
……
0F9FH
Byte 2 Byte 1 Byte 0
AFFFH
Se ctor 7
WL 116 - 119
1 28-byte
Byte 31
0FE2H 0FE1H 0FE0H
0FFFH
Se ctor 6
WL 112 - 115
1 28-byte
Byte 2 Byte 1 Byte 0
……………………………..
……
Byte 31
WL
Address
4-Kbyte Flash Variant Bank 0 Wordline Addresses
User’s Manual
Flash Memory, V 1.0
4-7
V1.1, 2010-09
XC83x
Flash Memory
For the 8-Kbyte Flash variant, a WL address can be calculated as follow:
0000H + 20H × n, with 0 ≤ n ≤ 127 for Flash Bank 0
(4.1)
1000H/A000H + 20H × n, with 0 ≤ n ≤ 127 for Flash Bank 1
(4.2)
For the 4-Kbyte Flash variant, a WL address can be calculated as follow:
0000H/A000H + 20H × n, with 0 ≤ n ≤ 127 for Flash Bank 0
(4.3)
Only one out of all the wordlines in the Flash banks can be programmed each time. The
maximum/minimum program width of each WL is 32 bytes. Before programming can be
done, the user must first write the number of bytes of data that is equivalent to the
program width into the IRAM using ‘MOV’ instructions. Then, the Boot-loader (BSL)
routine (see Section 4.6) or Flash program subroutine (see Section 4.7.1) will transfer
this IRAM data to the corresponding write buffers of the targeted Flash bank. Once the
data are assembled in the write buffers, the charge pump voltages are ramped up by a
built-in program and erase state machine. Once the voltage ramping is completed, the
volatile data content in the write buffers would have been stored into the non-volatile
Flash cells along the selected WL. The WL is selected via the WL addresses shown in
Figure 4-3, Figure 4-4 and Figure 4-5. It is necessary to fill the IRAM with the number
of bytes of data as defined by the program width, otherwise the previous values stored
in the write buffers will remain and be programmed into the WL.
The same WL can be programmed twice before erasing is required as the Flash cells
are able to withstand two gate disturbs. This means if the number of data bytes that need
to be written is smaller than the 32 bytes minimum programming width, the user can opt
to program this number of data bytes (x; where x can be any integer from 1 to 31) first
and program the remaining bytes (32-x) later. However, since the minimum
programming width of Flash is always 32 bytes, the bytes that are unused in each
programming cycle must be written with all zeros.
Figure 4-6 shows an example of programming the same wordline twice with 16 bytes of
data. In the first program cycle, the lower 16 bytes are written with valid data while the
upper 16 bytes that do not contain meaningful data are written with all zeros. In the
second program cycle, it will be opposite as now only the upper 16 bytes can be written
with valid data and the lower 16 bytes, which already contain meaningful data, must be
written with all zeros.
User’s Manual
Flash Memory, V 1.0
4-8
V1.1, 2010-09
XC83x
Flash Memory
16 bytes
16 bytes
0000 ….. 0000 H
32 bytes (1 WL)
0000 ….. 0000 H
Program 1
0000 ….. 0000 H
1111 ….. 1111 H
0000 ….. 0000 H
1111 ….. 1111 H
Program 2
1111 ….. 0000 H
0000 ….. 0000 H
1111 ….. 0000 H
1111 ….. 1111 H
Note: A Flash memory cell can be programmed
from 0 to 1, but not from 1 to 0.
Flash memory cells
Figure 4-6
32-byte write buffers
Flash Program
User’s Manual
Flash Memory, V 1.0
4-9
V1.1, 2010-09
XC83x
Flash Memory
4.4
Operating Modes
The Flash operating modes for each bank are shown in Figure 4-7.
Sector(s) Erase
Ready-to-Read
Call of
Flash erase routine
or by BSL
Program
Call of
Flash program routine
or by BSL
Power-Down
System Power-Down
Figure 4-7
Flash Operating Modes
In general, the Flash operating modes are controlled by the BSL and Flash
program/erase subroutines (see Section 4.7).
Each Flash bank must be in ready-to-read mode before the program mode or sector(s)
erase mode is entered. In the ready-to-read mode, the 32-byte write buffers for each
Flash bank can be written and the memory cell contents read via CPU access. In the
program mode, data in the 32-byte write buffers is programmed into the Flash memory
cells of the targeted wordline.
The operating modes for each Flash bank are enforced by its dedicated state machine
to ensure the correct sequence of Flash mode transition. This avoids inadvertent
destruction of the Flash contents with a reasonably low software overhead. The state
machine also ensures that a Flash bank is blocked (no read access possible) while it is
being programmed or erased. At any time, a Flash bank can only be in ready-to-read,
program or sector(s) erase mode. However, it is possible to program/erase one Flash
bank while reading from another.
When the user sets bit PMCON0.PD = 1 to enter the system power-down mode, the
Flash banks are automatically brought to its power-down state by hardware. Upon
wake-up from system power-down, the Flash banks are brought to ready-to-read mode
to allow access by the CPU.
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Flash Memory, V 1.0
4-10
V1.1, 2010-09
XC83x
Flash Memory
4.5
Error Detection and Correction
The 8-bit data from the CPU is encoded with an Error Correction Code (ECC) before
being stored in the Flash memory. During a read access, data is retrieved from the Flash
memory and decoded for dynamic error detection and correction.
The correction algorithm (hamming code) has the capability to:
•
•
Detect and correct all 1-bit errors
Detect all 2-bit errors, but cannot correct
No distinction is made between a corrected 1-bit error (result is valid) and an uncorrected
2-bit error (result is invalid). In both cases, an ECC non-maskable interrupt (NMI) event
is generated; bit FNMIECC in register NMISR is set, and if enabled via
NMICON.NMIECC, an NMI to the CPU is triggered. The 16-bit Flash address at which
the ECC error occurs is stored in the system control SFRs FEAL and FEAH, and can be
accessed by the interrupt service routine to determine the Flash bank/sector in which the
error occurred.
User’s Manual
Flash Memory, V 1.0
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V1.1, 2010-09
XC83x
Flash Memory
4.5.1
Flash Error Address Register
The FEAL and FEAH registers together store the 16-bit Flash address at which the ECC
error occurs. The bit field PAGE of SCU_PAGE register must be programmed before
accessing these registers.
FEAL
Flash Error Address Register, Low byte(F6H)
RMAP: 0, PAGE: 5
7
6
5
4
Reset Value: 00H
3
2
1
0
ECCERRADDR[7:0]
rh
Field
Bits
Type Description
ECCERRADDR
[7:0]
rh
ECC Error Address Value [7:0]
FEAH
Flash Error Address Register, High byte(F7H)
RMAP: 0, PAGE: 5
7
6
5
4
Reset Value: 00H
3
2
1
0
ECCERRADDR[15:8]
rh
Field
Bits
Type Description
ECCERRADDR
[7:0]
rh
User’s Manual
Flash Memory, V 1.0
ECC Error Address Value [15:8]
4-12
V1.1, 2010-09
XC83x
Flash Memory
4.6
In-System Programming
In-System Programming (ISP) of the Flash memory is supported via the Boot ROMbased Boot-loader (BSL), allowing a blank microcontroller device mounted onto an
application board to be programmed with the user code, and also a previously
programmed device to be erased then reprogrammed without removal from the board.
This feature offers ease-of-use and versatility for the embedded design.
ISP is supported through the microcontroller’s serial interface (UART) which is
connected to the personal computer host via the commonly available RS-232 serial
cable. The BSL mode is selected if the programmed BMI and BMI values match the
corresponding values defined for the BSL mode after power-on or hardware reset. The
BSL routine will first perform an automatic synchronization with the transfer speed (baud
rate) of the serial communication partner (personal computer host). Communication
between the BSL routine and the host is done via a transfer protocol; information is sent
from the host to the microcontroller in blocks with specified block structure, and the BSL
routine acknowledges the received data by returning a single acknowledge or error byte.
User can program, erase or execute the Flash bank(s).
The available working modes include:
•
•
•
•
Transfer user program from host to Flash
Execute user program in Flash
Erase Flash sector(s) from the same or different Flash bank(s)
Mass Erase of all Flash sectors
User’s Manual
Flash Memory, V 1.0
4-13
V1.1, 2010-09
XC83x
Flash Memory
4.7
In-Application Programming
In some applications, the Flash contents may need to be modified during program
execution. In-Application Programming (IAP) is supported so that users can program or
erase the Flash memory from their Flash user program by calling some subroutines in
the Boot ROM (see Figure 4-8 and Chapter 23). The Flash subroutines will first perform
some checks and an initialization sequence before starting the program or erase
operation. A manual check on the Flash data is necessary to determine if the
programming or erasing was successful by using the ‘MOVC’ instruction to read out the
Flash contents. Other special subroutines include aborting the Flash erase operation
and checking the Flash bank ready-to-read status.
Boot ROM
special Flash
program/erase
subroutines
user program
0073 H
Flash NMI
service routine
Flash NMI
RETI instruction
Figure 4-8
Flash Program/Erase Flow
User’s Manual
Flash Memory, V 1.0
4-14
V1.1, 2010-09
XC83x
Flash Memory
4.7.1
Flash Programming
Each call of the Flash program subroutine allows the programming of 32 bytes of data
into the selected wordline (WL) of the:
•
•
Flash bank; or
64-byte User BSL Flash sector1).
Before calling this subroutine, the user must ensure that the 32-byte WL contents are
stored incrementally in the IRAM, starting from the address specified in R5 of the current
register bank. In addition, the input DPTR must contain a valid Flash WL address and all
NMI flags in SFR NMISR must be 0. Otherwise, PSW.CY bit will be set and no
programming will occur.
Two types of Flash program subroutines are provided in the Boot ROM to program the
Flash:
•
•
Non-background Flash Program subroutine (see Section 4.7.1.1)
Background Flash Program subroutine (see Section 4.7.1.2)
4.7.1.1
Non-background Flash Program Subroutine
The first type of subroutine, Non-background Flash Program, waits until Flash
programming is completed before allowing the user code to continue with its execution.
This type of routine can be used to program the Flash bank where the user code is in
execution. The Flash cannot be in both program mode and read mode at the same time.
It can also be used for programming the Flash bank where the interrupt vectors are
defined, as interrupts cannot be handled when the Flash is in program mode.
For this subroutine, the FNMIFLASH flag in SFR NMISR is cleared automatically and
therefore, need not be handled by the user.
4.7.1.2
Background Flash Program Subroutine
The second type of subroutine, Background Flash Program, allows the user program
code to continue execution from where it last stopped until the Flash NMI event is
generated. The FNMIFLASH flag is set and if enabled via bit NMIFLASH in SFR
NMICON, an NMI to the CPU will be triggered to enter the Flash NMI service routine. At
this point, the Flash bank is in ready-to-read mode i.e. programming is done.
This subroutine can be used in either of the following two cases:
•
•
The Flash bank where the code execution is taking place, is not the same as the
Flash bank that is targeted for programming.
The subroutine is called from XRAM.
1) Available only in the 8-Kbyte Flash variant.
User’s Manual
Flash Memory, V 1.0
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V1.1, 2010-09
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Flash Memory
Note: The case where the subroutine is called from Flash bank 1 to program the User
BSL Flash sector (and vice versa) should be avoided. Instead, the Nonbackground Flash Program subroutine should be used in this case.
4.7.2
Flash Erasing
Each call of the Flash erase subroutine allows the user to select for erase:
•
•
•
one sector; or
the 64-byte User BSL Flash sector1); or
a combination of sectors from the same or different Flash banks2)
Before calling the Flash erase subroutine, the user must ensure that R4 to R7 of the
current register bank are set accordingly. To select a sector for erase, the bit
corresponding to the sector in R4 to R7 must be set to 1. Sectors not to be erased must
have their corresponding bits cleared to 0. If no or invalid inputs are provided, PSW.CY
bit will be set and no programming will occur.
Two types of Flash erase subroutines are provided in the Boot ROM to erase the Flash:
•
•
Non-background Flash erase subroutine (see Section 4.7.2.1)
Background Flash erase subroutine (see Section 4.7.2.2)
4.7.2.1
Non-background Flash Erase Subroutine
The first type of subroutine, non-background Flash erase, waits until erasing is
completed before allowing the user code to continue with its execution.
This type of routine is necessary for users who need to erase the Flash bank where the
user code is in execution. The Flash cannot be in both erase mode and read mode at the
same time. It can also be used for erasing the Flash Bank where the interrupt vectors
are defined, as interrupts cannot be handled when the Flash is in erase mode as the
interrupt handler cannot be fetched.
For this subroutine, the FNMIFLASH flag is cleared automatically and therefore, need
not be handled by the user.
Note: As program will return to user code after erasing is completed, customer should
take care that they do not erase their user program code as well.
4.7.2.2
Background Flash Erase Subroutine
The second type of subroutine, background Flash erase, allows the user program code
to continue execution from where it last stopped until the Flash NMI event is generated.
The FNMIFLASH flag is set and if enabled via bit NMIFLASH, an NMI to the CPU will be
1) Available only in the 8-Kbyte Flash variant.
2) The sectors may include the User BSL Flash sector.
User’s Manual
Flash Memory, V 1.0
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V1.1, 2010-09
XC83x
Flash Memory
triggered to enter the Flash NMI service routine. At this point, the Flash bank is in readyto-read mode i.e. erasing is done.
This subroutine can be used in either of the following two cases:
•
•
The Flash bank where the code execution is taking place, is not the same as the
Flash bank that is targeted for erasing.
The subroutine is called from XRAM.
Note: The case where the subroutine is called from Flash bank 1 to erase the User BSL
Flash sector (and vice versa) should be avoided. Instead, the non-background
Flash erase subroutine should be used in this case.
4.7.3
Aborting Background Flash Erase
Each complete erase operation on a Flash bank requires approximately 100 ms, during
which read and program operations on the Flash bank cannot be performed. For the
XC83x, provision has been made to allow an on-going background Flash erase
operation to be interrupted so that higher priority tasks such as reading/programming of
critical data from/to the Flash bank can be performed. Hence, erase operations on
selected Flash bank sector(s) may be aborted to allow data in other sectors to be read
or programmed. To minimize the effect of aborted erase on the Flash data
retention/cycling and to guarantee data reliability, the following points must be noted for
each Flash bank:
•
•
•
•
•
An erase operation cannot be aborted earlier than 5 ms after it starts.
Maximum of two consecutive aborted erase (without complete erase in-between) are
allowed on each sector.
Complete erase operation (approximately 100 ms) is required and initiated by userprogram after a single or two consecutive aborted erase as data in relevant sector(s)
is corrupted.
For the specified cycling time1), each aborted erase constitutes one program/erase
cycling.
Maximum allowable number of aborted erase for each Flash sector during lifetime is
2500.
The Flash erase abort subroutine call cannot be performed anytime within 5 ms after the
erase operation has started. This is a strict requirement that must be ensured by the
user. Otherwise, the erase operation cannot be aborted. Once exited from this
subroutine, user can call the Flash Read Mode Status subroutine to check if the abort
erase operation has been completed. When the selected bank is already in Read Mode,
it indicates that the abort erase operation has been completed.
1) Refer to XC83x Data Sheet for Flash data profile
User’s Manual
Flash Memory, V 1.0
4-17
V1.1, 2010-09
XC83x
Flash Memory
4.7.4
Flash Read Mode Status
Besides the Flash program and erase subroutines, a subroutine to check the ready-toread mode status of the Flash Bank is additionally provided.
Before calling this subroutine, the user must ensure that the input R7 is configured to the
selected Flash Bank. The carry flag is cleared when Flash is in ready-to-read mode,
otherwise it is set. The carry flag is also set if the input to the subroutine is invalid.
This routine is especially useful when the abort background Flash erase subroutine is
used. After calling the erase-abort routine, the user can call this Flash Read Mode Status
subroutine to check if the erase operation has been successfully aborted and that the
Flash is already in ready-to-read mode.
User’s Manual
Flash Memory, V 1.0
4-18
V1.1, 2010-09
XC83x
Boot and Startup
5
Boot and Startup
Entry to various boot modes such as User mode, Boot-loader mode (BSL) and On-chip
Debug (OCDS) mode will depend on the Boot Mode Index (BMI) value. Section 5.2
describes the behaviors of each boot modes.
The BMI/BMI value is programmable via BSL mode 6 or user routine,
BR_PROG_USER_ID. User need to program the BMI and BMI to enter each boot mode.
Default mode is the UART BSL Mode. BMI is introduced to detect if the BMI value is
valid. Thus, BMI value is valid when BMI + BMI + 1 = 0. Table 5-1 shows the BMI value
required for each mode.
Table 5-1
Boot Mode Index
1)
Boot Mode
BMI
BMI
UART BSL Mode
00H
FFH
UART BSL Mode2)
00H
00H
3)
ALT USER BSL Mode
01H
FEH
User Mode (Productive)
10H
EFH
User Mode (Diagnostic) with SPD pin SPD_0
50H
AFH
User Mode (Diagnostic) with SPD pin SPD_1
52H
ADH
User Mode (Diagnostic) with SPD pin SPD_2
54H
ABH
OCDS Mode with SPD pin SPD_0
60H
9FH
OCDS Mode with SPD pin SPD_1
62H
9DH
OCDS Mode with SPD pin SPD_2
64H
9BH
Reserved
Others
Others
1) SPD : Single Pin DAP;
2) UART BSL Mode can be entered when BMI is 00 and BMI is either 00 or FF.
3) Jump directly to DFlash Bank 1 address location FF40H and execute the code. Only available in 8 Kbyte Flash
variant.
The BMI and BMI are part of the User Identification, USER_ID. USER_ID is a 4-byte data
that contains user’s specific information, see Section 5.1. Beside the BMI, the user can
also select either the 8 MHz active mode or 24 MHz active mode by programming the
USER_ID. The mode selection is performed before the start of the user code.
Once the device is in user mode (productive), changing of the BMI value to enter another
boot mode could be done by a specific code embedded in the user code. This code
should only be executed under a defined user condition. In this specific code, user can
use one of the following instructions to change the BMI value:
•
LJMP to user routine BR_UART_BSL to enter BSL mode (using BSL mode 6)
User’s Manual
5-1
V1.1, 2010-09
XC83x
Boot and Startup
•
LCALL the user routine BR_PROG_USER_ID to program USER_ID to enter other
boot mode.
For code protection, user may want to erase all flash contents before executing this
code. Detailed description of these user routines are found in the Boot ROM User
Routines Chapter.
Note: A soft reset will be performed after the BMI has been updated. Switching off the
supply voltage before the soft reset happened may cause the BMI to be updated
wrongly. No additional reset is necessary for the system to use the new BMI value.
Note: It is advisable to disable the Watchdog Timer (WDT) during the changing of BMI
value. A WDT reset during the programming of BMI may cause the BMI to update
wrongly. Beside that, a stable power supply is also mandatory. A wrong BMI could
cause the device to enter a deadlock situation.
Note: Unintentional execution of the BR_PROG_USER_ID user routine will affect the
BMI value. Device may not be able to boot up properly because of an invalid BMI.
A user-defined condition must be included to prevent an unintentional jump to this
routine.
In OCDS mode and User mode (Diagnostic), the respective debug interface of the single
pin DAP (SPD) will be enabled based on the BMI and BMI values.
5.1
User Identification Number
The USER_ID is a 4-byte data that contains user’s specific information, including the
boot-up options, BMI. It can be accessed by user using BR_GET_4_BYTES_INFO user
routine or via BSL Mode A. USER_ID can be programmed via BR_FEATURE_SETTING
user routine or via BSL Mode 6. Detailed description of these BSL Modes can be found
in UART Boot-loader chapter.
USER_ID, Byte 0
7
6
5
4
3
2
1
0
BMI
Field
Bits
Description
BMI
[7:0]
Boot Mode Index
The boot option to enter User Mode, UART BSL Mode and
OCDS Mode as described in Table 5-1.
User’s Manual
5-2
V1.1, 2010-09
XC83x
Boot and Startup
USER_ID, Byte 1
15
14
13
12
11
10
9
8
BMI
Field
Bits
Description
BMI
[15:8]
Inverse of Boot Mode Index
The inverse of BMI. BMI is checked for validity with BMI. BMI
is valid when BMI + BMI + 1 = 0
USER_ID, Byte 2
23
22
21
20
19
18
17
16
27
26
25
24
0
Field
Bits
Description
0
[23:16]
Reserved
USER_ID, Byte 3
31
30
29
28
CLKMOD PERIPHER
E_SEL
ALS_EN
0
Field
Bits
Description
0
[29:24]
Reserved
User’s Manual
5-3
V1.1, 2010-09
XC83x
Boot and Startup
Field
Bits
Description
PERIPHERALS_EN 30
Peripherals Enable Bit
0
Disable all peripherals defined in register
PMCON1
1
Enable all peripherals defined in register
PMCON1
CLKMODE_SEL
Clock Mode Selection
0
8 MHz active mode (Flash read with no wait state)
1
24 MHz active mode (Flash read with 1 wait state)
5.2
31
Boot ROM Operating Mode
After a reset, the CPU will always start by executing the Boot ROM code which occupies
the program memory address space 0000H – 1FFFH. The Boot ROM start-up procedure
will first switch the address space for the Boot ROM to C000H – DFFFH. Then remaining
Boot ROM start-up procedure will be executed from C00XH. The memory organization
of the XC83x shown in this document is after the Boot ROM address switch where the
different operating modes are executed.
5.2.1
User Mode (Productive)
If the User mode (productive) is selected, the Boot ROM will jump to program memory
address 0000H to execute the user code in the Flash memory. In this mode, the content
in the Flash memory are protected from external access. This is the normal operating
mode of the XC83x.
5.2.2
User Mode (Diagnostic)
If the User mode (diagnostic) is selected, the Boot ROM will jump to program memory
address 0000H to execute the user code in the Flash memory. This is similar to the user
mode (productive) described in Section 5.2.1, with the addition that the specified SPD
port is automatically configured to allow hot-attach.
5.2.3
Boot-Loader Mode
If the Boot-loader (BSL) mode is selected, the software routines of the BSL located in the
Boot ROM will be executed, allowing the XRAM and Flash memory to be programmed,
erased and executed. Refer to the UART BSL chapter for the different BSL working
modes.
5.2.4
OCDS Mode
If the OCDS mode is selected, the debug mode will be entered for debugging program
code. The OCDS hardware is initialized and a jump to program memory address 0000H
User’s Manual
5-4
V1.1, 2010-09
XC83x
Boot and Startup
is performed next. The user code in the Flash memory is executed and the debugging
process may be started.
During the OCDS mode, the lowest 64 bytes (00H – 3FH) in the internal data memory
address range may be alternatively mapped to the 64-byte monitor RAM or the internal
data RAM.
5.2.4.1
Alternate User BSL Mode
The Alternate User BSL mode allows the user to execute his/her own customized BSL
code. This code has to be first programmed into the 64 bytes user BSL Flash sector
located in the program memory address range FF40H to FF7FH.
If the Alternate User BSL mode is selected, the Boot ROM will jump to program memory
address FF40H to execute the user BSL code.
Note: This mode is available only in the 8 Kbyte Flash variant.
User’s Manual
5-5
V1.1, 2010-09
XC83x
UART Boot-Loader
6
UART Boot-Loader
The XC83x includes a UART Boot-Loader (BSL) Mode that can be entered with the BMI
settings as described in Boot and Startup chapter. The main purpose of BSL Mode is to
allow easy and quick programming/erasing of the Flash and XRAM via UART.
The UART BSL mode consists of two functional parts that presents two phases as
described below:
•
•
Phase I: Establish a serial connection and automatically synchronize to the transfer
speed (baud rate) of the serial communication partner (host).
Phase II: Perform the serial communication with the host. The host controls the
communication by sending special header information which selects one of the
working modes. These modes are:
– Mode0: Program customer code to XRAM
– Mode1: Execute customer code in XRAM
– Mode2: Program customer code to FLASH1)
– Mode3: Execute customer code in FLASH
– Mode4: Erase customer code in FLASH sector(s)1)
– Mode6: Program 4 bytes of USER_ID
– ModeA: Get 4 bytes Information
Except Mode 1, Mode 3 and Mode 6, the µC would return to the beginning of Phase II
and wait for the next command from the host after executing all other Modes.
The serial communication, which is activated in Phase II, is based a byte received in
Phase I (after baud rate 0x0055) to select single pin (0xAA) or dual pins (0x55) UART
of XC83x. UART auto-baud routine uses the LIN baud rate detection to calculate the
baud rate. The port settings for BSL Mode are listed in Table 6-1.
Table 6-1
Port Settings for UART BSL Mode
Device
XC83x
UART_INIT_ID
Single / Dual Pin(s) Pin(s) used
0xAA
Single pin
P 3.2 as RXD
P 3.2 as TXD
0x55
Dual pins
P 3.2 as RXD
P 0.7 as TXD
The serial transfer is working in asynchronous mode with the serial parameters 8N1
(eight data bits, no parity and one stop bit). The host can vary the baud rate in a wide
range because the µC does an automatic synchronization with the host in Phase I.
1) Include the User BSL Flash Sector. For XC83x-8K device only.
User’s Manual
UART BSL Mode, V 1.2
6-1
V1.1, 2010-09
XC83x
UART Boot-Loader
6.1
Phase I: Automatic Serial Synchronization to the Host
Upon entering UART BSL Mode, a serial connection is established and the transfer
speed (baud rate) of the serial communication partner (host) is automatically
synchronized in the following steps:
•
•
•
•
•
•
STEP 1: Initialize serial interface for reception and timer for baud rate measurement
STEP 2: Wait for SYN Break (13 bits low) and SYN Byte (0x55) from host
STEP 3: Synchronize the baud rate to the host
STEP 4: Acquire UART_INIT_ID (0xAA or 0x55) to determine single pin or dual pins
UART and initialize pins
STEP 5: Send Acknowledge byte (55H) to the host
STEP 6: Enter Phase II
6.1.1
General Description
The baud rate detection feature provides the capability to detect the baud rate using
Timer 2. Initialization consists of:
•
•
•
•
•
Serial port of the microcontroller set to Mode 1 (8-bit UART, variable baud rate) for
communication
Baud rate selection for detection (BCON.BGSEL) is defined as 00 (left as default)
Capture Timer 2 data register contents on negative transition at pin T2EX
Timer 2 external events are enabled (EXF2 flag is set when a negative transition
occurs at pin T2EX)
fT2=fPCLK / 4 (T2PRE=010)
The auto baud for UART BSL consists of the:
•
•
•
SYN Break (13 Bit time low)
SYN byte (55H)
UART_INIT_ID
The Break is used to signal the beginning of a new frame and must be at least 13 bits of
dominant value. When negative transition is detected at pin T2EX at the beginning of
Break, the Timer 2 External Start Enable bit (T2MOD.T2RHEN) is set. This will then
automatically start Timer 2 at the next negative transition of pin T2EX. Finally, the End
of SYN Byte Flag (FDCON.EOFSYN) is polled. When this flag is set, Timer 2 is stopped.
T2 Reload/Capture register (RC2H/L) is the time taken for 8 bits. Then the auto baud
routine calculates the actual baud rate, sets the PRE and BG values and activates Baud
Rate Generator. Once all are done, UART_INIT_ID value is read to determine the setting
of the UART BSL Mode to be single or dual pins, before ACK bytes (0x55) are sent out.
The baud rate detection is shown in Figure 6-1
User’s Manual
UART BSL Mode, V 1.2
6-2
V1.1, 2010-09
XC83x
UART Boot-Loader
1st negative transition,
set T2RHEN bit
T2 automatically
starts
Last captured value of T2
upon negative transition
EOFSYN bit is set,
T2 is stopped
SYN CHAR (55H)
SYN BREAK
Start
Bit
Stop
Bit
Captured Value (8 bits)
Figure 6-1
6.1.2
UART_INIT_ID
0x55 (Dual pins UART)
0xAA (Single pin UART)
Auto Baud Rate Detection
Calculation of BG and PRE values
To set up auto baud rate detection, the BG and PRE must be preload. As there are two
unknown values, two formulas are therefore needed. Firstly, the correlation between the
baud rate (baud) and the reload value (BG) depends on the internal peripheral frequency
(fPCLK):
(6.1)
f PCLK
baud = ---------------------------------------------------------------------------n- 
16  PREx  BRVALUE + ----



32
Second, the relation between the baud rate (baud) and the recording value of Timer 2
(T2) depends on the T2 peripheral frequency (fT2)and the number of received bits (Nb)
(6.2)
f T2 × N b
baud = ---------------------T2
Combining Equation (6.1) and Equation (6.2), together with Nb = 8, fT2 = fPCLK / 4
(T2PRE=010), PRE=1
(6.3)
f PCLK
------------------ × 8
f PCLK
4
----------------------------------------------------------------------------- = --------------------------T2
n




16 PREx BRVALUE + -----

32 
User’s Manual
UART BSL Mode, V 1.2
6-3
V1.1, 2010-09
XC83x
UART Boot-Loader
Simplifying Equation (6.3), we get
(6.4)
n  T2
 BRVALUE + ----- = ------
32 32
The capturing of the timing for 8 bits makes the formula easy for realization in assembly
language. The division with 32 can be simply achieved by a 5-bit right shift operation. In
previous Acropolis family, the shift operation causes a loss in the decimal digits, thus
reducing the baud rate accuracy. Therefore in XC83x, the concept (SFRs BGL and BGH)
is implemented in such a way that the actual shift (division) is not necessary by firmware
as it will be executed by hardware. In this way, we keep the decimal digits after division
and giving a better accuracy of the baud rate detection. Thus after capturing the 8 bits
timing in R2CH and R2CL, the values are programmed directly to BGH and BGL
respectively.
After setting BG and PRE, the Baud Rate Generator will then be enabled, and the
subsequent frames will follow this baud rate. After receiving UART_INIT_ID to determine
single or dual pins for UART BSL, the UART BSL routine sends an Acknowledge byte
(55H) to the host. If this byte is received correctly, it will be guaranteed that both serial
interfaces are working with the same baud rate.
6.2
Phase II: Serial Communication Protocol and the Modes
After the successful synchronization to the host, the UART BSL routine enters Phase II,
during which it communicates with the host to select the desired working modes. The
detailed communication protocol is explained as follows:
6.2.1
Serial Communication Protocol
The communication between the host and the UART BSL routine is done by a simple
transfer protocol. The information is sent from the host to the µC in blocks. All the blocks
follow the specified block structure. The communication is nearly unidirectional, that is,
that the host is sending several transfer blocks and the UART BSL routine is just
confirming them by sending back single acknowledge or error bytes. The µC itself does
not send any transfer blocks.
However, the above regulation does not apply to some modes where the µC might need
to send the required data to the host besides the acknowledge or error byte.
6.2.1.1
Transfer Block Structure
A transfer block consists of three parts:
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UART Boot-Loader
Block Type
(1 byte)
•
•
•
Data Area
(X bytes)
Checksum
(1 byte)
Block Type: the type of block, which determines how the data in the data area is
interpreted. Implemented block types are:
– 00H type “HEADER”
– 01H type “DATA”
– 02H type “END OF TRANSMISSION” (EOT)
Data Area: A list of bytes, which represents the data of the block. The length of data
area cannot exceed 96/97 bytes for Mode 0 and 2, depending on whether it is a Data
Block or EOT Block
Checksum: the XOR checksum of the block type and data area.
The host will decide the number of transfer blocks and their respective lengths during
one serial communication process. For safety purpose, the last byte of each transfer
block is a simple checksum of the block type and data area. The host generates the
checksum by XOR-ING all the bytes of the block type and data area. Every time the
UART BSL routine receives a transfer block, it recalculates the checksum of the received
bytes (block type and data area) and compares it with the attached checksum.
Note: If there is less than 1WL to be programmed to Flash, the PC Host will have to fill
up the vacancies with 00H, and transfer data in the length of 32n bytes (n=1-3).
6.2.1.2
Transfer Block Type
There are three types of transfer blocks depending on the value of the block type.
Table 6-2 provides the general information on these block types. More details will be
described in the corresponding sections later.
Table 6-2
Block Name
Type of Transfer Block
Block Type Description
Header Block 00H
User’s Manual
UART BSL Mode, V 1.2
This block has a fixed length of 8 bytes. Special
information is contained in the data area of the block,
which is used to select different working modes.
6-5
V1.1, 2010-09
XC83x
UART Boot-Loader
Table 6-2
Type of Transfer Block
Block Name
Block Type Description
Data Block
01H
This block length depends on the special information
given in the previous header block. This block is used in
working mode 0 and 2 to transfer a portion of program
code. The program code is in the data area of the block.
EOT Block
02H
This block length depends on the special information
given in the previous header block. This block is the last
block in data transmission in working mode 0 and 2. The
last program code to be transferred are in the data area
of the block.
6.2.1.3
Response codes to the host
The µC would let the host know whether a block has been successfully received by
sending out a response code. If a block is received correctly, an Acknowledge Code
(55H) is sent. In case of failure, there are two kinds of errors. The error might be a wrong
block type and the UART BSL would send back a block type error (0FFH) to the host.
This kind of error is caused by two conditions. One is the µC receives a block type other
than the implemented ones. The other is the µC receives the transfer blocks in wrong
sequences. For example, in working mode 0, immediately after the header block is
received, if another header block instead of a data block is received, the µC would
consider this case be a wrong block type error. Besides wrong block type error, the other
error is checksum error. If the checksum comparison fails, the UART BSL routine is
rejecting the transfer block by sending back a checksum error code (0FEH) to the host.
In both error cases the UART BSL routine awaits the actual block from the host again.
There is no flash protection, thus the flash protection type error is removed for XC83x.
UART BSL does not check for validity of address of XRAM/Flash, it is to the user’s
responsibility to ensure that the DPTR of Flash/XRAM is valid.
Table 6-3 gives a summary of the response codes to be sent back to the host by the µC
after it receives each transfer block.
Table 6-3
Type of Response Codes
Communication Status
Response Code to the Host
Successful
55H
Block Type Error
0FFH
Checksum Error
0FEH
Table 6-4 shows a tabulated summary of the possible responses the device may
transmit following the reception of a Header, Data or EOT Block.
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6-6
V1.1, 2010-09
XC83x
UART Boot-Loader
Table 6-4
Mode
Possible Responses for Various Block Types
Header Block
Data Block
EOT Block
0
Acknowledge, Block Type
Error, Checksum Error
Acknowledge, Block
Acknowledge, Block
Type Error, Checksum Type Error,
Error
Checksum Error
1
Acknowledge, Block Type
Error, Checksum Error
2
Acknowledge, Block Type
Error, Checksum Error
3
Acknowledge, Block Type
Error, Checksum Error
4
Acknowledge, Block Type
Error, Checksum Error
6
Acknowledge, Block Type
Error, Checksum Error
A
Acknowledge, Block Type
Error, Checksum Error
E
Acknowledge, Block Type
Error, Checksum Error
Acknowledge, Block
Acknowledge, Block
Type Error, Checksum Type Error,
Error
Checksum Error
The responses are defined in Table 6-5, which lists the possible reasons and/or
implications for error and suggests the possible corrective actions that the host can take
upon notification of the error.
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UART BSL Mode, V 1.2
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V1.1, 2010-09
XC83x
UART Boot-Loader
Table 6-5
Definitions of Responses
Response Value Description
Block
Type
Acknowledge
55H
Head
er
EOT
Block
Error
FFH
Checksum FEH
Error
6.2.2
BSL Reasons / Implications
Mode
1, 3
Corrective
Action
The requested operation will
be performed once the
response is sent.
6, A
The requested operation has
0, 2, 4 been performed and is
successful.
All others
Reception of the Block is
successful. Transmission of
IDs follow in Mode A. Ready
to receive the next Block.
All others
Either the Block_Type is
undefined or option is invalid
or the flow is invalid.
All
There is a mismatch between Retransmit a valid
the calculated and the
Block
received Checksum.
Retransmit a valid
Block
The Selection of Working Modes
When the UART BSL routine enters Phase II, it first waits for an eight-byte long header
block from the host. The header block contains the information for the selection of the
working modes. Depending on this information, the UART BSL routine selects and
activates the desired working mode. If the µC receives an incorrect header block, the
UART BSL routine sends, instead of an Acknowledge code, a checksum or block error
code to the host and awaits the header block again. In this case the host may react by
re-sending the header block or by releasing a message to the customer.
6.2.2.1
Receiving the Header Block
The header block is always the first transfer block to be sent by the host during one data
communication process. It contains the working mode number and special information
on the related mode (referred to as “mode data”). The general structure of a Header
Block is shown below.
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UART BSL Mode, V 1.2
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XC83x
UART Boot-Loader
Block Type
00H
(Header Block)
Data Area
Mode
(1 byte)
Mode Data
(5 bytes)
Checksum
(1 byte)
Description:
•
•
•
•
00H: The block type, which marks the block as a Header Block
Mode: The working mode. The implemented working modes are:
– 00H (Mode0: Program customer code to XRAM)
– 01H (Mode1: Execute customer code in XRAM)
– 02H (Mode2: Program customer code to FLASH)
– 03H (Mode3: Execute customer code in FLASH)
– 04H (Mode4: Erase customer code in FLASH sector(s))
– 06H (Mode6: Program 4 bytes of USER_ID)
– 0AH (ModeA: Get 4 bytes Information)
Mode Data: Five bytes of special information, which are necessary to activate
corresponding working mode.
Checksum: The checksum of the header block.
6.2.2.2
Mode0: Program customer code to XRAM
Mode 0 is used to transfer a customer program from the host to the XRAM of the µC via
serial interface.
The header block for this working mode has the following structure:
The Header Block
Data Area
00H
(Header
Block)
00H
(Mode 0 )
StartAddr
High
(1 byte)
StartAddr
Low
(1 byte)
Block
Length
(1 byte)
Not Used
Checksum
(1 byte)
(2 bytes)
Mode Data Description:
Start Addr High, Low: 16-bit Start Address, which determines where to copy the
received program codes in the XRAM.
Block_Length: The length of the following Data Blocks or EOT Block at each
transmission.
Not used: 2 bytes, these bytes are not used and will be ignored in Mode 0.
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UART Boot-Loader
Note: The Block-Length refers to the whole length (block type, data area and
checksum) of the following transfer block (Data Block or EOT Block). For each
transmission, length of Data Block(s) and EOT Block should be the same.
Note: Maximum length for Data Blocks (when sending Header Block, followed by 1-255
Data Blocks and finally end transmission with one EOT Block) is 96+2 = 98 bytes.
Note: Maximum length for EOT Blocks (when sending one Header Block followed by
one EOT Block each time only) is = 96 + 3 = 99 bytes
After successfully receiving the Header Block, the µC enters Mode 0, during which the
program codes are transmitted from the host to the µC by Data Block(s) and EOT Block,
which are describe as below.
Note: No empty Data Block is allowed.
The Data Block
01H
(Data
Block)
(1 byte)
Program Codes
((Block_Length-2) bytes)
Checksum
(1 byte)
Description:
Program Codes: The program codes have a length of (Block_Length-2) byte, where
the Block_Length is provided in the previous Header Block.
The EOT Block
02H
(EOT
Block)
(1 byte)
Last_Code
_Length
(1 byte)
Program Code
Not Used
Checksum
(1 byte)
Description:
Last_Codelength: This byte indicates the length of the program codes in this EOT
Block.
Program Codes: The last program codes to be sent to the µC
Not used: The length is (Block_Length-3-Last_Codelength). These bytes are not
used and they can be set to any value.
User’s Manual
UART BSL Mode, V 1.2
6-10
V1.1, 2010-09
XC83x
UART Boot-Loader
6.2.2.3
Mode1: Execute customer code in XRAM
Mode 1 is used to execute a customer program in the XRAM of the µC at 0F000H. The
Header Block for this working mode has the following structure:
The Header Block
Data Area
00H
(Header
Block)
01H
(Mode 1 )
Checksum
(1 byte)
Not Used
Mode Data Description:
Not used: The five bytes are not used and will be ignored in Mode 1.
Under working Mode 1, the Header Block is the only transfer block to be sent by the host,
no further serial communication is necessary. The µC will exit the UART BSL Mode and
jump to the XRAM address at 0F000H.
6.2.2.4
Mode2: Program customer code to FLASH
Mode 2 is used to transfer a customer program from the host to the Flash of the µC via
serial interface.
The header block for this working mode has the following structure:
The Header Block
Data Area
00H
(Header
Block)
02H
(Mode 2 )
StartAddr
High
(1 byte)
StartAddr
Low
(1 byte)
Block
Length
(1 byte)
Not Used
Checksum
(1 byte)
(2 bytes)
Mode Data Description:
Start Addr High, Low: 16-bit Start Address, which determines where to copy the
received program codes in the Flash. This address must be valid and aligned to the page
address.
Block_Length: The length of the following Data Bocks or EOT Block. At each time, PC
Host can sent minimum 1WL (32 bytes) and maximum 3 WLs (96 bytes). If data blocks
are to be sent, the maximum block_length has to be 98 (=96+2) bytes. If only EOT block
is sent, the maximum block_length has to be 99 (=96+3)bytes.
Not used: 2 bytes, these bytes are not used and will be ignored in Mode 2.
User’s Manual
UART BSL Mode, V 1.2
6-11
V1.1, 2010-09
XC83x
UART Boot-Loader
Note: If the data starts in a non-page address, PC Host must fill up the beginning
vacancies with 00H and provide the start address of that page address. For e.g.,
if data starts in 0F82H, the PC Host will fill up the addresses 0F80H and 0F81H with
00H and provide the Start Address 0F80H to microcontroller. And if data is only
8 bytes, the PC Host will also fill up the remaining addresses with 00H and transfer
32n data bytes.
Note: The Block_Length refers to the whole length (block type, data area and
checksum) of the following transfer block (Data Block or EOT Block). Since the
data area is multiples of 32 bytes, thus by adding block type and checksum bytes,
the Block_Length is 32n+2 bytes.
Note: User BSL Flash Sector can be programmed via this Mode. For XC83x-8K device
only.
After successfully receiving the Header Block, the µC enters Mode 2, during which the
program codes are transmitted from the host to the µC by Data Block and EOT Block,
which are describe as below.
Note: No empty Data Block is allowed.
The Data Block
01H
(Data
Block)
(1 byte)
Program Codes
((Block_Length-2) bytes)
Checksum
(1 byte)
Description:
Program Codes: The program codes have a length of (Block_Length-2) byte, where
the Block_Length is provided in the previous Header Block.
The EOT Block
02H
(EOT
Block)
(1 byte)
Last_Code
_Length
(1 byte)
Program Code
Not Used
Checksum
(1 byte)
Description:
Last_Codelength: This byte indicates the length of the program codes in this EOT
Block.
User’s Manual
UART BSL Mode, V 1.2
6-12
V1.1, 2010-09
XC83x
UART Boot-Loader
Note: If Data blocks are sent, this byte should be zero. If this byte is not zero, additional
undesired bytes will be programmed
Program Codes: The last program codes to be sent to the µC
Not used: The length is (Block_Length-3-Last_Codelength) and should be filled with
zeros.
6.2.2.5
Mode3: Execute customer code in FLASH
Mode 3 is used to execute a customer program in the Flash of the µC at 0000H. The
Header Block for this working mode has the following structure:
The Header Block
Data Area
00H
(Header
Block)
03H
(Mode 3 )
Checksum
(1 byte)
Not Used
Mode Data Description:
Not used: The five bytes are not used and will be ignored in Mode 3.
In working Mode 3, the Header Block is the only transfer block to be sent by the host, no
further serial communication is necessary. The µC will exit the UART BSL Mode and
jump to the Flash address at 0000H.
6.2.2.6
Mode4: Erase customer code in FLASH sector(s)
Mode 4 is used to erase different sector(s) in the Flash Bank 01) and Flash Bank 12). It
also support the erasing of User BSL Flash Sector2).
The Header Block for Flash Sector erase
Data Area
00H
(Header
Block)
04H
(Mode 4 )
Flash_B0_
SectorL
(1 byte)
Flash_B0_
SectorH
(1 byte)
Flash_B1_
SectorL
(1 byte)
Flash_B1_
SectorH
(1 byte)
Not Used
(1 byte)
Checksum
(1 byte)
1) For XC83x-4K and XC83x-8K devices
2) For XC83x-8K device only.
User’s Manual
UART BSL Mode, V 1.2
6-13
V1.1, 2010-09
XC83x
UART Boot-Loader
Mode Data Description:
Flash_B0_SectorL: In this byte, the sectors 0 to 7 of Flash Bank 0 are represented by
bits 0 to 7. When the bit contains a 1, the corresponding sector is selected. E.g. byte of
0x12 selects sectors 1 and 4 of Flash Bank 0 for erase.
Flash_B0_SectorH: In this byte, the sectors 8 to 9 of Flash Bank 0 are represented by
bits 0 to 1. When the bit contains a 1, the corresponding sector is selected. E.g. byte of
0x01 selects sectors 8 of Flash Bank 0 for erase.
Flash_B1_SectorL: In this byte, the sectors 0 to 7 of Flash Bank 1 are represented by
bits 0 to 7. When the bit contains a 1, the corresponding sector is selected. E.g. byte of
0x12 selects sectors 1 and 4 of Flash Bank 1 for erase.
Flash_B1_SectorH: In this byte, the sectors 8 to 9 of Flash Bank 1 are represented by
bits 0 to 1. In this byte, the User BSL Flash Sector is also represented by bit 2. When the
bit contains a 1, the corresponding sector is selected. E.g. byte of 0x05 selects sectors
8 and User BSL Flash Sector for erase.
Note: Unwanted/unselected bits should be cleared to 0
Note: Selection of Flash_B1_SectorL and Flash_B1_SectorH are available only for
XC83x-8K only. For other configurations, these 2 bytes are ignored, not used.
6.2.2.7
Mode6: Program 4 bytes of USER_ID
Mode 6 is used to program User indentification, USER_ID (4 bytes). The Header block
for this working mode has the following structure:
The Header Block
Data Area
00H
(Header
Block)
06H
(Mode 6 )
USER_ID_
3
(1 byte)
USER_ID_
2
(1 byte)
USER_ID_
1
(1 byte)
USER_ID_
0
(1 byte)
Not Used
(1 byte)
Checksum
(1 byte)
Mode Data Description
User_ID: These 4 bytes is given by user as USER_ID for BMI values and initialization of
settings.
Not used: This byte is not used and will be ignored in Mode 6.
After programming the USER_ID and sending back the acknowledge response to the
Host (to indicate successful operation has executed), a software reset will be triggered
and the programmed boot-up mode will be entered.
User’s Manual
UART BSL Mode, V 1.2
6-14
V1.1, 2010-09
XC83x
UART Boot-Loader
Note: This Mode should be handled and executed with care. It should be executed last.
User should program their Flash code first, program XRAM code (if needed), and
finally program USER_ID.
Note: There is no erasing option for USER_ID. To erase the USER_ID, simply write
0x00 to the 4 bytes USER_ID.
6.2.2.8
ModeA: Get 4 bytes Information
Mode A is used to get 4 bytes data determined by the Option byte in the header block.
The header block for this working mode has the following structure:
The Header Block
Data Area
00H
(Header
Block)
0AH
(Mode A )
Not Used
Option
(4 bytes)
(1 byte)
Checksum
(1 byte)
Mode Data Description:
Option: This byte will determine the 4 bytes data to be sent to the host. Only option 00H
- 02H are valid options.
00H - Chip Identification Number (MSB byte 1... LSB byte 4)
01H - USER_ID (MSB byte 1... LSB byte 4)
In Mode A, the header block is the only transfer block to be sent by the host. The
microcontroller will return an acknowledgement followed by 4 bytes of data to the host if
the header block is received successfully. If an invalid option is received, the
microcontroller will return 4 bytes of 00H. USER_ID is the user identification number and
the order of the 4 bytes of USER_ID_INFO are as followed: USER_ID_4, USER_ID_3,
USER_ID_2 and USER_ID_1.
User’s Manual
UART BSL Mode, V 1.2
6-15
V1.1, 2010-09
XC83x
System Control Unit
7
System Control Unit
The System Control Unit (SCU) of the XC83x handles all system control tasks besides
the debug related tasks which are controlled by the OCDS/Cerberus. All functions
described in this chapter are tightly coupled, thus, they are conveniently handled by one
unit, the SCU. The SCU contains the following functional sub-blocks:
•
•
•
•
Embedded Voltage Regulator (EVR) (see Section 7.1 on Page 7-1)
Reset Control (see Section 7.2 on Page 7-6)
Clock System and Control (see Section 7.3 on Page 7-11)
Power Management (see Section 7.4 on Page 7-17)
The XC83x provides a range of utility features for secure system performance under
critical conditions (e.g., brownout).
At the center of the XC83x clock system is the Clock Control Unit (CCU), which
generates a master clock frequency using the 48 MHz oscillator. In-phase synchronized
clock signals are derived from the master clock and distributed throughout the system.
7.1
Power Supply System with Embedded Voltage Regulator
The power supply to the core, memories and the peripherals is regulated by the
Embedded Voltage Regulator (EVR) that comes with detection circuitries to ensure that
the supplied voltages are within the specified operating range. The main voltage and low
power voltage regulators in the EVR may be independently switched off to reduce power
consumption for the different power saving modes.
The XC83x microcontroller requires two different levels of power supply:
•
•
2.5 V to 5.5 V for the Embedded Voltage Regulator (EVR) and Ports
2.5 V for the core, memory, on-chip oscillator, and peripherals
Figure 7-1 shows the XC83x power supply system. A power supply of 2.5 V to 5.5 V
must be provided from the external power supply pin. The 2.5 V power supply for the
logic is generated by the EVR. The EVR helps reduce the power consumption of the
whole chip and the complexity of the application board design.
User’s Manual
7-1
V1.1, 2010-09
XC83x
System Control Unit
CPU &
Memory
On-chip
OSC
Peripheral
logic
V D D C (2.5V)
FLASH
ADC
GPIO
Ports
(P0-P2)
EVR
VD D P (2.5V-5.5V)
VSSP
Figure 7-1
XC83x Power Supply System
EVR Features:
•
•
•
•
•
•
Input voltage (VDDP): 3.0 V to 5.5 V @ full operation condition
Input voltage (VDDP) down to 2.5 V in active mode or power down mode with a
reduction in the load conditions @ reduced voltage condition
Output Voltage (VDDC): 2.5 V +/- 7.5%
Low power voltage regulator provided in power-down mode
VDDC and VDDP prewarning detection
VDDC brownout detection
The EVR consists of a main voltage regulator and a low power voltage regulator. In
active mode, both voltage regulators are enabled. In power-down mode, the main
voltage regulator is switched off, while the low power voltage regulator continues to
function and provide power supply to the system with low power consumption.
The EVR works within an input voltage range of 3.0 V to 5.5V under full operation
condition and within an input range down to 2.5 V under reduced voltage condition.
XC83x will only work in power down mode or in active mode with limited load available
in the reduced voltage condition.
The EVR has the VDDC and VDDP detectors. There are two threshold voltage levels for
VDDC detection: prewarning (2.4 V) and brownout (2.3 V). When VDDC is below a nominal
voltage of 2.4 V, the VDDC NMI flag, NMISR.FNMIVDDC is set and an NMI request to the
User’s Manual
7-2
V1.1, 2010-09
XC83x
System Control Unit
CPU is activated provided VDDC NMI is enabled (NMICON.NMIVDDC). The prewarning
detection is disabled by default via bit VDDCPW in SDCON register. This is necessary
especially in the reduced voltage condition. This bit has to be set to 1 to enable the
prewarning detection. If VDDC is below a nominal voltage of 2.3 V, the brownout reset will
be activated, putting the microcontroller into a reset state. In power down mode,
brownout reset happens when VDDC is below 1.5 V.
For VDDP, there is a nominal prewarning level of 3.6 V and a nominal brownout reset
threshold of 2.9 V. When VDDP is below a nominal voltage of 3.6 V, the VDDP NMI flag,
NMISR.FNMIVDDP is set and an NMI request to the CPU is activated provided VDDP NMI
is enabled (NMICON.NMIVDDP). If VDDP is below a nominal voltage of 2.9 V, the
brownout reset will be activated, putting the microcontroller into a reset state. The
detection of these 2 levels could be disabled via bits VDDPPW and VDDPBOA in
SDCON register in active mode especially in the reduced voltage condition. These 2
detections are automatically shut down in power down mode. In power down mode,
brownout reset happens when VDDP is below 3.6 V if bit VDDPBOPD is set to 1.
Besides the various brownout threshold levels for VDDP and VDDC, EVR enters into the
reset mode when VDDP is below 2.4 V. It could happened if the VDDP brownout detection
in active mode or power down mode is disabled via bit VDDPBOA and VDDPBOPD.
7.1.1
Reduced Voltage Condition
In the reduced voltage conditon of 2.5 V < VDDP < 3.0 V, the active current must be
below a sets of values based on the EVR driving capability. These limits can be found in
the Data Sheet. The active current consumption needs to be below the specified values
as according to the VDDP voltage. If the conditions are not met, a brownout reset may be
triggered. A guideline of the current consumption for some of the modules is also
available in the datasheet.
Note: The full operation of XC83x is specified for 3 V < VDDP < 5.5 V.
User’s Manual
7-3
V1.1, 2010-09
XC83x
System Control Unit
7.1.2
EVR Register Description
The SDCON is used to enable or disable the various detectors. The status of VDDP and
VDDC threshold levels are also indicated in this register. The bit field PAGE of
SCU_PAGE register must be programmed before accessing these registers.
SDCON
Supply Detection Control Register
RMAP: 0, PAGE: 1
7
6
5
(EEH)
Reset Value: 34H
4
3
0
VDDPTH
VDDCTH
r
rh
rh
2
1
0
VDDPBO
VDDPBOA VDDPPW
PD
rw
Field
Bits
Type Description
VDDCPW
0
rw
rw
VDDCPW
rw
rw
VDDC Prewarning Detection Enable
0
VDDC prewarning detection is disabled.
1
VDDC prewarning detection is enabled.
Note: VDDC prewarning flag and NMI will only be
triggered when this bit is set to 1.
VDDPPW
1
rw
VDDP Prewarning Detection Enable
0
VDDP prewarning detection is disabled.
1
VDDP prewarning detection is enabled.
Note: VDDP prewarning flag and NMI will only be
triggered when this bit is set to 1.
VDDPBOA
2
rw
VDDP Brownout Detection Enable in active mode
0
VDDP brownout detection in active mode is
disabled.
1
VDDP brownout detection in active mode is
enabled.
VDDPBOPD
3
rw
VDDP Brownout Detection Enable in power down
mode
0
VDDP brownout detection in power down
mode is disabled.
1
VDDP brownout detection in power down
mode is enabled.
User’s Manual
7-4
V1.1, 2010-09
XC83x
System Control Unit
Field
Bits
Type Description
VDDCTH
4
rh
VDDC Threshold Indication
0
Below VDDC prewarning threshold level.
1
Above VDDC prewarning threshold level.
Note: It is not affected by the bit VDDCPW.
VDDPTH
5
rh
VDDP Threshold Indication
0
Below VDDP prewarning threshold level.
1
Above VDDP prewarning threshold level.
Note: It is not affected by the bit VDDPPW.
0
User’s Manual
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
7-5
V1.1, 2010-09
XC83x
System Control Unit
7.2
Reset Control
The XC83x has five types of resets: power-on reset, watchdog timer reset, soft reset,
power-down wake-up reset, and brownout reset.
When the XC83x is first powered up or with brownout condition triggered by supply
voltage input(s) going below the threshold, proper voltage thresholds must be reached
before the system starts operation with the release of the system reset. The CPU then
starts to execute from the Boot ROM firmware.
The Watchdog Timer (WDT) module is also capable of resetting the device if it detects
a malfunction in the system.
Another type of reset that needs to be detected is the reset while the device is in
power-down mode (i.e., wake-up reset). While the contents of the static RAM are
undefined after a power-on reset, they are well defined after a wake-up reset from
power-down mode.
A brownout reset is triggered if the VDDC supply voltage dips below 2.3 V or VDDP supply
voltage dips below 2.9 V provided the detector is enabled.
As for soft reset, it can be triggered by application software where applicable.
7.2.1
Types of Reset
7.2.1.1
Power-On Reset
The supply voltage VDDP is used to power up the chip. The EVR is the first module in the
chip to be reset, which includes:
1. Startup of the main voltage regulator and the low power voltage regulator.
2. When VDDP and VDDC reach the threshold of the VDDP and VDDC detectors, the reset of
EVR becomes inactive.
When the system starts up, the device is running in active 8 MHz mode using internal
48 MHz oscillator clock as the system frequency. Once the 48 MHz oscillator is stable
which is 480 oscillations after EVR is stable, Flash has to be in the ready-to-read mode
before the deassertion of the system reset. In user mode, the system clock can be
switched by the startup firmware in Boot ROM to the user selectable mode (active 8 MHz
mode or 24 MHz mode). P0.4 pin serves as a reset indication to the external world to
indicate that the device has executed a reset.
The startup firmware starts to run after the system is out of reset. The user specified
settings in USER_ID such as the boot mode (User Mode, BSL Mode, OCDS Mode) to
enter and the system clock speed will be decoded in the startup firmware. Based on the
value decoded, the startup firmware will performed the necessary setup before entering
the selected boot mode.
User’s Manual
7-6
V1.1, 2010-09
XC83x
System Control Unit
Note: When VDDP is not powered on, the current over any GPIO pin must not source
VDDP higher than 0.3 - 0.5 V.
7.2.1.2
Watchdog Timer Reset
The watchdog timer reset is an internal reset. The Watchdog Timer (WDT) maintains a
counter that must be refreshed or cleared periodically. If the WDT is not serviced
correctly and in time, it will generate an NMI request to the CPU and then reset the
device after a predefined time-out period. Bit RSTCON.WDTRST is used to indicate the
watchdog timer reset status.
For watchdog timer reset, as the EVR and 48 MHz oscillator is already stable, the timing
for watchdog timer reset is shorter compared to the other types of resets.
7.2.1.3
Soft Reset
Soft reset is an internal reset that is caused by a software set of the soft reset request
bit, SWRQ, in RSTCON register. It can be triggered by application software where
necessary. Bit RSTCON.SOFTRS is used to indicate the soft reset status.
7.2.1.4
Power-Down Wake-Up Reset
Power is still applied to the XC83x during power-down mode, as the low power voltage
regulator is still operating. If power-down mode is entered appropriately, all important
system states will have been preserved in the Flash by software.
If the XC83x is in power-down mode, three options are available to awaken it:
•
•
•
through RTC wake-up event (depending on the type of power down mode)
through EXINT0 pin
through the failure of the RTC clock source
Selection of option through EXINT0 pin is made via the control bit PMCON0.EWS. The
RTC wake-up event and RTC clock failure could be used as the wake-up sources
depending on the type of power down mode. The wake-up from power-down can be with
reset or without reset; this is chosen by the PMCON0.WKSEL bit. The wake-up status
(with or without reset) is indicated by the RSTCON.WKRS bit.
The time needed for the device to be out of reset is faster as compared to the power-on
reset as the EVR takes a shorter time period to become stable.
7.2.1.5
Brownout Reset
In active mode, the VDDC detector in EVR detects brownout when the core supply voltage
VDDC dips below
•
•
•
the threshold voltage VDDC_TH (approximately 2.3 V) or
the threshold voltage VDDP_TH (approximately 2.9 V) if the detector is enabled or
the threshold voltage VDDP_TH (approximately 2.4 V) if the detector is disabled
User’s Manual
7-7
V1.1, 2010-09
XC83x
System Control Unit
The brownout will cause the device to be reset. In power-down mode, the VDDC is
monitored by the POR in EVR and a reset is generated when VDDC drops below 1.5 V.
Once the brownout reset takes place, the reset sequence is the same as the power-on
reset sequence.
7.2.2
Module Reset Behavior
Table 7-1 lists the functions of the XC83x and the various reset types that affect these
functions. The symbol “■” signifies that the particular function is reset to its default state.
Table 7-1
Effect of Reset on Modules/Functions
Module/
Function
Power-On
Reset
Brown-Out
Reset
Wake-up
Reset
Soft
Reset
Watchdog
Reset
CPU Core
■
■
■
■
■
SCU
■
■
■
■
■
except
except
except
indication bits indication bits indication bits
Peripherals ■
■
■
■
■
Debug
System
■
■
■
■
■
Port
Control
■
■
■
■
■
FW Startup Executes all Executes all Executes all
Execution INIT
INIT
INIT
Executes all
INIT
Executes all
INIT
On-Chip
Affected,
Static RAM unreliable
Affected,
unreliable
Not affected,
reliable
Not affected,
reliable
Not affected,
reliable
Flash
■
■
■
■
■
EVR
■
■
■
■
■
Clock
System
■
■
■
■
■
User’s Manual
7-8
V1.1, 2010-09
XC83x
System Control Unit
7.2.3
Reset Control Register Description
RSTCON register consist of the indication bits of a wake-up event, WDT reset and soft
reset. Table 7-2 shows the reset value of RSTCON register after these events.
RSTCON
Reset Control Register
RMAP: 0, PAGE: 1
7
6
(F7H)
5
4
Reset Value: 00H
3
2
1
0
SWRQ
0
SOFTRS
WDTRST
WKRS
rwh
r
rwh
rwh
rwh
Field
Bits
Type Description
WKRS
0
rwh
Wake-up Indication Bit
0
No Wake-up occurred.
1
Wake-up has occurred.
This bit can only be set by hadware and clear by
software.
WDTRST
1
rwh
Watchdog Timer Reset Indication Bit
0
No watchdog reset occurred.
1
Watchdog reset has occurred.
This bit can only be set by hadware and clear by
software.
SOFTRS
2
rwh
Soft Reset Indication Bit
0
No soft reset occurred.
1
Soft reset has occurred.
This bit can only be set by hadware and clear by
software.
SWRQ
7
rwh
Soft Reset Request
0
No action.
1
On set, soft reset is requested.
This bit is automatically cleared by hardware.
The SWRQ bit is a protected bit. When the
Protection Scheme is activated, this bit cannot be
written directly.
0
[6:3]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
7-9
V1.1, 2010-09
XC83x
System Control Unit
Table 7-2
Reset Value of Register RSTCON
Reset Source
Reset Value
Power-down Wake-up Reset
0000 0001B
WDT Reset
0000 0010B
Soft Reset
0000 0100B
Power-On Reset/Brown-out Reset
0000 0000B
User’s Manual
7-10
V1.1, 2010-09
XC83x
System Control Unit
7.3
Clock System and Control
Figure 7-2 shows the block diagram of the clock system in XC83x. It consists of a
48 MHz oscillator and a clock control unit (CCU). The system clock fSYS is generated by
the 48 MHz internal oscillator. In addition, fSYS is also the input clock to the Clock Control
Unit (CCU).
The CCU generates all clock signals required within the microcontroller from the system
clock. It consists of:
•
•
Clock mode selection in active mode
Centralized enable/disable circuit for clock control
SPCLK
/6
LEDTSCU
FPCLK
48 MHz
OSC
fsys=
48MHz
CLKMODE=1
PCLK
1)
/2
CLKMODE=0
1)
SSC, UART, T0, T1, T2,
IIC, WDT2), RTC2)
SCLK
CCLK
/3
CCU6, CORDIC, MDU, ADC
CCLKn
CORE
FLASH
Interface
Clock Control Unit (CCU)
1) CLKMODE is an input to a BROM user routine that is used to select the core frequency
2) Refer to the respective module chapter for the clock source to the counter in WDT and RTC
Figure 7-2
Clock System Block Diagram
In normal running mode, the typical frequencies of different modules are as follows:
•
•
•
•
•
CPU clock (CCLK, SCLK) = 24 MHz
Flash Interface clock (CCLKn) = 48 MHz
Fast peripherial clock (FPCLK) = 48 MHz
Slow peripherial clock (SPCLK) = 8 MHz
Peripheral clock (PCLK) = 24 MHz (same as CPU clock)
User’s Manual
7-11
V1.1, 2010-09
XC83x
System Control Unit
Peripherals that are running in FPCLK frequency are CCU6, CORDIC, MDU, ADC, LED
and Touch -sense controller. Other peripherials are clocked by PCLK which is the same
as CPU clock. In normal running mode, PCLK= CCLK.
In active mode, there are 2 clocking frequencies, 8 MHz and 24 MHz, for the CPU clock
(CCLK, SCLk) and the peripherials clock (PCLK). A user routine called
BR_CLKMODE_SETTING in the Boot ROM is used to switch between these 2 clock
frequencies. If the CLKMODE input of the user routine is set to 0, 8 MHz frequency is
selected. 24 MHz is selected when CLKMODE is set to 1. While changing the frequency
of CPU clock and PCLK clock, it is recommended to disable all interrupts to prevent any
access to flash that may results in an unsuccessful flash operation. There is one wait
state inserted during a read access on Flash when CPU clock is set to 24 MHz. As for
CPU clock running at 8 MHz, no wait state will be inserted.
In idle mode, only the CPU clock CCLK is disabled. In power-down mode, CCLK, SCLK,
FPCLK, SPCLK, CCLKn and PCLK are all disabled.
Beside the 48 MHz internal oscillator, there is a 75 kHz oscillator in XC83x. It is used as
a secondary system clock when a loss of 48 MHz clock happens. It is also used to clock
the Watchdog Timer (WDT).
In addition, XC83x requires an external oscillator of 32.768 kHz via the oscillator pad to
support the time keeping function using real-time clock mode 0.
7.3.1
Oscillator Watchdog
There are 3 oscillator watchdogs in XC83x, namely, the 48 MHz oscillator watchdog
(48 MHz OWD), 75 kHz oscillator watchdog (75 kHz OWD) and the 32.768 kHz external
oscilator watchdog (32.768 kHz OWD). The 48 MHz OWD monitors the 48 MHz clock
source. Incoming frequencies that are below 43 MHz (typical) are detected as “oscillator
too low”. The 75 kHz OWD monitors the 75 kHz clock source and it is detected as “too
low” when it is oscillating below 35 kHz (typical). By setting bit OSC_CON.RCOWDRST,
the detection for 48 MHz oscillator and 75 kHz oscillator can be restarted. The detection
status output is only valid after 13 cycles of the 75 kHz frequency (approximately
180 us). The third oscillator watchdog is used to monitor the 32.768 kHz external clock
source of the Real-time clock.
After reset, both the 48 MHz and 75 kHz OWD are default disabled. User need to check
the status of OSC_CON.INTOSC_ST status flag before both OWDs can be enabled.
When a 1 is detected in bit INTOSC_ST, the 75 kHz oscillator should be running in a
stable trimmed frequency. Next, the OWD function could be enabled by setting bit
RCOWDRST in OSC_CON register. User code is recommended to continue when
48MOSC2L and 75KOSC2L is both 0. User can also choose to continue with other
operations while waiting for a stable 48MOSC2L and 75KOSC2L. The loss of oscillator
clock NMI would be based on these 2 signals to trigger a NMI if it is enabled via bit
NMICON.NMIOSCCLK.
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XC83x
System Control Unit
The third oscillator watchdog is used to detect the loss of 32.768 kHz crystal oscillator
when it is below 16 kHz (typical).
7.3.2
Loss of Clock Detection and Recovery
Loss of clock happens when the 48 MHz oscillator watchdog detects a nominal
frequency that is less than 43 MHz during normal operation. In this case, an NMI
interrupt will be generated if it is enabled by NMICON.NMIOSCCLK. Concurrently, the
oscillator status flag, 48MOSC2L, is set to 1 and the system clock will switch to the
75 kHz oscillator as the clock source. Emergency routines can be executed with the
XC83x clocked with this oscillator.
The XC83x remains in this loss of clock state until the next power on reset or after a
successful clock recovery has been performed. A clock recovery could be carried out by
restarting the detection by setting bit OSC_CON.RCOWDRST. Upon detecting a stable
oscillator frequency of more than 43 MHz, 48MOSC2L will be set to 0 and the system
clock will switched automatically to the 48 MHz clock source.
When a loss of clock is detected on the 75 kHz oscillator , the 75 kHz oscillator watchdog
status flag, 75KOSC2L, is set to 1. An NMI interrupt will be generated if it is enabled by
NMICON.NMIOSCCLK. Under this situation, there will be no switching to 48MHz
oscillator. However, the 48 MHz oscillator watchdog will not be functioning. No
monitoring of this master clock is possible. Emergency routines can be executed using
48 MHz as the system clock.
Note: With 75 kHz as the system frequency in loss of clock state, read from flash is
possible. However, Flash program and erase is not allowed.
Note: NMICON.NMIOSCCLK is used to enable the NMI interrupt for loss of clock failure
in 48 MHz or 75 kHz oscillators.
When a nominal frequency below 16 kHz is detected on the 32.768 kHz oscillator
watchdog, an NMI interrupt will be generated if it is enabled by NMICON.NMIXTALCLK.
Concurrently, the external oscillator status flag, XTAL2L, will be set to 1. Under this
condition, the RTC module will result in a loss of clock situation if it is running in the time
keeping mode. It is recommended to stop the RTC operation or select another RTC clock
source because the time keeping mode (RTC mode 0) will not be functioning properly.
7.3.3
Startup Control for 32.768 kHz Oscillator Clock
In XC83x, the 32.768 kHz external clock is used for real time keeping. To enable this
clock, the following sequence need to be performed:
•
•
•
Power up the 32.768 kHz oscillator pad by setting OSC_CON.XPD bit to 0.
Wait for 2 second for the oscillation to be stable.
Ensure that the 75 kHz oscillator is stabled (OSC_CON.INTOSC_ST = 1) before
enabling the 32.768 kHz OWD.
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XC83x
System Control Unit
•
•
Restart the 32.768 kHz OWD by setting OSC_CON.XTALOWDRST to 1.
When bit XTAL2L is 0, select the Real Time Clock Mode 0 (Time Keeping Mode).
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XC83x
System Control Unit
7.3.4
CCU Register Description
The registers of the clock control unit are reset to the default value after any type of reset.
Register OSC_CON controls the 48 MHz oscillator watchdog, 75 kHz oscillattor
watchdog and the 32.768 kHz oscillator watchdog.
OSC_CON
OSC Control Register
RMAP: 0, PAGE: 1
(F4H)
7
6
0
INTOSC
_ST
5
XPD
r
rh
rw
Reset Value: 30H
4
3
2
XTALOWD 75KOSC
XTAL2L
RST
2L
rh
rwh
rh
1
0
48MOSC
2L
RCOWD
RST
rh
rwh
Field
Bits
Type Description
RCOWDRST
0
rwh
48 MHz and 75 kHz Oscillators Watchdog Reset
Setting this bit will restart the oscillator detection.
This bit will be automatically reset to 0 and thus
always be read back as 0.
0
No effect.
1
Restart the oscillator watchdog for 48 MHz
and 75 kHz oscillation. 48MOSC2L and
75KOSC2L flag will be held in the last value
until it is updated after 180 usec.
48MOSC2L
1
rh
48 MHz Oscillator Too Low Flag
The Oscillator Watchdog monitors the fSYS (same
as fOSC). System frequency is generated from the
internal 48 MHz oscillator.
fSYS is above threshold.
0
1
fSYS is below threshold.
75KOSC2L
2
rh
75 kHz Oscillator Too Low Flag
The Oscillator Watchdog monitors the 75 kHz
oscillation.
0
75 kHz oscillates above threshold.
1
75 kHz oscillates below threshold.
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XC83x
System Control Unit
Field
Bits
Type Description
XTALOWDRST
3
rwh
32.768 kHz External Oscillator Watchdog Reset
Setting this bit will restart the oscillator detection.
This bit will be automatically reset to 0 and thus
always be read back as 0.
0
No effect.
1
Restart the oscillator watchdog for
32.768 kHz oscillation. XTAL2L flag will be
held in the last value until it is updated after
250 usec.
XTAL2L
4
rh
32.768 kHz External Oscillator Too Low Flag
The Oscillator Watchdog monitors the 32.768 kHz
external oscillation.
0
External oscillator oscillates above threshold.
1
External oscillator oscillates below threshold.
XPD
5
rw
32.768 kHz Oscillator Pad Power Down Control
0
32.768 kHz OSC pad is not powered down.
1
32.768 kHz OSC pad is powered down.
GPIO functions is available.
INTOSC_ST
6
rh
Internal Oscillator Stable Indication
0
48MHz and 75 kHz oscillators are not stable.
1
48MHz and 75 kHz oscillators are stable.
0
7
r
Reserved
Returns 0 if read; should be written with 0.
Note: The reset value of OSC_CON register is 0011 0110B. One clock after reset, bits
48MOSC2L and 75KOSC2L will be set to 0 if both oscillators are running, then the
value 0011 0000B will be observed.
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XC83x
System Control Unit
7.4
Power Management
The power saving modes in the XC83x provide flexible power consumption through a
combination of techniques, including:
•
•
•
•
Stopping the CPU clock
Stopping the clocks of individual system components
Reducing clock speed of some peripheral components
Power-down of the entire system with fast restart capability
After a reset, the active mode (normal operating mode) is selected by default (see
Figure 7-3) and the system runs in the main system clock frequency. In active mode, the
system clock could be running in 24 MHz or 8 MHz. From active mode, different power
saving modes can be selected by software. They are:
•
•
•
•
•
Idle mode
Power down mode 1
Power down mode 2
Power down mode 3
Power down mode 4
POWER-DOWN
MODE 1
EXINT0 pin
Set bits
PDMODE=00B
set IDLE bit
IDLE
EXINT0 pin/
RTC wake-up event/
loss of RTC clock
set bits PDMODE=01B
ACTIVE
set bits PDMODE=10B
any interrupt
EXINT0 pin/RTC
wake-up event
EXINT0/RTC
wake-up event
POWER-DOWN
MODE 2
POWER-DOWN
MODE 3
Set bits
PDMODE=11B
POWER-DOWN
MODE 4
Figure 7-3
Transition between Power Saving Modes (without reset)
In XC83x, all functions must be operational in the active mode and idle mode when the
normal VDDP supply range of 3.0 V to 5.5 V is applied to the system. For reduced voltage
condition in active mode and idle mode, required functions as needed by user will be
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XC83x
System Control Unit
available as long as the active current is kept under the limits. As for power down mode,
specified modules as described in Section 7.4.1.2 must continue to function when the
VDDP is as low as 2.5 V but maybe performance could be reduced.
7.4.1
Functional Description
7.4.1.1
Idle Mode
The idle mode is used to reduce power consumption by stopping the core’s clock.
In idle mode, the oscillator continues to run, but the core is stopped with its clock
disabled. Peripherals whose input clocks are not disabled are still functional. The user
should disable the Watchdog Timer (WDT) before the system enters the idle mode;
otherwise, it will generate an internal reset when an overflow occurs and thus will disrupt
the idle mode. The CPU status is preserved in its entirety; the stack pointer, program
counter, program status word, accumulator, and all other registers maintain their data
during idle mode. The port pins hold the logical state they had at the time the idle mode
was activated.
Software requests idle mode by setting the bit PCON.IDLE to 1.
The idle mode can be terminated and the system will returned to active mode by
activating any enabled interrupt. The CPU operation is resumed and the interrupt will be
serviced. Upon RETI instruction, the core will return to execute the next instruction after
the instruction that sets the IDLE bit to 1.
7.4.1.2
Power Down Mode
In order to achieve different levels of power saving, the XC83x has four types of power
down modes, Power Down mode 1, 2, 3 and 4. Generally, the 48 MHz oscillator and the
Flash memory are put into power down state in all the modes. In addition, the main
voltage regulator is switched off, with only low power voltage regulator still operating in
these power down modes. Therefore, most of the functions of the microcontroller are
stopped while the contents of the Flash, on-chip RAM, XRAM, and the SFRs are
maintained.
Table 7-3 shows the behaviour of several modules during power down mode. In power
down mode 2, RTC is running in the periodic wake-up mode. It allows the device to exit
power down mode at a specfic period of time. The function is useful in low power
application. Modules running in power down mode remain functioning at the reduced
voltage condition where the main power supply could be as low as 2.5 V. However, it
may shows a reduced performance. The rest of the modules are powered down in all
power down modes. Table 7-4 shows the available wake-up source for each power
down mode. One of the available source is to receives an external wake-up signal via
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XC83x
System Control Unit
EXINT0 pin by setting bit EWS to 1. The edge that trigger the wake-up signal will
depends on bit EXINT0 in EXICON0 register.
Note: EXICON0.EXINT0 = 11B cannot be used to wake-up from power down mode.
Table 7-3
Modules Behavior in Power Down Mode1)
Modules
Power Down Power Down Power Down Power Down
Mode 1
Mode 22)
Mode 32)
Mode 42)
RTC
N
Y
Y
Y
75 kHz OSC
N
Y
N
Y
32.768 kHz OSC PAD
N
Y
Y
N
75 kHz OWD
N
N
N
N
32.768 kHz OWD
N
Y
N
N
1) N indicates that the module is shut down and Y indicates that it is running in power down mode.
2) RTC Mode 2 and 3 are not supported in power down mode. The RTCCLK pin will be shut down once power
down mode is entered.
Table 7-4
Available Wake-up Source for Power Down Mode
Modules
Power Down Power Down Power Down Power Down
Mode 1
Mode 2
Mode 3
Mode 4
RTC wake-up
Not available Available
Available
Available
Clock Failure
Not available Available
Not available Not available
EXINT01)
Available
Available
Available
Available
1) EXINT0 wake-up source is selected using bit PMCON0.EWS
Power Down Mode 1
All peripherial blocks and CPU including the real-time clock that operates with either the
32.768 kHz XTAL pad or the 75 kHz oscillator are stopped. Both 32.768 kHz and 75 kHz
oscillator watchdog are also stopped. With the clock being turned off, the system cannot
be awakened by an interrupt or the Real-time clock. It will be awakened only when it
receives an external wake-up signal via EXINT0 pin by setting bit EWS to 1. The wakeup source and wake-up type must be selected before the system enters the power-down
mode.
The sequence to enter power down mode 1 is:
•
•
Select power down mode 1 by setting bit PMCON0.PDMODE to 00B.
Power down all modules including the 48 MHz and 75 kHz oscillator by setting bit
PMCON0.PD to 1.
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XC83x
System Control Unit
Two NOP instructions must be inserted after the bit PMCON0.PD is set to 1. This
ensures the first instruction (after two NOP instructions) is executed correctly after wakeup from power-down mode.
Power Down Mode 2
In this mode, all the modules except those that are described in Table 7-3 are powered
down. The real-time clock that operates with the 32.768 kHz XTAL pad running in the
time keeping mode (RTC Mode 0) and the real-time count is maintained. In addition, the
75 kHz oscillator and the 32.768 kHz oscillator watchdog (OWD) can be enabled in
power down mode 2 to monitor the status of the external oscillation. To exit power down
mode 2, the real-time clock wake up event can be used as one of the wake-up source.
EXINT0 is also available when bit PMCON0.EWS is 1. For the case of the loss of
external 32.768 kHz oscillation, power down mode 2 will be exited when the
OSC_CON.XTAL2L flag set to 1.
The sequence to enter power down mode 2 is:
•
•
•
•
•
•
•
•
•
Power up the 32.768 kHz oscillator pad by setting bit OSC_CON.XPD to 0.
Wait for 2 second for the oscillation to be stable.
Ensure that the 75 kHz oscillator is stabled (OSC_CON.INTOSC_ST = 1) before
enabling the 32.768 kHz OWD.
Restart the 32.768 kHz OWD by setting bit OSC_CON.XTALOWDRST to 1.
When bit XTAL2L is 0, select the Real Time Clock Mode 0 (Time Keeping Mode).
Ensure the real-time clock is enabled by setting bit RTCON.RTCC to 1.
Disable the WDT module by setting bit WDTCON.WDTEN to 0.
Select power down mode 2 by setting PMCON0.PDMODE to 01B.
Enter power down mode by setting bit PMCON0.PD to 1.
Two NOP instructions must be inserted after the bit PMCON0.PD is set to 1. This
ensures the first instruction (after two NOP instructions) is executed correctly after wakeup from power-down mode.
Note: The WDT timer must be disabled by software before entering power down mode.
The device will not be able to wake-up if a WDT overflow occurs in the power down
mode.
Power Down Mode 3
Power down mode 3 is similiar to power down mode 2 except that the 32.768 kHz
oscillator watchdog and the 75 kHz oscillator are powered down. No monitoring of the
status of the external oscillation is possible in this mode. To exit power down mode 3,
the real-time clock wake up event can be used provided that the external oscillation is
stable. The wake-up time must be longer than the time needed to enter power down
mode. Besides this wake-up source source, it can also be awakened when it receives
an external wake-up signal via EXINT0 pin by setting bit PMCON0.EWS to 1.
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XC83x
System Control Unit
The sequence to enter power down mode 3 is:
•
•
•
•
•
•
Power up the 32.768 kHz oscillator pad by setting OSC_CON.XPD bit to 0.
Wait for 2 second for the oscillation to be stable.
Select the Real Time Clock Mode 0 (Time Keeping Mode).
Ensure that real-time clock is enabled by setting bit RTCON.RTCC set to 1.
Select power down mode 3 by setting PMCON0.PDMODE to 10B.
Enter power down mode by setting bit PMCON0.PD to 1.
Note: The above sequence did not include the enabing of the 32.768 kHz OWD. It can
be enabled during active mode for monitoring the external oscillation. Upon
entering Power Down Mode 3, OWD and 75 kHz oscillator will be shut down
automatically by hardware.
Two NOP instructions must be inserted after the bit PMCON0.PD is set to 1. This
ensures the first instruction (after two NOP instructions) is executed correctly after wakeup from power-down mode.
Power Down Mode 4
In this mode, all the modules except those that are described in Table 7-3 are powered
down. The real-time clock that operates with the 75 kHz oscillators is running in the
periodic wake-up mode and the real-time count is maintained. However, no monitoring
of the status of the 75 kHz oscillation is possible. This is because the 75 kHz oscillator
watchdog is powered down. To exit power down mode 4, the real-time clock wake up
event can be used. Besides this wake-up source, it can also be awakened when it
receives an external wake-up signal via EXINT0 pin by setting bit PMCON0.EWS to 1.
The sequence to enter power down mode 4 is:
•
•
•
•
Ensure that real-time clock is enabled by setting bit RTCON.RTCC to 1.
Disable the WDT module by setting bit WDTCON.WDTEN to 0.
Select power down mode 4 by setting PMCON0.PDMODE to 11B.
Enter power down mode by setting bit PMCON0.PD to 1.
Two NOP instructions must be inserted after the bit PMCON0.PD is set to 1. This
ensures the first instruction (after two NOP instructions) is executed correctly after wakeup from power-down mode.
For all types of power down mode, the port pins hold the logicial state they had when the
power down mode was activated. For digital ports, the input and output driver of all port
pins that are not used as wake-up source are disabled once the chip enters power down
mode. This can reduce the leakage current in the power down mode. If the user intend
to maintain a level of “1” or “0” on output pin during power down, the pull-up/pull-down
device should be enabled before entering power down mode. Upon wake-up, the port
pins will be enabled again.
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XC83x
System Control Unit
Note: The WDT timer must be disabled by software before entering power down mode.
The device will not be able to wake-up if a WDT overflow occurs in the power down
mode.
Exiting Power Down Mode
Power down mode can be exited in various ways:
•
•
•
The EXINT0 pin detects a edge based on the setting in bit EXICON0.EXINT0
The wake-up event request from the real-time clock
The RTC clock source failure
Note: EXICON0.EXINT0 = 11B cannot be used to wake-up from power down mode
The EXINT0 wake-up source is enabled by PMCON0.EWS. Bit MODPISEL1.EXINT0IS
can be used for the EXINT0 input pin selection. The wake-up with reset or without reset
is selected by bit PMCON0.WKSEL.
If bit WKSEL was set to 1 before entering power-down mode, the system will execute a
reset sequence similar to the power-on reset sequence. Therefore, all port pins are put
into their reset state and will remain in this state until they are affected by program
execution.
If bit WKSEL was cleared to 0 before entering power-down mode, a fast wake-up
sequence is used. The port pins continue to hold their state which was valid during
power-down mode until they are affected by program execution.
The wake-up from power-down without reset using EXINT0 wake-up source undergoes
the following procedure:
1. In power-down mode, EXINT0 pin must be held at the inactive level.
2. Power-down mode is exited when EXINT0 pin goes active for at least 100 ns.
3. The main voltage regulator is switched on and takes approximately 150 µs to
become stable.
4. The on-chip oscillator is started. Typically, the on-chip oscillator takes approximately
10 us to stabilize.
5. Subsequently, the FLASH will enter ready-to-read mode. This does not require the
typical 160 µs as is the case for the normal reset. The timing for this part can be
ignored.
6. The CPU operation is resumed. The core will return to execute the next instruction
after the instruction which sets the PD bit.
Note: No interrupt will be generated by the EXINT0 wake-up source even if EXINT0 is
enabled before entering power-down mode. It is the same for the rest of the wakeup sources. An interrupt will be generated only if EXINT0 fulfils the interrupt
generation conditions after CPU resumes operation.
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XC83x
System Control Unit
As for exiting power down mode to active mode in reduced voltage condition, the active
current must be below the limits as specified in the Data Sheet. A brownout reset may
occurred immediately after wakeup if the condition is not met.
After wake-up from power down mode without reset, the status flag of the wake-up event
can be used to indicate the source of wake-up. In addition, the oscillator watchdog needs
to be re-enabled if necessary by setting bit RCOWDRST in OSC_CON register. But
before the oscillator watchdog can be enabled, it is required to ensure that the 48 MHz
and 75 kHz oscillators are stable by checking the status of OSC_CON.INTOSC_ST
status flag. See Section 7.3.1 for more detail descriptions.
In power down mode 1, real-time clock is stopped and user is required to enabled it once
the chip exit power down mode.
7.4.1.3
Peripheral Clock Management
The amount of reduction in power consumption that can be achieved by this feature
depends on the number of peripherals running. Peripherals that are not required for a
particular functionality can be disabled by gating off the clock inputs. For example, in idle
mode, if all timers are stopped, and ADC, CCU6, MDU and the serial interfaces are not
running, maximum power reduction can be achieved. However, the user must take care
when determining which peripherals should continue running and which must be
stopped during active and idle modes.
The ADC, SSC, CCU6, MDU, LEDTSCU, IIC, Timer 2 can be disabled (clock is gated
off) by setting the corresponding bit in the PMCON1 register. Furthermore, the analog
part of the ADC module may be disabled by resetting the GLOBCTR.ANON bit. This
feature causes the generation of the ADC analog clock to be stopped and allows a
reduction in power consumption when no conversion is needed.
In order to save power consumption when the on-chip oscillator is used, XTAL should be
powered down by setting bit OSC_CON.XPD. When the external oscillator is used, the
on-chip oscillator can be powered down by setting bit OSC_CON.OSCPD.
PMCON1
Peripheral Management Control Register 1(EFH)
RMAP: 0, PAGE: 1
7
6
IIC_DIS
LTS_DIS
rw
rw
User’s Manual
5
4
CDC_DIS MDU_DIS
rw
rw
7-23
Reset Value: FFH
3
2
1
0
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
rw
rw
rw
rw
V1.1, 2010-09
XC83x
System Control Unit
Field
Bits
Type Description
ADC_DIS
0
rw
ADC Disable Request. Active high.
0
ADC is in normal operation.
1
Request to disable the ADC. (default)
SSC_DIS
1
rw
SSC Disable Request. Active high.
0
SSC is in normal operation.
1
Request to disable the SSC. (default)
CCU_DIS
2
rw
CCU Disable Request. Active high.
0
CCU is in normal operation.
1
Request to disable the CCU. (default)
T2_DIS
3
rw
T2 Disable Request. Active high.
0
T2 is in normal operation.
1
Request to disable the T2. (default)
MDU_DIS
4
rw
MDU Disable Request. Active high.
0
MDU is in normal operation.
1
Request to disable the MDU. (default)
CDC_DIS
5
rw
CORDIC Disable Request. Active high.
0
CORDIC is in normal operation.
1
Request to disable the CORDIC. (default)
LTS_DIS
6
rw
LEDTSCU Disable Request. Active high.
0
LEDTSCU is in normal operation.
1
Request to disable the LEDTSCU. (default)
IIC_DIS
7
rw
IIC Disable Request. Active high.
0
IIC is in normal operation.
1
Request to disable the IIC. (default)
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XC83x
System Control Unit
7.4.2
Power Management Register Description
PMCON0
Power Mode Control Register 0
RMAP: 0, PAGE: 1
7
6
5
(F3H)
4
Reset Value: 01H
3
2
1
0
0
WKSEL
PDMODE
PD
EWS
r
rw
rw
rwh
rw
Field
Bits
Type Description
EWS
0
rw
External interrupt 0 Wake-up Source Selected
0
External interrupt 0 wake-up is not selected.
1
External interrupt 0 wake-up is selected.
PD
1
rwh
Power Down Mode Enable. Active High.
Setting this bit will cause the chip to go into a power
down mode as indicated by bit PDMODE. Reset by
wake-up circuit.
The PD bit is a protected bit. When the Protection
Scheme is activated, this bit cannot be written
directly. For more information on Protection
Scheme, see Chapter 3.4.4.
PDMODE
[3:2]
rw
Power Down Mode Select
00
Power down mode 1 is selected.
01
Power down mode 2 is selected.
10
Power down mode 3 is selected.
11
Power down mode 4 is selected.
WKSEL
4
rw
Wake-up Reset Select Bit
0
Wake-up without reset.
1
Wake-up with reset.
0
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
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XC83x
System Control Unit
PCON [Note: This register is located within XC800 core]
Power Control Register [Not bitaddressable](87H)
RMAP: 0, PAGE: X
7
6
5
4
Reset Value: 00H
3
2
1
0
SMOD
0
GF1
GF0
0
IDLE
rw
r
rw
rw
r
rw
Field
Bits
Type Description
IDLE
0
rw
User’s Manual
Idle Mode Enable
0
Do not enter Idle Mode
1
Enter Idle Mode
7-26
V1.1, 2010-09
XC83x
System Control Unit
7.5
SCU Register Mapping
The system control SFRs are used to control the overall system functionalities, such as
interrupts, variable baud rate generation, clock management, bit protection scheme and
oscillator. The SFRs are located in the standard memory area (RMAP = 0) and are
organized into 8 pages. The SCU_PAGE register is located at F1H. It contains the page
value and page control information.
SCU_PAGE
Page Register for SCU
RMAP: 0, PAGE: X
7
6
(F1H)
5
4
Reset Value: 00H
3
2
1
OP
STNR
0
PAGE
w
w
r
rwh
0
Field
Bits
Type Description
PAGE
[3:0]
rwh
Page Bits
When written, the value indicates the new page address.
When read, the value indicates the currently active page
= addr [y:x+1]
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the target
of the operation defined by bit OP.
If OP = 10B,
the contents of PAGE are saved in SCU_STx before
being overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the contents of
SCU_STx. The value written to the bit positions of PAGE
is ignored.
00
SCU_ST0 is selected.
01
SCU_ST1 is selected.
10
SCU_ST2 is selected.
11
SCU_ST3 is selected.
User’s Manual
7-27
V1.1, 2010-09
XC83x
System Control Unit
Field
Bits
Type Description
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is ignored
and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the former contents of
PAGE are saved in the storage bit field SCU_STx
indicated by STNR.
11
Automatic restore page action. The value written
to the bit positions PAGE is ignored and instead,
PAGE is overwritten by the contents of the storage
bit field SCU_STx indicated by STNR.
The addresses of the system control SFRs are listed in Table 7-5. Not listed in the tables
is the register SYSCON0, which can be accessed in both standard (non-mapped) and
mapped address of 8FH.
Table 7-5
SFR Address List for SCU Pages 0 - 7
Address
Page 0
Page 1
Page 2
Page 3
F2H
IRCON0
PASSWD
XADDRH
F3H
IRCON1
PMCON0
MODPISEL
F4H
EXICON1
OSC_CON
MODPISEL1
F5H
IRCON2
ID
MODPISEL2
F6H
IRCON3
WDTCON
MODSUSP
F7H
NMISR
RSTCON
MODIEN
EEH
NMICON
SDCON
MODPISEL3
EFH
EXICON0
PMCON1
Address
Page 4
Page 5
F3H
WDTREL
F4H
WDTWINB
BGH
F5H
WDTL
LINST
F6H
WDTH
FEAL
F7H
User’s Manual
Page 6
Page 7
BCON
F2H
BGL
FEAH
7-28
V1.1, 2010-09
XC83x
Watchdog Timer
8
Watchdog Timer
8.1
Overview
The Watchdog Timer (WDT) provides a highly reliable and secure way to detect and
recover from software or hardware failures. The WDT is reset at a regular interval that is
predefined by the user. The CPU must service the WDT within this interval to prevent the
WDT from causing an XC83x system reset. Hence, routine service of the WDT confirms
that the system is functioning properly. This ensures that an accidental malfunction of
the XC83x will be aborted in a user-specified time period.
The WDT is by default disabled.
In debug mode, the WDT is default suspended and stops counting (its debug suspend
bit is default set i.e., MODSUSP.WDTSUSP = 1. Therefore during debugging, there is
no need to refresh the WDT.
Features
•
•
•
•
16-bit Watchdog Timer
Programmable reload value for upper 8 bits of timer
Programmable window boundary
Input frequency from a secondary clock source of 75 kHz internal oscillator
User’s Manual
WDT, V1.0
8-1
V1.1, 2010-09
XC83x
Watchdog Timer
8.2
System Information
This section consist of the system information required to use the WDT.
8.2.1
Reset effects
The Watchdog Timer maintains a counter which must be refreshed or cleared
periodically. Otherwise, the counter will overflow and the watchdog reset will be
asserted. The occurrence of a WDT reset is indicated by the bit WDTRST in RSTCON
register. The bit field of
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
RSTCON register.
RSTCON
Reset Control Register
RMAP: 0, PAGE: 1
7
6
Reset Value: 00H1)
(F7H)
5
4
3
2
1
0
SWRQ
0
SOFTRS
WDTRST
WKRS
rwh
r
rwh
rwh
rwh
1) The reset value for watchdog timer reset is 02H.
Field
Bits
Type Description
WDTRST
1
rwh
Watchdog Timer Reset Indication Bit
0
No watchdog reset occurred.
1
Watchdog reset has occurred.
This bit can only be set by hadware and clear by
software.
0
[6:3]
r
Reserved
Returns 0 if read; should be written with 0.
8.2.2
Clocking Configuration
The WDT runs on the 75 kHz Oscillator.
8.2.3
Interrupt Events and Assignment
Table 1-1 shows the non-maskable interrupt node assignment of the WDT interrupt
source.
User’s Manual
WDT, V1.0
8-2
V1.1, 2010-09
XC83x
Watchdog Timer
Table 8-1
WDT Events’ Non-maskable Interrupt Node Control
Event
Interrupt Node
Enable Bit
Interrupt Node Flag Vector
Bit
Address
WDT Overflow
NMICON.NMIWDT
NMISR.FNMIWDT
8.2.4
73H
Module Suspend Control
The timer in WDT is by default suspended on entering debug mode. The WDT can be
allowed to run in debug mode by clearing the bit WDTSUSP in SFR MODSUSP to 0.
Refer to Chapter 10.2.4 for the definition of register MODSUSP.
8.3
Functional Description
The Watchdog Timer (WDT) is a 16-bit timer, which is incremented by a count rate of
75 kHz clock. This 16-bit timer is realized as two concatenated 8-bit timers. The upper 8
bits of the WDT can be preset to a user-programmable value via a watchdog service
access in order to vary the watchdog expire time. The lower 8 bits are reset on each
service access. Figure 8-1 shows the block diagram of the WDT unit.
WDT
Control
WDTREL
Clear
75 KHz
Oscillator
WDT Low Byte
Overflow/Time-out Control &
Window-boundary control
ENWDT
ENWDT_P
WDT High Byte
WDTTO
WDTRST
Logic
WINBCNT
Figure 8-1
WDT Block Diagram
If the WDT is enabled by setting WDTEN to 1, the timer is set to a user-defined start
value and begins counting up. It must be serviced before the counter overflows.
Servicing is performed through refresh operation (setting bit WDTRS to 1). This reloads
the timer with the start value, and normal operation continues.
User’s Manual
WDT, V1.0
8-3
V1.1, 2010-09
XC83x
Watchdog Timer
If the WDT is not serviced before the timer overflows, a system malfunction is assumed
and normal mode is terminated. A WDT NMI request (FNMIWDT) is then asserted and
prewarning is entered. The prewarning lasts for 30H count. During the prewarning period,
refreshing of the WDT is ignored and the WDT cannot be disabled. A reset (WDTRST)
of the XC83x is imminent and can no longer be avoided. The occurrence of a WDT reset
is indicated by the bit WDTRST in RSTCON register. If refresh happens at the same time
an overflow occurs, WDT will not go into prewarning period
The WDT must be serviced periodically so that its count value will not overflow. Servicing
the WDT clears the low byte and reloads the high byte with the preset value in bit field
WDTREL. Servicing the WDT also clears the bit WDTRS.
The WDT has a “programmable window boundary”, which disallows any refresh during
the WDT’s count-up. A refresh during this window-boundary constitutes an invalid
access to the WDT and causes the WDT to activate WDTRST, although no NMI request
is generated in this instance. The window boundary is from 0000H to the value obtained
from the concatenation of WDTWINB and 00H. This feature can be enabled by WINBEN.
After being serviced, the Watchdog Timer continues counting up from the value
(<WDTREL> * 28). The time period for an overflow of the Watchdog Timer is
programmable by the reload value, WDTREL. It is the high byte of WDT and can be
programmed in register WDTREL.
The period PWDT between servicing the WDT and the next overflow can be determined
by the following formula:
( 2 16 – WDTREL × 2 8 )
P WDT = ----------------------------------------------------------
(8.1)
f PCLK
If the Window-Boundary Refresh feature of the WDT is enabled, the period PWDT
between servicing the WDT and the next overflow is shortened if WDTWINB is greater
than WDTREL. See also Figure 8-2. This period can be calculated by the same formula
by replacing WDTREL with WDTWINB. In order for this feature to be useful, WDTWINB
cannot be smaller than WDTREL.
User’s Manual
WDT, V1.0
8-4
V1.1, 2010-09
XC83x
Watchdog Timer
Count
FFFF H
WDTWINB
WDTREL
time
No refresh
allowed
Figure 8-2
Refresh allowed
WDT Timing Diagram
Table 8-2 lists the possible ranges for the watchdog time which can be achieved using
a certain module clock. Some numbers are rounded to 3 significant digits.
Table 8-2
Watchdog Time Ranges
Reload Value in WDTREL
75 kHz Input frequency
FFH
3.4 ms
7FH
440 ms
00H
874 ms
Note: For safety reasons, the user is advised to rewrite WDTCON each time before the
WDT is serviced.
Note: The Watchdog Timer can be suspended when OCDS enters Monitor Mode and
has the Debug-Suspend signal activated, provided the respective suspend bit,
WDTSUSP in SFR MODSUSP, are set. See Module Suspend Control section.
User’s Manual
WDT, V1.0
8-5
V1.1, 2010-09
XC83x
Watchdog Timer
8.4
Registers Description
Five SFRs control the operations of the WDT. They can be accessed from the mapped
SFR area.
Table 8-3 lists the addresses of these SFRs.
Table 8-3
Register Map
Address
Page
Register
F6H
1
WDTCON
F3H
4
WDTREL
F4H
4
WDTWINB
F5H
4
WDTL
F6H
4
WDTH
8.4.1
Watchdog Timer Registers
The Watchdog Timer Current Count Value is contained in the Watchdog Timer Register
WDTH and WDTL, which are non-bitaddressable read-only register. The operation of the
WDT is controlled by its bitaddressable WDT Control Register WDTCON. This register
also selects the input clock prescaling factor. The register WDTREL specifies the reload
value for the high byte of the timer. WDTWINB specifies Watchdog Window-Boundary
count value.
WDTREL
Watchdog Timer Reload Register
RMAP: 0, PAGE: 4
7
6
5
(F3H)
4
Reset Value: 00H
3
2
1
0
WDTREL
rw
Field
Bits
Type Description
WDTREL
[7:0]
rw
User’s Manual
WDT, V1.0
Watchdog Timer Reload Value
(for the high byte of WDT)
8-6
V1.1, 2010-09
XC83x
Watchdog Timer
WDTCON
Watchdog Timer Control Register
RMAP: 0, PAGE: 1
7
6
(F6H)
Reset Value: 00H
5
4
3
2
1
0
0
WINBEN
WDTPR
0
WDTEN
WDTRS
0
r
rw
rh
r
rw
rwh
r
Field
Bits
Type Description
WDTRS
1
rwh
WDT Refresh Start
Active high. Set to start refresh operation on the
watchdog timer. Cleared automatically by hardware
after it is set by software.
WDTEN
2
rw
WDT Enable
0
WDT is disabled
1
WDT is enabled
WDTEN is a protected bit. If the Protection Scheme
is activated then this bit cannot be written directly.
See protection Scheme for more details..
Note: Clearing WDTEN bit to 0 during Prewarning
Mode (WDTPR = 1) has no effect.
WDTPR
4
rh
Watchdog Prewarning Mode Flag
0
Normal mode (default after reset)
1
The Watchdog is operating in Prewarning
Mode
This bit is set to 1 when a Watchdog error is
detected. The Watchdog Timer has issued an NMI
trap and is in Prewarning Mode. A reset of the chip
occurs after the prewarning period has expired.
WINBEN
5
rw
Watchdog Window-Boundary Enable
0
Watchdog Window-Boundary feature is
disabled. (default)
1
Watchdog Window-Boundary feature is
enabled.
0
0, 3,
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
WDT, V1.0
8-7
V1.1, 2010-09
XC83x
Watchdog Timer
WDTL
Watchdog Timer, Low Byte
RMAP: 0, PAGE: 4
7
6
(F5H)
5
4
Reset Value: 00H
3
2
1
0
WDT
rh
Field
Bits
Type Description
WDT
[7:0]
rh
Watchdog Timer Current Value
WDTH
Watchdog Timer, High Byte
RMAP: 0, PAGE: 4
7
6
(F6H)
5
4
Reset Value: 00H
3
2
1
0
WDT
rh
Field
Bits
Type Description
WDT
[7:0]
rh
Watchdog Timer Current Value
WDTWINB
Watchdog Window-Boundary Count (F4H)
RMAP: 0, PAGE: 4
7
6
5
4
Reset Value: 00H
3
2
1
0
WDTWINB
rw
User’s Manual
WDT, V1.0
8-8
V1.1, 2010-09
XC83x
Watchdog Timer
Field
Bits
Type Description
WDTWINB
[7:0]
rw
User’s Manual
WDT, V1.0
Watchdog Window-Boundary Count Value
This value is programmable. Within this WindowBoundary range from 0000H to (WDTWINB, 00H),
the WDT cannot do a Refresh, else it will cause a
WDTRST to be asserted.
WDTWINB is matched to WDTH.
8-9
V1.1, 2010-09
XC83x
Interrupt System
9
Interrupt System
The XC800 Core supports one non-maskable interrupt (NMI) and 14 maskable interrupt
requests. In addition to the standard interrupt functions supported by the core, e.g.,
configurable interrupt priority and interrupt masking, the XC83x interrupt system
provides extended interrupt support capabilities such as the mapping of each interrupt
vector to several interrupt sources to increase the number of interrupt sources
supported, and additional status registers for detecting and identifying the interrupt
source.
9.1
Interrupt Sources
The XC83x supports 14 interrupt vectors with four priority levels. Ten of these interrupt
vectors are assigned to the on-chip peripherals: Timer 0, Timer 1, UART and SSC are
each assigned one dedicated interrupt vector; while Timer 2, A/D Converter, LIN,
LEDTSCU, Port 1 HCPADA and the Capture/Compare Unit share six interrupt vectors.
In addition, four interrupt vectors are assigned to the external interrupts, MDU, CORDIC,
RTC and IIC. External interrupts 0 to 1 are each assigned one dedicated interrupt vector.
External interrupt 2 is shared with MDU, CORDIC and IIC. RTC and External interrupt
[6:3] share the same interrupt vector.
A non-maskable interrupt (NMI) with the highest priority is shared by the following:
•
•
•
•
•
•
•
•
Watchdog Timer, warning before overflow
48 MHz and 75 kHz Oscillators, loss of oscillator clock
32.768 kHz XTAL Oscillator, loss of XTAL clock
Flash Timer, on operation complete e.g. erase.
OCDS, on user IRAM event
Flash ECC error
VDDP prewarning
VDDC prewarning
Figure 9-1, Figure 9-2, Figure 9-3, Figure 9-4 and Figure 9-5 give a general overview
of the interrupt sources and nodes, and their corresponding control and status flags.
Figure 9-6 gives the corresponding overview for the NMI sources.
User’s Manual
Interrupt System, V 2.3.3
9-1
V1.1, 2010-09
XC83x
Interrupt System
Highest
Timer 0
Overflow
TF0
TCON.5
ET0
000B
H
IEN0.1
Timer 1
Overflow
Lowest
Priority Level
IP.1/
IPH.1
TF1
TCON.7
ET1
001B
H
IEN0.3
UART
Receive
IP.3/
IPH.3
RI
SCON.0
UART
Transmit
>=1
TI
ES
SCON.1
IEN0.4
0023
H
IP.4/
IPH.4
IE0
EINT0
P
o
l
l
i
n
g
TCON.1
IT0
EX0
0003
H
IEN0.0
TCON.0
S
e
q
u
e
n
c
e
IP.0/
IPH.0
EXINT0
EXICON0.0/1
IE1
EINT1
TCON.3
IT1
EX1
0013
H
IEN0.2
TCON.2
EXINT1
IP.2/
IPH.2
EA
EXICON0.2/3
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 9-1
Interrupt Request Sources (Part 1)
User’s Manual
Interrupt System, V 2.3.3
9-2
V1.1, 2010-09
XC83x
Interrupt System
Highest
Timer 2
Overflow
TF2
T2_T2CON.7
T2EX
Lowest
Priority Level
TF2EN
T2_T2CON1.1
>=1
EXF2
EXEN2 T2_T2CON.6
EXF2EN
T2_T2CON1.0
T2_T2CON.3
EDGES
EL
T2_T2MOD.5
>=1
ET2
End of
Synch Byte
EOFSYN
H
IP.5/
IPH.5
>=1
LINST.4
ERRSYN
Synch Byte
Error
002B
IEN0.5
SYNEN
LINST.5
LINST.6
ADC Service
Request 0
ADCSR0
ADC Service
Request 1
ADCSR1
EADC
IRCON1.4
IEN1.0
IRCON1.3
>=1
0033
H
IP1.0/
IPH1.0
P
o
l
l
i
n
g
S
e
q
u
e
n
c
e
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 9-2
Interrupt Request Sources (Part 2)
User’s Manual
Interrupt System, V 2.3.3
9-3
V1.1, 2010-09
XC83x
Interrupt System
Highest
SSC_EIR
EIR
Lowest
Priority Level
EIREN
IRCON1.0
MODIEN.0
SSC_TIR
>=1
TIR
IRCON1.1
TIREN
MODIEN.1
ESSC
RIR
SSC_RIR
003B
H
IEN1.1
IRCON1.2
IP1.1/
IPH1.1
RIREN
MODIEN.2
P
o
l
l
i
n
g
EXINT2
EINT2
IRCON0.2
EXINT2
EXICON0.4/5
MDU_0
IRDY
EX2
IE
MDUSTAT.0
H
IP1.2/
IPH1.2
>=1
MDU_1
IERR
IE
MDUSTAT.1
CORDIC
MDUCON.7
EOC
CD_STATC.2
IIC
0043
IEN1.2
MDUCON.7
S
e
q
u
e
n
c
e
INT_ EN
CD_STATC.3
IFLG
IIC_CNTR.3
IEN
IIC_CNTR.7
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 9-3
Interrupt Request Sources (Part 3)
User’s Manual
Interrupt System, V 2.3.3
9-4
V1.1, 2010-09
XC83x
Interrupt System
Highest
Lowest
Priority Level
EXINT3
EINT3
IRCON0.3
EXINT3
EXICON0.6/7
EXINT4
EINT4
IRCON0.4
EXINT3
EXICON1.0/1
EXM
EXINT5
EINT5
>=1
004B
H
IEN1.3
IRCON0.5
S
e
q
u
e
n
c
e
EXINT5
EXICON1.2/3
RTC
Compare/
Wakeup
CFRTC
RTCON.6
ECRTC
RTCON.4
RTC
SEC_TIME
IP1.3/
IPH1.3
P
o
l
l
i
n
g
>=1
SFRTC
RTCON.7
ESRTC
RTCON.5
EA
IEN0.7
Bit-addressable
Request flag is cleared by hardware
Figure 9-4
Interrupt Request Sources (Part 4)
User’s Manual
Interrupt System, V 2.3.3
9-5
V1.1, 2010-09
XC83x
Interrupt System
Highest
Lowest
CCU6SR0
CCU6 Node 0
IRCON2.0
ECCIP0
0053
Priority Level
H
IEN1.4
IP1.4/
IPH1.4
CCU6SR1
CCU6 Node 1
IRCON2.4
>=1
LED/TS
Time-frame
TFF
ECCIP1
GLOBCTL1.5
ITF_EN
005 B
H
IEN1.5
GLOBCTL1.4
P1.0
Overcurrent
IP1.5/
IPH1.5
P0_OCF
P1_OCD.0
P0_OCEN
P
o
l
l
i
n
g
P1_OCD.4
P1.1
Overcurrent
P1.2
Overcurrent
P1_OCF
P1_OCD.1
P1_OCEN
P1_OCD.5
>=1
P2_OCF
P1_OCD.2
>=1
P2_OCEN
P1_OCD.6
P1.3
Overcurrent
P3_OCF
P1_OCD.3
P3_OCEN
ECCIP2
P1_OCD.7
0063
H
IEN1.6
CCU6 Node 2
IP1.6/
IPH1.6
CCU6SR2
IRCON3.0
CCU6
SR2EN
S
e
q
u
e
n
c
e
MODIEN.6
CCU6 Node 3
CCU6SR3
CCU6
SR3 EN
IRCON3.4
LED/TS
Time-slice
>=1
MODIEN.7
ECCIP3
TSF
GLOBCTL1.7
IEN1.7
ITS_EN
GLOBCTL1.6
006B
H
IEN0.7
EA
IP1.7/
IPH1.7
Bit-addressable
Request flag is cleared by hardware
Figure 9-5
Interrupt Request Sources (Part 5)
User’s Manual
Interrupt System, V 2.3.3
9-6
V1.1, 2010-09
XC83x
Interrupt System
WDT Overflow
FNMIWDT
NMISR.0
NMIWDT
NMICON.0
48MHz or 75KHz
Loss-of-clock
FNMIOSCCLK
NMISR.1
NMIOSCCLK
NMICON.1
FNMIFLASH
Flash
NMISR.2
NMIFLASH
NMICON.2
IRAM read
event *
FNMIRR
MMICR.2
NMIRRE
MMICR.0
IRAM write
event *
>=1
FNMIOCDS
NMISR.3
FNMIRW
MMICR.3
NMIOCDS
NMICON.3
NMIRWE
MMICR.1
VDDC Prewarning
>=1
0073
H
Non
Maskable
Interrupt
FNMIVDDC
NMISR.4
NMIVDD
NMICON.4
VDDP Prewarning
FNMIVDDP
NMISR.5
NMIVDDP
NMICON.5
Flash ECC Error
FNMIECC
NMISR.6
NMIECC
NMICON.6
32.768 KHz
Loss-of-clock
FNMIXTALCLK
NMISR.7
NMIXTALCLK
NMICON.7
Figure 9-6
Non-Maskable Interrupt Request Source
User’s Manual
Interrupt System, V 2.3.3
9-7
V1.1, 2010-09
XC83x
Interrupt System
9.1.1
Interrupt Source and Vector
Each interrupt event source has an associated interrupt vector address for the interrupt
node it belongs to. This vector is accessed to service the corresponding interrupt node
request. The interrupt service of each interrupt node can be individually enabled or
disabled via an enable bit. The assignment of the XC83x interrupt sources to the
interrupt vector address and the corresponding interrupt node enable bits are
summarized in Table 9-1.
Table 9-1
Interrupt Vector Address
Interrupt
Node
Vector
Address
Assignment for XC83x
Enable Bit
SFR
NMI
0073H
Watchdog Timer NMI
NMIWDT
NMICON
48 MHz and 75 kHz clock NMI NMIOSCCLK
32.768 kHz XTAL clock NMI
NMIXTALCLK
Flash Operation Complete
NMI
NMIFLASH
OCDS NMI
NMIOCDS
ECC Error NMI
NMIECC
VDDP Prewarning NMI
NMIVDDP
VDDC Prewarning NMI
NMIVDDC
XINTR0
0003H
External Interrupt 0
EX0
XINTR1
000BH
Timer 0
ET0
XINTR2
0013H
External Interrupt 1
EX1
XINTR3
001BH
Timer 1
ET1
XINTR4
0023H
UART
ES
XINTR5
002BH
Timer2
ET2
IEN0
LIN
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Interrupt System, V 2.3.3
9-8
V1.1, 2010-09
XC83x
Interrupt System
Table 9-1
Interrupt Vector Address (cont’d)
Interrupt
Node
Vector
Address
Assignment for XC83x
Enable Bit
SFR
XINTR6
0033H
ADC
EADC
IEN1
XINTR7
003BH
SSC
ESSC
XINTR8
0043H
External Interrupt 2
EX2
CORDIC
MDU
IIC
XINTR9
004BH
External Interrupt 3
EXM
External Interrupt 4
External Interrupt 5
External Interrupt 6
RTC Interrupt
XINTR10
0053H
CCU6 SR0
ECCIP0
XINTR11
005BH
CCU6 SR1
ECCIP1
LEDTSCU Time Frame
XINTR12
0063H
CCU6 SR2
ECCIP2
Port 1 HCPADA
XINTR13
006BH
CCU6 SR3
ECCIP3
LEDTSCU Time Slice
9.1.2
Interrupt Source and Priority
An interrupt that is currently being serviced can only be interrupted by a higher-priority
interrupt, but not by another interrupt of the same or lower priority. Hence, an interrupt of
the highest priority cannot be interrupted by any other interrupt request.
If two or more requests of different priority levels are received simultaneously, the
request with the highest priority is serviced first. If requests of the same priority are
received simultaneously, an internal polling sequence determines which request is
serviced first. Thus, within each priority level, there is a second priority structure
determined by the polling sequence as shown in Table 9-2.
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XC83x
Interrupt System
Table 9-2
Priority Structure within Interrupt Level
Source
Level
Non-maskable Interrupt (NMI)
(highest)
External Interrupt 0
1
Timer 0
2
External Interrupt 1
3
Timer 1
4
UART
5
Timer 2 / LIN
6
A/D Converter and ORC
7
SSC
8
External Interrupt 2 / CORDIC / MDU / IIC
9
EXINT[6:3] / Real-time clock
10
CCU6 Interrupt Node Pointer 0
11
CCU6 Interrupt Node Pointer 1 / LED and Touch-sense
12
CCU6 Interrupt Node Pointer 2 / Port 1 HCPADA
13
CCU6 Interrupt Node Pointer 3 / LED and Touch-sense
14
9.2
Interrupt Structure
An interrupt event source may be generated from the on-chip peripherals or from
external. Detection of interrupt events is controlled by the respective on-chip peripherals.
Interrupt status flags are available for determining which interrupt event has occurred,
especially useful for an interrupt node which is shared by several event sources. Each
interrupt node (except NMI) has a global enable/disable bit. In most cases, additional
enable bits are provided for enabling/disabling particular interrupt events (provided for
NMI events). No interrupt will be requested for any occurred event that has its interrupt
enable bit disabled.
The XC83x has, in general, two interrupt structures distinguished mainly by the manner
in which the pending interrupt request (one per interrupt vector/node going directly to the
core) is generated (due to the events) and cleared.
Common among these two interrupt structures is the interrupt masking bit, EA, which is
used to globally enable or disable all interrupt requests (except NMI) to the core.
Resetting bit EA to 0 only masks the pending interrupt requests from the core, but does
not block the capture of incoming interrupt requests.
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Interrupt System
Note: The NMI node is similar to the other interrupt nodes, except for the exclusion of
EA bit. Effectively, NMI node is non-maskable.
9.2.1
Interrupt Structure 1
For interrupt structure 1 (see Figure 9-7), the interrupt event will set the interrupt status
flag which doubles as a pending interrupt request to the core. An active pending interrupt
request will interrupt the core only if its corresponding interrupt node is enabled. Once
an interrupt node is serviced (interrupt acknowledged), its pending interrupt request
(represented by the interrupt status flag) may be automatically cleared by hardware (the
core).
interrupt
acknowledge
(from core)
software
clear
interrupt
event
set
pending
interrupt
request
clear
interrupt status
flag
interrupt node
enable bit
AND
to core
EA bit
Figure 9-7
Interrupt Structure 1
For the XC83x, interrupt sources Timer 0, Timer 1, external interrupt 0 and external
interrupt 1 (each have a dedicated interrupt node) will have their respective interrupt
status flags TF0, TF1, IE0 and IE1 in register TCON cleared by the core once their
corresponding pending interrupt request is serviced. In the case that an interrupt node is
disabled (e.g. software polling is used), its interrupt status flag must be cleared by
software since the core will not be interrupted (and therefore the interrupt acknowledge
is not generated). For the UART which has its dedicated interrupt node, interrupt status
flags RI and TI in register SCON will not be cleared by the core even when its pending
interrupt request is serviced. The UART interrupt status flags (and hence the pending
interrupt request) can only be cleared by software.
9.2.2
Interrupt Structure 2
This structure applies to the Timer 2, LIN, external interrupts 2 to 6, ADC, SSC, IIC, RTC,
LEDTSCU, Port 1 HCPADA, CCU6, CORDIC and MDU interrupt sources. For interrupt
structure 2 (see Figure 9-8), the interrupt status flag does not directly drive the pending
interrupt request.
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XC83x
Interrupt System
All qualified flags of the
interrupt node
Corresponding
event status
flag
NOR
Event interrupt request
Event
occurrence
Corresponding
event interrupt
enable bit
clear
AND
interrupt node
enable bit
set/clear
FF*
pending
interrupt
request
AND
* Implemented as latch, cannot set by software
Figure 9-8
interrupt
acknowledge
(from core)
OR
to core
EA bit
Interrupt Structure 2
An event generated by its corresponding interrupt source will set the status flag, and in
parallel, if the event is enabled for interrupt, activate the pending interrupt request.
Consider the case where interrupt event occurred while its interrupt node was disabled
(assume global interrupt enable EA is set). When the interrupt node is enabled later,
previously activated pending interrupt request will now cause an active interrupt request
to the core. Note for the special case of NMI node, that it is essentially non-maskable.
An active pending interrupt request interrupts the core and is automatically cleared by
hardware (the core) once the interrupt node is serviced (interrupt acknowledged); the
status flag remains set and must be cleared by software. A pending interrupt request can
also be cleared by software: only on clearing all interrupt-enabled status flags of the
node will indirectly clear its pending interrupt request. Note that this is not exactly like
interrupt structure 1 where the pending interrupt request is cleared directly by resetting
the node’s interrupt status flags.
In summary, the following lists in descending order the priority handling of pending
interrupt request for interrupt nodes of structure 2: 1) CPU acknowledge of interrupt on
vectoring to the service routine will clear the pending interrupt request, 2) Any event
occurring and enabled for interrupt will set the pending interrupt request, 3) on clearing
of all interrupt-enabled status flags will clear the pending interrupt request.
9.3
Interrupt Handling
The interrupt request signals are sampled at phase 2 in each machine cycle. The
sampled requests are then polled during the following machine cycle. If one interrupt
node request was active at phase 2 of the preceding cycle, the polling cycle will find it
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Interrupt System
and the interrupt system will generate a LCALL to the node’s service routine, provided
this hardware-generated LCALL is not blocked by any of the following conditions:
1. An interrupt of equal or higher priority is already in progress.
2. The current (polling) cycle is not in the final cycle of the instruction in progress.
3. The instruction in progress is RETI or any write access to registers IEN0/IEN1 or
IP/IPH or IP1/IPH1.
Any of these three conditions will block the generation of the LCALL to the interrupt
service routine. Condition 2 ensures that the instruction in progress is completed before
vectoring to any service routine. Condition 3 ensures that if the instruction in progress is
RETI or any write access to registers IEN0/IEN1 or IP/IPH or IP1/IPH1, then at least one
more instruction will be executed before any interrupt is vectored to; this delay
guarantees that changes of the interrupt status can be observed by the CPU.
The polling cycle is repeated with each machine cycle, and the values polled are the
values that were present at phase 2 of the previous machine cycle. Note that if any
interrupt flag is active but its node interrupt request was not responded to for one of the
conditions already mentioned, and if the flag is no longer active at a later time when
servicing the interrupt node, the corresponding interrupt source will not be serviced. In
other words, the fact that the interrupt flag was once active but not serviced is not
remembered. Every polling cycle interrogates only the pending interrupt requests.
The processor acknowledges an interrupt request by executing a hardware generated
LCALL to the corresponding service routine. In some cases, hardware also clears the
flag that generated the interrupt, while in other cases, the flag must be cleared by the
user’s software. The hardware-generated LCALL pushes the contents of the Program
Counter (PC) onto the stack (but it does not save the PSW) and reloads the PC with an
address that depends on the interrupt node being vectored to, as shown in the
Table 9-1.
Program execution returns to the next instruction after calling the interrupt when the
RETI instruction is encountered. The RETI instruction informs the processor that the
interrupt routine is no longer in progress, then pops the two top bytes from the stack and
reloads the PC. Execution of the interrupted program continues from the point where it
was stopped. Note that the RETI instruction is important because it informs the
processor that the program has left the current interrupt priority level. A simple RET
instruction would also have returned execution to the interrupted program, but it would
have left the interrupt control system on the assumption that an interrupt was still in
progress. In this case, no interrupt of the same or lower priority level would be
acknowledged.
9.4
Interrupt Response Time
Due to an interrupt event of (the various sources of) an interrupt node, its corresponding
request signal will be sampled active at phase 2 in every machine cycle. The value is not
polled by the circuitry until the next machine cycle. If the request is active and conditions
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Interrupt System
are right for it to be acknowledged, a hardware subroutine call to the requested service
routine will be the next instruction to be executed. The call itself takes two machine
cycles. Thus, a minimum of three complete machine cycles will elapse from activation of
the interrupt request to the beginning of execution of the first instruction of the service
routine as shown in Figure 9-9.
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
fCCLK
Interrupt
request
active/sampled
Interrupt request
polled
(last cycle of
current
instruction)
LCALL
1st instruction at
interrupt vector
Interrupt response time = 3 x machine cycle
Figure 9-9
Minimum Interrupt Response Time
A longer response time would be obtained if the request is blocked by one of the three
previously listed conditions:
1. If an interrupt of equal or higher priority is already in progress, the additional wait time
will depend on the nature of the other interrupt's service routine.
2. If the instruction in progress is not in its final cycle, the additional wait time cannot be
more than three machine cycles since the longest instructions (MUL and DIV) are
only four machine cycles long. See Figure 9-10.
3. If the instruction in progress is RETI or a write access to registers IEN0, IEN1 or
IP(H), IP1(H), the additional wait time cannot be more than five cycles (a maximum
of one more machine cycle to complete the instruction in progress, plus four machine
cycles to complete the next instruction, if the instruction is MUL or DIV). See
Figure 9-11.
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Interrupt System
P1
P2
P1
P2
P1
P2
P1
P2
P1
P1
P2
P2
P1
P2
P1
P2
fCCLK
4-cycle current instruction
(MUL or DIV)
Interrupt
request
sampled active
Interrupt
request
sampled
Interrupt
request
polled
(last cycle of
current
instruction)
1st instruction at
interrupt vector
LCALL
Interrupt response time = 6 x machine cycle
Figure 9-10 Interrupt Response Time for Condition 2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
P1
P2
fCCLK
Interrupt
request
sampled active
2-cycle current instruction
Interrupt
request
sampled
Interrupt request
polled
(RETI or write
access to interrupt
registers)
4-cycle next instruction
(MUL or DIV)
Interrupt
request
sampled
Interrupt request
polled
(last cycle of
current
instruction)
LCALL
1st instruction at
interrupt vector
Interrupt response time = 8 x machine cycle
Figure 9-11 Interrupt Response Time for Condition 3
Thus in a single interrupt system, the response time is always more than three machine
cycles and less than nine machine cycles (wait states are not considered). When
considering wait states, the interrupt response time will be extended depending on the
user instructions (also the hardware generated LCALL) being executed during the
interrupt response time (shaded region in Figure 9-10 and Figure 9-11).
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XC83x
Interrupt System
9.5
Registers Description
Interrupt Special Function Registers or bits are used for interrupt configuration such as
node enable, external interrupt control, interrupt flags and interrupt priority setting.
Table 9-3 lists the SFRs and corresponding address.
Table 9-3
Register Map
Address
Register
RMAP = 0 or 1
A8H
IEN0
E8H
IEN1
B8H
IP
B9H
IPH
F8H
IP1
F9H
IPH1
88H
TCON
98H
SCON
RMAP = 0
EEH (SCU page 0)
NMICON
EFH (SCU page 0)
EXICON0
F4H (SCU page 0)
EXICON1
F4H (SCU page 3)
MODPISEL1
F2H (SCU page 0)
IRCON0
F3H (SCU page 0)
IRCON1
F5H (SCU page 0)
IRCON2
F6H (SCU page 0)
IRCON3
F7H (SCU page 0)
NMISR
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9.5.1
Interrupt Node Enable Registers
Each interrupt node can be individually enabled or disabled by setting or clearing the
corresponding bit in the interrupt enable registers IEN0 and IEN1. Register IEN0 also
contains the global interrupt masking bit (EA), which can be cleared to block all pending
interrupt requests at once.
The NMI interrupt vector is shared by a number of sources, each of which can be
enabled or disabled individually via register NMICON.
After reset, the enable bits in IEN0, IEN1 and NMICON are cleared to 0. This implies that
all interrupt nodes are disabled by default.
IEN0
Interrupt Enable Register 0
RMAP: X, PAGE: X
(A8H)
Reset Value: 00H
7
6
5
4
3
2
1
0
EA
0
ET2
ES
ET1
EX1
ET0
EX0
rw
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
EX0
0
rw
Interrupt Node XINTR0 Enable
0
XINTR0 is disabled
1
XINTR0 is enabled
ET0
1
rw
Interrupt Node XINTR1 Enable
0
XINTR1 is disabled
1
XINTR1 is enabled
EX1
2
rw
Interrupt Node XINTR2 Enable
0
XINTR2 is disabled
1
XINTR2 is enabled
ET1
3
rw
Interrupt Node XINTR3 Enable
0
XINTR3 is disabled
1
XINTR3 is enabled
ES
4
rw
Interrupt Node XINTR4 Enable
0
XINTR4 is disabled
1
XINTR4 is enabled
ET2
5
rw
Interrupt Node XINTR5 Enable
0
XINTR5 is disabled
1
XINTR5 is enabled
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Interrupt System
Field
Bits
Type Description
EA
7
rw
Global Interrupt Mask
0
All pending interrupt requests (except NMI)
are blocked from the core.
1
Pending interrupt requests are not blocked
from the core.
0
6
r
Reserved
Returns 0 if read; should be written with 0.
IEN1
Interrupt Enable Register 1
RMAP: X, PAGE: X
(E8H)
Reset Value: 00H
7
6
5
4
3
2
1
0
ECCIP3
ECCIP2
ECCIP1
ECCIP0
EXM
EX2
ESSC
EADC
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
EADC
0
rw
Interrupt Node XINTR6 Enable
0
XINTR6 is disabled
1
XINTR6 is enabled
ESSC
1
rw
Interrupt Node XINTR7 Enable
0
XINTR7 is disabled
1
XINTR7 is enabled
EX2
2
rw
Interrupt Node XINTR8 Enable
0
XINTR8 is disabled
1
XINTR8 is enabled
EXM
3
rw
Interrupt Node XINTR9 Enable
0
XINTR9 is disabled
1
XINTR9 is enabled
ECCIP0
4
rw
Interrupt Node XINTR10 Enable
0
XINTR10 is disabled
1
XINTR10 is enabled
ECCIP1
5
rw
Interrupt Node XINTR11 Enable
0
XINTR11 is disabled
1
XINTR11 is enabled
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XC83x
Interrupt System
Field
Bits
Type Description
ECCIP2
6
rw
Interrupt Node XINTR12 Enable
0
XINTR12 is disabled
1
XINTR12 is enabled
ECCIP3
7
rw
Interrupt Node XINTR13 Enable
0
XINTR13 is disabled
1
XINTR13 is enabled
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
NMICON register.
NMICON
NMI Control Register
RMAP: 0, PAGE: 0
7
6
NMIXTALCLK
NMIECC
rw
rw
(EEH)
5
4
Reset Value: 00H
3
NMIVDDP NMIVDDC NMIOCDS
rw
rw
rw
2
1
0
NMIFLASH
NMIOSCCLK
NMIWDT
rw
rw
rw
Field
Bits
Type Description
NMIWDT
0
rw
Watchdog Timer NMI Enable
0
WDT NMI is disabled.
1
WDT NMI is enabled.
NMIOSCCLK
1
rw
Loss of 48 MHz or 75 kHz Oscillator Clock NMI
Enable
0
Loss of 48 MHz or 75 kHz Oscillator Clock
NMI is disabled.
1
Loss of 48 MHz or 75 kHz Oscillator Clock
NMI is enabled.
NMIFLASH
2
rw
Flash NMI Enable
0
Flash Timer NMI is disabled.
1
Flash Timer NMI is enabled.
NMIOCDS
3
rw
OCDS NMI Enable
0
OCDS NMI is disabled.
1
OCDS NMI is enabled.
NMIVDDC
4
rw
VDDC Prewarning NMI Enable
0
VDDC prewarning NMI is disabled.
1
VDDC prewarning NMI is enabled.
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XC83x
Interrupt System
Field
Bits
Type Description
NMIVDDP
5
rw
VDDP Prewarning NMI Enable
0
VDDP prewarning NMI is disabled.
1
VDDP prewarning NMI is enabled.
NMIECC
6
rw
ECC Error NMI Enable
0
ECC Error NMI is disabled.
1
ECC Error NMI is enabled.
NMIXTALCLK
7
rw
Loss of 32.768 kHz XTAL Clock NMI Enable
0
Loss of 32.768 kHz XTAL clock NMI is
disabled.
1
Loss of 32.768 kHz XTAL clock NMI is
enabled.
Note: When the external power supply is 3.3 V or below, the user must disable
NMIVDDP.
9.5.2
External Interrupt Control Registers
The seven external interrupts, EXT_INT[6:0], are driven into the XC83x from the ports.
The external exterrupt pin assignment for XC83x is shown in Table 9-4. External
interrupts can be positive, negative or double edge triggered. Registers EXICON0 and
EXICON1 specify the active edge for the external interrupt. Among the external
interrupts, external interrupt 0 and external interrupt 1 can be selected to bypass edge
detection in the SCU, for direct feed-through to the core. This signal to the core can be
further programmed to either low-level or negative transition activated, by the bits IT0
and IT1 in the TCON register. However for edge detection in SCU, TCON.IT0/1 must be
set to falling edge triggered. An active edge event detected in SCU will generate
internally two CCLK cycle low pulse for detection by core.
If the external interrupt is positive (negative) edge triggered, the external source must
hold the request pin low (high) for at least one CCLK cycle, and then hold it high (low)
for at least one CCLK cycle to ensure that the transition is recognized. If edge detection
is bypassed for external interrupt 0 and external interrupt 1, the external source must
hold the request pin “high” or “low” for at least two CCLK cycles.
External interrupts 2 to 6 share their interrupt node with other interrupt sources.
Therefore in addition to the corresponding interrupt node enable, each external interrupt
2 to 6 may be disabled individually, and are disabled by default after reset.
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Interrupt System
Table 9-4
External interrupt [6:0] Pin Functions and Selection
Pin
Function
Desciption
Selected By
P0.5
EXINT0_0
External Interrupt Input 0
MODPISEL1.EXINT0IS = 000B
P0.6
EXINT0_1
MODPISEL1.EXINT0IS = 001B
P1.0
EXINT0_2
MODPISEL1.EXINT0IS = 010B
P2.0
EXINT0_3
MODPISEL1.EXINT0IS = 011B
P2.7
EXINT0_4
MODPISEL1.EXINT0IS = 100B
P3.1
EXINT0_5
MODPISEL1.EXINT0IS = 101B
P3.2
EXINT0_6
P0.4
EXINT1_0
P2.1
EXINT1_1
MODPISEL1.EXINT0IS = 110B
External Interrupt Input 1
MODPISEL1.EXINT1IS = 0B
MODPISEL1.EXINT1IS = 1B
P2.2
EXINT2_0
P3.0
EXINT2_1
External Interrupt Input 2
MODPISEL1.EXINT2IS = 0B
P2.3
EXINT3
External Interrupt Input 3
–
P1.2
EXINT4
External Interrupt Input 4
–
P1.4
EXINT5
External Interrupt Input 5
–
P2.6
EXINT5
External Interrupt Input 6
–
MODPISEL1.EXINT2IS = 1B
The bit field PAGE of SCU_PAGE register must be programmed before accessing
EXICON0, EXICON1 and MODPISEL1 registers.
Note: Several external interrupts support alternative input pin. When switching inputs,
the active edge/level trigger select and the level on the associated pins should be
considered to prevent unintentional interrupt generation.
EXICON0
External Interrupt Control Register 0 (EFH)
RMAP: 0, PAGE: 0
7
6
5
4
Reset Value: F0H
3
2
1
0
EXINT3
EXINT2
EXINT1
EXINT0
rw
rw
rw
rw
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Interrupt System
Field
Bits
Type Description
EXINT0
1:0
rw
External Interrupt 0 Trigger Select
00
Interrupt on falling edge.
01
Interrupt on rising edge.
10
Interrupt on both rising and falling edge.
11
Bypass the edge detection in SCU. The input
signal directly feeds to the core.
EXINT1
3:2
rw
External Interrupt 1 Trigger Select
00
Interrupt on falling edge.
01
Interrupt on rising edge.
10
Interrupt on both rising and falling edge.
11
Bypass the edge detection in SCU. The input
signal directly feeds to the core.
EXINT2
5:4
rw
External Interrupt 2 Trigger Select
00
Interrupt on falling edge.
01
Interrupt on rising edge.
10
Interrupt on both rising and falling edge.
11
External interrupt 2 is disabled.
EXINT3
7:6
rw
External Interrupt 3 Trigger Select
00
Interrupt on falling edge.
01
Interrupt on rising edge.
10
Interrupt on both rising and falling edge.
11
External interrupt 3 is disabled.
EXICON1
External Interrupt Control Register 1 (F4H)
RMAP: 0, PAGE: 0
7
6
5
4
Reset Value: 3FH
3
2
1
0
0
EXINT6
EXINT5
EXINT4
r
rw
rw
rw
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XC83x
Interrupt System
Field
Bits
Type Description
EXINT4
1:0
rw
External Interrupt 4 Trigger Select
00
Interrupt on falling edge.
01
Interrupt on rising edge.
10
Interrupt on both rising and falling edge.
11
External interrupt 4 is disabled.
EXINT5
3:2
rw
External Interrupt 5 Trigger Select
00
Interrupt on falling edge.
01
Interrupt on rising edge.
10
Interrupt on both rising and falling edge.
11
External interrupt 5 is disabled.
EXINT6
5:4
rw
External Interrupt 6 Trigger Select
00
Interrupt on falling edge.
01
Interrupt on rising edge.
10
Interrupt on both rising and falling edge.
11
External interrupt 6 is disabled.
0
7:6
r
Reserved
Returns 0 if read; should be written with 0.
MODPISEL1
Peripheral Input Select Register 1
RMAP: 0, PAGE: 3
7
6
EXINT2IS0 EXINT1IS
rw
rw
User’s Manual
Interrupt System, V 2.3.3
5
(F4H)
4
Reset Value: 00H
3
2
1
EXINT0IS
URRIS
rw
rw
9-23
0
V1.1, 2010-09
XC83x
Interrupt System
Field
Bits
Type Description
EXINT0IS
[5:3]
rw
External Interrupt Input 0 Input Select
000 External Interrupt Input EXINT0_0 is selected.
001 External Interrupt Input EXINT0_1 is selected.
010 External Interrupt Input EXINT0_2 is selected.
011 External Interrupt Input EXINT0_3 is selected.
100 External Interrupt Input EXINT0_4 is selected.
101 External Interrupt Input EXINT0_5 is selected.
110 External Interrupt Input EXINT0_6 is selected.
111 Unused.
EXINT1IS
6
rw
External Interrupt 1 Input Select
0
External Interrupt Input EXINT1_0 is selected.
1
External Interrupt Input EXINT1_1 is selected.
EXINT2IS
7
rw
External Interrupt 2 Input Select
0
External Interrupt Input EXINT2_0 is selected.
1
External Interrupt Input EXINT2_1 is selected.
TCON
Timer and Counter Control/Status Register(88H)
RMAP: X, PAGE: X
Reset Value: 00H
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
rwh
rw
rwh
rw
rwh
rw
rwh
rw
Field
Bits
Type Description
IT0
0
rw
External Interrupt 0 Level/Edge Trigger Control
0
Low level triggered external interrupt 0 is
selected
1
Falling edge triggered external interrupt 0 is
selected
IT1
2
rw
External Interrupt 1 Level/Edge Trigger Control
0
Low level triggered external interrupt 1 is
selected
1
Falling edge triggered external interrupt 1 is
selected
User’s Manual
Interrupt System, V 2.3.3
9-24
V1.1, 2010-09
XC83x
Interrupt System
9.5.3
Interrupt Flag Registers
The interrupt flags for the different interrupt sources are located in several Special
Function Registers. In case of software and hardware access to a flag bit at the same
time, hardware will have higher priority. The bit field PAGE of SCU_PAGE register must
be programmed before accessing IRCONx and NMISR register.
IRCON0
Interrupt Request Register 0
RMAP: 0, PAGE: 0
(F2H)
Reset Value: 00H
7
6
5
4
3
2
1
0
0
EXINT6
EXINT5
EXINT4
EXINT3
EXINT2
0
r
rwh
rwh
rwh
rwh
rwh
r
Field
Bits
Type Description
EXINTx
(x = 2 - 6)
[6:2]
rwh
Interrupt Flag for External Interrupt x
This bit is set by hardware and can only be cleared
by software.
0
Interrupt event has not occurred.
1
Interrupt event has occurred.
0
[1:0], 7
r
Reserved
Returns 0 if read; Should be written with 0.
IRCON1
Interrupt Request Register 1
RMAP: 0, PAGE: 0
7
6
Reset Value: 00H
4
3
2
1
0
0
ADCSR1
ADCSR0
RIR
TIR
EIR
r
rwh
rwh
rwh
rwh
rwh
User’s Manual
Interrupt System, V 2.3.3
5
(F3H)
9-25
V1.1, 2010-09
XC83x
Interrupt System
Field
Bits
Type Description
EIR
0
rwh
Error Interrupt Flag for SSC
This bit is set by hardware and can only be cleared
by software.
0
Interrupt event has not occurred.
1
Interrupt event has occurred.
TIR
1
rwh
Transmit Interrupt Flag for SSC
This bit is set by hardware and can only be cleared
by software.
0
Interrupt event has not occurred.
1
Interrupt event has occurred.
RIR
2
rwh
Receive Interrupt Flag for SSC
This bit is set by hardware and can only be cleared
by software.
0
Interrupt event has not occurred.
1
Interrupt event has occurred.
ADCSR0
3
rwh
Interrupt Flag 0 for ADC
This bit is set by hardware and can only be cleared
by software.
0
Interrupt event has not occurred.
1
Interrupt event has occurred.
ADCSR1
4
rwh
Interrupt Flag 1 for ADC
This bit is set by hardware and can only be cleared
by software.
0
Interrupt event has not occurred.
1
Interrupt event has occurred.
0
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
IRCON2
Interrupt Request Register 2
RMAP: 0, PAGE: 0
7
6
5
(F5H)
4
Reset Value: 00H
3
2
1
0
0
CCU6SR1
0
CCU6SR0
r
rwh
r
rwh
User’s Manual
Interrupt System, V 2.3.3
9-26
V1.1, 2010-09
XC83x
Interrupt System
Field
Bits
Type Description
CCU6SR0
0
rwh
Interrupt Flag 0 for CCU6
This bit is set by hardware and can only be cleared
by software.
0
Interrupt event has not occurred.
1
Interrupt event has occurred.
CCU6SR1
4
rwh
Interrupt Flag 1 for CCU6
This bit is set by hardware and can only be cleared
by software.
0
Interrupt event has not occurred.
1
Interrupt event has occurred.
0
[3:1],
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
IRCON3
Interrupt Request Register 3
RMAP: 0, PAGE: 0
7
6
5
(F6H)
4
Reset Value: 00H
3
2
1
0
0
CCU6SR3
0
CCU6SR2
r
rwh
r
rwh
Field
Bits
Type Description
CCU6SR3
4
rwh
Interrupt Flag 3 for CCU6
This bit is set by hardware and can only be cleared
by software.
0
Interrupt event has not occurred.
1
Interrupt event has occurred.
CCU6SR2
0
rwh
Interrupt Flag 2 for CCU6
This bit is set by hardware and can only be cleared
by software.
0
Interrupt event has not occurred.
1
Interrupt event has occurred.
0
[3:1],
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Interrupt System, V 2.3.3
9-27
V1.1, 2010-09
XC83x
Interrupt System
TCON
Timer and Counter Control/Status Register(88H)
RMAP: X, PAGE: X
Reset Value: 00H
7
6
5
4
3
2
1
0
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
rwh
rw
rwh
rw
rwh
rw
rwh
rw
Field
Bits
Type Description
IE0
1
rwh
External Interrupt 0 Flag
Set by hardware when external interrupt 0 event is
detected.
Cleared by hardware when the processor vectors to
interrupt routine. Can also be cleared by software.
IE1
3
rwh
External Interrupt 1 Flag
Set by hardware when external interrupt 1 event is
detected.
Cleared by hardware when the processor vectors to
interrupt routine. Can also be cleared by software.
TF0
5
rwh
Timer 0 Overflow Flag
Set by hardware on Timer/Counter 0 overflow.
Cleared by hardware when processor vectors to
interrupt routine. Can also be cleared by software.
TF1
7
rwh
Timer 1 Overflow Flag
Set by hardware on Timer/Counter 1 overflow.
Cleared by hardware when processor vectors to
interrupt routine. Can also be cleared by software.
SCON
UART Control/Status Register
RMAP: X, PAGE: X
(98H)
Reset Value: 00H
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
rw
rw
rw
rw
rw
rwh
rwh
rwh
User’s Manual
Interrupt System, V 2.3.3
9-28
V1.1, 2010-09
XC83x
Interrupt System
Field
Bits
Type Description
RI
0
rwh
Serial Interface Receiver Interrupt Flag
Set by hardware if a serial data byte has been
received. Must be cleared by software.
TI
1
rwh
Serial Interface Transmitter Interrupt Flag
Set by hardware at the end of a serial data
transmission. Must be cleared by software.
NMISR
NMI Status Register
RMAP: 0, PAGE: 0
7
6
FNMI
FNMIECC
XTALCLK
rwh
rwh
(F7H)
Reset Value: 00H
5
4
3
2
FNMI
VDDP
FNMI
VDDC
FNMI
OCDS
FNMI
FLASH
rwh
rwh
rwh
rwh
1
0
FNMI
FNMIWDT
OSCCLK
rwh
rwh
Field
Bits
Type Description
FNMIWDT
0
rwh
Watchdog Timer NMI Flag
0
No watchdog NMI has occurred.
1
WDT prewarning has occurred.
FNMIOSCCLK
1
rwh
48 MHz or 75 kHz Oscillator Clock NMI Flag
0
No 48 MHz or 75 kHz Oscillator NMI has
occurred.
1
48 MHz or 75 kHz loss of clock has occurred.
FNMIFLASH
2
rwh
Flash Operation Complete NMI Flag
0
No Flash NMI has occurred.
1
Flash operation complete event has occurred.
FNMIOCDS
3
rwh
OCDS NMI Flag
0
No OCDS NMI has occurred.
1
JTAG-receiving or user interrupt request in
Monitor Mode has occurred.
FNMIVDDC
4
rwh
VDDC Prewarning NMI Flag
0
No VDDC NMI has occurred.
1
VDDC prewarning (drop below 2.3V) has
occurred.
User’s Manual
Interrupt System, V 2.3.3
9-29
V1.1, 2010-09
XC83x
Interrupt System
Field
Bits
Type Description
FNMIVDDP
5
rwh
VDDP Prewarning NMI Flag
0
No VDDP NMI has occurred.
1
VDDP prewarning (drop below 4.0V for
external power supply of 5.0V) has occurred.
FNMIECC
6
rwh
ECC NMI Flag
0
No ECC error has occurred.
1
ECC error has occurred.
FNMIXTALCLK 7
rwh
32.768 kHz XTAL Oscillator Clock NMI Flag
This bit is set by hardware and can only be cleared
by software.
0
No 32.768 kHz XTAL Oscillator NMI has
occurred.
1
32.768 kHz XTAL loss of clock has occurred.
Note: NMISR register can only be cleared by software or reset to the default value after
the Power-On Reset. Its value is retained on any other resets. This allows the
cause of the previous NMI to be checked.
User’s Manual
Interrupt System, V 2.3.3
9-30
V1.1, 2010-09
XC83x
Interrupt System
9.5.4
Interrupt Priority Registers
Each interrupt node can be individually programmed to one of the four priority levels
available. Two pairs of Interrupt Priority Registers are available to program the priority
level of the each interrupt vector. The first pair of Interrupt Priority Registers are SFRs IP
and IPH. The second pair of Interrupt Priority Registers are SFRs IP1 and IPH1.
The corresponding bits in each pair of Interrupt Priority Registers select one of the four
priority levels as shown in Table 9-5.
Table 9-5
Interrupt Priority Level Selection
IPH.x / IPH1.x
IP.x / IP1.x
Priority Level
0
0
Level 0 (lowest)
0
1
Level 1
1
0
Level 2
1
1
Level 3 (highest)
Note: NMI always has the highest priority (above Level 3); it does not use the priority
level selection shown in Table 9-5.
IP
Interrupt Priority Register
RMAP: X, PAGE: X
7
6
(B8H)
Reset Value: 00H
5
4
3
2
1
0
0
PT2
PS
PT1
PX1
PT0
PX0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
PX0
0
rw
Priority Level Low Bit for Interrupt Node XINTR0
PT0
1
rw
Priority Level Low Bit for Interrupt Node XINTR1
PX1
2
rw
Priority Level Low Bit for Interrupt Node XINTR2
PT1
3
rw
Priority Level Low Bit for Interrupt Node XINTR3
PS
4
rw
Priority Level Low Bit for Interrupt Node XINTR4
PT2
5
rw
Priority Level Low Bit for Interrupt Node XINTR5
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
Interrupt System, V 2.3.3
9-31
V1.1, 2010-09
XC83x
Interrupt System
IPH
Interrupt Priority High Register
RMAP: X, PAGE: X
7
6
(B9H)
Reset Value: 00H
5
4
3
2
1
0
0
PT2H
PSH
PT1H
PX1H
PT0H
PX0H
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
PX0H
0
rw
Priority Level High Bit for Interrupt Node XINTR0
PT0H
1
rw
Priority Level High Bit for Interrupt Node XINTR1
PX1H
2
rw
Priority Level High Bit for Interrupt Node XINTR2
PT1H
3
rw
Priority Level High Bit for Interrupt Node XINTR3
PSH
4
rw
Priority Level High Bit for Interrupt Node XINTR4
PT2H
5
rw
Priority Level High Bit for Interrupt Node XINTR5
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
IP1
Interrupt Priority 1 Register
RMAP: X, PAGE: X
(F8H)
Reset Value: 04H
7
6
5
4
3
2
1
0
PCCIP3
PCCIP2
PCCIP1
PCCIP0
PXM
PX2
PSSC
PADC
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
PADC
0
rw
Priority Level Low Bit for Interrupt Node XINTR6
PSSC
1
rw
Priority Level Low Bit for Interrupt Node XINTR7
PX2
2
rw
Priority Level Low Bit for Interrupt Node XINTR8
PXM
3
rw
Priority Level Low Bit for Interrupt Node XINTR9
PCCIP0
4
rw
Priority Level Low Bit for Interrupt Node XINTR10
PCCIP1
5
rw
Priority Level Low Bit for Interrupt Node XINTR11
User’s Manual
Interrupt System, V 2.3.3
9-32
V1.1, 2010-09
XC83x
Interrupt System
Field
Bits
Type Description
PCCIP2
6
rw
Priority Level Low Bit for Interrupt Node XINTR12
PCCIP3
7
rw
Priority Level Low Bit for Interrupt Node XINTR13
IPH1
Interrupt Priority 1 High Register
RMAP: X, PAGE: X
(F9H)
Reset Value: 04H
7
6
5
4
3
2
1
0
PCCIP3H
PCCIP2H
PCCIP1H
PCCIP0H
PXMH
PX2H
PSSCH
PADCH
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
PADCH
0
rw
Priority Level High Bit for Interrupt Node XINTR6
PSSCH
1
rw
Priority Level High Bit for Interrupt Node XINTR7
PX2H
2
rw
Priority Level High Bit for Interrupt Node XINTR8
PXMH
3
rw
Priority Level High Bit for Interrupt Node XINTR9
PCCIP0H
4
rw
Priority Level High Bit for Interrupt Node
XINTR10
PCCIP1H
5
rw
Priority Level High Bit for Interrupt Node
XINTR11
PCCIP2H
6
rw
Priority Level High Bit for Interrupt Node
XINTR12
PCCIP3H
7
rw
Priority Level High Bit for Interrupt Node
XINTR13
9.6
Interrupt Flag Overview
The interrupt events have interrupt flags that are located in different SFRs. Table 9-6
shows the corresponding SFR to which each interrupt flag belongs. Detailed information
on the interrupt flags is provided in the respective peripheral chapters.
Table 9-6
Location of the Interrupt Flags
Interrupt Event
Interrupt Flag
SFR
Timer 0 Overflow
TF0
TCON
Timer 1 Overflow
TF1
TCON
User’s Manual
Interrupt System, V 2.3.3
9-33
V1.1, 2010-09
XC83x
Interrupt System
Table 9-6
Location of the Interrupt Flags (cont’d)
Interrupt Event
Interrupt Flag
SFR
Timer2 Overflow
TF2
T2_T2CON
Timer2 External Event
EXF2
T2_T2CON
UART Receive
RI
SCON
UART Transmit
TI
SCON
LIN End of Synch Byte
EOFSYN
LINST
LIN Synch Byte Error
ERRSYN
LINST
External Interrupt 0
IE0
TCON
External Interrupt 1
IE1
TCON
External Interrupt 2
EXINT2
IRCON0
External Interrupt 3
EXINT3
IRCON0
External Interrupt 4
EXINT4
IRCON0
External Interrupt 5
EXINT5
IRCON0
External Interrupt 6
EXINT6
IRCON0
RTC compare/wakeup interrupt
CFRTC
RTC_RTCON
RTC second time interrupt
SFRTC
RTC_RTCON
A/D Converter Service Request 0
ADCSR0
IRCON1
A/D Converter Service Request 1
ADCSR1
IRCON1
CORDIC End of Calculation
EOC
CD_STATC
MDU Result Ready
IRDY
MDU_MDUSTAT
MDU Error
IERR
MDU_MDUSTAT
SSC Error
EIR
IRCON1
SSC Transmit
TIR
IRCON1
SSC Receive
RIR
IRCON1
IIC Interrupt
IFLG
IIC_CNTR
P1.0 HCPADA Overcurrent Interrupt
P0_OCF
P1_OCD
P1.1 HCPADA Overcurrent Interrupt
P1_OCF
P1_OCD
P1.2 HCPADA Overcurrent Interrupt
P2_OCF
P1_OCD
P1.3 HCPADA Overcurrent Interrupt
P3_OCF
P1_OCD
CCU6 Node 0 Interrupt
CCU6SR0
1)
IRCON2
CCU6 Node 1 Interrupt
CCU6SR11)
IRCON2
User’s Manual
Interrupt System, V 2.3.3
9-34
V1.1, 2010-09
XC83x
Interrupt System
Table 9-6
Location of the Interrupt Flags (cont’d)
Interrupt Event
Interrupt Flag
SFR
CCU6SR2
1)
CCU6 Node 3 Interrupt
CCU6SR3
1)
LEDTSCU Time Slice Interrupt
TSF
LTS_GLOBCTL1
LEDTSCU Time Frame Interrupt
TFF
LTS_GLOBCTL1
CCU6 Node 2 Interrupt
IRCON3
IRCON3
Watchdog Timer NMI
FNMIWDT
NMISR
48 MHz and 75 kHz Oscillator NMI
FNMIOSCCLK
NMISR
32.768 kHz XTAL Oscillator NMI
FNMIXTALCLK
NMISR
Flash Operation Complete NMI
FNMIFLASH
NMISR
OCDS NMI
FNMIOCDS
NMISR
VDDC Prewarning NMI
FNMIVDDC
NMISR
VDDP Prewarning NMI
FNMIVDDP
NMISR
Flash ECC NMI
FNMIECC
NMISR
1) Each CCU6 interrupt can be assigned to any of the CCU6 interrupt nodes [3:0] via CCU6 registers INPL/INPH.
User’s Manual
Interrupt System, V 2.3.3
9-35
V1.1, 2010-09
XC83x
Debug System
10
Debug System
This chapter describes the XC800 debug system, in particular focus on the OCDS unit
which provides the hardware to support debug functionality.
10.1
Overview
The debug system comprises of the On-Chip Debug Support (OCDS) unit and DebugMonitor in ROM which provides basic debug functionality for XC800-based systems,
controlled directly by an external tool via debug interface pin(s).
Features
The main debug functionality supported are:
•
•
•
•
•
•
Set breakpoints on instruction address and on address range within the Program
Memory
Set breakpoints on Internal RAM address range
Support unlimited software breakpoints in Flash/RAM code region
Process external breaks via debug interface
Step through the program code
User handling of OCDS NMI in case of IRAM read/write breakpoint
10.1.1
Components of the Debug System
The components of the debug system are briefly described here.
Debug Interface
The debug interface allows to access the device, such as for data read or write. The
debug interface supported:
•
•
Single-pin DAP (SPD)
1- or 2-pin UART
The SPD interface refers to the single-pin Device Access Port standardized for the
Infineon microcontrollers. It utilizes only one pin DAP1 for serial data in/out.
The UART is a standard interface, however OCDS hardware commands are not
supported.
Monitor Program
Part of the Boot ROM is occupied by the OCDS Monitor program (or OCDS firmware).
On the command from the debugger, the Monitor program executes the actual
instructions for accessing the addressable locations such as memories, sfrs of the
device.
User’s Manual
OCDS, V 2.7.2
10-1
V1.1, 2010-09
XC83x
Debug System
On-Chip Debug System Unit (OCDS)
The OCDS hardware is the core of the debug system, controlling the debugging with
interfaces to the XC800 CPU.
10.2
Product Specific Information
This section provides product specific information relevant to the OCDS.
10.2.1
Pinning
Figure 10-1 describes the debug pin function in XC83x.
Table 10-1
Pin
XC83x Pin Functions and Selection
Function Desciption
P3.2 SPD_0
Selected By
Single-pin debug access port:
data
P0.6 SPD_1
Selectable via BMI value. Refer
to Chapter 5 for more details.
P1.0 SPD_2
10.2.2
Clocking Configuration
The OCDS runs at the CPU operating frequency of either 8 MHz or 24 MHz.
10.2.3
Interrupt Events and Assignment
Instead of entering Monitor Mode on a break event, it can be configured such that OCDS
NMI is vectored to. In this configuration, the action on OCDS NMI is fully under user
software control. Details of this usage is described in later sections.
Table 10-2 lists the interrupt event sources from the OCDS, and the corresponding
event interrupt enable bit and flag bit.
Table 10-2
OCDS Interrupt Events
Event
Event Interrupt Enable Bit
Event Flag Bit
IRAM read event
MMICR.NMIRRE
MMICR.FNMIRR
IRAM write event
MMICR.NMIRWE
MMICR.FNMIRW
Table 10-3 shows the interrupt node assignment for each OCDS interrupt source.
User’s Manual
OCDS, V 2.7.2
10-2
V1.1, 2010-09
XC83x
Debug System
Table 10-3
OCDS Events’ Interrupt Node Control
Event
Interrupt Node
Enable Bit
Interrupt Node Flag Vector
Bit
Address
IRAM read event
NMICON.NMIOCDS
NMISR.FNMIOCDS
73H
IRAM write event
10.2.4
Debug Suspend Control
It is enabled for selected modules to suspend operation when Monitor Mode becomes
active. The module functions that can be enabled for debug suspend are:
•
•
•
•
•
•
Watchdog timer
Timer 12 of CCU6
Timer 13 of CCU6
Timer 2
RTC timer
LEDTSCU counters
By debug suspend, these module functions are frozen during the duration of the device
in Monitor Mode, e.g. timers stop counting. Register MODSUSP is used to control the
debug suspend function. The bit field of SCU_PAGE register must be programmed
before accessing the MODSUSP register.
MODSUSP
Module Suspend Control Register
RMAP: 0, PAGE: 3
7
6
5
0
(F6H)
4
3
LTSSUSP RTCSUSP
r
rw
T2SUSP
rw
rw
Field
Bits
Type Description
WDTSUSP
0
rw
User’s Manual
OCDS, V 2.7.2
Reset Value: 01H
2
1
0
T13SUSP T12SUSP WDTSUSP
rw
rw
rw
SCU Watchdog Timer Debug Suspend Bit
0
WDT will not be suspended.
1
WDT will be suspended.
10-3
V1.1, 2010-09
XC83x
Debug System
Field
Bits
Type Description
T12SUSP
1
rw
Timer 12 Debug Suspend Bit
0
Timer 12 in Capture/Compare Unit will not be
suspended.
1
Timer 12 in Capture/Compare Unit will be
suspended.
In addition, the T12 PWM outputs are set to the
inactive level and capture inputs are disabled when
suspended.
T13SUSP
2
rw
Timer 13 Debug Suspend Bit
0
Timer 13 in Capture/Compare Unit will not be
suspended.
1
Timer 13 in Capture/Compare Unit will be
suspended.
In addition, the T13 PWM outputs are set to the
inactive level and capture inputs are disabled when
suspended.
T2SUSP
3
rw
Timer 2 Debug Suspend Bit
0
Timer2 will not be suspended.
1
Timer2 will be suspended.
RTCSUSP
4
rw
Real-time Clock Debug Suspend Bit
0
Real-time clock will not be suspended.
1
Real-time clock will be suspended.
LTSSUSP
5
rw
LED and Touch-Sense Counters Debug Suspend
Bit
0
LED and Touch-sense Counters will not be
suspended.
1
LED and Touch-sense Counters will be
suspended.
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
OCDS, V 2.7.2
10-4
V1.1, 2010-09
XC83x
Debug System
10.2.5
JTAG ID
The JTAG ID for the XC83x devices is given in Table 10-4.
Table 10-4
JTAG ID Number
Device Type
Device Name
JTAG ID
Flash
XC83x - 2FGI
101BA083H
XC83x - 2FRI
XC83x - 1FRI
10.3
101BB083H
Functional Overview of the Debug System
XC800 debug-operation is based on close interaction between the OCDS-hardware and
the Monitor program in ROM.
These operations are elaborated in the following.
10.3.1
Recognizing Debug-events
The OCDS hardware takes care to startup properly the Monitor, in case some Debugevent happens.
The debug events (breakpoints) supported are described in following.
Hardware Breakpoints
Up to 4 hardware breakpoints can be set, causing a break in case of
•
•
•
code is fetched from a defined Program Memory (IP) address - the break is set just
at one instruction from the user software
code is fetched from a defined Program Memory (IP) address-range - the break is
set over a number of consecutive instructions from the user software
Read or Write (selectable) is performed at a defined Internal RAM address - the
break is caused by moving data from/to a memory location
For setting of breakpoint on instruction address,HWBPx defines the 16-bit address. For
setting of breakpoint on IRAM address, HWBP2/3L and HWBP2/3H define the 8-bit
IRAM address range.
The configurations supported are:
•
•
Breakpoint 0
Breakpoint 1
– Two equal breakpoints on
Instruction Address = HWBP0 and
Instruction Address = HWBP1 or
User’s Manual
OCDS, V 2.7.2
10-5
V1.1, 2010-09
XC83x
Debug System
•
•
– One range breakpoint on
HWBP0 <= Instruction Address <= HWBP1
Breakpoint 2
– One equal breakpoint on Instruction Address = HWBP2, or
– One range breakpoint on HWBP2L <= IRAM Read Address <= HWBP2H
Breakpoint 3
– One equal breakpoint on Instruction Address = HWBP3, or
– One range breakpoint on HWBP3L <= IRAM Write Address <= HWBP3H
Setting both values for a range breakpoint to the same address leads to generation of
an equal breakpoint.
Software Breakpoints
These are implemented by storing into the code XC800-specific TRAP instruction (not
8051-standard), while at the same time TRAP_EN bit within the Extended Operation
(EO) register is also set to 1.
Upon fetching a TRAP instruction, a breakpoint is generated and the relevant Break
Action is taken.
The software breakpoints are in fact similar in behavior to the equal breakpoints on
Instruction address, except that they are raised by a program code instead of specialized
(compare) logic.
An unlimited number of software breakpoints can be set by replacing the original
instruction codes into the user program. Of course this is possible only at addresses,
where RAM/Flash is implemented.
External Breaks
External breaks could be:
•
Requested via the debug interface by OCDS command: An external Debugger can
activate the Monitor and interrupt a user program, running on the target XC800.
10.3.2
Activating the Monitor Program
Once a Debug-event is identified and the OCDS-registers are properly programmed, the
Monitor program (in ROM) is started as a primary reaction.
The OCDS hardware ensures that the Monitor is always safely started, and fully
independent of the current system status at the moment when the debug action is taken.
Also, interrupt requests optionally raised during Monitor-entry will not disturb the Monitor
firmware functioning.
Once started, the Monitor runs with its own stack- and data- memory, which guarantees
that all of the core and memory resources will be found untouched when returning control
back to the user program. Therefore the OCDS-debugging is fully non-destructive.
User’s Manual
OCDS, V 2.7.2
10-6
V1.1, 2010-09
XC83x
Debug System
The functions of the Monitor include:
•
•
•
•
Communication with an external Debugger via the debug interface
Read/write access to arbitrary memory locations and Special Function Registers
(SFRs), including the Instruction Pointer and password-protected bits
Configuring OCDS and setting/removing breakpoints
Executing a single instruction (step-mode)
Note: Details of the Monitor program functionality is not covered in this documentation.
10.3.3
Debug Suspend Control
Next to the basic debug functionality - setting breakpoints and halting the execution of
user software - OCDS supports also for module suspend during debugging.
As long as the device is in monitor mode (i.e. while the user software is not running but
in break) and if debug suspend functionality is generally enabled by on-chip software,
modules or functions can be suspended in this duration.
This feature could be quite useful, especially regarding the Watchdog Timer: it prevents
unintentional WDT-resets during the debug session. Usually debug suspend is provided
for other timer-modules. Stopping counters provide for a complete “freeze” of the devicestatus during a break.
Generally, the debug suspend control bits (global enable in OCDS and individual
selections in SCU) are disabled after reset, i.e. by default no module will be suspended
upon a break. Normally for debugging the device will be started in OCDS mode and then
the monitor will be invoked before to start any user code. The debugger should provide
for user configuration of suspend-controls.
10.3.4
Running the Monitor
The Monitor runs with its own stack- and data- work space, therefore the complete status
of the core is saved and later - restored before returning to the user code.
Once the Monitor is running, it can access for read and write all of the system resources,
and data can be communicated with the Debugger.
10.3.5
Returning to the User Program
When a return to User-Program is requested, the Monitor sets core-registers including
the Instruction Pointer (IP) as required. This can be either the same status as at the
Breakpoint, or including some changes done during the Break by a host debugger. Then
a jump to the location pointed by IP is performed and the target system returns to User
Mode.
User’s Manual
OCDS, V 2.7.2
10-7
V1.1, 2010-09
XC83x
Debug System
10.3.6
Single Step Execution
For this functionality OCDS operates at first as when Returning to the User Program, but
also a dedicated flag is set into a control-register (MMCR.MSTEP). This way, just one
user-instruction is executed before re-entering the Monitor again.
User’s Manual
OCDS, V 2.7.2
10-8
V1.1, 2010-09
XC83x
Debug System
10.4
Breakpoint Generation Module
Breakpoint generation is only possible in Monitor Mode.
Attention: To be able to debug via Monitor Mode, the application software should
not change the TRAP_EN bit within Extended Operation (EO) register.
Breakpoints can be classified into three types:
•
•
•
Break Before Make
The break happens just before the break instruction (i.e. the instruction causing the
break) is executed. Therefore, the break instruction itself will be the next instruction
from the user program flow but executed only after the relevant debug action has
been taken.
Break After Make
The break happens immediately after the instruction causing it has been executed.
Therefore, the break instruction itself has already been executed when the relevant
debug action is taken.
Break Now
The events of this type are asynchronous to the code execution inside the XC83x and
there is no “instruction causing the debug event” in this case. The debug action is
performed by OCDS “as soon as possible” once the debug event is raised.
10.4.1
Generating Hardware Breakpoints
This block is built around a set of comparators, dedicated to recognize two types of
hardware breakpoints:
10.4.1.1 Breakpoints on Instruction Address
These IP breakpoints are generated, only when the BP-address is matched for the first
byte of an instruction - i.e. just for the opcode. In case of 2- and 3- byte instructions, the
break will not be generated at all for addresses of the second and third instruction-bytes.
The IP breakpoints are of Break Before Make type, therefore the instruction at the
breakpoint is executed only after the proper debug action is taken.
Address Comparators, Control bits and Flags
Below the comparators used for IP Breakpoints are described:
•
CMP0
A 16-bit comparator between the two HWBP0 registers (A-side) and the 16-bit
Program Memory Address Bus (B-side).
Two output signals are generated:
– A=B - (break on IP= HWBP0)
– A=<B - see below.
User’s Manual
OCDS, V 2.7.2
10-9
V1.1, 2010-09
XC83x
Debug System
•
•
•
CMP1
A 16-bit comparator between the two HWBP1 registers (A-side) and the 16-bit
Program Memory Address Bus (B-side).
Two output signals are generated:
– A=B - (break on IP= HWBP1 )
– A>=B when activated together with A=<B from CMP0 - (break on HWBP0 =<IP<=
HWBP1)
CMPIP2
A 16-bit comparator between the two HWBP2 registers (A-side) and the 16-bit
Program Memory Address Bus (B-side).
One output signal is generated:
– A=B - (break on IP = HWBP2)
CMPIP3
A 16-bit comparator between the two HWBP3 registers (A-side) and the 16-bit
Program Memory Address Bus (B-side).
One output signal is generated:
– A=B - (break on IP = HWBP3)
10.4.1.2 Breakpoints on Internal RAM Address
These Internal RAM (IRAM) Breakpoints are recognized primary by observing the
Internal Data Memory Address Buses, respectively for Breakpoints on Read and Write
addresses respectively.
The IRAM breakpoints are of Break After Make type, therefore the proper debug action
is taken immediately after the operation to the breakpoint address is performed.
The OCDS supports only range breakpoints on IRAM address.
The OCDS differentiates between a breakpoint on read and a breakpoint on write
operation to the IRAM.
The exact processing is different in case of Read and Write Breakpoints.
Address Comparators, Control bits and Flags
Below the comparators used for Memory Access Breakpoints are described:
•
CMPRL2, CMPRH2
Two 8-bit comparators:
– CMPRL2 - between HWBP2L register (A-side) and the 8-bit IRAM Source Address
Bus (B-side), generating A=<B;
– CMPRH2 - between HWBP2H register (A-side) and the 8-bit IRAM Source
Address Bus (B-side), generating A>=B.
Then:
break on HWBP2L=<IRAM Read Address<=HWBP2H.
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OCDS, V 2.7.2
10-10
V1.1, 2010-09
XC83x
Debug System
•
CMPWL3, CMPWH3
Two 8-bit comparators:
– CMPWL3 - between HWBP3L register (A-side) and the 8-bit IRAM Destination
Address Bus (B-side), generating A=<B;
– CMPWH3 - between HWBP3H register (A-side) and the 8-bit IRAM Destination
Address Bus (B-side), generating A>=B.Then:
break on HWBP3L=<IRAM Write Address<=HWBP3H.
10.4.1.3 Tracing changes in Break Address
The mechanism to generate Hardware Breakpoints assures, that "immediately" upon a
break-condition match, the XC800 core is forced to Debug Mode. The Program Counter
freezes then at a value, related to the address of instruction that would have been
fetched, had the core not been in Debug Mode.
When entered, the Monitor will determine the source of the Break and relevant
information is to be forwarded to the Debugger, concerning the Break Event source
(IRAM read/write)
10.4.2
Processing External Breaks
Possible external break-requests are generated and processed as follows:
1. a request comes from one of the possible source(s)
a) Debugger-request via SPD - a dedicated command has been sent, with
MMODE_r=1, RRF_r=0 and data-Byte=A5H, while at the same time:
MMCR2.MMODE=0 and MMCR2.ALTDI=0
2. the core ends executing current instruction,
the core enters Debug Mode
Note: External Breaks are not possible inside a NMI-servicing routine.
For more information refer to Section 10.7.
10.4.3
Processing Software Breakpoints
Software breakpoints are of Break Before Make type, therefore the instruction at the
breakpoint is executed only after the proper debug action is taken.
Upon fetching a TRAP instruction, Software Breakpoint is effected. Due to this, it goes
to Debug Mode.
Attention: The user software must not clear the TRAP_EN bit in EO register.
The OCDS reacts in two ways:
•
•
a Break eventis recognized for Entering Monitor Mode
the Software Break is ignored
This happens when the above condition is not satisfied, i.e. basically when the
Software Breakpoints are disabled.
User’s Manual
OCDS, V 2.7.2
10-11
V1.1, 2010-09
XC83x
Debug System
Upon matching a not enabled Software Breakpoint, the user software execution is
suppressed for 4 clock cycles after the TRAP instruction.
10.5
Reactions on Breakpoints without Monitor Entry
In case a Break-event happens while Monitor Mode is disabled
, the Monitor program is not started (MM_no_entry) but another action is triggered by
OCDS system.
10.5.1
Triggering a NMI request
Instead of starting the Monitor program, OCDS NMI is requested, refer Section 10.6.1.
The flags FNMIRR/FNMIRW here set can be cleared only per software - this must be
done by the user NMI-servicing routine.
User’s Manual
OCDS, V 2.7.2
10-12
V1.1, 2010-09
XC83x
Debug System
10.6
NMI Request and Control by OCDS
The OCDS module provides hardware allowing to generate a NMI request itself as well
as to control the general NMI-processing within the XC800 system.
10.6.1
NMI request from OCDS
The OCDS generates one interrupt request at the output ocds_nmi_o. This signal goes
to the Interrupt-Management Module into XC800 SCU (System Control Unit), where it
sets a flag within NMI Status Register NMISR. In case OCDS is an enabled source in
NMI Control Register NMICON, a non-maskable interrupt request will be activated to the
core.
The NMI-request can be activated by OCDS upon memory-access performed to defined
address areas (separately configurable for read/write operations) in XC800 Internal
RAM. This is an advanced and fully controllable by application code feature, allowing to
utilize parts of OCDS not for debugging but to support a general, user-accessible
functionality.
The basics for implementation of this feature are:
•
•
the Breakpoint Generation module is able to recognize read/write accesses to IRAM
address-ranges (refer to Section 10.4.1.2)
upon a breakpoint match but while MMCR2.MBCON=1, the Monitor firmware is not
started and therefore in fact no debug-session takes place.
Note: It is required to set the EO.TRAP_EN bit to enable the breakpoint generation.
To configure, trigger and handle an OCDS-NMI request upon IRAM access (refer also
to Section 10.5.1):
1. at all is possible only as long as MMCR2.MBCON=1
2. user software must execute the following sequence:
a) set the NMI-enable bit(s) NMIRRE/NMIRWE in MMICR, respectively for request
upon IRAM read/write
b) write the low address(es) of the observed area into HWBP2L/HBWBP3L,
respectively for NMI-request upon IRAM read/write
c) write the high address(es) of the observed area into HWBP2H/HBWBP3H,
respectively for NMI-request upon IRAM read/write
3. after the settings according to point 2) are done and as long as MBCON=1, a NMIrequest will be triggered by the OCDS upon an access to the respectively configured
(for read/write) IRAM area(s).
4. in case a NMI-request has been raised by the OCDS, respective flag
FNMIRR/FNMIRW is set in MMICR - refer to the register-description in
Section 10.8.1 and functional definition in Section 10.5.1.
If the request is sent to the core - in case enabled by NMICON.NMIOCDS=1 (in
SCU) - then a NMI-servicing routine will be invoked by a jump to its standard
location in XC800 Program Memory, and this routine:
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OCDS, V 2.7.2
10-13
V1.1, 2010-09
XC83x
Debug System
a) can identify OCDS as NMI-requesting source and the type of IRAM-access
causing the request by evaluating NMISR.FNMIOCDS (in SCU) and
MMICR.FNMIRR/FNMIRW (in OCDS)
b) must clear FNMIRR/FNMIRW flags before its end, to allow a proper reaction on
next NMIs.
5. any attempt to configure/activate a Breakpoint for debugging by writing into
MMBPCR will reset the internal nmi_r*e/nmi_r*e_l flags and therefore - disable the
generation of NMI-request upon IRAM access.
Attention: all the software-handling of OCDS NMI (servicing routine) is to be
supported by user code!
10.6.2
OCDS NMI Service Routine Handling
For the correct HW behavior when the OCDS NMI is triggered due to IRAM read/write
access, special handling is necessary in OCDS NMI service routine to set up a correct
RETI address.
The recommended code handling is:
NMI_OCDS_MAIN: ;OCDS NMI service routine
POP RETADD_H ;get the return address stored in SP
POP RETADD_L
;//---user code to handle the OCDS NMI---//
;// USER CODE BEGIN
...
;// USER CODE END
MOV A,RETADD_L
CJNE A,#00H,DEC_LOW_BYTE ;low address byte under-flow?
DEC RETADD_H
DEC_LOW_BYTE:
DEC RETADD_L ;decrement return address by one location
PUSH RETADD_L ;store the correct return address back to SP
PUSH RETADD_H
RETI
10.6.3
General NMI control by OCDS
The controls are aimed to support a correct NMI-related behavior:
•
all the pending NMI requests raised before Monitor Mode entry and as long as the
system is in Monitor Mode will be not affected, i.e. these requests are safely kept and
sent to the core when the system returns to User Mode
User’s Manual
OCDS, V 2.7.2
10-14
V1.1, 2010-09
XC83x
Debug System
10.7
NMI-mode priority over Debug-mode
While the core is in NMI-mode (after an NMI-request has been accepted and before the
RETI instruction is executed, i.e. the time during a NMI-servicing routine), certain debug
functions are blocked/restricted:
1. No external break (refer to Section 10.4.2) is possible while the core is servicing a
NMI.
External break requested inside a NMI-servicing routine will be taken only after RETI
is executed.
2. A breakpoint into NMI-servicing routine is taken, but single stepping is not possible
afterwards.
If a step is requested, the servicing routine will run continuously and monitor mode
will be invoked again only after a RETI is executed.
Hardware breakpoints and software breakpoints proceed as normal while CPU is in NMImode.
10.8
Registers Description
The OCDS Special Function Registers are accessed from the mapped SFR area.
Table 10-5 lists the (direct addressable) SFRs and corresponding address.
Table 10-5
Register Map (Direct Addressable)
Address
Register
F4H
MMICR
F6H
HWBPSR
F7H
HWBPDR
ECH
MMWR2
Additionally, there are Hardware Breakpoint Registers, which are indirect accessible via
HWBPSR (register select) and HWBPDR (data) - refer to Table 10-6 and Table 10-7
(for more information look at Section 10.8).
Table 10-6
Hardware Breakpoint Registers (Indirect Accessed)
Register
Description
HWBP0L
Hardware Breakpoint 0 Low Register
HWBP0H
Hardware Breakpoint 0 High Register
HWBP1L
Hardware Breakpoint 1 Low Register
HWBP1H
Hardware Breakpoint 1 High Register
HWBP2L
Hardware Breakpoint 2 Low Register
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OCDS, V 2.7.2
10-15
V1.1, 2010-09
XC83x
Debug System
Table 10-6
Hardware Breakpoint Registers (Indirect Accessed)
Register
Description
HWBP2H
Hardware Breakpoint 2 High Register
HWBP3L
Hardware Breakpoint 3 Low Register
HWBP3H
Hardware Breakpoint 3 High Register
Table 10-7
HWBPSR [3:0]: Selecting Hardware Breakpoint Registers
BPSEL
Register Selected
0xxx
reserved - no selection
1000
HWBP0L
1001
HWBP0H
1010
HWBP1L
1011
HWBP1H
1100
HWBP2L
1101
HWBP2H
1110
HWBP3L
1111
HWBP3H
10.8.1
BPSEL Register Selected
Control and Status Registers
MMICR
Monitor Mode Interrupt Control Register (F4H)
RMAP: 1, PAGE: X
7
6
5
4
Reset value: 00H
3
2
1
0
FNMIRW
FNMIRR
NMIRWE
NMIRRE
rwh
rwh
rw
rw
Field
Bits
Type Description
NMIRRE
0
rw
NMI upon IRAM read (refer to Section 10.6.1):
0
Disabled
1
Enabled
NMIRWE
1
rw
NMI upon IRAM write (refer to Section 10.6.1):
0
Disabled
1
Enabled
FNMIRR
2
rwh
IRAM Read NMI Flag
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OCDS, V 2.7.2
10-16
V1.1, 2010-09
XC83x
Debug System
Field
Bits
Type Description
FNMIRW
3
rwh
IRAM Write NMI Flag
FNMIRR / FNMIRW bits:
-set by hardware in case of NMI request from OCDS activated upon read/write access
to the Internal RAM (refer to Section 10.5.1 and Section 10.6.1)
-the software can only reset these bits
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OCDS, V 2.7.2
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XC83x
Debug System
10.8.2
Hardware Breakpoint Registers
All of the Hardware Breakpoint Registers HWBP0L..HWBP3H within OCDS can be set
to the desired compare-values indirectly - by writing only to one software-accessible
register HWBPDR, after BPSEL bitfield within the select-register HWBPSR has been
properly programmed (refer to Table 10-7).
HWBPSR
Hardware Breakpoints Select Register (F6H)
RMAP: 1, PAGE: X
Reset value: 00H
7
6
5
4
3
2
1
0
0
0
BPSEL_P
BPSEL
r
r
r
w
rw
0
Field
Bits
Type Description
BPSEL
[3:0]
rw
BreakPoint register Select - refer to Table 10-7
BPSEL_P
4
w
Bit protection:
0
BPSEL unchangeable
1
BPSEL can be changed
0
[7:5]
r
Reserved
HWBPDR
Hardware Breakpoints Data Register (F7H)
RMAP: 1, PAGE: X
7
6
5
4
Reset value: 00H
3
2
1
0
HWBPxx
rw
Field
Bits
Type Description
HWBPxx
[7:0]
rw
User’s Manual
OCDS, V 2.7.2
Data to be written into/read from a HWBPxx register,
as currently selected by HWBPSR
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V1.1, 2010-09
XC83x
Debug System
HWBP0L
Hardware Breakpoint 0 Low Register written via HWBPDR
7
6
5
4
3
2
Reset value: 00H
1
0
HWBP0L
Field
Bits
HWBP0L
[7:0]
Type Description
The Low Byte from Compare Address HWBP0
HWBP0H
Hardware Breakpoint 0 High Register written via HWBPDR
7
6
5
4
3
2
Reset value: 00H
1
0
HWBP0H
Field
Bits
HWBP0H
[7:0]
Type Description
The High Byte from Compare Address HWBP0
HWBP1L
Hardware Breakpoint 1 Low Register written via HWBPDR
7
6
5
4
3
2
Reset value: 00H
1
0
HWBP1L
Field
Bits
HWBP1L
[7:0]
User’s Manual
OCDS, V 2.7.2
Type Description
The Low Byte from Compare Address HWBP1
10-19
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XC83x
Debug System
HWBP1H
Hardware Breakpoint 1 High Register written via HWBPDR
7
6
5
4
3
2
Reset value: 00H
1
0
HWBP1H
Field
Bits
HWBP1H
[7:0]
Type Description
The High Byte from Compare Address HWBP1
HWBP2L
Hardware Breakpoint 2 Low Register written via HWBPDR
7
6
5
4
3
2
Reset value: 00H
1
0
HWBP2L
Field
Bits
HWBP2L
[7:0]
Type Description
The Low Byte from Compare Address HWBP2
HWBP2H
Hardware Breakpoint 2 High Register written via HWBPDR
7
6
5
4
3
2
Reset value: 00H
1
0
HWBP2H
Field
Bits
HWBP2H
[7:0]
User’s Manual
OCDS, V 2.7.2
Type Description
The High Byte from Compare Address HWBP2
10-20
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XC83x
Debug System
HWBP3L
Hardware Breakpoint 3 Low Register written via HWBPDR
7
6
5
4
3
2
Reset value: 00H
1
0
HWBP3L
Field
Bits
HWBP3L
[7:0]
Type Description
The Low Byte from Compare Address HWBP3
HWBP3H
Hardware Breakpoint 3 High Register written via HWBPDR
7
6
5
4
3
2
Reset value: 00H
1
0
HWBP3H
Field
Bits
HWBP3H
[7:0]
10.8.3
Type Description
The High Byte from Compare Address HWBP3
Monitor Work Register
MMWR2 can be used for general pusposes when no debug-session is possible: if the
device is not started in OCDS mode and no external device is connected.
MMWR2
Monitor Work Register 1
RMAP: 1, PAGE: X
7
6
(ECH)
5
4
Reset value: 00H
3
2
1
0
MMWR2
rw
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OCDS, V 2.7.2
10-21
V1.1, 2010-09
XC83x
Debug System
Field
Bits
Type Description
MMWR2
[7:0]
rw
User’s Manual
OCDS, V 2.7.2
Work location 2 for the Monitor Program
10-22
V1.1, 2010-09
XC83x
Parallel Ports
11
Parallel Ports
XC83x are organized into four parallel ports, Port 0 (P0) to Port 3 (P3). Table 11-1 shows
the type of port pin used in XC83x.
Each pin has a pair of internal pull-up and pull-down devices that can be individually
enabled or disabled. Ports P0, P1 and P3 are birectional port and can be used as general
purpose input/output (GPIO) or to perform alternate input/output functions for the on-chip
peripherals. When configured as an output, the open drain mode can be selected. P1
are the high current bidirectional port that can be used for motor and LED applications.
Port P2 is an input-only port, providing general purpose input functions, alternate input
functions for the on-chip peripherals, and also analog inputs for the Analog-to-Digital
Converter (ADC).
Table 11-1
Port Type in XC83x
Port Pins
Port Type
P0.1 - P0.7
Standard Bidirectional Port
P1.0 - P1.3
High Current Bidirectional Port Type A (HCPADA)1)
P1.4 - P1.5
High Current Bidirectional Port Type B (HCPADB)2)
P2.0 - P2.7
Input Port
P3.0 - P3.2
Standard Bidirectional Port
1)
HCPADA are designed for direct drive of motor and LED.
2)
HCPADB are designed for LED application only. It is not design for direct drive of motor.
High Current Bidirectional Port Type A (HCPADA) Features:
•
•
•
•
•
•
•
•
•
•
•
•
Configurable pin direction
Configurable pull-up/pull-down devices
Configurable open drain mode
Transfer data through digital inputs and outputs (general purpose I/O)
Alternate input/output for on-chip peripherals
Input and output drivers are disabled during power save mode
Supports single 2 phase stepper motor (i.e using 4 HCPADA port pins)
Supports LED drive
Slew rate control
Overcurrent Protection Enable control
Overcurrent Detect indication & shutdown
Able to trigger TRAP function during an overcurrent event
High Current Bidirectional Port Type B (HCPADB) Features:
•
Configurable pin direction
User’s Manual
11-1
V1.1, 2010-09
XC83x
Parallel Ports
•
•
•
•
•
•
Configurable pull-up/pull-down devices
Configurable open drain mode
Transfer data through digital inputs and outputs (general purpose I/O)
Alternate input/output for on-chip peripherals
Input and output drivers are disabled during power save mode
Supports LED drive
Standard Bidirectional Port Features:
•
•
•
•
•
•
Configurable pin direction
Configurable pull-up/pull-down devices
Configurable open drain mode
Transfer data through digital inputs and outputs (general purpose I/O)
Alternate input/output for on-chip peripherals
Input and output drivers are disabled during power save mode
Input Port Features:
•
•
•
•
•
•
Configurable input driver
Configurable pull-up/pull-down devices
Receive data through digital input (general purpose input)
Alternate input for on-chip peripherals
Analog input for ADC module
Input driver is disabled during power save mode
11.1
General Port Operation Description
Figure 11-1 shows the block diagram of a XC83x standard bidirectional port pin. Each
port pin is equipped with a number of control and data bits, thus enabling very flexible
usage of the pin. By defining the contents of the control register, each individual pin can
be configured as an input or an output. The user can also configure each pin as an open
drain pin with or without internal pull-up/pull-down device.
The input and output drivers of the standard bidirectional port are always enabled during
normal operation except in power-down mode. However, port pin(s) required as a wakeup source during power-down mode will not be disabled.
In output mode, the output driver drives the value supplied through the multiplexer to the
port pin. Each pin in output mode can be switched to open drain mode or normal mode
(push-pull mode) via the register Px_OD (x = 0, 1).
The output multiplexer in front of the output driver enables the port output function to be
used for different purposes. If the pin is used for general purpose output, the multiplexer
is switched by software to the data register Px_DATAOUT. Software can set or clear the
bit in Px_DATAOUT and therefore directly influence the state of the port pin. If an onchip peripheral uses the pin for output signals, alternate output lines (AltDataOut) can be
User’s Manual
11-2
V1.1, 2010-09
XC83x
Parallel Ports
switched via the multiplexer to the output driver circuitry. Selection of the alternate
function is defined in registers P0_ALTSEL0, P0_ALTSEL1, P0_ALTSEL2,
P1_ALTSEL0 and P1_ALTSEL1.
Internal
Bus
Px_PUDSEL
Pull -up/Pull -down
Select Register
Pull-up/Pull-down
Control Logic
Px_PUDEN
Pull -up/Pull -down
Enable Register
Px_OD
Open Drain
Control Register
Px_ALTSEL0
Alternate Select
Register 0
Px_ALTSEL1
Alternate Select
Register 1
Px_ALTSEL2
Pull
Device
Alternate Select
Register 2
AltDataOut 7
:
:
:
:
AltDataOut 1
Output
Driver
111
:
Pin
001
000
Input
Driver
Px_DATAOUT Out
Data Register
Schmitt
Trigger
Px_DATAIN
Port Output
Driver Control
Registers
Pad
AltDataIn
AnalogIn
Figure 11-1 General Structure of Standard Bidirectional Port and High Current
Bidirectional Port Type B
To configure the pin to input mode (default after reset), the output driver must be
switched to high-impedance using the following steps:
User’s Manual
11-3
V1.1, 2010-09
XC83x
Parallel Ports
•
•
•
Set output driver to high-impedance by writting ‘1’ to the port pin via register
Px_DATAOUT
Enable the open drain function via register Px_OD
Select normal GPIO as alternate output function via register Px_ALTSELx
Setting to normal GPIO alternate function is not necessary if the alternate output line is
ensured to held at high during input mode.
The actual voltage level present at the port pin is translated into a logic 0 or 1 via a
Schmitt-Trigger device and can be read via the register Px_DATAIN.
Each pin can also be programmed to activate an internal weak pull-up or pull-down
device. Register Px_PUDSEL selects whether a pull-up or the pull-down device is
activated while register Px_PUDEN enables or disables the pull device.
A following code shows the configuration of all Port 0 pins to input mode.
ANL
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
SYSCON0, #0xFE
PORT_PAGE, #0x00
P0_DATAOUT, #0xFF
PORT_PAGE, #0x03
P0_OD, #0xFF
PORT_PAGE, #0x02
P0_ALTSEL0, #0x00
P0_ALTSEL1, #0x00
P0_ALTSEL2, #0x00
User’s Manual
;Set P0_DATAOUT
;Enable open drain
;Select Alternate function as GPIO
;Px_ALTSELx in PORT_PAGE = 0x02
11-4
V1.1, 2010-09
XC83x
Parallel Ports
Figure 11-2 shows the block diagram of an high current bidirectional type A port pin in
XC83x. Besides the features of a standard bidirectional port pin, additional features are
included to support the direct drive of motor. One of the feature is the overcurrent
protection function that is controllable via Px_OCPEN. When the protection is enable, it
is able to provide self protection against overload condition by disabling the input and
output driver within the port. To recover from an overcurrent condition, the status flag,
Px_OCF needs to be cleared by software. Once the flag is cleared, the input and output
driver will be enabled. When overcurrent condition occurs, bit Px_OCF in Px_OCD
register is set to 1B. An interrupt can be triggered when an overcurrent event occurs if bit
Px_OCEN in Px_OCD register is set to 1B. In addition, the slew rate of the port can be
selected using Px_SLEW register.
The TRAP function from the CCU6 module could be triggered when an overcurrent event
happened by setting CCU6_PISEL0L.ISTRP[7:6] to 01B or 10B.
Type B of the high current bidirectional port do not have the overcurrent protection and
detection functions and the block diagram is similiar to the standard bidirectional port as
shown in Figure 11-1. This type of port has a high sink capability to support LED
application.
User’s Manual
11-5
V1.1, 2010-09
XC83x
Parallel Ports
Px_SLEW
Slew Rate Control
Register
Px_OCD
Overcurrent Detect
Register
Input /output
Drivers Control
Logic
Px_OCPEN
Overcurrent Protection
Enable Register
Internal
Bus
Px_PUDSEL
Pull -up/Pull -down
Select Register
Pull-up/Pull-down
Control Logic
Px_PUDEN
Pull -up/Pull -down
Enable Register
Px_OD
Open Drain
Control Register
Px_ALTSEL0
Alternate Select
Register 0
Px_ALTSEL1
Alternate Select
Register 1
Pull
Device
AltDataOut 3
:
:
:
:
AltDataOut 1
Output
Driver
11
:
01
00
Overcurrent
Detection
Device
Pin
Input
Driver
Px_DATAOUT Out
Data Register
Schmitt
Trigger
Px_DATAIN
Port Output
Driver Control
Registers
Pad
AltDataIn
AnalogIn
Figure 11-2 General Structure of High Current Bidirectional Port Type A
User’s Manual
11-6
V1.1, 2010-09
XC83x
Parallel Ports
Figure 11-3 shows the structure of an input-only port pin. Each P2 pin can only function
in input mode. Register P2_EN is provided to enable or disable the input driver. When
the input driver is enabled, the actual voltage level present at the port pin is translated
into a logic 0 or 1 via a Schmitt-Trigger device and can be read via the register
P2_DATAIN. Each pin can also be programmed to activate an internal weak pull-up or
pull-down device. Register P2_PUDSEL selects whether a pull-up or the pull-down
device is activated while register P2_PUDEN enables or disables the pull device. The
analog input (AnalogIn) bypasses the digital circuitry and Schmitt-Trigger device for
direct feed-through to the ADC input channel.
Internal
Bus
Px_PUDSEL
Pull-up/Pull-down
Select Register
Pull-up/Pull-down
Control Logic
Px_PUDEN
Pull-up/Pull-down
Enable Register
Px_EN
Input Control Register
Pull
Device
Px_DATAIN
Input
Driver
In
Pin
Data Register
Schmitt
Trigger
Pad
AltDataIn
AnalogIn
Figure 11-3 General Structure of Input Port
User’s Manual
11-7
V1.1, 2010-09
XC83x
Parallel Ports
11.1.1
General Register Description
This section describes the SFR registers available on the XC83x module.
11.1.1.1 Register Map
The Port SFRs are located in the standard memory area (RMAP = 0) and are organized
into 4 pages. The PORT_PAGE register is located at address 8EH. It contains the page
value and page control information.
The addresses of the Port SFRs are listed in Table 11-2.
Table 11-2
SFR Address List for Pages 0-3
Address
Page 0
Page 1
Page 2
Page 3
80H
P0_DATAOUT
P0_PUDSEL
P0_ALTSEL0
P0_OD
86H
P0_DATAIN
P0_PUDEN
P0_ALTSEL1
P0_ALTSEL2
85H
90H
P1_DATAOUT
P1_PUDSEL
P1_ALTSEL0
91H
P1_DATAIN
P1_PUDEN
P1_ALTSEL1
92H
P1_OCD
P1_OCPEN
93H
P1_OD
P1_SLEW
P2_PUDSEL
94H
P2_DATAIN
P2_PUDEN
C8H
P3_DATAOUT
P3_PUDSEL
P3_ALTSEL0
C9H
P3_DATAIN
P3_PUDEN
P3_ALTSEL1
PORT_PAGE
Page Register for PORT
RMAP: 0, PAGE: X
7
6
P2_EN
(8EH)
5
4
P3_OD
Reset Value: 00H
3
2
1
OP
STNR
0
PAGE
w
w
r
rwh
User’s Manual
11-8
0
V1.1, 2010-09
XC83x
Parallel Ports
Field
Bits
Type Description
PAGE
[2:0]
rwh
Page Bits
When written, the value indicates the new page
address.
When read, the value indicates the currently active
page = addr [y:x+1]
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the
target of the operation defined by bit OP.
If OP = 10B,
the contents of PAGE are saved in PORT_STx
before being overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the
contents of PORT_STx. The value written to the bit
positions of PAGE is ignored.
00
PORT_ST0 is selected.
01
PORT_ST1 is selected.
10
PORT_ST2 is selected.
11
PORT_ST3 is selected.
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is
ignored and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the former
contents of PAGE are saved in the storage bit
field PORT_STx indicated by STNR.
11
Automatic restore page action. The value
written to the bit positions PAGE is ignored
and instead, PAGE is overwritten by the
contents of the storage bit field PORT_STx
indicated by STNR.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
11-9
V1.1, 2010-09
XC83x
Parallel Ports
11.1.1.2 Register Overview
The individual control and data bits of each parallel port are implemented in a number of
8-bit registers. Bits with the same meaning and function are assembled together in the
same register. The registers configure and use the port as general purpose I/O or
alternate function input/output.
For port P0 and P2, not all the registers in Table 11-3 are implemented. The availability
and definition of registers specific to each port is defined in Section 11.2 to
Section 11.5. This section provides only an overview of the different port registers.
Table 11-3
Port Registers
Register Short Name
Register Long Name
Description
Px_DATAOUT
Port x Data Out Register
Page 11-11
Px_DATAIN
Port x Data In Register
Page 11-11
Px_OD
Port x Open Drain Control Register
Page 11-12
Px_PUDSEL
Port x Pull-Up/Pull-Down Select Register
Page 11-12
Px_PUDEN
Port x Pull-Up/Pull-Down Enable Register
Page 11-12
Px_ALTSEL0
Port x Alternate Select Register 0
Page 11-13
Px_ALTSEL1
Port x Alternate Select Register 1
Page 11-13
Px_ALTSEL2
Port x Alternate Select Register 2
Page 11-13
Px_OCD
Port x Overcurrent Detect Register
Page 11-15
Px_OCPEN
Port x Overcurrent Protection Enable Register Page 11-16
Px_SLEW
Port x Slew Rate Control Register
Page 11-16
Px_EN
Port x Input Control Register
Page 11-17
Note: Not all the registers are implemented for each port.
User’s Manual
11-10
V1.1, 2010-09
XC83x
Parallel Ports
Port Data Out Register
If a port pin is used as general purpose output, output data is written into register
Px_DATAOUT of port x.
A read operation of Px_DATAOUT returns the register value and not the state of the
Px_DATAOUT pins.
Px_DATAOUT
Port x Data Out Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
Port x Pin n Data Value
0
Port x pin n data value = 0
1
Port x pin n data value = 1 (default)
Port Data In Register
If a port pin is used as general purpose input, the value at a port pin can be read through
the register Px_DATAIN. The data register Px_DATAIN always contains a latched value
of the assigned port pin, even if the port pin is assigned as output.
Px_DATAIN
Port x Data In Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rh
User’s Manual
Port x Pin n Data Value
0
Port x pin n data value = 0
1
Port x pin n data value = 1
11-11
V1.1, 2010-09
XC83x
Parallel Ports
Open Drain Control Register
Each pin in output mode can be switched to open drain mode. If driven with 1, no driver
will be activated and the pin output state depends on the internal pull-up/pull-down
device setting; if driven with 0, the driver’s pull-down transistor will be activated.
The open drain mode is controlled by the register Px_OD.
Px_OD
Port x Open Drain Control Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
Port x Pin n Open Drain Mode
0
Normal Mode, output is actively driven for 0
and 1 state
1
Open Drain Mode, output is actively driven
only for 0 state (default)
Pull-Up/Pull-Down Device Register
Internal pull-up/pull-down devices can be optionally applied to a port pin. This offers the
possibility to configure the following input characteristics:
•
•
•
Tristate
High-impedance with a weak pull-up device
High-impedance with a weak pull-down device
and the following output characteristics:
•
•
•
Push/pull (optional pull-up/pull-down)
Open drain with internal pull-up
Open drain with external pull-up
The pull-up/pull-down device can be fixed or controlled via the registers Px_PUDSEL
and Px_PUDEN. Register Px_PUDSEL selects the type of pull-up/pull-down device,
while register Px_PUDEN enables or disables it. The pull-up/pull-down device can be
selected pinwise.
User’s Manual
11-12
V1.1, 2010-09
XC83x
Parallel Ports
Px_PUDSEL
Port x Pull-Up/Pull-Down Select Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
Pull-Up/Pull-Down Select Port x Bit n
0
Pull-down device is selected
1
Pull-up device is selected
Px_PUDEN
Port x Pull-Up/Pull-Down Enable Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
Pull-Up/Pull-Down Enable at Port x Bit n
0
Pull-up or Pull-down device is disabled
1
Pull-up or Pull-down device is enabled
Alternate Input Functions
The number of alternate functions that uses a pin for input is not limited. Each port control
logic of an I/O pin provides several input paths of digital input value via register. These
port input selection registers are described in each peripheral chapter.
Alternate Output Functions
Alternate functions are selected via an output multiplexer which can select up to eight
output lines. This multiplexer can be controlled by the following signals:
•
•
•
Register Px_ALTSEL0
Register Px_ALTSEL1
Register Px_ALTSEL2
User’s Manual
11-13
V1.1, 2010-09
XC83x
Parallel Ports
Selection of alternate functions is defined in registers Px_ALTSEL0, Px_ALTSEL1 and
Px_ALTSEL2. Px_ALTSEL2 is optional for ports that does not required more than 4
alternate functions.
Note: Set Px_ALTSEL0.Pn, Px_ALTSEL1.Pn and Px_ALTSEL2.Pn to select only
implemented alternate output functions.
Px_ALTSELn (n = 0, 1, 2)
Port x Alternate Select Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
User’s Manual
Pin Output Functions
Configuration of Px_ALTSEL0.Pn, Px_ALTSEL1.Pn
and Px_ALTSEL2.Pn for GPIO or alternate settings:
000 Normal GPIO
001 Alternate Select 1
010 Alternate Select 2
011 Alternate Select 3
100 Alternate Select 4
101 Alternate Select 5
110 Alternate Select 6
111 Alternate Select 7
11-14
V1.1, 2010-09
XC83x
Parallel Ports
Overcurrent Detect Register
Each port pin have a overcurrent detect circuitry which will set the Px_OCF bit on the
overcurrent detect register when overcurrent condition is detected. Concurrently, an
interrupt is generated if bit Px_OCEN is set to 1.
Px_OCD
Port x Overcurrent Detect Register
7
6
5
4
P3_OCEN P2_OCEN P1_OCEN P0_OCEN
h
rw
rw
rw
3
2
1
0
P3_OCF
P2_OCF
P1_OCF
P0_OCF
rwh
rwh
rwh
rwh
rw
Field
Bits
Type Description
Pn_OCF
(n = 0 - 3)
n
rwh
Overcurrent Detected at High Current Port x Bit n
0
No overcurrent condition. Upon writing a logic
“0” to this bit clears the latched register bit.
1
Overcurrent condition detected.
Pn_OCEN
(n = 0 - 3)
n
rw
Overcurrent Interrupt Enable at High current Port
x Bit n
0
The overcurrent interrupt is disabled.
1
The overcurrent interrupt is enabled.
User’s Manual
11-15
V1.1, 2010-09
XC83x
Parallel Ports
Overcurrent Protection Enable Register
When the Overcurrent Protection Enable Register is enabled and the overcurrent detect
register is latched (i.e indicating a overcurrent condition occured), the input and output
driver of the high current port would be disabled automatically
Px_OCPEN
Port x Overcurrent Protection Enable Register
7
6
5
4
3
2
1
0
0
P3
P2
P1
P0
r
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 3)
n
rw
Overcurrent Protection Enable at High Current
Port x Bit n
0
Overcurrent Protection Disabled.
1
Overcurrent Protection Enabled.
Slew Register
Slew register controls the slew rate of each high current port.
Px_SLEW
Port x Slew Register
7
6
5
4
3
2
1
0
0
P3
P2
P1
P0
r
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 3)
n
rw
User’s Manual
Slew Rate Control at High Current Port x Bit n
0
Fast Edge is selected
1
Slow Edge is selected
11-16
V1.1, 2010-09
XC83x
Parallel Ports
Input Control Register
Input control register controls the input driver of each port pin. This register is use in port
P2.
Px_EN
Port x Input Control Register
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
User’s Manual
Input Driver Control at Port x Bit n
0
Input driver is enabled
1
Input driver is disabled
11-17
V1.1, 2010-09
XC83x
Parallel Ports
11.2
Port 0
Port 0 is a 8-bit general purpose bidirectional port. It uses the standard bidirectional pad
for each pin. The registers of Port 0 are summarized in Table 11-4.
Table 11-4
Port 0 Registers
Register Short Name Register Long Name
P0_DATAIN
Port 0 Data In Register
P0_DATAOUT
Port 0 Data Out Register
P0_OD
Port 0 Open Drain Control Register
P0_PUDSEL
Port 0 Pull-Up/Pull-Down Select Register
P0_PUDEN
Port 0 Pull-Up/Pull-Down Enable Register
P0_ALTSEL0
Port 0 Alternate Select Register 0
P0_ALTSEL1
Port 0 Alternate Select Register 1
P0_ALTSEL2
Port 0 Alternate Select Register 2
11.2.1
Functions
Port 0 input and output functions are shown in Table 11-5.
Table 11-5
Port 0 Input/Output Functions
Port Pin
Input/Output Select
Connected Signal(s)
P0.0
Input
P0_DATAIN.P0
Output
User’s Manual
GPI
From/to Module
ALT1
T2_0
Timer 2
ALT2
T13HR_1
CCU6
ALT3
MTSR_2
SSC
ALT4
MRST_3
SSC
ALT5
T12HR_0
CCU6
ALT6
CCPOS0_0
CCU6
ALT7
TSIN0
LEDTSCU
GPO
P0_DATAOUT.P0
ALT1
LINE0/TSIN0
LEDTSCU
ALT2
MTSR_2
SSC
ALT3
COUT61_1
CCU6
11-18
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-5
Port 0 Input/Output Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
P0.1
Input
GPI
P0_DATAIN.P1
ALT1
T0_0
Timer 0
ALT2
CC61_1
CCU6
ALT3
MTSR_3
SSC
ALT4
MRST_2
SSC
ALT5
T13HR_0
CCU6
Output
P0.2
Input
Output
User’s Manual
From/to Module
ALT6
CCPOS1_0
CCU6
ALT7
TSIN1
LEDTSCU
GPO
P0_DATAOUT.P1
ALT1
LINE1/TSIN1
LEDTSCU
ALT2
MRST_2
SSC
ALT3
CC61_1
CCU6
GPI
P0_DATAIN.P2
ALT1
T1_0
Timer 1
ALT2
CC62_1
CCU6
ALT3
SCL_1
IIC
ALT4
–
ALT5
–
ALT6
CCPOS2_0
CCU6
ALT7
TSIN2
LEDTSCU
GPO
P0_DATAOUT.P2
ALT1
LINE2/TSIN2
LEDTSCU
ALT2
SCL_1
IIC
ALT3
CC62_1
CCU6
11-19
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-5
Port 0 Input/Output Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
P0.3
Input
GPI
P0_DATAIN.P3
ALT1
–
ALT2
CC60_1
CCU6
ALT3
SDA_1
IIC
ALT4
–
ALT5
–
Output
P0.4
Input
Output
User’s Manual
From/to Module
ALT6
CTRAP_0
CCU6
ALT7
TSIN3
LEDTSCU
GPO
P0_DATAOUT.P3
ALT1
LINE3/TSIN3
SSC
ALT2
SDA_1
IIC
ALT3
CC60_1
CCU6
GPI
P0_DATAIN.P4
ALT1
T2EX_1
Timer 2
ALT2
SCL_0
IIC
ALT3
SCK_0
SSC
ALT4
–
ALT5
EXINT1_0
SCU
ALT6
CTRAP_1
CCU6
ALT7
TSIN4
LEDTSCU
GPO
P0_DATAOUT.P4
ALT1
LINE4/TSIN4
LEDTSCU
ALT2
SCK_0
SSC
ALT3
EXF2_0
Timer 2
ALT4
SCL_0
IIC
ALT5
COL0_1
LEDTSCU
ALT6
COL3_2
LEDTSCU
ALT7
COLA_4
LEDTSCU
11-20
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-5
Port 0 Input/Output Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
P0.5
Input
P0_DATAIN.P5
Output
User’s Manual
GPI
From/to Module
ALT1
RXD_0
UART
ALT2
MTSR_0
SSC
ALT3
MRST_1
SSC
ALT4
EXINT0_0
SCU
ALT5
–
ALT6
TSIN5
GPO
P0_DATAOUT.P5
ALT1
LINE5/TSIN5
LEDTSCU
ALT2
MTSR_0
SSC
ALT3
COUT62_1
CCU6
ALT4
TXD_4
UART
LEDTSCU
ALT5
COL1_1
LEDTSCU
ALT6
EXF2_3
Timer 2
11-21
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-5
Port 0 Input/Output Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
P0.6
Input
P0_DATAIN.P6
Output
User’s Manual
GPI
From/to Module
ALT1
RXD_1
UART
ALT2
SDA_0
IIC
ALT3
MTSR_1
SSC
ALT4
MRST_0
SSC
ALT5
EXINT0_1
SCU
ALT6
T2EX_0
Timer 2
ALT7
TSIN6
LEDTSCU
OTHERS
SPD_1
SPD
GPO
P0_DATAOUT.P6
ALT1
LINE6/TSIN6
LEDTSCU
ALT2
MRST_0
SSC
ALT3
TXD_0
UART
ALT4
SDA_0
IIC
ALT5
COL2_1
LEDTSCU
ALT6
COLA_2
LEDTSCU
OTHERS
SPD_1
SPD
11-22
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-5
Port 0 Input/Output Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
P0.7
Input
GPI
P0_DATAIN.P7
ALT1
–
ALT2
SCL_3
ALT3
–
ALT4
–
ALT5
–
ALT6
–
ALT7
TSIN7
GPO
P0_DATAOUT.P7
ALT1
LINE7/TSIN7
LED/TS
ALT2
TXD_5
UART
ALT3
COUT63_0
CCU6
Output
User’s Manual
From/to Module
IIC
LED/TS
ALT4
SCL_3
IIC
ALT5
COL3_1
LED/TS
ALT6
COLA_3
LED/TS
11-23
V1.1, 2010-09
XC83x
Parallel Ports
11.2.2
Registers Description
P0_DATAIN
Port 0 Data In Register
RMAP: 0, PAGE: 0
(86H)
Reset Value: XXH
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rh
Port 0 Pin n Data Value
0
Port 0 pin n data value = 0
1
Port 0 pin n data value = 1
P0_DATAOUT
Port 0 Data Output Register
RMAP: 0, PAGE: 0
(80H)
Reset Value: FFH
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
User’s Manual
Port 0 Pin n Data Value
0
Port 0 pin n data value = 0
1
Port 0 pin n data value = 1
11-24
V1.1, 2010-09
XC83x
Parallel Ports
P0_OD
Port 0 Open Drain Control Register
RMAP: 0, PAGE: 3
(80H)
Reset Value: FFH
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
Port 0 Pin n Open Drain Mode
0
Normal Mode, output is actively driven for 0 and
1 state
1
Open Drain Mode, output is actively driven only
for 0 state (default)
P0_PUDSEL
Port 0 Pull-Up/Pull-Down Select Register(80H)
RMAP: 0, PAGE: 1
Reset Value: EFH
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
Pull-Up/Pull-Down Select Port 0 Bit n
0
Pull-down device is selected
1
Pull-up device is selected (default)
P0_PUDEN
Port 0 Pull-Up/Pull-Down Enable Register(86H)
RMAP: 0, PAGE: 1
Reset Value: 50H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
User’s Manual
11-25
V1.1, 2010-09
XC83x
Parallel Ports
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
Pull-Up/Pull-Down Enable at Port 0 Bit n
0
Pull-up or Pull-down device is disabled
1
Pull-up or Pull-down device is enabled
Note: P0.4 has a default pull down device enabled which will be changed to pull up
device enabled by firmware in the startup code.
P0_ALTSEL0
Port 0 Alternate Select Register 0
RMAP: 0, PAGE: 2
(80H)
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
See Table 11-6
P0_ALTSEL1
Port 0 Alternate Select Register 1
RMAP: 0, PAGE: 2
(86H)
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
User’s Manual
See Table 11-6
11-26
V1.1, 2010-09
XC83x
Parallel Ports
P0_ALTSEL2
Port 0 Alternate Select Register 2
RMAP: 0, PAGE: 2
(85H)
Reset Value: 00H
7
6
5
4
3
2
1
P7
P6
P5
P4
0
rw
rw
rw
rw
r
0
Field
Bits
Type Description
Pn
(n = 4 - 7)
n
rw
See Table 11-6
0
[3:0]
r
Reserved
Returns 0 if read; should be written with 0.
Table 11-6
Function of Bits P0_ALTSEL2.Pn, P0_ALTSEL1.Pn and
P0_ALTSEL0.Pn
P0_ALTSEL2.Pn P0_ALTSEL1.Pn
P0_ALTSEL0.Pn
Function
0
0
0
Normal GPIO (default)
0
0
1
Alternate Select 1
0
1
0
Alternate Select 2
0
1
1
Alternate Select 3
1
0
0
Alternate Select 4
1
0
1
Alternate Select 5
1
1
0
Alternate Select 6
1
1
1
Alternate Select 7
User’s Manual
11-27
V1.1, 2010-09
XC83x
Parallel Ports
11.3
Port 1
Port 1 is a general purpose bidirectional port. In XC83x, P1.0, P1.1, P1.2 and P1.3 uses
the high current bidirectional port type A. As for P1.4 and P1.5, high current bidirectional
port type B is used for each pin. The registers of Port 1 are summarized in Table 11-7.
Table 11-7
Port 1 Registers
Register Short Name Register Long Name
P1_DATAOUT
Port 1 Data Out Register
P1_DATAIN
Port 1 Data In Register
P1_OD
Port 1 Open Drain Control Register
P1_PUDSEL
Port 1 Pull-Up/Pull-Down Select Register
P1_PUDEN
Port 1 Pull-Up/Pull-Down Enable Register
P1_ALTSEL0
Port 1 Alternate Select Register 0
P1_ALTSEL1
Port 1 Alternate Select Register 1
P1_OCD
Port 1 Overcurrent Detect Register
P1_OCPEN
Port 1 Overcurrent Protection Enable Register
P1_SLEW
Port 1 Slew Rate Control Register
User’s Manual
11-28
V1.1, 2010-09
XC83x
Parallel Ports
11.3.1
Functions
Port 1 input and output functions are shown in Table 11-8.
Table 11-8
Port 1 Input / Output Functions
Port Pin
Input/Output Select
P1.0
Input
Connected Signal(s)
GPI
P1_DATAIN.P0
ALT 1
RXD_2
UART
ALT 2
T2EX_2
Timer 2
ALT 3
–
ALT 4
–
ALT 5
EXINT0_2
ALT 6
–
OTHERS SPD_2
Output
GPO
P1_DATAOUT.P0
ALT 1
COL0_0
Input
Output
User’s Manual
SCU
SPD
LEDTSCU
ALT 2
COUT60_0
CCU6
ALT 3
TXD_1
UART
OTHERS SPD_2
P1.1
From/to Module
GPI
P1_DATAIN.P1
ALT 1
–
ALT 2
–
ALT 3
–
ALT 4
–
ALT 5
–
ALT 6
CC60_0
GPO
P1_DATAOUT.P1
SPD
CCU6
ALT 1
COL1_0
LEDTSCU
ALT 2
CC60_0
CCU6
ALT 3
TXD_2
UART
11-29
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-8
Port 1 Input / Output Functions (cont’d)
Port Pin
Input/Output Select
P1.2
Input
Output
P1.3
Input
Output
User’s Manual
Connected Signal(s)
GPI
P1_DATAIN.P2
ALT 1
–
ALT 2
–
ALT 3
–
ALT 4
–
ALT 5
EXINT4
ALT 6
–
GPO
P1_DATAOUT.P2
From/to Module
SCU
ALT 1
COL2_0
LEDTSCU
ALT 2
COUT61_0
CCU6
ALT 3
COUT63_1
CCU6
GPI
P1_DATAIN.P3
ALT 1
–
ALT 2
–
ALT 3
–
ALT 4
–
ALT 5
–
ALT 6
CC61_0
GPO
P1_DATAOUT.P3
CCU6
ALT1
COL3_0
LEDTSCU
ALT2
CC61_0
CCU6
ALT3
EXF2_2
Timer 2
11-30
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-8
Port 1 Input / Output Functions (cont’d)
Port Pin
Input/Output Select
P1.4
Input
Output
P1.5
Input
Output
User’s Manual
Connected Signal(s)
From/to Module
GPI
P1_DATAIN.P4
ALT 1
–
ALT 2
–
ALT 3
–
ALT 4
–
ALT 5
EXINT5
ALT 6
–
GPO
P1_DATAOUT.P4
ALT1
COL4
LEDTSCU
ALT2
COUT62_0
CCU6
ALT3
COUT63_2
CCU6
SCU
GPI
P1_DATAIN.P5
ALT 1
–
ALT 2
–
ALT 3
–
ALT 4
–
ALT 5
–
ALT 6
CC62_0
GPO
P1_DATAOUT.P5
ALT1
COL5
LEDTSCU
ALT2
CC62_0
CCU6
ALT3
COLA_1
LEDTSCU
11-31
CCU6
V1.1, 2010-09
XC83x
Parallel Ports
11.3.2
Registers Description
P1_DATAIN
Port 1 Data In Register
RMAP: 0, PAGE: 0
7
(91H)
6
Reset Value: XXH
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
Pn
(n = 0 - 5)
n
rh
Port 1 Pin n Data Value
0
Port 1 pin n data value = 0
1
Port 1 pin n data value = 1
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
P1_DATAOUT
Port 1 Data Out Register
RMAP: 0, PAGE: 0
7
6
(90H)
Reset Value: 3FH
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 5)
n
rw
Port 1 Pin n Data Value
0
Port 1 pin n data value = 0
1
Port 1 pin n data value = 1
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
11-32
V1.1, 2010-09
XC83x
Parallel Ports
P1_OD
Port 1 Open Drain Control Register
RMAP: 0, PAGE: 3
7
6
(90H)
Reset Value: 3FH
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 5)
n
rw
Port 1 Pin n Open Drain Mode
0
Normal Mode, output is actively driven for 0 and
1 state
1
Open Drain Mode, output is actively driven only
for 0 state (default)
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
P1_PUDSEL
Port 1 Pull-Up/Pull-Down Select Register(90H)
RMAP: 0, PAGE: 1
7
6
Reset Value: 3FH
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 5)
n
rw
Pull-Up/Pull-Down Select Port 1 Bit n
0
Pull-down device is selected
1
Pull-up device is selected (default)
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
11-33
V1.1, 2010-09
XC83x
Parallel Ports
P1_PUDEN
Port 1 Pull-Up/Pull-Down Enable Register(91H)
RMAP: 0, PAGE: 1
7
6
Reset Value: 00H
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 5)
n
rw
Pull-Up/Pull-Down Enable at Port 1 Bit n
0
Pull-up or Pull-down device is disabled (default)
1
Pull-up or Pull-down device is enabled
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
P1_ALTSELx (x = 0 - 1)
Port 1 Alternate Select Register
RMAP: 0, PAGE: 2
7
6
(90H + x)
Reset Value: 00H
5
4
3
2
1
0
0
P5
P4
P3
P2
P1
P0
r
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 5)
n
rw
See Table 11-9
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
Table 11-9
Function of Bits P1_ALTSEL0.Pn and P1_ALTSEL1.Pn
P1_ALTSEL1.Pn
P1_ALTSEL0.Pn
Function
0
0
Normal GPIO (default)
0
1
Alternate Select 1
User’s Manual
11-34
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-9
Function of Bits P1_ALTSEL0.Pn and P1_ALTSEL1.Pn (cont’d)
P1_ALTSEL1.Pn
P1_ALTSEL0.Pn
Function
1
0
Alternate Select 2
1
1
Alternate Select 3
P1_SLEW
Port 1 Slew Register
RMAP: 0, PAGE: 3
7
6
(92H)
5
4
Reset Value: 00H
3
2
1
0
0
P3
P2
P1
P0
r
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 3)
n
rw
Slew Rate Control at High Current Port 1 Bit n
0
Fast Edge is selected
1
Slow Edge is selected
0
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
P1_OCPEN
Port 1 Overcurrent Protection Enable Register (92H)
RMAP: 0, PAGE: 1
7
6
5
4
Reset Value: 00H
3
2
1
0
0
P3
P2
P1
P0
r
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 3)
n
rw
Overcurrent Protection Enable at High Current
Port 1 Bit n
0
Overcurrent Protection Disabled.
1
Overcurrent Protection Enabled.
0
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
11-35
V1.1, 2010-09
XC83x
Parallel Ports
P1_OCD
Port 1 Overcurrent Detect Register
RMAP: 0, PAGE: 0
7
6
5
(92H)
4
P3_OCEN P2_OCEN P1_OCEN P0_OCEN
h
rw
rw
rw
Reset Value: 00H
3
2
1
0
P3_OCF
P2_OCF
P1_OCF
P0_OCF
rwh
rwh
rwh
rwh
rw
Field
Bits
Type Description
Pn_OCF
(n = 0 - 3)
n
rwh
Overcurrent Detected at High Current Port 1 Bit n
0
No Overcurrent condition. Upon writing 0B to
this bit clears the latched register bit.
1
Overcurrent condition detected. This register
bit is latched.
Py_OCEN
(y = 0 - 3)
y+4
rw
Overcurrent Interrupt Enable at High current Port
1 Bit y
0
The overcurrent interrupt is disabled.
1
The overcurrent interrupt is enabled.
User’s Manual
11-36
V1.1, 2010-09
XC83x
Parallel Ports
11.4
Port 2
Port 2 is a general purpose input-only port. In XC83x, Port 2 has 8 pins, P2.0 - P2.7. The
registers of Port 2 are summarized in Table 11-10.
Table 11-10 Port 2 Registers
Register Short Name Register Long Name
P2_DATAIN
Port 2 Data Register
P2_EN
Port 2 Enable Register
P2_PUDSEL
Port 2 Pull-Up/Pull-Down Select Register
P2_PUDEN
Port 2 Pull-Up/Pull-Down Enable Register
User’s Manual
11-37
V1.1, 2010-09
XC83x
Parallel Ports
11.4.1
Functions
Port 2 input and output functions are shown in Table 11-11.
Table 11-11 Port 2 Input Functions
Port Pin
Input/Output Select
P2.0
Input
P2.1
P2.2
Input
Input
User’s Manual
Connected Signal(s)
From/to Module
GPI
P2_DATAIN.P0
ALT 1
CCPOS0_1
CCU6
ALT 2
T12HR_2
CCU6
ALT 3
T13HR_2
CCU6
ALT 4
T2EX_3
Timer 2
ALT 5
T2_1
Timer 2
ALT 6
EXINT0_3
SCU
ANALOG
AN0
ADC
GPI
P2_DATAIN.P1
ALT 1
CCPOS1_1
CCU6
ALT 2
RXD_5
UART
ALT 3
MTSR_6
SSC
ALT 4
–
ALT 5
T0_1
Timer 0
ALT 6
EXINT1_1
SCU
ANALOG
AN1
ADC
GPI
P2_DATAIN.P1
ALT 1
CCPOS2_1
CCU6
ALT 2
T12HR_3
CCU6
ALT 3
T13HR_3
CCU6
ALT 4
SCK_3
SSC
ALT 5
T1_1
Timer 1
ALT 6
EXINT2_0
SCU
ANALOG
AN2
ADC
11-38
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-11 Port 2 Input Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
P2.3
Input
GPI
P2_DATAIN.P3
ALT 1
CCPOS0_2
CCU6
ALT 2
CTRAP_2
CCU6
ALT 3
–
P2.4
P2.5
Input
Input
User’s Manual
From/to Module
ALT 4
–
ALT 5
T2_2
Timer 2
ALT 6
EXINT3
SCU
ANALOG
AN3
ADC
GPI
P2_DATAIN.P4
ALT 1
–
ALT 2
T12HR_5
CCU6
ALT 3
T13HR_5
CCU6
ALT 4
–
ALT 5
T2_3
ALT 6
–
ANALOG
AN4
GPI
P2_DATAIN.P5
ADC
ALT 1
–
ALT 2
T12HR_7
CCU6
ALT 3
T13HR_7
CCU6
ALT 4
–
ALT 5
–
ALT 6
–
ANALOG
AN5
11-39
ADC
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-11 Port 2 Input Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
P2.6
Input
GPI
P2_DATAIN.P6
ALT 1
–
ALT 2
–
ALT 3
–
P2.7
Input
User’s Manual
ALT 4
SCK_2
ALT 5
–
From/to Module
SSC
ALT 6
EXINT6
SCU
ANALOG
AN6
ADC
GPI
P2_DATAIN.P7
ALT 1
–
ALT 2
RXD_6
UART
ALT 3
T2EX_6
Timer 2
ALT 4
MTSR_7
SSC
ALT 5
–
ALT 6
EXINT0_4
SCU
ANALOG
AN7
ADC
11-40
V1.1, 2010-09
XC83x
Parallel Ports
11.4.2
Registers Description
P2_DATAIN
Port 2 Data Register
RMAP: 0, PAGE: 0
(94H)
Reset Value: XXH
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rh
Port 2 Pin n Data Value
0
Port 2 pin n data value = 0
1
Port 2 pin n data value = 1
P2_EN
Port 2 Enable Register
RMAP: 0, PAGE: 3
(94H)
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
Port 2 Pin n Input Driver Control
0
Input driver is enabled (default)
1
Input driver is disabled
P2_PUDSEL
Port 2 Pull-Up/Pull-Down Select Register(93H)
RMAP: 0, PAGE: 1
Reset Value: FFH
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
User’s Manual
11-41
V1.1, 2010-09
XC83x
Parallel Ports
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
Pull-Up/Pull-Down Select Port 2 Bit n
0
Pull-down device is selected
1
Pull-up device is selected (default)
P2_PUDEN
Port 2 Pull-Up/Pull-Down Enable Register(94H)
RMAP: 0, PAGE: 1
Reset Value: 00H
7
6
5
4
3
2
1
0
P7
P6
P5
P4
P3
P2
P1
P0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 7)
n
rw
User’s Manual
Pull-Up/Pull-Down Enable at Port 2 Bit n
0
Pull-up or Pull-down device is disabled (default)
1
Pull-up or Pull-down device is enabled
11-42
V1.1, 2010-09
XC83x
Parallel Ports
11.5
Port 3
Port 3 is a general purpose bidirectional port. The registers of Port 3 are summarized in
Table 11-12.
Table 11-12 Port 3 Registers
Register Short Name Register Long Name
P3_DATAIN
Port 3 Data In Register
P3_DATAOUT
Port 3 Data Out Register
P3_OD
Port 3 Open Drain Control Register
P3_PUDSEL
Port 3 Pull-Up/Pull-Down Select Register
P3_PUDEN
Port 3 Pull-Up/Pull-Down Enable Register
P3_ALTSEL0
Port 3 Alternate Select Register 0
P3_ALTSEL1
Port 3 Alternate Select Register 1
User’s Manual
11-43
V1.1, 2010-09
XC83x
Parallel Ports
11.5.1
Functions
Port 3 input and output functions are shown in Table 11-13.
Table 11-13 Port 3 Input/Output Functions
Port Pin
Input/Output Select
Connected Signal(s)
P3.0
Input
GPI
P3_DATAIN.P0
ALT1
–
ALT2
SCL_2
IIC
ALT3
SCK_1
SSC
ALT4
–
ALT5
EXINT2_1
Output
P3.1
Input
Output
User’s Manual
ALT6
–
GPO
P3_DATAOUT.P0
From/to Module
SCU
ALT1
COL6
LED/TS
ALT2
SCK_1
SSC
ALT3
SCL_2
IIC
ANALOG
XTAL4
XTAL OSC
GPI
P3_DATAIN.P1
ALT1
RXD_4
ALT2
RTCCLK
ALT3
MTSR_4
UART
ALT4
MRST_4
SSC
ALT5
EXINT0_5
SSC
ALT6
–
SCU
ANALOG
XTAL3
XTAL OSC
GPO
P3_DATAOUT.P1
ALT1
COLA_0
LED/TS
ALT2
MTSR_4
SSC
ALT3
EXF2_1
Timer 2
11-44
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-13 Port 3 Input/Output Functions (cont’d)
Port Pin
Input/Output Select
Connected Signal(s)
P3.2
Input
GPI
P3_DATAIN.P2
ALT1
RXD_3
UART
ALT2
SDA_2
IIC
ALT3
MTSR_5
SSC
Output
User’s Manual
From/to Module
ALT4
MRST_5
SSC
ALT5
EXINT0_6
SCU
ALT6
T2EX_7
Timer 2
OTHERS
SPD_0
SPD
GPO
P3_DATAOUT.P2
ALT1
TXD_3
UART
ALT2
MRST_5
SSC
ALT3
SDA_2
IIC
OTHERS
SPD_0
SPD
11-45
V1.1, 2010-09
XC83x
Parallel Ports
11.5.2
Register Description
P3_DATAIN
Port 3 Data In Register
RMAP: 0, PAGE: 0
7
(C9H)
6
5
4
Reset Value: XXH
3
2
1
0
0
P2
P1
P0
r
rh
rh
rh
Field
Bits
Type Description
Pn
(n = 0 - 2)
n
rh
Port 3 Pin n Data Value
0
Port 3 pin n data value = 0
1
Port 3 pin n data value = 1
0
[7:3]
r
Reserved
Returns 0 if read; should be written with 0.
P3_DATAOUT
Port 3 Data Out Register
RMAP: 0, PAGE: 0
7
6
(C8H)
5
4
Reset Value: 07H
3
2
1
0
0
P2
P1
P0
r
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 2)
n
rw
Port 3 Pin n Data Value
0
Port 3 pin n data value = 0
1
Port 3 pin n data value = 1
0
[7:3]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
11-46
V1.1, 2010-09
XC83x
Parallel Ports
P3_OD
Port 3 Open Drain Control Register
RMAP: 0, PAGE: 3
7
6
5
(C8H)
4
Reset Value: 07H
3
2
1
0
0
P2
P1
P0
r
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 2)
n
rw
Port 3 Pin n Open Drain Mode
0
Normal Mode, output is actively driven for 0 and
1 state (default)
1
Open Drain Mode, output is actively driven only
for 0 state
0
[7:3]
r
Reserved
Returns 0 if read; should be written with 0.
P3_PUDSEL
Port 3 Pull-Up/Pull-Down Select Register(C8H)
RMAP: 0, PAGE: 1
7
6
5
4
3
Reset Value: 07H
2
1
0
0
P2
P1
P0
r
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 2)
n
rw
Pull-Up/Pull-Down Select Port 3 Bit n
0
Pull-down device is selected
1
Pull-up device is selected (default)
0
[7:3]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
11-47
V1.1, 2010-09
XC83x
Parallel Ports
P3_PUDEN
Port 3 Pull-Up/Pull-Down Enable Register(C9H)
RMAP: 0, PAGE: 1
7
6
5
4
3
Reset Value: 07H
2
1
0
0
P2
P1
P0
r
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 2)
n
rw
Pull-Up/Pull-Down Enable at Port 3 Bit n
0
Pull-up or Pull-down device is disabled
1
Pull-up or Pull-down device is enabled (default)
0
[7:3]
r
Reserved
Returns 0 if read; should be written with 0.
P3_ALTSELx (x = 0 - 1)
Port 3 Alternate Select Register
RMAP: 0, PAGE: 2
7
6
5
(C8H + x)
4
Reset Value: 00H
3
2
1
0
0
P2
P1
P0
r
rw
rw
rw
Field
Bits
Type Description
Pn
(n = 0 - 2)
n
rw
See Table 11-14
0
[7:3]
r
Reserved
Returns 0 if read; should be written with 0.
Table 11-14 Function of Bits P3_ALTSEL0.Pn and P3_ALTSEL1.Pn
P3_ALTSEL1.Pn
P3_ALTSEL0.Pn
Function
0
0
Normal GPIO
0
1
Alternate Select 1
User’s Manual
11-48
V1.1, 2010-09
XC83x
Parallel Ports
Table 11-14 Function of Bits P3_ALTSEL0.Pn and P3_ALTSEL1.Pn (cont’d)
P3_ALTSEL1.Pn
P3_ALTSEL0.Pn
Function
1
0
Alternate Select 2
1
1
Alternate Select 3
User’s Manual
11-49
V1.1, 2010-09
XC83x
Multiplication/Division Unit
12
Multiplication/Division Unit
12.1
Overview
The Multiplication/Division Unit (MDU) provides fast 16-bit multiplication, 16-bit and
32-bit division as well as shift and normalize features. It has been integrated to support
the XC83x Core in real-time control applications, which require fast mathematical
computations.
The MDU uses a total of 14 registers; 12 registers for data manipulation, one register to
control the operation of MDU and one register for storing the status flags. These
registers are memory mapped as special function registers like any other registers for
peripheral control. The MDU operates concurrently with and independent of the CPU.
Features
•
•
•
•
•
•
Fast signed/unsigned 16-bit multiplication
Fast signed/unsigned 32-bit divide by 16-bit and 16-bit divide by 16-bit operations
Signed 16-bit multiplication with single left shift (to support fixed-point number
calculations in Q15 format)
Signed 32-bit divide by 16-bit with single right shift (to support fixed-point number
calculations in Q15 format)
32-bit unsigned normalize operation
32-bit arithmetic/logical shift operations
User’s Manual
MDU, V2.9
12-1
V1.1, 2010-09
XC83x
Multiplication/Division Unit
Table 5-1 specifies the number of clock cycles used for calculation in various operations.
Table 12-1
MDU Operation Characteristics
Operation
Result
Reminder
No. of Clock Cycles Used for
Calculation
Signed 32-bit/16-bit
32-bit
16-bit
33
Signed 32-bit/16-bit with
Single Right Shift
32-bit
16-bit
33
Signed 16-bit/16bit
16-bit
16-bit
17
Signed 16-bit x 16-bit
32-bit
–
16
Signed 16-bit x 16-bit with 32-bit
Single Left Shift
–
16
Unsigned 32-bit/16-bit
32-bit
16-bit
32
Unsigned 16-bit/16-bit
16-bit
16-bit
16
Unsigned 16-bit x 16-bit
32-bit
–
16
32-bit normalize
–
–
No. of shifts + 1 (Max. 32)
32-bit shift L/R
–
–
No. of shifts + 1 (Max. 32)
12.2
System Information
This section provides system information relevant to the MDU.
12.2.1
Clocking Configuration
The MDU runs on the FPCLK at a fixed frequency of 48 MHz.
If the MDU functionality is not required at all, it can be completely disabled by gating off
its clock input for maximal power reduction. This is done by setting bit MDU_DIS in
register PMCON1 as described below.
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
PMCON1 register.
PMCON1
Peripheral Management Control Register 1(EFH)
RMAP: 0, PAGE: 1
7
6
IIC_DIS
LTS_DIS
rw
rw
User’s Manual
MDU, V2.9
5
4
CDC_DIS MDU_DIS
rw
rw
12-2
Reset Value: FFH
3
2
1
0
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
rw
rw
rw
rw
V1.1, 2010-09
XC83x
Multiplication/Division Unit
Field
Bits
Type Description
MDU_DIS
4
rw
12.2.2
MDU Disable Request. Active high.
0
MDU is in normal operation.
1
Request to disable the MDU. (default)
Interrupt Events and Assignment
Table 1-1 lists the interrupt event sources from the MDU, and the corresponding event
interrupt enable bit and flag bit.
Table 12-2
MDU Interrupt Events
Event
Event Interrupt Enable Bit
Event Flag Bit
End-of-Calculation
MDUCON.IE
MDUSTAT.IRDY
Occurrence-of-Error
MDUSTAT.IERR
Table 1-2 shows the interrupt node assignment for each MDU interrupt source.
Table 12-3
MDU Events’ Interrupt Node Control
Event
Interrupt Node
Enable Bit
Interrupt Node Flag Vector
Bit
Address
End-of-Calculation
IEN1.EX2
–
43H
Occurrence-of-Error
12.3
Functional Description
The MDU can be regarded as a special coprocessor for multiplication, division,
normalization and shift. Its operation can be divided into three phases (see Figure 12-1).
Phase One: Load MDx Registers
In this phase, the operands are loaded into the MDU Operand (MDx) registers by the
CPU.
The type of calculation the MDU must perform is selected by writing a 4-bit opcode that
represents the required operation into the bit field MDUCON.OPCODE.
Phase Two: Execute Calculation
This phase commences only when the start bit MDUCON.START is set, which in turn
sets the busy flag. The start bit is automatically cleared in the next cycle.
User’s Manual
MDU, V2.9
12-3
V1.1, 2010-09
XC83x
Multiplication/Division Unit
During this phase, the MDU works on its own, in parallel with the CPU. The result of the
calculation is made available in the MDU Result (MRx) registers at the end of this phase.
Phase Three: Read Result from the MRx Registers
In this final phase, the result is fetched from the MRx registers by the CPU. The MRx
registers will be overwritten at the start of the next calculation phase.
First Write
Start bit is
set
First Read
Phase 1
Load Registers
Phase 2
Calculate
Last Read
Phase 3
Read Registers
Time
Figure 12-1 Operating Phases of the MDU
12.3.1
Division
The MDU supports the truncated division operation, which is also the ISO C99 standard
and the popular choice among modern processors. The division and modulus functions
of the truncated division are related in the following way:
If q = D div d
and r = D mod d
then D = q * d + r
and | r | < | d |
where “D” is the dividend, “d” is the divisor, “q” is the quotient and “r” is the remainder.
The truncated division rounds the quotient towards zero and the sign of its remainder is
always the same as that of its dividend, i.e., sign (r) = sign (D).
User’s Manual
MDU, V2.9
12-4
V1.1, 2010-09
XC83x
Multiplication/Division Unit
12.3.2
Normalize
The MDU supports up to 32-bit unsigned normalize.
Normalizing is done on an unsigned 32-bit variable stored in MD0 (least significant byte)
to MD3 (most significant byte). This feature is mainly meant to support applications
where floating point arithmetic is used. During normalization, all leading zeros of an
unsigned 32-bit variable in registers MD0 to MD3 are removed by shift left operations.
The whole operation is completed when the MSB (most significant bit) contains a 1.
After normalizing, bit field MR4.SCTR contains the number of shift left operations that
were done. This number may be used later as an exponent. The maximum number of
shifts in a normalize operation is 31 (= 25 - 1).
12.3.3
Shift
The MDU implements both logical and arithmetic shifts to support up to 32-bit unsigned
and signed shift operations.
During logical shift, zeros are shifted in from the left end of register MD3 or right end of
register MD0. An arithmetic left shift is identical to a logical left shift, but during arithmetic
right shifts, signed bits are shifted in from the left end of register MD3. For example, if
the data 0101B and 1010B are to undergo an arithmetic shift right, the results obtained
will be 0010B and 1101B, respectively.
For any shift operation, register bit MD4.SLR specifies the shift direction, and
MD4.SCTR the shift count.
Note: The MDU does not detect overflows due to an arithmetic shift left operation. User
must always ensure that the result of an arithmetic shift left is within the
boundaries of MDU.
12.3.4
Multiplication with Single Left Shift
The multiplication with single left shift is similar to a signed 16-bit multiplication except
that after the multiplication, the MDU performs a single left shift on the product.
This operation can be used to facilitate signed fixed-point number multiplications in Q151)
format. Multiplication of two Q15 numbers will result in a Q1.30 fixed-point product. A
single left shift on this product gives a Q31 value and the product in Q15 format can be
obtained by taking only the upper 16-bit of the 32-bit value.
1) The Q number is a fixed point number representation that takes the form Qx.y, where x is the number of bits
in the integer portion of the number (default is 0) while y is the number of bits in the fractional portion. The
signed bit is always excluded from the Qx.y notation.
User’s Manual
MDU, V2.9
12-5
V1.1, 2010-09
XC83x
Multiplication/Division Unit
12.3.5
Division with Single Right Shift
The division with single right shift is similar to a signed 32-bit by 16-bit division except
that the MDU performs a single right shift first before the division.
This operation can be used to facilitate signed 16-bit by 16-bit fixed point number
divisions in Q15 format. Normally to divide a Q15 fixed number by another and obtain a
Q15 quotient, the dividend has to be scaled up first by a factor of 215 before performing
a 32-bit by 16-bit division.
User software can write the 16-bit dividend to the upper half-word of the 32-bit operand
(data) register and select the division with single right shift to have the same effect.
12.3.6
Busy Flag
A busy flag is provided to indicate the MDU is still performing a calculation. The flag
MDUSTAT.BSY is set at the start of a calculation and cleared after the calculation is
completed at the end of phase two. It is also cleared when the error flag is set.
If a second operation needs to be executed, the status of the busy flag will be polled first
and only when it is not set, can the start bit be written and the second operation begin.
Any unauthorized write to the start bit while the busy flag is still set will be ignored.
12.3.7
Error Detection
The error flag MDUSTAT.IERR is provided to indicate that an error has occurred while
performing a calculation. The flag is set by hardware when one of these occurs:
•
•
Division by zero
Writing of reserved opcodes to MDUCON register
The setting of the error flag causes the current operation to be aborted and triggers an
interrupt (see Section 12.4 below). A division by zero error does not set the error flag
immediately but rather, at the end of calculation phase for a division operation. An
opcode error is detected upon setting MDUCON.START to 1. Errors due to division by
zero lead to the loading of a saturated value into the MRx registers.
Note: The accuracy of any result obtained when the error flag is set is not guaranteed
by MDU and hence the result should not be used.
12.4
Interrupt Generation
The interrupt structure of the MDU is shown in Figure 12-2. There are two possible
interrupt events in the MDU, and each event sets one of the two interrupt flags. The
interrupt flags is reset by software by writing 0 to it.
At the end of phase two, the interrupt flag MDUSTAT.IRDY is set by hardware to indicate
the successful completion of a calculation. The results can then be obtained from the
MRx registers. The interrupt line INT_O0 is mapped directly to this interrupt source.
User’s Manual
MDU, V2.9
12-6
V1.1, 2010-09
XC83x
Multiplication/Division Unit
An interrupt can also be triggered when an error occurs during calculation. This is
indicated by the setting of the interrupt flag MDUSTAT.IERR. In the event of a division
by zero error, MDUSTAT.IERR is set only at the end of the calculation phase. Once the
MDUSTAT.IERR is set, any ongoing calculation will be aborted. For division by zero, a
saturated value is then loaded into the MRx registers. The bit MDUCON.IR determines
the interrupt line to be mapped to this interrupt source.
An interrupt is only generated when interrupt enable bit MDUCON.IE is 1 and the
corresponding interrupt event occurs. An interrupt request signal is always asserted
positively for 2 CCLK clocks.
int_reset_SW
reset
IRDY
set
Completion of
Calculation
&
to INT_O0
IE
int_reset_SW
to INT_O1
&
Occurrence
of Error
set
reset
IR
IERR
Figure 12-2 Interrupt Generation
User’s Manual
MDU, V2.9
12-7
V1.1, 2010-09
XC83x
Multiplication/Division Unit
12.5
Registers Description
The MDU Special Function Registers are accessed from the standard (non-mapped)
SFR area. Table 12-4 lists the MDU registers with their addresses.
Table 12-4
Register Map
SFR
Address
Name
MDU_MDUCON
B1H
MDU Control Register
MDU_MDUSTAT
B0H
MDU Status Register
MDU_MD0/MR0
B2H
MDU Data/Result Register 0
MDU_MD1/MR1
B3H
MDU Data/Result Register 1
MDU_MD2/MR2
B4H
MDU Data/Result Register 2
MDU_MD3/MR3
B5H
MDU Data/Result Register 3
MDU_MD4/MR4
B6H
MDU Data/Result Register 4
MDU_MD5/MR5
B7H
MDU Data/Result Register 5
The MDx and MRx registers share the same address. However, since MRx registers
should never be written to, any write operation to one of these addresses will be
interpreted as a write to an MDx register.
In the event of a read operation, an additional bit MDUCON.RSEL is needed to select
which set of registers, MDx or MRx, the read operation must be directed to. By default,
the MRx registers are read.
The 14 SFRs of the MDU consist of a control register MDUCON, a status register
MDUSTAT and 2 sets of data registers, MD0 to MD5 (which contain the operands) and
MR0 to MR5 (which contain the results).
Depending on the type of operation, the individual MDx and MRx registers assume
specific roles as summarized in Table 12-5 and Table 12-6. For example, in a
multiplication operation, the low byte of the 16-bit multiplicator must be written to register
MD4 and the high byte to MD5.
Table 12-5
MDx Registers
Register
Roles of Registers in Operations
16-bit
Multiplication
32/16-bit
Division
16/16-bit
Division
Normalize and
Shift
MD0
M’andL
D’endL
D’endL
OperandL
MD1
M’andH
D’end
D’endH
Operand
MD2
–
D’end
–
Operand
User’s Manual
MDU, V2.9
12-8
V1.1, 2010-09
XC83x
Multiplication/Division Unit
Table 12-5
MDx Registers (cont’d)
Register
Roles of Registers in Operations
16-bit
Multiplication
32/16-bit
Division
16/16-bit
Division
Normalize and
Shift
MD3
–
D’endH
–
OperandH
MD4
M’orL
D’orL
D’orL
Control
MD5
M’orH
D’orH
D’orH
–
Table 12-6
MRx Registers
Register
Roles of Registers in Operations
16-bit
Multiplication
MR0
PrL
32/16-bit
Division
16/16-bit
Division
Normalize and
Shift
QuoL
QuoL
ResultL
MR1
Pr
Quo
QuoH
Result
MR2
Pr
Quo
–
Result
MR3
PrH
QuoH
–
ResultH
MR4
M’orL
RemL
RemL
Control
MR5
M’orH
RemH
RemH
–
Abbreviations:
•
•
•
•
•
•
•
•
•
D’end: Dividend, 1st operand of division
D’or: Divisor, 2nd operand of division
M’and: Multiplicand, 1st operand of multiplication
M’or: Multiplicator, 2nd operand of multiplication
Pr: Product, result of multiplication
Rem: Remainder
Quo: Quotient, result of division
...L: means that this byte is the least significant of the 16-bit or 32-bit operand
...H: means that this byte is the most significant of the 16-bit or 32-bit operand
The MDx registers are built with shadow registers, which are latched with data from the
actual registers at the start of a calculation. This frees up the MDx registers to be written
with the next set of operands while the current calculation is ongoing.
MDx and MRx registers not used in an operation are undefined to the user. For normalize
and shift operations, the registers MD4 and MR4 are used as shift input and output
control registers to specify the shift direction and store the number of shifts performed.
User’s Manual
MDU, V2.9
12-9
V1.1, 2010-09
XC83x
Multiplication/Division Unit
12.5.1
Operand and Result Registers
The MDx and MRx registers are used to store the operands and results of a calculation.
MD4 and MR4 are also used as input and output control registers for shift and normalize
operations.
MDU_MDx (x = 0 - 5)
MDU Data Register x [Operand]
RMAP: 0, PAGE: X
7
6
5
(B2H + x * 1)
4
3
Reset Value: 00H
2
1
0
DATA
rw
Field
Bits
Type Description
DATA
[7:0]
rw
MDU_MRx (x = 0 - 5)
MDU Data Register x [Result]
RMAP: 0, PAGE: X
7
6
5
Operand Value
See Table 12-5.
(B2H + x * 1)
4
3
Reset Value: 00H
2
1
0
DATA
rh
Field
Bits
Type Description
DATA
[7:0]
rh
User’s Manual
MDU, V2.9
Result Value
See Table 12-6.
12-10
V1.1, 2010-09
XC83x
Multiplication/Division Unit
MDU_MD4
Shift Input Control Register
RMAP: 0, PAGE: X
7
6
5
(B6H)
4
Reset Value: 00H
3
2
0
SLR
SCTR
rw
rw
rw
1
0
Field
Bits
Type Description
SCTR
[4:0]
rw
Shift Counter
The count written to SCTR determines the number of
shifts to be performed during a shift operation.
SLR
5
rw
Shift Direction
Selects shift left operation.
0B
1B
Selects shift right operation.
0
[7:6]
rw
Reserved
Should be written with 0. Returns undefined data if
read.
MDU_MR4
Shift Output Control Register
RMAP: 0, PAGE: X
7
6
5
(B6H)
4
Reset Value: 00H
3
2
0
SCTR
rh
rh
1
0
Field
Bits
Type Description
SCTR
[4:0]
rw
Shift Counter
After a normalize operation, SCTR contains the
number of normalizing shifts performed.
0
[7:5]
rh
Reserved
Returns undefined data if read.
User’s Manual
MDU, V2.9
12-11
V1.1, 2010-09
XC83x
Multiplication/Division Unit
12.5.2
Control Register
Register MDUCON contains control bits that select and start the type of operation to be
performed.
MDU_MDUCON
MDU Control Register
RMAP: 0, PAGE: X
(B1H)
Reset Value: 00H
7
6
5
4
3
2
1
IE
IR
RSEL
START
OPCODE
rw
rw
rw
rwh
rw
0
Field
Bits
Type Description
OPCODE
[3:0]
rw
Operation Code
0000B Unsigned 16-bit Multiplication
0001B Unsigned 16-bit/16-bit Division
0010B Unsigned 32-bit/16-bit Division
0011B 32-bit Logical Shift L/R
0100B Signed 16-bit Multiplication
0101B Signed 16-bit/16-bit Division
0110B Signed 32-bit/16-bit Division
0111B 32-bit Arithmetic Shift L/R
1000B 32-bit Normalize
1001B Signed 16-bit Multiplication with Single Left
Shift
1010B Signed 32-bit/16-bit Division with Single Right
Shift
Others: Reserved
START
4
rwh
Start Bit
The bit START is set by software and reset by
hardware.
Operation is not started.
0B
Operation is started.
1B
RSEL
5
rw
Read Select
Read the MRx registers.
0B
1B
Read the MDx registers.
User’s Manual
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XC83x
Multiplication/Division Unit
Field
Bits
Type Description
IR
6
rw
Interrupt Routing
0B
The two interrupt sources have their own
dedicated interrupt lines.
The two interrupt sources share one interrupt
1B
line INT_O0.
IE
7
rw
Interrupt Enable
0B
The interrupt is disabled.
The interrupt is enabled.
1B
Note: Write access to MDUCON is not allowed when the busy flag MDUSTAT.BSY is
set during the calculation phase.
Note: Writing reserved opcode values to MDUCON results in an error condition when
MDUCON.START bit is set to 1.
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Multiplication/Division Unit
12.5.3
Status Register
Register MDUSTAT contains the status flags of the MDU.
MDU_MDUSTAT
MDU Status Register
RMAP: 0, PAGE: X
7
6
(B0H)
5
4
Reset Value: 00H
3
2
1
0
0
BSY
IERR
IRDY
r
rh
rwh
rwh
Field
Bits
Type Description
IRDY
0
rwh
Interrupt on Result Ready
The bit IRDY is set by hardware and reset by
software.
0B
No interrupt is triggered at the end of a
successful operation.
1B
An interrupt is triggered at the end of a
successful operation.
IERR
1
rwh
Interrupt on Error
The bit IERR is set by hardware and reset by
software.
No interrupt is triggered with the occurrence of
0B
an error.
An interrupt is triggered with the occurrence of
1B
an error.
BSY
2
rh
Busy Bit
0B
The MDU is not running any calculation.
The MDU is still running a calculation.
1B
0
[7:3]
r
Reserved
Returns 0 if read; should be written with 0.
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XC83x
CORDIC Coprocessor
13
CORDIC Coprocessor
This chapter describes the CORDIC Coprocessor.
13.1
Overview
This document describes the features of the CORDIC Coprocessor for XC800 product
family. It is not the purpose of this document to cover the theoretical background of the
CORDIC algorithm.
The CORDIC algorithm is a useful convergence method for computing trigonometric,
linear, hyperbolic and related functions. It allows performance of vector rotation not only
in the Euclidian plane, but also in the Linear and Hyperbolic planes.
The CORDIC algorithm is an iterative process where truncation errors are inherent.
Higher accuracy is achieved in the CORDIC Coprocessor with 16 iterations per
calculation and kernel data width of at least 20 bits. The main advantage of using this
algorithm is the low hardware costs involved compared to other complex algorithms.
The generalized CORDIC algorithm has the following CORDIC equations. The factor m
controls the vector rotation and selects the set of angles for the circular, linear and
hyperbolic function:
xi+1 = xi - m · di · yi · 2-i
(13.1)
yi+1 = yi + di · xi · 2-i
(13.2)
zi+1 = zi - di · ei
(13.3)
Where
m = 1 Circular function (basic CORDIC) with ei = atan(2-i)
m = 0 Linear function with ei = 2-i
m = -1 Hyperbolic function with ei = atanh(2-i)
For clarity, the document uses the following terms for referencing CORDIC data:
•
•
•
Result Data: Final result data at the end of CORDIC calculation (Bit BSY no longer
active).
Calculated Data: Intermediate or last data resulting from CORDIC iterations.
Initial Data: Data used for the very first CORDIC iteration, is usually user-initialized
data.
Features
The key features of the CORDIC Coprocessor are listed below.
•
Modes of operation
– Supports all CORDIC operating modes for solving circular (trigonometric), linear
(multiply-add, divide-add) and hyperbolic functions
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CORDIC Coprocessor
•
•
•
•
•
•
•
•
•
•
•
– Integrated look-up tables (LUTs) for all operating modes
Circular vectoring mode: Extended support for values of initial X and Y data up to full
range of [-215,(215-1)] for solving angle and magnitude
Circular rotation mode: Extended support for values of initial Z data up to full range
of [-215,(215-1)], representing angles in the range [-π,((215-1)/215)π] for solving
trigonometry
Gated clock input to support disabling of module
16-bit accessible data width
– 24-bit kernel data width plus 2 overflow bits for X and Y each
– 20-bit kernel data width plus 1 overflow bit for Z
– With KEEP bit to retain the last value in the kernel register for a new calculation
16 iterations per calculation: Approximately 41 clock-cycles or less, from set of start
(ST) bit to set of end-of-calculation flag, excluding time taken for write and read
access of data bytes.
Twos complement data processing
– Only exception: X result data with user selectable option for unsigned result
X and Y data generally accepted as integer or rational number; X and Y must be of
the same data form
Entries of LUTs are 20-bit signed integers
– Entries of atan and atanh LUTs are integer representations (S19) of angles with
the scaling such that [-215,(215-1)] represents the range [-π,((215-1)/215)π]
– Accessible Z result data for circular and hyperbolic functions is integer in data form
of S15
Emulated LUT for linear function
– Data form is 1 integer bit and 15-bit fractional part (1.15)
– Accessible Z result data for linear function is rational number with fixed data form
of S4.11 (signed 4Q16)
Truncation Error
– The result of a CORDIC calculation may return an approximation due to truncation
of LSBs
– Good accuracy of the CORDIC calculated result data, especially in circular mode
Interrupt
– On completion of a calculation
– Interrupt enabling and corresponding flag
13.2
System Information
This section provides system information relevant to the CORDIC Coprocessor.
13.2.1
Clocking Configuration
The CORDIC Coprocessor runs on the FPCLK at fixed frequency of 48 MHz.
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XC83x
CORDIC Coprocessor
If the CORDIC Coprocessor functionality is not required at all, it can be completely
disabled by gating off its clock input for maximal power reduction. This is done by setting
bit CDC_DIS in register PMCON1 as described below.
13.2.1.1 Peripheral Management Control Register 1
PMCON1
Peripheral Management Control Register 1(EFH)
RMAP: 0, PAGE: 1
7
6
5
IIC_DIS
LTS_DIS
rw
rw
4
CDC_DIS MDU_DIS
rw
3
2
1
0
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
rw
rw
rw
rw
rw
Field
Bits
Type Description
CDC_DIS
5
rw
13.2.2
Reset Value: FFH
CORDIC Disable Request. Active high.
0
CORDIC is in normal operation.
1
Request to disable the CORDIC. (default)
Interrupt Events and Assignment
Table 13-1 lists the interrupt event sources from the CORDIC Coprocessor, and the
corresponding event interrupt enable bit and flag bit.
Table 13-1
CORDIC Coprocessor Interrupt Events
Event
Event Interrupt Enable Bit
Event Flag Bit
End-of-Calculation
STATC.INT_EN
STATC.EOC
Table 13-2 shows the interrupt node assignment for each CORDIC Coprocessor
interrupt source.
Table 13-2
CORDIC Coprocessor Events’ Interrupt Node Control
Event
Interrupt Node
Enable Bit
Interrupt Node Flag Vector
Bit
Address
End-of-Calculation
IEN1.EX2
–
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CORDIC Coprocessor
13.3
Functional Description
The following sections describe the function of the CORDIC Coprocessor.
13.3.1
Operation of the CORDIC Coprocessor
The CORDIC Coprocessor can be used for the circular (trigonometric), linear (multiplyadd, divide-add) or hyperbolic function, in either rotation or vectoring mode. The modes
are selectable by software via the CD_CON control register.
Initialization of the kernel data register is enabled by clearing respective KEEP bits of the
register CD_CON. If ST_MODE = 1, writing 1 to bit ST starts a new calculation.
Otherwise, by default where ST_MODE = 0, a new calculation starts after a write access
to register CD_CORDXL. Each calculation involves a fixed number of 16 iterations. Bit
BSY is set while a calculation is in progress to indicate busy status. It is cleared by
hardware at the end of a calculation.
As the first step on starting a CORDIC calculation (provided the corresponding KEEP
bits are not set), the initial data is loaded from the data registers CD_CORDxL and
CD_CORDxH to the internal kernel data registers. During the calculation, the kernel data
registers always hold the latest intermediate data. On completion of the calculation, they
hold the result data.
The data registers CD_CORDxL and CD_CORDxH function as shadow registers which
can be written to without affecting an ongoing calculation. Values are transferred to the
kernel data registers only on valid setting of bit ST, or if ST_MODE = 0, after write access
to X low byte CD_CORDXL (provided KEEP bit of corresponding data is not set). The
result data must be read at the end of calculation (BSY no longer active) before starting
a new calculation. The result data is read directly from the kernel data registers with bit
CD_STATC.DMAP = 0. The kernel data is placed directly on the bus so the data
registers which function as shadow registers are not overwritten during this operation.
Alternatively, the shadow data registers are read (DMAP = 1), although this would be
merely reading back the user-initialized initial data.
At the end of each calculation, CD_STATC.BSY returns to 0, the End-of-Calculation
(EOC) flag is set and the interrupt request signal will be activated if interrupt is enabled
by INT_EN = 1. The result data in X, Y and Z are internally checked, and in case of data
overflow, the ERROR bit is set. This bit is automatically cleared on the start of a new
calculation, or when read.
On starting a new calculation, the kernel data registers can no longer be expected to hold
the result of the previous calculation. The kernel data registers always hold either the
initial value or the (intermediate) result of the last CORDIC iteration.
Setting the bit ST during an ongoing calculation while BSY is set has no effect. In order
to start a new calculation, bit ST must be set again at a later time when BSY is no longer
active. In the same manner, changing the operating mode during a running calculation
(as indicated by BSY) has no effect.
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CORDIC Coprocessor
13.3.2
Normalized Result Data
In all operating modes, the CORDIC Coprocessor returns a normalized result data for X
and Y, as shown in the following equation:
X or Y Result Data =
CORDIC Calculated Data
MPS
On the other hand, the interpretation for Z result data differs, which is also dependent on
the CORDIC function used:
For linear function, there is no additional processing of the CORDIC calculated Z data,
as such it is taken directly as the result data. The accessible Z result data is a real
number expressed as signed 4Q16.
For circular and hyperbolic functions, the accessible Z result data is a normalized
integer value, angles in the range [-π,((215-1)/215)π] are represented by [-215,(215-1)]. The
CORDIC Coprocessor expects Z data to be interpreted with this scaling:
Input Z Initial Data = Real Z Initial Value (in radians) x
Real Z Result Value (in radians) = Z Result Data x
32768
π
π
32768
The CORDIC calculated data includes an inherent gain factor Κ resulting from the
rotation or vectoring. The value Κ is different for each CORDIC function, as shown in
Table 13-3.
Table 13-3
CORDIC Function Inherent Gain Factor for Result Data
Function
Approximated Gain K
Circular
1.64676
Hyperbolic
0.828
Linear
1
13.3.3
CORDIC Coprocessor Operating Modes
Table 13-4 gives an overview of the CORDIC Coprocessor operating modes. In this
table, X, Y and Z represent the initial data, while Xfinal, Yfinal and Zfinal represent the final
result data when all processing is complete and BSY is no longer active.
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CORDIC Coprocessor
The CORDIC equations are:
xi+1 = xi - m · di · yi · 2-i
(13.4)
yi+1 = yi + di · xi · 2-i
(13.5)
zi+1 = zi - di · ei
(13.6)
Table 13-4
CORDIC Coprocessor Operating Modes and Corresponding Result
Data
Function
Rotation Mode
Vectoring Mode
Circular
m=1
ei = atan(2-i)
di = sign (zi), zi→0
Xfinal = K[X cos(Z) - Y sin(Z)] / MPS
Yfinal = K[Y cos(Z) + X sin(Z)] / MPS
Zfinal = 0
di = -sign (yi), yi→0
Xfinal = K sqrt(X2+Y2) / MPS
Yfinal = 0
Zfinal = Z + atan(Y / X)
For solving cos(Z) and sin(Z), set X
= 1 / K, Y = 0.
Useful domain: Full range of X, Y
and Z supported due to preprocessing logic.
For solving magnitude of vector
(sqrt(x2+y2)), set X = x / K, Y = y / K.
Useful domain: Full range of X and
Y supported due to pre- and postprocessing logic.
where K ≈ 1.64676
where K ≈ 1.64676
For solving atan(Y / X), set Z = 0.
Useful domain: Full range of X and
Y, except X = 0.
Linear
m=0
ei = 2-i
Relationships:
tan(v) = sin(v) / cos(v)
Relationships:
acos(w) = atan[sqrt(1-w2) / w]
asin(w) = atan[w / sqrt(1-w2)]
Xfinal = X / MPS
Yfinal = [Y + X Z] / MPS
Zfinal = 0
For solving X · Z, set Y = 0.
Useful domain: |Z| ≤ 2.
Xfinal = X / MPS
Yfinal = 0
Zfinal = Z + Y / X
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For solving ratio Y / X, set Z = 0.
Useful domain: |Y / X| ≤ 2, X > 0.
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CORDIC Coprocessor
Table 13-4
Function
CORDIC Coprocessor Operating Modes and Corresponding Result
Data
Rotation Mode
Vectoring Mode
Hyperbolic Xfinal = k[X cosh(Z) - Y sinh(Z)] /
m = -1
MPS
ei = atanh(2-i) Yfinal = k[Y cosh(Z) + X sinh(Z)] /
MPS
Zfinal = 0
where k ≈ 0.828
Xfinal = k sqrt(X2-Y2) / MPS
Yfinal = 0
Zfinal = Z + atanh(Y / X)
where k ≈ 0.828
For solving cosh(Z) and sinh(Z) and For solving sqrt(x2-y2), set X = x / k,
eZ, set X = 1 / k, Y = 0.
Y = y / k.
Useful domain: |Z| ≤ 1.11rad, Y = 0. Useful domain: |y| < |x|, X > 0.
For solving atanh(Y / X), set Z = 0.
Useful domain: |atanh(Y / X)| ≤
1.11rad, X > 0.
Relationships:
tanh(v) = sinh(v) / cosh(v)
ev = sinh(v) + cosh(v)
wt = et ln(w)
Relationships:
ln(w) = 2 atanh[(w-1) / (w+1)]
sqrt(w) = sqrt((w+0.25)2-(w-0.25)2)
acosh(w) = ln[w+sqrt(1-w2)]
asinh(w) = ln[w+sqrt(1+w2)]
Usage Notes
•
•
•
•
•
For solving the respective functions, user must initialize the CORDIC data (X, Y and
Z) with meaningful initial values within domain of convergence to ensure result
convergence. The ‘useful domain’ listed in Table 13-4 covers the supported domain
of convergence for the CORDIC algorithm and excludes the not-meaningful range(s)
for the function. For details regarding the supported domain of convergence, refer to
Section 13.3.3.1. For result data accuracy, refer to Section 13.3.5.
Function limitations must be considered, e.g., setting initial X = 0 for atan(Y / X) is not
meaningful. Violations of such function limitations may yield incoherent CORDIC
result data.
All data inputs are processed and handled as twos complement. Only exception is
user-option for X result data (only) to be read as unsigned value.
The only case where the result data is always positive and larger than the initial data
is X result data (only) in circular vectoring mode; therefore, the user may want to use
the MSB bit as data bit instead of sign bit. By setting X_USIGN = 1, X result data will
be processed as unsigned data.
For circular and hyperbolic functions, and due to the corresponding fixed LUT, the
Z data is always handled as signed integer S19 (accessible as S15). The LUTs
contain scaled integer values (S19) of atan(2-i) for i = 0, 1, 2, ..., 15 and atanh(2-i) for
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CORDIC Coprocessor
•
•
•
•
i = 1, 2, ..., 15, such that angles in the range [-π,((219-1)/219)π] are represented by
integer values ranging [-219,(219-1)]. Therefore, Z data is limited (not considering
domain of convergence) to represent angles [-π,((215-1)/215)π] for these CORDIC
functions. Any calculated value of Z outside of this range will result in overflow error.
For linear function, the Z data is always handled as signed fraction S4.15 (accessible
as S4.11 in the form signed 4Q16). The emulated LUT is actually a shift register that
holds data in the form 1.15 which gives the real value of 2-i. Therefore, regardless of
the domain of convergence, Z data is logically only useful for values whose
magnitude is smaller than 16. Overflow error is indicated by the CD_STATC.ERROR
bit.
The MPS setting has no effect on Z data. User must ensure proper initialization of Z
initial data to prevent overflow and incorrect result data.
The CORDIC Coprocessor is designed such that with correct user setting of
MPS > 1, there is no internal overflow of the X and Y data and the read result data is
complete. However, note that in these cases, the higher the MPS setting, the lower
the resolution of the result data due to loss of LSB bit(s).
The hyperbolic rotation mode is limited, in terms of result accuracy, in that initial Y
data must be set to zero. In other words, the CORDIC Coprocessor is not able to
return accurate result for cosh(Z)+/-sinh(Z) in a single calculation.
13.3.3.1 Domains of Convergence
It is not intended for this document to cover the theory of the inherent limits of CORDIC
convergence, which varies with different CORDIC function in rotation or vectoring mode.
For convergence of result data, there are limitations to the magnitude or value of initial
data and corresponding useful data form, depending on the operating mode used. The
following are generally applicable regarding convergence of CORDIC result data.
Rotation Mode: Z data must converge towards 0. Initial Z data must be equal or smaller
than ∑di · ei, where ei is always decreasing for iteration i. In other words, |Z| ≤ Sum of
LUT. In circular function, this means |Z| ≤ integer value representing 1.74 radians. For
linear function, |Z| ≤ 2. In hyperbolic function, |Z| ≤ integer value representing 1.11
radians.
Vectoring Mode: Y data must converge towards 0. The values of initial X and Y are
limited by the Z function which is dependent on the corresponding LUT. For circular
function, this means |atan(Y / X)| ≤ 1.74 radians. For linear function, |Y / X| ≤ 2. For
hyperbolic function, |atanh(Y / X)| ≤ 1.11 radians. In vectoring mode, the additional
requirement is that X > 0.
While the operating modes of the CORDIC Coprocessor are generally bounded by these
convergence limits, there are exceptions for the circular rotation and circular vectoring
modes which use additional pre- (and post-)processing logic to support wider range of
inputs.
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CORDIC Coprocessor
Circular Rotation Mode: The full range of Z input [-215,(215-1)] representing angles [π,((215-1)/215)π] is supported. No limitations on initial X and Y inputs, except for overflow
considerations which can be overcome with MPS setting.
Circular Vectoring Mode: The full range of X and Y inputs [-215,(215-1)] are supported,
while Z initial value should satisfy |Z| ≤ π / 2 to prevent possible Z result data overflow.
Note: Considerations should also be given to function limitations such as the meaning
of the result data, e.g. divide by zero is not meaningful. The ‘useful domain’
included within Table 13-4 for each of the main functions, attempts to cover both
for CORDIC convergence and useful range of the function.
Note: Input values may be within the domain of convergence, however, this does not
guarantee a fixed level of accuracy of the CORDIC result data. Refer to
Section 13.3.5 for details on accuracy of the CORDIC Coprocessor.
13.3.3.2 Overflow Considerations
Besides considerations for domain of convergence, the limitations on the magnitude of
input data must also be considered to prevent result data overflow.
Data overflow is handled by the CORDIC Coprocessor in the same way in all operating
modes. Overflow for X and Y data can be prevented by correct setting by the user of the
MPS bit, whose value is partly based on the CORDIC Coprocessor operating mode and
the application data.
The MPS setting has no effect on the Z data. For circular and hyperbolic functions, any
value of Z outside of the range [-π,((215-1)/215)π] cannot be represented and will result in
Z data overflow error. Note that kernel data Z has values in the range [-π,((219-1)/219)π]
scaled to the range [-219,(219-1)], so the written and read values of Z data are always
normalized as such. For linear function, where Z is a real value, magnitude of Z must not
exceed 4 integer bits.
13.3.4
CORDIC Coprocessor Data Format
The CORDIC Coprocessor accepts (initial) data X, Y and Z inputs in twos complement
format. The result data are also in twos complement format.
The only exception is for the X result data in circular vectoring mode. The X result data
has a default data format of twos complement, but the user can select via bit
CD_CON.X_USIGN = 1 for the X result data to be read as unsigned value. This option
prevents a potential overflow of the X result data (taken together with the MPS setting),
as the MSB bit is now a data bit. Note that setting bit X_USIGN = 1 is only effective when
operating in the circular vectoring mode, which always yields result data that is positive
and larger than the initial data.
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CORDIC Coprocessor
Generally, the input data for X and Y can be integer or rational number (fraction).
However, in any calculation, the data form must be the same for both X and Y. Also, in
case of fraction, X and Y must have the same number of bits for decimal place.
The Z data is always handled as integer, based on the normalization factor for circular
or hyperbolic function. In case of linear function, accessible Z data is a real number with
fixed input and result data form of S4.11 (signed 4Q16) which is a fraction with
11 decimal places.
Refer to Section 13.3.2 for details on data normalization.
13.3.5
Accuracy of CORDIC Coprocessor
Each CORDIC calculation involves a fixed number of 16 CORDIC iterations starting from
iteration 0. The hyperbolic function is special in this respect in that it starts from
iteration 1 with repeat iterations at defined steps. The addressable data registers are
16 bits wide, while the internal kernel X and Y data registers used for calculation are
each 26 bits wide (24 data bits plus 2 overflow bits) and internal kernel Z data register is
21 bits wide (20 data bits plus 1 overflow bit). For more details on the data form of the
LUTs, refer to Section 13.5.1 and Section 13.5.2.
For input data values within the specified useful domain (see Table 13-4), the result of
each calculation of the CORDIC Coprocessor is guaranteed to converge, although the
accuracy is not fixed per data form in each operating mode. The accuracy is a measure
of the magnitude of the difference between the result data and the expected data from a
high-accuracy calculator. “Normalized Deviation” (ND) is a generic term used to refer to
the magnitude of deviation of the result data from the expected result. The deviation is
calculated as if the input/result data is integer. In case the data is a rational number, the
magnitude of deviation has to be interpreted. For example, Z for linear vectoring mode
of the data form S4.11 - ND = 1 (01B) means the difference from expected real data has
magnitude of no more than |2-11 + 2-11|; ND = 2 (10B) means the difference is no more
than |2-10+2-11|; ND = 3 (11B) means the difference is no more than |2-11+2-10+2-11|;
ND = 4 (100B) means the difference is no more than |2-9+2-11|, and so on. The value of
2-11 is always added to account for possible truncation error.
Table 13-5 lists the probability of Normalized Deviation in a single calculation, obtained
from simulation with approximately one million different input sets for each respective
CORDIC Coprocessor operating mode, based on the input conditions specified (always
within useful domain, possibly with additional conditions).
The accuracy of each mode can be easily increased, by working with rational numbers
(fraction) instead of integers. This refers to X and Y data only (X and Y must always be
of same data form), while the data form of Z is fixed per the respective LUT’s definition.
It is obvious to expect that for a given input of X and Y (and Z), the calculated result will
always return a constant value—regardless of whether X and Y are integers or rational
numbers. The only difference is with regards to interpreting the input and result data, i.e.,
with no decimal place or how many decimal places. The deviation of the CORDIC result
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from the expected data is never smaller if X and Y are integers instead of rational
numbers. Therefore, wherever possible, assign X and Y as rational numbers with
carefully selected decimal place point, which could be based on the maximum ND of that
mode.
Table 13-5
Normalized Deviation of a Calculation
Mode
X Normalized Deviation
Circular
Vectoring
Input conditions: Useful Domain and [(1.64676/2)·sqrt(X2+Y2) ≥ 600]
Circular
Rotation
Input conditions: Useful Domain (Full range of X, Y and Z)
Linear
Vectoring
Input conditions: Useful Domain (|Y / X| ≤ 2, X > 0)
Linear
Rotation
Input conditions: Useful Domain (|Z| ≤ 2)
Hyperbolic
Vectoring
0 : 50.8317%
1 : 49.1683%
ND for X ≤ 1
Y or Z Normalized Deviation
0 : 55.8702%
1 : 44.1298%
ND for Z ≤ 1
0 : 50.7715%
1 : 48.8579%
2 : 0.3681%
3 : 0.0023%
4 : 0.0002%
ND for X ≤ 4
0 : 51.2011%
1 : 48.4944%
2 : 0.3024%
3 : 0.0020%
4 : 0.0001%
ND for Y ≤ 4
0 : 66.9170%
1 : 33.0830%
ND for X ≤ 1
0 : 88.5676%
1 : 11.4322%
2 : 0.0002%
ND for Z ≤ 2
0 : 69.7141%
1 : 30.2859%
ND for X ≤ 1
0 : 62.4055%
1 : 37.1965%
2 : 0.3980%
ND for Y ≤ 2
Input conditions: Useful Domain (|Y| < |X|, X > 0, |atanh(Y / X)| ≤
1.11rad)
0 : 34.5399%
1 : 34.5438%
2 : 17.9254%
3 : 11.6747%
4 : 1.3162%
ND for X ≤ 4
User’s Manual
CORDIC Coprocessor, V 1.2.5
0 : 58.3062%
1 : 41.6938%
ND for Z ≤ 1
13-11
V1.1, 2010-09
XC83x
CORDIC Coprocessor
Table 13-5
Normalized Deviation of a Calculation
Mode
X Normalized Deviation
Hyperbolic
Rotation
Input conditions: Useful Domain (|Z| ≤ 1.11rad, Y = 0)
0 : 14.9401%
1 : 31.6474%
2 : 23.7692%
3 : 14.8353%
4 : 7.4881%
5 : 4.3398%
6 : 2.4387%
7 : 0.5267%
8 : 0.0146%
ND for X ≤ 8
Y or Z Normalized Deviation
0 : 40.4787%
1 : 40.6711%
2 : 11.9209%
3 : 4.6940%
4 : 1.7290%
5 : 0.4453%
6 : 0.0607%
7 : 0.0003%
ND for Y ≤ 7
Note: The accuracy/deviation as stated above for each mode is not guaranteed for the
final result of multi-step calculations, e.g. if an operation involves two CORDIC
calculations, the second calculation uses the result data from the first calculation
(enabled with corresponding KEEP bit set). This is due to accumulated
approximations and errors.
13.3.6
Performance of CORDIC Coprocessor
The CORDIC calculation time increases linearly with increased precision. Increased
precision is achieved with greater number of iterations, which requires increased width
of the data parameters.
The CORDIC Coprocessor uses barrel shifters for data shifting. For a fixed number of
16 iterations per calculation, the total time from the start of calculation to the instant the
EOC flag is set is approximately 41 clock cycles (or less). It should be noted that the
ERROR flag is valid only after one cycle. This timing for one complete calculation is
applicable also to those modes which involve additional data processing, and also to the
hyperbolic modes which involve repeat iterations and an extra cycle for mode setup.
Note: The above timing exclude time taken for software loading of initial data and
reading of the final result data, to and from the six data registers.
User’s Manual
CORDIC Coprocessor, V 1.2.5
13-12
V1.1, 2010-09
XC83x
CORDIC Coprocessor
13.4
Interrupt
The End-of-Calculation (EOC) is the only interrupt source of the CORDIC Coprocessor.
If interrupt is enabled by CD_STATC.INT_EN = 1, an interrupt request signal is activated
at the end of CORDIC calculation and also indicated by the CD_STATC.EOC flag. If not
cleared by software, the EOC flag remains set until cleared by hardware when a read
access is performed to the low byte of Z result data (DMAP = 0).
During EOC data processing, a check must be made to ensure that the ERROR flag is
not set (indicates data overflow has occurred).
13.5
CORDIC Coprocessor Hardware
This section provides the user with need-to-know information regarding the CORDIC
Coprocessor look-up-tables.
13.5.1
Arctangent and Hyperbolic Arctangent Look-Up Tables
The LUTs are 20 bits and 21 bits wide respectively, for the arctangent table (atan LUT)
and hyperbolic arctangent table (atanh LUT). Each entry of the atan LUT is divided into
1 sign bit (MSB) followed by 19-bit integer part. For the atanh LUT, each entry has 1
repeater bit (MSB), followed by 1 sign bit, then 19-bit integer part.
The contents of the LUTs are:
•
atan LUT with data form of S19, see Table 13-6
Table 13-6
Precomputed Scaled Values for atan(2-i)
Iteration No.
Scaled atan(2-i) in hex
Iteration No. Scaled atan(2-i) in hex
i=0
20000
i=8
28C
i=1
12E40
i=9
146
i=2
9FB4
i = 10
A3
i=3
5111
i = 11
51
i=4
28B1
i = 12
29
i=5
145D
i = 13
14
i=6
A2F
i = 14
A
i=7
518
i = 15
5
•
atanh LUT with data form of S19, see Table 13-7
User’s Manual
CORDIC Coprocessor, V 1.2.5
13-13
V1.1, 2010-09
XC83x
CORDIC Coprocessor
Precomputed Scaled Values for atanh(2-i)
Table 13-7
Iteration No.
Scaled atanh(2-i) in hex
Iteration No. Scaled atanh(2-i) in hex
i=0
-
i=8
28C
i=1
16618
i=9
146
i=2
A681
i = 10
A3
i=3
51EA
i = 11
51
i=4
28CC
i = 12
29
i=5
1461
i = 13
14
i=6
A30
i = 14
A
i=7
518
i = 15
5
The Z data is a normalized representation of the actual angle. The internal scaling is
such that [-π,((219-1)/219)π] is equivalent to [-219,(219-1)]. The last 4 LSB bits are
truncated, as 16-bit data is transferred to the data bus when addressed. From user’s
point, the angles [-π,((215-1)/215)π] are therefore represented by the range [-215,(215-1)].
13.5.2
Linear Function Emulated Look-Up Table
The emulated LUT for linear function is actually a shift register. The emulated LUT has
1 integer bit (MSB) followed by 15-bit fractional part of the form 1Q16.
In linear function, where Z is a real number, the internal Z data is of the form signed
4Q20. The externally read data has the last 4 bits of the fractional part truncated,
resulting in a sign bit followed by 4-bit integer part, and finally 11-bit fractional part.
User’s Manual
CORDIC Coprocessor, V 1.2.5
13-14
V1.1, 2010-09
XC83x
CORDIC Coprocessor
13.6
Registers Description
The CORDIC Coprocessor Special Function Registers are accessed from the standard
(non-mapped) SFR area. Table 13-8 lists the SFRs and corresponding address.
Table 13-8
Register Map
Address
Register
BAH
CD_CORDXL
BBH
CD_CORDXH
BCH
CD_CORDYL
BDH
CD_CORDYH
BEH
CD_CORDZL
BFH
CD_CORDZH
A0H
CD_STATC
A1H
CD_CON
13.6.1
Control Register
The CD_CON register allows for the general control of the CORDIC Coprocessor. Write
action to this register while CD_STATC.BSY is set has no effect.
CD_CON
CORDIC Control Register
RMAP: 0, PAGE: X
7
6
MPS
rw
5
(A1H)
4
Reset Value: 62H
3
X_USIGN ST_MODE ROTVEC
rw
User’s Manual
CORDIC Coprocessor, V 1.2.5
rw
rw
13-15
2
1
0
MODE
ST
rw
rwh
V1.1, 2010-09
XC83x
CORDIC Coprocessor
Field
Bits
Type Description
ST
0
rwh
Start Calculation
If ST_MODE = 1, set ST to start a CORDIC
calculation. Is effective only while BSY is not set.
This bit may be set with the other bits of this register
in one write access.
Cleared by hardware at the beginning of calculation.
MODE
2:1
rw
Operating Mode
00
Linear Mode
01
Circular Mode (default)
10
Reserved
11
Hyperbolic Mode
ROTVEC
3
rw
Rotation Vectoring Selection
0
Vectoring Mode (default)
1
Rotation Mode
ST_MODE
4
rw
Start Method
0
Auto start of calculation after write access to X
low byte CD_CORDXL (default)
1
Start calculation only after bit ST is set
X_USIGN
5
rw
Result Data Format for X in Circular Vectoring
Mode
When reading the X result data with DMAP = 0,
X data has a data format of:
0
Signed, twos complement
1
Unsigned (default)
With this bit set, the MSB bit of the X result data is
processed as a data bit instead of a sign bit.
Note: This bit is only effective when operating in
circular vectoring mode. In all other modes, X
is always processed as twos complement
data.
Note: X_USIGN = 1 is meaningful in circular
vectoring mode because the result data is
always positive and always larger than the
initial data.
User’s Manual
CORDIC Coprocessor, V 1.2.5
13-16
V1.1, 2010-09
XC83x
CORDIC Coprocessor
Field
Bits
Type Description
MPS
7:6
rw
User’s Manual
CORDIC Coprocessor, V 1.2.5
X and Y Magnitude Prescaler
After the last iteration of a calculation, the calculated
value of X and Y are each divided by this factor to
yield the result.
Proper setting of these bits is important to avoid an
overflow of the result in the respective kernel data
registers.
00
Divide by 1
01
Divide by 2 (default)
10
Divide by 4
11
Reserved, retain the last MPS setting
13-17
V1.1, 2010-09
XC83x
CORDIC Coprocessor
13.6.2
Status and Data Control Register
The CD_STATC register is bit-addressable, and generally reflects the status of the
CORDIC Coprocessor. The register also contain bits for data control, as well as for
interrupt control.
CD_STATC
CORDIC Status and Data Control Register(A0H)
RMAP: 0, PAGE: X
Reset Value: 00H
7
6
5
4
3
2
1
0
KEEPZ
KEEPY
KEEPX
DMAP
INT_EN
EOC
ERROR
BSY
rw
rw
rw
rw
rw
rwh
rh
rh
Field
Bits
Type Description
BSY
0
rh
Busy Indication
Indicates a running calculation when set. The flag is
asserted one clock cycle after bit ST was set. It is
deasserted at the end of a calculation.
ERROR
1
rh
Error Indication
In case of overflow error in the calculated result for
X, Y or Z, this bit is set at the end of CORDIC
calculation. Cleared when a new CORDIC
calculation is started.
EOC
2
rwh
End of Calculation Flag
Set at the end of a complete CORDIC calculation
when BSY goes inactive.
Unless cleared by software, bit remains set until a
read access is performed to the low byte of Z result
data (DMAP = 0) where the bit is automatically
cleared by hardware.
INT_EN
3
rw
Interrupt Enable
Set to enable CORDIC Coprocessor interrupt
DMAP
4
rw
Data Map
0
Read (result) data from kernel data registers
(default)
1
Read (initial) data from the shadow data
registers
User’s Manual
CORDIC Coprocessor, V 1.2.5
13-18
V1.1, 2010-09
XC83x
CORDIC Coprocessor
Field
Bits
Type Description
KEEPX
5
rw
Last X Result as Initial Data for New Calculation
If set, a new calculation will use as initial data, the
value of the result from the previous calculation. In
other words, the respective kernel data register will
not be overwritten by the contents of the shadow
data register at the beginning of new calculation.
This bit should always be cleared for the very first
calculation to load the initial X data.
Note: Independent of the KEEP bit, the shadow data
registers will continue to hold the last written
initial data value until the next software write.
Note: If KEEPx bit is set for a multi-step calculation,
the accuracy of the corresponding final x result
data may be reduced and is not guaranteed as
shown in Section 13.3.5.
KEEPY
6
rw
Last Y Result as Initial Data for New Calculation
<See description for KEEPX>
KEEPZ
7
rw
Last Z Result as Initial Data for New Calculation
<See description for KEEPX>
13.6.3
Data Registers
The Data registers are used to initialize the X, Y and Z parameters. The result data from
CORDIC calculation can also be read (DMAP = 0). Reading of the shadow registers for
initial data are also possible (DMAP = 1). Regardless of the DMAP setting for reading,
these data registers always hold the last written initial value until the next user software
write, or reset.
CD_CORDXL
CORDIC X Data Low Byte
RMAP: 0, PAGE: X
7
6
5
(BAH)
4
Reset Value: 00H
3
2
1
0
DATAL
rw
User’s Manual
CORDIC Coprocessor, V 1.2.5
13-19
V1.1, 2010-09
XC83x
CORDIC Coprocessor
Field
Bits
Type Description
DATAL
7:0
rw
Low Byte Data
Write to this byte always writes to the low byte of the
corresponding shadow data register. New data may
be written during an ongoing CORDIC calculation.
For read,
DMAP=0: Result data from kernel data byte
DMAP=1: Initial data from the shadow data byte
CD_CORDXH
CORDIC X Data High Byte
RMAP: 0, PAGE: X
7
6
5
(BBH)
4
Reset Value: 00H
3
2
1
0
DATAH
rw
Field
Bits
Type Description
DATAH
7:0
rw
High Byte Data
Write to this byte always writes to the high byte of the
corresponding shadow data register. New data may
be written during an ongoing CORDIC calculation.
For read,
DMAP=0: Result data from kernel data byte
DMAP=1: Initial data from the shadow data byte
CD_CORDYL
CORDIC Y Data Low Byte
RMAP: 0, PAGE: X
7
6
5
(BCH)
4
Reset Value: 00H
3
2
1
0
DATAL
rw
User’s Manual
CORDIC Coprocessor, V 1.2.5
13-20
V1.1, 2010-09
XC83x
CORDIC Coprocessor
Field
Bits
Type Description
DATAL
7:0
rw
Low Byte Data
Write to this byte always writes to the low byte of the
corresponding shadow data register. New data may
be written during an ongoing CORDIC calculation.
For read,
DMAP=0: Result data from kernel data byte
DMAP=1: Initial data from the shadow data byte
CD_CORDYH
CORDIC Y Data High Byte
RMAP: 0, PAGE: X
7
6
5
(BDH)
4
Reset Value: 00H
3
2
1
0
DATAH
rw
Field
Bits
Type Description
DATAH
7:0
rw
High Byte Data
Write to this byte always writes to the high byte of the
corresponding shadow data register. New data may
be written during an ongoing CORDIC calculation.
For read,
DMAP=0: Result data from kernel data byte
DMAP=1: Initial data from the shadow data byte
CD_CORDZL
CORDIC Z Data Low Byte
RMAP: 0, PAGE: X
7
6
5
(BEH)
4
Reset Value: 00H
3
2
1
0
DATAL
rw
User’s Manual
CORDIC Coprocessor, V 1.2.5
13-21
V1.1, 2010-09
XC83x
CORDIC Coprocessor
Field
Bits
Type Description
DATAL
7:0
rw
Low Byte Data
Write to this byte always writes to the low byte of the
corresponding shadow data register. New data may
be written during an ongoing CORDIC calculation.
For read,
DMAP=0: Result data from kernel data byte
DMAP=1: Initial data from the shadow data byte
CD_CORDZH
CORDIC Z Data High Byte
RMAP: 0, PAGE: X
7
6
5
(BFH)
4
Reset Value: 00H
3
2
1
0
DATAH
rw
Field
Bits
Type Description
DATAH
7:0
rw
High Byte Data
Write to this byte always writes to the high byte of the
corresponding shadow data register. New data may
be written during an ongoing CORDIC calculation.
For read,
DMAP=0: Result data from kernel data byte
DMAP=1: Initial data from the shadow data byte
User’s Manual
CORDIC Coprocessor, V 1.2.5
13-22
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
14
Timer 0 and Timer 1
14.1
Overview
Timer 0 and Timer 1 can function as both timers or counters. When functioning as a
timer, Timer 0 and Timer 1 are incremented every machine cycle, i.e. every 2 input
clocks (or 2 PCLKs). When functioning as a counter, Timer 0 and Timer 1 are
incremented in response to a 1-to-0 transition (falling edge) at their respective external
input pins, T0 or T1.
They are useful in many timing applications such as measuring the time interval between
events, counting events and generating signals at regular intervals. In particular, Timer 1
can be used as the baud-rate generator for the on-chip serial port.
Features:
•
Four operational modes :
– Mode 0: 13-bit timer/counter
– Mode 1: 16-bit timer/counter
– Mode 2: 8-bit timer/counter with auto-reload
– Mode 3: Two 8-bit timers/counters
14.2
System Information
This section provides system information relevant to the Timer 0 and 1.
14.2.1
Pinning
Timer 0 and 1 can be used as an event counter which count 1-to-0 transitions at their
external input pins, T0 and T1. These pins are selected from two different sources, T0_0
and T0_1 for Timer 0, and T1_0 and T1_1 for Timer 1.The Timer 0 and 1 pin assignment
for XC83x is shown in Table 1-1. This selection is performed by the SFR bits
MODPISEL2.T0IS and MODPISEL2.T1IS.
Table 14-1
Pin
Timer 0 and 1 Pin Functions in XC83x
Function Desciption
P0.1 T0_0
Selected By
Timer 0 Input
MODPISEL2.T0IS = 0B
P2.1 T0_1
P0.2 T1_0
MODPISEL2.T0IS = 1B
Timer 1 Input
MODPISEL2.T1IS = 0B
P2.2 T1_1
User’s Manual
Timer 0 and 1, V1.0
MODPISEL2.T1IS = 1B
14-1
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
MODPISEL2 register.
MODPISEL2
Peripheral Input Select Register 2
RMAP: 0, PAGE: 3
(F5H)
4
Reset Value: 00H
7
6
5
3
2
1
0
0
T0IS
T1IS
T2IS
T2EXIS
r
rw
rw
rw
rw
Field
Bits
Type Description
T1IS
5
rw
Timer 1 Input Select
0
Timer 1 Input T1_0 is selected.
1
Timer 1 Input T1_1 is selected.
T0IS
6
rw
Timer 0 Input Select
0
Timer 0 Input T0_0 is selected.
1
Timer 0 Input T0_1 is selected.
0
7
r
Reserved
Returns 0 if read; should be written with 0.
14.2.2
Clocking Configuration
The Timer 0 and 1 runs on the PCLK at a frequency of either 8 MHz or 24 MHz.
14.2.3
Interrupt Events and Assignment
Table 1-2 lists the interrupt event sources from the Timer 0 and 1, and the interrupt node
assignment for each Timer 0 and 1 interrupt source.
Table 14-2
Timer 0 and 1 Events’ Interrupt Node Control
Event
Interrupt Node Enable Interrupt Node Flag Vector
Bit
Bit
Address
Timer 0 Overflow
IEN0.ET0
TCON.TF0
0BH
Timer 1 Overflow
IEN0.ET1
TCON.TF1
1BH
User’s Manual
Timer 0 and 1, V1.0
14-2
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
14.3
Basic Timer Operations
The operations of the two timers are controlled using the Special Function Registers
(SFRs) TCON and TMOD. To enable a timer, i.e., allow the timer to run, its control bit
TCON.TRx is set. To select the timer input to be either from internal system clock or
external pin, the input selector bit TMOD is used.
Note: The “x” (e.g., TCON.TRx) in this chapter denotes either 0 or 1.
Each timer consists of two 8-bit registers - TLx (low byte) and THx (high byte) which
defaults to 00H on reset. Setting or clearing TCON.TRx does not affect the timer
registers.
Timer Overflow
When a timer overflow occurs, the timer overflow flag, TCON.TFx, is set, and an interrupt
may be raised if the interrupt enable control bit, IEN0.ETx, is set. The overflow flag is
automatically cleared when the interrupt service routine is entered.
When Timer 0 operates in mode 3, the Timer 1 control bits, TR1, TF1 and ET1 are
reserved for TH0, see Section 14.4.4.
External Control
In addition to pure software control, the timers can also be enabled or disabled through
external port control. When external port control is used, SFR EXICON0 must first be
configured to bypass the edge detection circuitry for EXINTx to allow direct feed-through.
When the timer is enabled (TCON.TRx = 1) and TMOD.GATEx is set, the respective
timer will only run if the core external interrupt EXINTx = 1. This facilitates pulse width
measurements. However, this is not applicable for Timer 1 in mode 3.
If TMOD.GATEx is cleared, the timer reverts to pure software control.
User’s Manual
Timer 0 and 1, V1.0
14-3
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
14.4
Timer Modes
Timers 0 and 1 are fully compatible and can be configured in four different operating
modes, as shown in Table 14-3. The bit field TxM in register TMOD selects the operating
mode to be used for each timer.
In modes 0, 1 and 2, the two timers operate independently, but in mode 3, their functions
are specialized.
Table 14-3
Timer 0 and Timer 1 Modes
Mode
Operation
0
13-bit timer/counter
The timer is essentially an 8-bit counter with a divide-by-32 prescaler. This
mode is included solely for compatibility with Intel 8048 devices.
1
16-bit timer/counter
The timer registers, TLx and THx, are concatenated to form a 16-bit timer/
counter.
2
8-bit timer/counter with auto-reload
The timer register TLx is reloaded with a user-defined 8-bit value in THx
upon overflow.
3
Timer 0 operates as two 8-bit timers/counters
The timer registers, TL0 and TH0, operate as two separate 8-bit counters.
Timer 1 is halted and retains its count even if enabled.
User’s Manual
Timer 0 and 1, V1.0
14-4
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
14.4.1
Mode 0
Putting either Timer 0 or Timer 1 into mode 0 configures it as an 8-bit timer/counter with
a divide-by-32 prescaler. Figure 14-1 shows the mode 0 operation.
In this mode, the timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the timer overflow flag TFx. The overflow flag TFx can then
be used to request an interrupt. The counted input is enabled for the timer when TRx = 1
and either GATEx = 0 or EXINTx = 1 (setting GATEx = 1 allows the timer to be controlled
by external input EXINTx to facilitate pulse width measurements). TRx is a control bit in
the register TCON; bit GATEx is in register TMOD.
The 13-bit register consists of all the 8 bits of THx and the lower 5 bits of TLx. The upper
3 bits of TLx are indeterminate and should be ignored. Setting the run flag (TRx) does
not clear the registers..
Mode 0 operation is the same for Timer 0 and Timer 1.
fPCLK/2
T0S = 0
TL0
(5 Bits)
TH0
(8 Bits)
TF0
T0S = 1
T0
Control
TR0
GATE0
&
=1
>1
EXINT0
Timer0_Mode0
Figure 14-1 Timer 0, Mode 0: 13-Bit Timer/Counter
User’s Manual
Timer 0 and 1, V1.0
14-5
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
14.4.2
Mode 1
Mode 1 operation is similar to that of mode 0, except that the timer register runs with all
16 bits. Mode 1 operation for Timer 0 is shown in Figure 14-2.
fPCLK/2
T0S = 0
TL0
(8 Bits)
TH0
(8 Bits)
TF0
Interrupt
T0S = 1
T0
Control
TR0
GATE0
&
=1
>1
EXINT0
Timer0_Mode1
Figure 14-2 Timer 0, Mode 1: 16-Bit Timer/Counter
User’s Manual
Timer 0 and 1, V1.0
14-6
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
14.4.3
Mode 2
In Mode 2 operation, the timer is configured as an 8-bit counter (TLx) with automatic
reload, as shown in Figure 14-3 for Timer 0.
An overflow from TLx not only sets TFx, but also reloads TLx with the contents of THx
that has been preset by software. The reload leaves THx unchanged.
fPCLK/2
T0S = 0
TL0
(8 Bits)
TF0
Interrupt
T0S = 1
T0
Control
TR0
GATE0
Reload
&
=1
TH0
(8 Bits)
>1
Timer0_Mode2
EXINT0
Figure 14-3 Timer 0, Mode 2: 8-Bit Timer/Counter with Auto-Reload
User’s Manual
Timer 0 and 1, V1.0
14-7
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
14.4.4
Mode 3
In mode 3, Timer 0 and Timer 1 behave differently. Timer 0 in mode 3 establishes TL0
and TH0 as two separate counters. Timer 1 in mode 3 simply holds its count. The effect
is the same as setting TR1 = 0
The logic for mode 3 operation for Timer 0 is shown in Figure 14-4. TL0 uses the Timer 0
control bits GATE0, TR0 and TF0, while TH0 is locked into a timer function (counting
machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now
sets TF1 upon overflow and generates an interrupt if ET1 is set.
Mode 3 is provided for applications requiring an extra 8-bit timer. When Timer 0 is in
mode 3 and TR1 is set, Timer 1 can be turned on by switching it to any of the other
modes and turned off by switching it into mode 3.
Timer Clock
fPCLK/2
T0S = 0
TL0
(8 Bits)
TF0
TH0
(8 Bits)
TF1
Interrupt
T0S = 1
T0
Control
TR0
&
=1
GATE0
>1
EXINT0
TR1
Interrupt
Timer0_Mode3
Figure 14-4 Timer 0, Mode 3: Two 8-Bit Timers/Counters
User’s Manual
Timer 0 and 1, V1.0
14-8
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
14.5
Registers Description
Seven SFRs control the operations of Timer 0 and Timer 1. They can be accessed from
both the standard (non-mapped) and mapped SFR area.
Table 14-4 lists the addresses of these SFRs.
Table 14-4
Register Map
Address
Register
88H
TCON
89H
TMOD
8AH
TL0
8BH
TL1
8CH
TH0
8DH
TH1
A8H
IEN0
14.5.1
Timer 0 and Timer 1 Registers
The low bytes(TL0, TL1) and high bytes(TH0, TH1)of both Timer 0 and Timer 1 can be
combined to a one-timer configuration depending on the mode used. Register TCON
controls the operations of Timer 0 and Timer 1. The operating modes of both timers are
selected using register TMOD. Register IEN0 contains bits that enable interrupt
operations in Timer 0 and Timer 1.
TLx (x = 0 - 1)
Timer x, Low Byte
RMAP: X, PAGE: X
7
6
(8AH + x)
5
4
Reset Value: 00H
3
2
1
0
VAL
rwh
User’s Manual
Timer 0 and 1, V1.0
14-9
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
Field
Bits
Type Description
VAL
[7:0]
rwh
Timer 0/1 Low Register
00B TLx holds the 5-bit prescaler value.
01B TLx holds the lower 8-bit part of the 16-bit timer
value.
10B TLx holds the 8-bit timer value.
11B TL0 holds the 8-bit timer value; TL1 is not used.
THx (x = 0 - 1)
Timer x, High Byte
RMAP: X, PAGE: X
7
(8CH + x)
6
5
4
Reset Value: 00H
3
2
1
0
VAL
rwh
Field
Bits
Type Description
VAL
[7:0]
rwh
Timer 0/1 High Register
00B THx holds the 8-bit timer value.
01B THx holds the higher 8-bit part of the 16-bit timer
value.
10B THx holds the 8-bit reload value.
11B TH0 holds the 8-bit timer value; TH1 is not used.
TCON
Timer 0/1 Control Registers
RMAP: X, PAGE: X
7
6
TF1
TR1
rwh
rw
User’s Manual
Timer 0 and 1, V1.0
r
(88H)
Reset Value: 00H
5
4
3
2
TF0
TR0
IE1
IT1
rwh
rw
rwh
14-10
rw
r
1
0
IE0
IT0
rwh
rw
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
Field
Bits
Type Description
TR0
4
rw
Timer 0 Run Control
Timer is halted
0B
Timer runs
1B
TF0
5
rwh
Timer 0 Overflow Flag
Set by hardware when Timer 0 overflows.
Cleared by hardware when the processor calls
the interrupt service routine.
TR1
6
rw
Timer 1 Run Control
Timer is halted
0B
1B
Timer runs
Note: Timer 1 Run Control affects TH0 also if
Timer 0 operates in Mode 3
TF1
7
rwh
Timer 1 Overflow Flag
Set by hardware when Timer 11) overflows.
Cleared by hardware when the processor calls
the interrupt service routine.
1) TF1 is set by TH0 instead if Timer 0 operates in Mode 3.
TMOD
Timer Mode Register
RMAP: X, PAGE: X
7
6
GATE1
T1S
rw
rw
User’s Manual
Timer 0 and 1, V1.0
(89H)
5
r
4
Reset Value: 00H
3
2
T1M
GATE0
T0S
T0M
rw
rw
rw
rw
14-11
1
0
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
Field
Bits
Type Description
T0M
[1:0]
rw
Mode Select Bits
00B 13-bit timer (M8048 compatible mode)
01B 16-bit timer
10B 8-bit auto-reload timer
11B Timer 0 is split into two halves. TL0 is an
8-bit timer controlled by the standard Timer
0 control bits, and TH0 is the other 8-bit
timer controlled by the standard Timer 1
control bits. TH1 and TL1 of Timer 1 are
held (Timer 1 is stopped).
T0S
2
rw
Timer 0 Selector
0B
Input is from internal system clock
Input is from T0 pin
1B
GATE0
3
rw
Timer 0 Gate Flag
Timer 0 will only run if TCON.TR0 = 1
0B
(software control)
1B
Timer 0 will only run if EXINT0 pin = 1
(hardware control) and TCON.TR0 is set
T1M
[5:4]
rw
Mode Select Bits
00B 13-bit timer (M8048 compatible mode)
01B 16-bit timer
10B 8-bit auto-reload timer
11B Timer 0 is split into two halves. TL0 is an
8-bit timer controlled by the standard Timer
0 control bits, and TH0 is the other 8-bit
timer controlled by the standard Timer 1
control bits. TH1 and TL1 of Timer 1 are
held (Timer 1 is stopped).
T1S
6
rw
Timer 1 Selector
Input is from internal system clock
0B
Input is from T1 pin
1B
GATE1
7
rw
Timer 1 Gate Flag
Timer 1 will only run if TCON.TR1 = 1
0B
(software control)
Timer 1 will only run if EXINT0 pin = 1
1B
(hardware control) and TCON.TR1 is set
User’s Manual
Timer 0 and 1, V1.0
14-12
V1.1, 2010-09
XC83x
Timer 0 and Timer 1
IEN0
Interrupt Enable Register
RMAP: X, PAGE: X
7
6
EA
0
rw
r
r
(A8H)
Reset Value: 00H
5
4
3
2
1
0
ET2
ES
ET1
EX1
ET0
EX0
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
ET0
1
rw
Timer 0 Overflow Interrupt Enable
0B
Timer 0 interrupt is disabled
Timer 0 interrupt is enabled
1B
ET1
3
rw
Timer 1 Overflow Interrupt Enable
Timer 1 interrupt is disabled
0B
1B
Timer 1 interrupt is enabled
Note: When Timer 0 operates in Mode 3, this
interrupt indicates an overflow in the Timer
0 register, TH0.
User’s Manual
Timer 0 and 1, V1.0
14-13
V1.1, 2010-09
XC83x
Timer 2
15
Timer 2
15.1
Overview
Timer 2 is a 16-bit general purpose timer which is functionally compatible with the
Timer 2 in the C501 product family. Timer 2 can function as a timer or counter in each of
its modes. As a timer, it counts with an input clock of PCLK/12 (if prescaler is disabled).
As a counter, Timer 2 counts 1-to-0 transitions on pin T2. In the counter mode, the
maximum resolution for the count is PCLK/24 (if prescaler is disabled).
Features
•
•
•
16-bit auto-reload mode
selectable up or down counting
One channel, 16-bit capture mode
15.2
System Information
This section provides system information relevant to the Timer 2.
15.2.1
Pinning
Timer 2 can be used as an event counter which count 1-to-0 transitions at the external
input pin, T2. These pins are selected from four different sources, T2_0, T2_1, T2_2 and
T2_3. This selection is performed by the SFR bits MODPISEL2.T2IS. In addition, there
are eight sources of T2EX pin for Timer 2. They can be selected by
MODPISEL2.T2EXIS. Among these sources, 6 of them are available as external pin. 2
of them are triggered internally by Out of Range 0 (ORC0) event and Out of Range 1
(ORC1) event from the ADC module.
The Timer 2 pin assignment for XC83x is shown in Table 1-2.
Table 15-1
Timer 2 Pin Functions in XC83x
Pin/Sources Function Desciption
Selected By
P0.0
T2_0
MODPISEL2.T2IS = 00B
P2.0
T2_1
MODPISEL2.T2IS = 01B
P2.3
T2_2
MODPISEL2.T2IS = 10B
P2.4
T2_3
MODPISEL2.T2IS = 11B
User’s Manual
Timer 2, V 1.2
Timer 2 Input
15-1
V1.1, 2010-09
XC83x
Timer 2
Table 15-1
Timer 2 Pin Functions in XC83x
Pin/Sources Function Desciption
Selected By
P0.6
T2EX_0
MODPISEL2.T2EXIS = 000B
P0.4
T2EX_1
P1.0
T2EX_2
MODPISEL2.T2EXIS = 010B
P2.0
T2EX_3
MODPISEL2.T2EXIS = 011B
ORC0 event
T2EX_4
MODPISEL2.T2EXIS = 100B
ORC1 event
T2EX_5
MODPISEL2.T2EXIS = 101B
P2.7
T2EX_6
MODPISEL2.T2EXIS = 110B
P3.2
T2EX_7
MODPISEL2.T2EXIS = 111B
P0.4
EXF2_0
P3.1
EXF2_1
P3_ALTSEL0.P1 = 1B
P3_ALTSEL1.P1 = 1B
P1.3
EXF2_2
P1_ALTSEL0.P3 = 1B
P1_ALTSEL1.P3 = 1B
P0.5
EXF2_3
P0_ALTSEL0.P5 = 0B
P0_ALTSEL1.P5 = 1B
P0_ALTSEL2.P5 = 1B
Timer 2 External Trigger
Input
Timer 2 Overflow Flag
MODPISEL2.T2EXIS = 001B
P0_ALTSEL0.P4 = 1B
P0_ALTSEL1.P4 = 1B
P0_ALTSEL2.P4 = 0B
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
MODPISEL2 register.
MODPISEL2
Peripheral Input Select Register 2
RMAP: 0, PAGE: 3
(F5H)
7
6
5
0
T0IS
T1IS
T2IS
T2EXIS
r
rw
rw
rw
rw
User’s Manual
Timer 2, V 1.2
4
Reset Value: 00H
3
15-2
2
1
0
V1.1, 2010-09
XC83x
Timer 2
Field
Bits
Type Description
T2EXIS
[2:0]
rw
Timer 2 External Input Select
000 Timer 2 Input T2EX_0 is selected.
001 Timer 2 Input T2EX_1 is selected.
010 Timer 2 Input T2EX_2 is selected.
011 Timer 2 Input T2EX_3 is selected.
100 Timer 2 Input T2EX_4 is selected.
101 Timer 2 Input T2EX_5 is selected.
110 Timer 2 Input T2EX_6 is selected.
111 Timer 2 Input T2EX_7 is selected.
Note: T2EX_4 and T2EX_5 are triggered by Out of
Range 0 event and Out of Range 1 event
respectively.
T2IS
[4:3]
rw
Timer 2 Input Select
00
Timer 2 Input T2_0 is selected.
01
Timer 2 Input T2_1 is selected.
10
Timer 2 Input T2_2 is selected.
11
Timer 2 Input T2_3 is selected.
0
7
r
Reserved
Returns 0 if read; should be written with 0.
15.2.2
Clocking Configuration
The Timer 2 runs on the PCLK at a frequency of either 8 MHz or 24 MHz.
If the Timer 2 functionality is not required at all, it can be completely disabled by gating
off its clock input for maximal power reduction. This is done by setting bit T2_DIS in
register PMCON1 as described below.
PMCON1
Peripheral Management Control Register 1(EFH)
RMAP: 0, PAGE: 1
7
6
IIC_DIS
LTS_DIS
rw
rw
User’s Manual
Timer 2, V 1.2
5
4
CDC_DIS MDU_DIS
rw
rw
15-3
Reset Value: FFH
3
2
1
0
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
rw
rw
rw
rw
V1.1, 2010-09
XC83x
Timer 2
Field
Bits
Type Description
T2_DIS
3
rw
15.2.3
T2 Disable Request. Active high.
0
T2 is in normal operation.
1
Request to disable the T2. (default)
Interrupt Events and Assignment
Table 1-3 lists the interrupt event sources from the Timer 2, and the corresponding event
interrupt enable bit and flag bit.
Table 15-2
Timer 2 Interrupt Events
Event
Event Interrupt Enable Bit
Event Flag Bit
Timer 2 Overflow
T2_T2CON1.TF2EN
T2_T2CON.TF2
Timer 2 External
T2_T2CON1.EXF2EN
T2_T2CON.EXF2
Table 1-4 shows the interrupt node assignment for each Timer 2 interrupt source.
Table 15-3
Timer 2 Events’ Interrupt Node Control
Event
Interrupt Node
Enable Bit
Interrupt Node Flag Vector
Bit
Address
Timer 2 Overflow
IEN0.ET2
–
2BH
Timer 2 External
15.2.4
IP interconnection
In XC83x, T2EX_4 input and T2EX_5 input can be triggered by Out of Range 0 (ORC0)
event and Out of Range 1 (ORC1) event from the ADC module respectively as shown in
Table 1-5. ORCx will generate a rising edge signal to the T2EX input when there is an
out of range event. To detect a rising edge signal in T2EX input, either bit EDGESEL or
T2REGS of T2_T2MODE register must be set to 1 depending on the usage of the pin.
In addition, T2EX_4 or T2EX_5 input needs to be setup via MODPISEL2 register as
shown in Table 1-2.
Table 15-4
Timer 2 Interconnections
Connected Other Module Function/Signal
Timer 2 Function/Signal
Out of Range 0 (o): ORC0
Timer 2 External Trigger (i): T2EX_4
Out of Range 1 (o): ORC1
Timer 2 External Trigger (i): T2EX_5
User’s Manual
Timer 2, V 1.2
15-4
V1.1, 2010-09
XC83x
Timer 2
15.2.5
Module Suspend Control
When the On-Chip Debug Support (OCDS) is in Monitor Mode (MMCR2.MMODE = 1)
and the Debug-Suspend signal is active (MMCR2.DSUSP = 1), the timer/counter in
Timer 2 module in XC83x can be suspended based on the settings of their
corresponding module suspend bits in register MODSUSP. When suspended, only the
timer stops counting as the counter input clock is gated off. The module is still clocked
so that module registers are accessible. Refer to Chapter 10.2.4 for the definition of
register MODSUSP.
User’s Manual
Timer 2, V 1.2
15-5
V1.1, 2010-09
XC83x
Timer 2
15.3
Basic Timer Operations
Timer 2 can be started by using TR2 bit by hardware or software. Timer 2 can be started
by setting TR2 bit by software. If bit T2RHEN is set, Timer 2 can be started by hardware.
Bit T2REGS defines the event on pin T2EX, falling edge or rising edge, that can set the
run bit TR2 by hardware. Timer 2 can only be stopped by resetting TR2 bit by software.
15.4
Auto-Reload Mode
The auto-reload mode is selected when the bit CP/RL2 in register T2CON is zero. In this
mode, Timer 2 counts to an overflow value and then reloads its register contents with a
16-bit start value for a fresh counting sequence. The overflow condition is indicated by
setting bit TF2 in the T2CON register. At the same time, an interrupt request to the core
will be generated (if interrupt is enabled). The overflow flag TF2 must be cleared by
software.
The auto-reload mode is further classified into two categories depending upon the DCEN
control bit in register T2MOD.
15.4.1
Up/Down Count Disabled
If DCEN = 0, the up-down count selection is disabled. The timer, therefore, functions as
a pure up counting timer only. The operational block diagram is shown in Figure 15-1.
If the T2CON register bit EXEN2 = 0, the timer starts to count up to a maximum of FFFFH
once the timer is started by setting the bit TR2 in register T2CON to 1. Upon overflow,
bit TF2 is set and the timer register is reloaded with the 16-bit reload value of the RC2
register. This reload value is chosen by software, prior to the occurrence of an overflow
condition. A fresh count sequence is started and the timer counts up from this reload
value as in the previous count sequence.
If EXEN2 = 1, the timer counts up to a maximum of FFFFH once TR2 is set. A 16-bit
reload of the timer registers from register RC2 is triggered either by an overflow condition
or by a negative/positive edge (chosen by the bit EDGESEL in register T2MOD) at input
pin T2EX. If an overflow caused the reload, the overflow flag TF2 is set. If a
negative/positive transition at pin T2EX caused the reload, bit EXF2 in register T2CON
is set. In either case, an interrupt is generated to the core if the related interrupt enable
bit EXF2EN/TF2EN in register T2CON1 is enabled and the timer proceeds to its next
count sequence. The EXF2 flag, similar to the TF2, must be cleared by software.
If bit T2RHEN is set, Timer 2 is started by first falling edge/rising edge at pin T2EX, which
is defined by bit T2REGS. If bit EXEN2 is set, bit EXF2 is also set at the same point when
Timer 2 is started with the same falling edge/rising edge at pin T2EX, which is defined
by bit EDGESEL. The reload will happen with the following negative/positive transitions
at pin T2EX, which is defined by bit EDGESEL.
User’s Manual
Timer 2, V 1.2
15-6
V1.1, 2010-09
XC83x
Timer 2
Note: In counter mode, if the reload via T2EX and the count clock T2 are detected
simultaneously, the reload takes precedence over the count. The counter
increments its value with the following T2 count clock.
PREN
/12
0
T2PRE
1
fPCLK
C/T2=0
THL2
C/T2=1
TR2
T2
Overflow
OR
RC2
TF2
Timer 2
OR
Interrupt
EXF2
EXEN2
T2EX
Figure 15-1 Auto-Reload Mode (DCEN = 0)
15.4.2
Up/Down Count Enabled
If DCEN = 1, the up-down count selection is enabled. The direction of count is
determined by the level at input pin T2EX. The operational block diagram is shown in
Figure 15-2.
A logic 1 at pin T2EX sets the Timer 2 to up counting mode. The timer, therefore, counts
up to a maximum of FFFFH. Upon overflow, bit TF2 is set and the timer register is
reloaded with a 16-bit reload value of the RC2 register. A fresh count sequence is started
and the timer counts up from this reload value as in the previous count sequence. This
reload value is chosen by software, prior to the occurrence of an overflow condition.
A logic 0 at pin T2EX sets the Timer 2 to down counting mode. The timer counts down
and underflows when the THL2 value reaches the value stored at register RC2. The
User’s Manual
Timer 2, V 1.2
15-7
V1.1, 2010-09
XC83x
Timer 2
underflow condition sets the TF2 flag and causes FFFFH to be reloaded into the THL2
register. A fresh down counting sequence is started and the timer counts down as in the
previous counting sequence.
If bit T2RHEN is set, Timer 2 can only be started either by rising edge (T2REGS = 1) at
pin T2EX and then proceed with the up counting, or be started by falling edge
(T2REGS = 0) at pin T2EX and then proceed with the down counting.
In this mode, bit EXF2 toggles whenever an overflow or an underflow condition is
detected. This flag, however, does not generate an interrupt request.
FFFFH
(Down count reload)
EXF2
PREN
Underflow
fPCLK
/12
0
T2PRE
1
Timer 2
C/T2=0
THL2
C/T2=1
OR
TF2
Interrupt
TR2
T2
16-bit
Comparator
Overflow
RC2
T2EX
Figure 15-2 Auto-Reload Mode (DCEN = 1)
User’s Manual
Timer 2, V 1.2
15-8
V1.1, 2010-09
XC83x
Timer 2
15.5
Capture Mode
In order to enter the 16-bit capture mode, bits CP/RL2 and EXEN2 in register T2CON
must be set. In this mode, the down count function must remain disabled. The timer
functions as a 16-bit timer and always counts up to FFFFH, after which, an overflow
condition occurs. Upon overflow, bit TF2 is set and the timer reloads its registers with
0000H. The setting of TF2 generates an interrupt request to the core.
Additionally, with a falling/rising edge (chosen by T2MOD.EDGESEL) on pin T2EX, the
contents of the timer register (THL2) are captured into the RC2 register. The external
input is sampled in every PCLK clock cycle. When a sampled input shows a low (high)
level in one PCLK clock cycle and a high (low) in the next PCLK clock cycle, a transition
is recognized. If the capture signal is detected while the counter is being incremented,
the counter is first incremented before the capture operation is performed. This ensures
that the latest value of the timer register is always captured.
If bit T2RHEN is set, Timer 2 is started by first falling edge/rising edge at pin T2EX, which
is defined by bit T2REGS. If bit EXEN2 is set, bit EXF2 is also set at the same point when
Timer 2 is started with the same falling edge/rising edge at pin T2EX, which is defined
by bit EDGESEL. The capture will happen with the following negative/positive transitions
at pin T2EX, which is defined by bit EDGESEL.
When the capture operation is completed, bit EXF2 is set and can be used to generate
an interrupt request. Figure 15-3 describes the capture function of Timer 2.
User’s Manual
Timer 2, V 1.2
15-9
V1.1, 2010-09
XC83x
Timer 2
PREN
/12
0
T2PRE
1
fPCLK
C/T2=0
THL2
C/T2=1
TR2
T2
Overflow
RC2
TF2
Timer 2
OR
Interrupt
EXF2
EXEN2
T2EX
Figure 15-3 Capture Mode
15.6
Count Clock
The count clock for the auto-reload mode is chosen by the bit C/T2 in register T2CON.
If C/T2 = 0, a count clock of fPCLK/12 (if prescaler is disabled) is used for the count
operation.
If C/T2 = 1, Timer 2 behaves as a counter that counts 1-to-0 transitions of input pin T2.
The counter samples pin T2 over 2 PCLK clock cycles. If a 1 was detected during the
first clock and a 0 was detected in the following clock, then the counter increments by
one. Therefore, the input levels should be stable for at least 1 clock.
If bit T2RHEN is set, Timer 2 can be started by the falling edge/rising edge on pin T2EX,
which is defined by bit T2REGS.
Note: The C501 compatible feature requires a count resolution of at least 24 clocks.
User’s Manual
Timer 2, V 1.2
15-10
V1.1, 2010-09
XC83x
Timer 2
15.7
External Interrupt Function
While the timer/counter function is disabled (TR2 = 0), it is still possible to generate a
Timer 2 interrupt to the core via an external event at T2EX, as long as Timer 2 remains
enabled (PMCON1.T2_DIS = 0). To achieve this, bit EXEN2 in register T2CON must be
set. As a result, any transition on T2EX will cause either a dummy reload or a dummy
capture, depending on the CP/ RL2 bit selection.
By disabling the timer/counter function, T2EX can be alternatively used to provide an
edge-triggered (rising or falling) external interrupt function, with bit EXF2 serving as the
external interrupt flag.
User’s Manual
Timer 2, V 1.2
15-11
V1.1, 2010-09
XC83x
Timer 2
15.8
Registers Description
All Timer 2 register names described in the following sections are referenced in other
chapters of this document with the module name prefix “T2_”, e.g., T2_T2CON.
The Timer 2 SFRs are located in the standard (non-mapped) SFR area. Table 15-5 lists
these addresses.
Table 15-5
Register Map
Address
Register
C0H
T2CON
C1H
T2MOD
C2H
RC2L
C3H
RC2H
C4H
T2L
C5H
T2H
C6H
T2CON1
User’s Manual
Timer 2, V 1.2
15-12
V1.1, 2010-09
XC83x
Timer 2
15.8.1
Mode Register
The T2MOD is used to configure Timer 2 for various modes of operation.
T2_T2MOD
Timer 2 Mode Register
RMAP: 0, PAGE: X
(C1H)
Reset Value: 00H
7
6
5
4
3
2
1
0
T2REGS
T2RHEN
EDGESEL
PREN
T2PRE
DCEN
rw
rw
rw
rw
rw
rw
Field
Bit
Type Description
DCEN
0
rw
Up/Down Counter Enable
0B
Up/Down Counter function is disabled
Up/Down Counter function is enabled and
1B
controlled by pin T2EX (Up = 1, Down = 0)
T2PRE
[3:1]
rw
Timer 2 Prescaler Bit
Selects the input clock for Timer 2 which is derived
from the peripheral clock.
000B fT2 = fPCLK
001B fT2 = fPCLK / 2
010B fT2 = fPCLK / 4
011B fT2 = fPCLK / 8
100B fT2 = fPCLK / 16
101B fT2 = fPCLK / 32
110B fT2 = fPCLK / 64
111B fT2 = fPCLK / 128
PREN
4
rw
Prescaler Enable
Prescaler is disabled and the 2 or 12 divider
0B
takes effect.
Prescaler is enabled (see T2PRE bit) and the
1B
2 or 12 divider is bypassed.
EDGESEL
5
rw
Edge Select in Capture Mode/Reload Mode
The falling edge at Pin T2EX is selected.
0B
1B
The rising edge at Pin T2EX is selected.
T2RHEN
6
rw
Timer 2 External Start Enable
0B
Timer 2 External Start is disabled.
1B
Timer 2 External Start is enabled.
User’s Manual
Timer 2, V 1.2
15-13
V1.1, 2010-09
XC83x
Timer 2
Field
Bit
Type Description
T2REGS
7
rw
15.8.2
Edge Select for Timer 2 External Start
The falling edge at Pin T2EX is selected.
0B
The rising edge at Pin T2EX is selected.
1B
Control Register
Control register T2CON is used to control the operating modes and interrupt of Timer 2.
In addition, it contains the status flags for interrupt generation.
T2_T2CON
Timer 2 Control Register
RMAP: 0, PAGE: X
(C0H)
Reset Value: 00H
7
6
5
4
3
2
1
0
TF2
EXF2
0
0
EXEN2
TR2
C_T2
CP_RL2
rwh
rwh
r
r
rw
rwh
rw
rw
Field
Bit
Type Description
CP_RL2
0
rw
Capture/Reload Select
0B
Reload upon overflow or upon
negative/positive transition at pin T2EX (when
EXEN2 = 1).
Capture Timer 2 data register contents on the
1B
negative/positive transition at pin T2EX,
provided EXEN2 = 1.The negative or positive
transition at Pin T2EX is selected by bit
EDGESEL.
C_T2
1
rw
Timer or Counter Select
Timer function selected.
0B
Count upon negative edge at pin T2.
1B
TR2
2
rwh
Timer 2 Start/Stop Control
Stop Timer 2.
0B
1B
Start Timer 2.
EXEN2
3
rw
Timer 2 External Enable Control
0B
External events are disabled.
1B
External events are enabled in
Capture/Reload Mode.
User’s Manual
Timer 2, V 1.2
15-14
V1.1, 2010-09
XC83x
Timer 2
Field
Bit
Type Description
EXF2
6
rwh
Timer 2 External Flag
In Capture/Reload Mode, this bit is set by hardware
when a negative/positive transition occurs at pin
T2EX, if bit EXEN2 = 1. This bit must be cleared by
software.
Note: When bit DCEN = 1 in auto-reload mode, no
interrupt request to the core is generated.
TF2
7
rwh
Timer 2 Overflow/Underflow Flag
Set by a Timer 2 overflow/underflow. Must be
cleared by software.
0
[5:4]
r
Reserved
Returns 0 if read; must be written with 0.
Register T2CON1is used to enable the external interrupt and the overflow interrupt.
T2_T2CON1
Timer 2 Control Register 1
RMAP: 0, PAGE: X
7
6
(C6H)
5
4
Reset Value: 03H
3
2
1
0
0
TF2EN
EXF2EN
r
rw
rw
Field
Bit
Type Description
EXF2EN
0
rw
External Interrupt Enable
0B
External interrupt is disabled.
External interrupt is enabled.
1B
TF2EN
1
rw
Overflow/Underflow Interrupt Enable
0B
Overflow/underflow interrupt is disabled.
Overflow/underflow interrupt is enabled.
1B
0
[7:2]
r
Reserved
Returns 0 if read; should be written with 0.
15.8.3
Timer 2 Reload/Capture Register
The RC2 register is used for a 16-bit reload of the timer count upon overflow or a capture
of current timer count depending on the mode selected.
User’s Manual
Timer 2, V 1.2
15-15
V1.1, 2010-09
XC83x
Timer 2
T2_RC2L
Timer 2 Reload/Capture Register, Low Byte(C2H)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
1
0
RC2
rwh
Field
Bit
Type Description
RC2
[7:0]
rwh
Reload/Capture Value [7:0]
If CP/RL2 = 0, these contents are loaded into the
timer register upon an overflow condition.
If CP/RL2 = 1, this register is loaded with the current
timer count upon a negative/positive transition at pin
T2EX when EXEN2 = 1.
T2_RC2H
Timer 2 Reload/Capture Register, Low Byte(C3H)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
1
0
RC2
rwh
Field
Bit
Type Description
RC2
[7:0]
rwh
15.8.4
Reload/Capture Value [15:8]
If CP/RL2 = 0, these contents are loaded into the
timer register upon an overflow condition.
If CP/RL2 = 1, this register is loaded with the current
timer count upon a negative/positive transition at pin
T2EX when EXEN2 = 1.
Timer 2 Count Register
Register T2L and T2L hold the current 16-bit value of the Timer 2 count.
User’s Manual
Timer 2, V 1.2
15-16
V1.1, 2010-09
XC83x
Timer 2
T2_T2L
Timer 2, Low Byte
RMAP: 0, PAGE: X
7
6
(C4H)
5
4
Reset Value: 00H
3
2
1
0
THL2
rwh
Field
Bit
Type Description
THL2
[7:0]
rwh
Timer 2 Value [7:0]
These bits indicate the current 16-bit timer value.
T2_T2H
Timer 2, High Byte
RMAP: 0, PAGE: X
7
6
(C5H)
5
4
Reset Value: 00H
3
2
1
0
THL2
rwh
Field
Bit
Type Description
THL2
[7:0]
rwh
User’s Manual
Timer 2, V 1.2
Timer 2 Value [15:8]
These bits indicate the current 16-bit timer value.
15-17
V1.1, 2010-09
XC83x
Real-Time Clock
16
Real-Time Clock
16.1
Overview
One of the XC83x’s perpherials is the Real-Time Clock (RTC) that, once started, can
work independently of the state of the rest of the microcontroller. There are three
possible clock sources for this real-time clock, mainly the 32.768 kHz external oscillator
via the 32.768 kHz oscillator pad, the 75 kHz internal oscillator and an external clock
input via RTCCLK pin. The 32.768 kHz frequency could be divided down to count time
elapsed with respect to an initial time. Hence a real-time clock.
Features
•
•
•
Time Keeping Mode with 32.768 kHz crystal clock
Periodic Wake-up Mode with 75 kHz internal oscillator
Wake-up source during power down mode
16.2
System Information
This section provides system information relevant to the Real-Time Clock.
16.2.1
Pinning
RTC clock source can be either from on-chip or an external source via a pin, RTCCLK.
The RTCCLK pin assignment for XC83x is shown in Table 16-1.
Table 16-1
RTC Pin Functions in XC83x
Pin
Function
Desciption
Selected By
P3.1
RTCCLK
RTC External Clock Input
–
P3.1
XTAL3
32.768 kHz External Oscillator Input
OSC_CON.XPD = 0B
P3.0
XTAL4
32.768 kHz External Oscillator Output
16.2.2
Interrupt Events and Assignment
Table 16-2 lists the interrupt event sources from the RTC, and the corresponding event
interrupt enable bit and flag bit.
User’s Manual
RTC, V1.0
16-1
V1.1, 2010-09
XC83x
Real-Time Clock
Table 16-2
RTC Interrupt Events
Event
Event Interrupt Enable Bit
Event Flag Bit
RTC compare/wake-up
RTC_RTCON.ECRTC
RTC_RTCON.CFRTC
RTC second time
RTC_RTCON.ESRTC
RTC_RTCON.SFRTC
Table 16-3 shows the interrupt node assignment for each RTC interrupt source.
Table 16-3
RTC Events’ Interrupt Node Control
Event
Interrupt Node
Enable Bit
Interrupt Node Flag Vector
Bit
Address
RTC compare/wake-up
IEN1.EXM
–
4BH
RTC second time
16.2.3
Module Suspend Control
When the On-Chip Debug Support (OCDS) is in Monitor Mode (MMCR2.MMODE = 1)
and the Debug-Suspend signal is active (MMCR2.DSUSP = 1), the timer/counter in RTC
module in XC83x can be suspended based on the settings of their corresponding module
suspend bits in register MODSUSP. The definition of this register is described in
Chapter 10.2.4.
When suspended, only the timer stops counting as the counter input clock is gated off.
The module is still clocked so that module registers are accessible.
16.3
Oscillators
Both 32.768 kHz external oscillator and 75 kHz internal oscillator can be used to clock
the RTC. The 32.768 kHz oscillator receives an input from an external quartz crystal
which is connected across two input pins,XTAL3 and XTAL4 of the 32.768 kHz oscillator
pad in the XC83x. In addition to the usage of 75 kHz oscillator as the input clock to RTC,
it is also used to clock an oscillation watchdog to monitor the 32.768 kHz external
oscillation.
Once power-up, these oscillators can operate irrespective of the state of the
microcontroller. That is, it keeps running even when the device has entered idle or power
down mode 2, 3 and 4. The 32.768 kHz oscillator pad can also be powered down by
software if necessary.
These oscillators, as well as the whole real-time clock, remains in operation during
certain power down modes with a power supply of 2.5 V - 5.5 V.
User’s Manual
RTC, V1.0
16-2
V1.1, 2010-09
XC83x
Real-Time Clock
16.4
Basic Timer Operation
The real-time clock consists of a 41-bit timer which count up. It contains a set of 4 to 6
count registers, collectively know at CNT register, that shows the current count value or
the current time of the real-time clock . Before starting the real-time clock, CNT register
can be written with any value. The value written is used as an initial value for the realtime clock when it is started. Another set of registers, RTCCR register, that consists of 4
to 6 registers can be used for interrupt generation. It can also be used to wake-up device
from power down mode. The RTCCR register is also used to store the capture value
when a capture event is triggered. The real-time clock is started by setting bit RTCC in
the RTCON register to 1. This enables the input clock into the real-time clock timer.
16.5
Real-Time Clock Modes
In the real-time clock operates in four modes. Mode 0 and Mode 2 are the time keeping
mode that a real-time system clock is maintained to represent the current day and time
in hours, minutes and seconds. In thesethis modes, an external oscillator of 32.768 kHz
or a direct external 1 Hz clock is used as the clock input to the real-time clock. Mode 1
is the periodic wake-up mode that uses a 41-bit counter. In this mode, an internal
oscillator of 75 kHz is used as the clock input. Mode 3 which has similiar functions as
Mode 1 uses an external clock input to a 32-bit counter. In XC83x, Mode 1 is selected
by default upon power up. User need to ensure that the switching of mode is performed
when the Real-time clock is in stop mode.
16.5.1
Mode 0: Time Keeping Mode with 32.768 kHz Crystal Clock
Mode 0 of the real-time clock has a time keeping function. It keeps running even when
the device has entered idle and power down mode 2 and 3.
Before the real-time clock starts to run, CNT register of the real-time clock can be written
with any values that indicate the range of milliseconds, seconds, minutes, hours and
days of desired by the user. The value written is used as an initial value for the real-time
clock timer, when it is started by setting bit RTCC in the RTCON register to 1. This bit
also enables the input clock into the real-time clock timer as shown in Figure 16-1. When
an out of range value are programmed to any of the CNT registers, for example, CNT1
register are written with a 70 sec or CNT2 with 80 mins, it will be reset to 0. A read
operation to these registers that are programmed with out of range value will give a 0
value. CNT register is protected by the bit protection scheme as described in the SCU
chapter. The initial count value can only be updated when the protection scheme is being
disabled in the stop mode (RTCC = 0).
User’s Manual
RTC, V1.0
16-3
V1.1, 2010-09
XC83x
Real-Time Clock
Real-Time
Clock Counter
32.768 KHz
OSC
CNT0
(msecs)
9-bits
prescaler
Bit 0
Bit 5
Seconds
Decoder
Minutes
Decoder
Hours
Decoder
Days
Decoder
CNT1
(secs)
CNT2
(mins)
CNT3
(hours)
CNT4/5
(days)
Bit 0
Bit 5
Bit 0
Bit 5
Bit 0
Bit 4
Bit 0
Bit 8
RTCC
RTCCT
RTCCT
RTCCT
Comparator
(msecs)
RTCCR0
(msecs)
Bit 0
Bit 5
RTCCT
RTCCR1
(secs)
Bit 0
Bit 5
RTCCT
Comparator
(mins)
Comparator
(secs)
RTCCR2
(mins)
Bit 0
Bit 5
Comparator
(days)
Comparator
(hours)
RTCCR3
(hours)
Bit 0
Bit 4
RTCCR4/5
(days)
Bit 0
Interrupt
Request
CFRTC
ECTRC
Bit 8
Real-Time Clock Compare/Capture Registers
These bits are unreadable
Figure 16-1 Real-time Clock Mode 0
The real-time clock’s lower 9 bits, which serve as a prescaler into the 32-bit counters,
CNT, are set to an initial value of 000000000B. One increment of the timer is then made
for every cycle of the input clock. With an input clock frequency of 32.768 kHz, one
second in real time will be equivalent to an overflow of a 15-bits timer. Under this
condition, the register CNT5-CNT0 actually hold the real time value in the range of
milliseconds, seconds, minutes, hours and days. Register CNT0 has 6 bits that holds the
range of milliseconds of the real-time clock. Register CNT1 and CNT2 have 6 bits each
that hold the seconds and minutes of the real-time clock. The seconds and minutes
counter will be reset to zero after 60 counts. The flag SFRTC is set to 1 at every second
when the device is in active mode. An interrupt can be triggered at the same time when
bit ESRTC in RTCON register is set to 1. CNT3 register holds the hours of the real-time
clock. It resets to zero after 24 counts. Registers CNT4 and CNT5 hold the days for the
real-time clock. They count for 1 year before it is reset to zero. 1 year could be 365 or
366 days. Bit RTYR in RTCON1 register is used to select between a normal year or a
leap year.
While the real-time clock is in operation, the contents of RTCCR register will be
compared to the real-time clock counter (CNT). This register is programmable by the
user with any values that indicates the seconds, minutes, hours and days. An interrupt
will be generated in active mode when the contents are equal if ECRTC is set to 1; bit
CFRTC in register RTCON will be set. This will generate a wake-up from the software
power-down when the device is in power down mode 2 and 3.The CFRTC flag can be
monitored for the real-time clock wake-up request, but the flag has to be cleared by user
software. In such situation, the real-time clock is not affected and it continues to run. The
User’s Manual
RTC, V1.0
16-4
V1.1, 2010-09
XC83x
Real-Time Clock
handling of the wake-up is similiar to the wake-up from power down mode through
EXINT0 pin.
Note: No wake-up interrupt is generated after wake-up from power down mode without
reset. It is irregardless of the status of ECRTC bit. However, the CFRTC flag must
be set to 1 after wake-up.
Note: User is recommended to read the content of the RTCCR register after writing to it
to ensure that it is a valid value. Any out of range value will caused the compare
operation to be unsuccessful.
Mode 0 of the real-time clock can generate a wake-up request to the XC83x during
power down mode provided all the following conditions are fulfilled:
•
•
•
•
XC83x is in either power down mode 2 and 3,
The power down mode is enabled (bit PD = 1 in PMCON0 register), and
The type of wake-up mode is selected (bit WKSEL in PMCON0 register),
Operating power supply levels (including reduced voltage conditions) are maintained
A capture event could be triggered by setting RTCCT bit in RTCON register to 1. The
previous content in the RTCCR register will be overwritten with the captured CNT values
after 2 CPU clock cycles. An update of the actual compared value is necessary once a
captured event is triggered. In XC83x, it is recommended to trigger a capture event to
read the value of the RTC counter (CNT). There is a potential of reading a wrong 32 bits
real-time value while the RTC is in running mode as only 8 bit of data could be fetch at
one time.
The real-time clock stops counting and CNT register holds the last value when the RTCC
bit is set to 0. Setting this bit subsequently will start a new counting sequence which
begin with the stop count.
Note: A compare match event could happen concurrently with the capture event when
both events happen within the same clock cycle.
16.5.2
Mode 1: Periodic Wake-up Mode with 75 kHz Oscillator Clock
Figure 16-2 shows Mode 1 of the real-time clock. It is the default mode upon power on
reset. In this mode, the real-time clock consists of a 41-bit general purposes timer. The
75 kHz oscillator is the input clock to the timer.
User’s Manual
RTC, V1.0
16-5
V1.1, 2010-09
XC83x
Real-Time Clock
Real-Time Clock Counter
75 KHz
OSC
9-bits
prescaler
CNT0
Bit 0
RTCC
RTCCT
CNT1
Bit 7
Bit 8
CNT2
Bit 15
Bit 16
CNT3
Bit 23 Bit 24
RTCCT
Bit 31
RTCCT
Reset
Timer
RTCCT
32-bits Comparator
Interrupt
Request
CFRTC
ECTRC
RTCCR0
Bit 0
Bit 7
RTCCR1
Bit 8
Bit 16
RTCCR2
Bit 17
RTCCR3
Bit 23 Bit 24
Bit 31
Real-Time Clock Compare/Capture Registers
These bits are unreadable
Figure 16-2 Real-time Clock Mode 1
During power down mode 4, it is able to wake-up at a fixed time by programming the
number of count value that is equivalent to the length of time to wake-up in the RTCCR
register. Similiarly to Mode 0, the timer runs until the CNT value matches the RTCCR
value and set the CFRTC flag. An interrupt will be generated in active mode when
ECRTC is enabled. Concurrently, the 41-bit timer will be reset and count from zero
again. In addition, the counting is always continuous; no reset of count value when a
minute, an hour or a day has reached. The rest of the operations in Mode 1 is similiar to
Mode 0 except that the SFRTC flag will not be set at this mode.
User’s Manual
RTC, V1.0
16-6
V1.1, 2010-09
XC83x
Real-Time Clock
16.5.3
Mode 2: Time Keeping Mode with 1 Hz External Clock
Figure 16-3 shows Mode 2 of the real-time clock. This mode has the similiar functions
as Mode 0 except that the 9 bits prescaler and CNT0 are bypassed. An external clock of
1 Hz via RTCCLK pin is the input clock to CNT1 - CNT5. Similiarly to Mode 0, the timer
runs until the CNT value (CNT1 - CNT5) matches the RTCCR value (RTCCR1 RTCCR5) and set the CFRTC flag. An interrupt will be generated when ECRTC is
enabled. User need to select the RTCCLK pin to input mode and connect to a external
1 Hz clock before the counter can start to run.
In XC83x, RTC Mode 2 cannot be used to wake-up from power down mode.
Real-Time Clock Counter
RTCCLK
(1 Hz
External
Clock)
Seconds
Decoder
Minutes
Decoder
Hours
Decoder
Days
Decoder
CNT1
(secs)
CNT2
(mins)
CNT3
(hours)
CNT4/5
(days)
Bit 0
Bit 5
Bit 0
Bit 5
Bit 0
Bit 4
Bit 0
Bit 8
RTCC
RTCCT
RTCCT
RTCCT
Comparator
(secs)
RTCCR1
(secs)
Bit 0
Bit 5
RTCCT
Comparator
(mins)
Comparator
(hours)
RTCCR2
(mins)
Bit 0
RTCCR3
(hours)
Bit 5
Bit 0
Bit 4
Comparator
(days)
RTCCR4/5
(days)
Bit 0
Interrupt
Request
CFRTC
ECTRC
Bit 8
Real-Time Clock Compare/Capture Registers
Figure 16-3 Real-time Clock Mode 2
16.5.4
Mode 3: Timer Mode with External Clock
Figure 16-4 shows Mode 3 of the real-time clock. In this mode, the real-time clock
consists of a 32-bit general purposes timer. It has the same function of Mode 1 except
that the 9 bits prescaler is bypassed. The external clock via RTCCLK pin is the input
clock to the timer. User need to select the RTCCLK pin to input mode and connect to a
external clock before the counter can start to run.
In XC83x, RTC Mode 3 cannot be used to wake-up from power down mode.
User’s Manual
RTC, V1.0
16-7
V1.1, 2010-09
XC83x
Real-Time Clock
Real-Time Clock Counter
RTCCLK
(External Clock)
CNT0
Bit 0
RTCC
RTCCT
CNT1
Bit 7
Bit 8
CNT2
Bit 15
Bit 16
CNT3
Bit 23 Bit 24
RTCCT
Bit 31
RTCCT
Reset
Timer
RTCCT
32-bits Comparator
Interrupt
Request
CFRTC
ECTRC
RTCCR0
Bit 0
Bit 7
RTCCR1
Bit 8
Bit 16
RTCCR2
Bit 17
RTCCR3
Bit 23 Bit 24
Bit 31
Real-Time Clock Compare/Capture Registers
Figure 16-4 Real-time Clock Mode 3
16.6
Power Saving Mode Option
Once started, the real-time clock continues counting until the bit RTCON.RTCC is
cleared. The real-time clock is not affected by the idle mode of the XC83x, and continues
counting in power down mode except in power down mode 1. In addition, the real-time
clock will not stopped automatically if the bit OSC_CON.XTAL2L or bit
OSC_CON.75KOSC2L status is set to 1. In power-down modes 2, 3 and 4, the real-time
clock continues to run provided:
•
•
the clock source for the real-time clock is available,
VDDP > 2.5 V,
The real-time clock stops operation in software power down mode 1.
User’s Manual
RTC, V1.0
16-8
V1.1, 2010-09
XC83x
Real-Time Clock
16.7
Registers Description
14 SFRs are used to control the operation of real-time clock. They can be accessed from
the standard (non-mapped) SFR area. The registers are described as follows.
Table 16-4 lists the addresses of these SFRs.
Table 16-4
Register Map
Address
Register
95H
RTCON
96H
RTCON1
E1H
CNT0
E2H
CNT1
E3H
CNT2
E4H
CNT3
E5H
CNT4
E6H
CNT5
E7H
RTCCR0
E9H
RTCCR1
EAH
RTCCR2
EBH
RTCCR3
ECH
RTCCR4
EDH
RTCCR5
User’s Manual
RTC, V1.0
16-9
V1.1, 2010-09
XC83x
Real-Time Clock
16.7.1
Real-Time Clock Registers
RTC_RTCON
Real-Time Clock Control Register
RMAP: 0, PAGE: X
(95H)
Reset Value: 02H
7
6
5
4
3
2
1
0
SFRTC
CFRTC
ESRTC
ECRTC
RTCCT
RTM
RTCC
rwh
rwh
rw
rw
rwh
rw
rw
Field
Bits
Type Description
RTCC
0
rw
Real-Time Clock Start/Stop Control
0B
Stop real-time clock Operation
1B
Start real-time clock Operation
RTM
[2:1]
rw
Real-Time Clock Mode
00B Mode 0; Time keeping mode with 32.768 kHz
XTAL clock is selected.
01B Mode 1; Periodic wake-up mode with 75 kHz
oscillator is selected.
10B Mode 2; Time keeping mode with direct 1 Hz
external clock via RTCCLK is selected
11B Mode 3; Timer mode with direct external clock via
RTCCLK is selected.
Note: Mode switching will caused the clock source to be
switched at the same time. Real-time clock must
be in stop operation before the mode can be
changed.
Note: To make a smooth switching of the clock source
from 75 kHz oscillator in Mode 1 to the 32.768 kHz
oscillator in Mode 0 or direct external clock in
Mode 2 and 3, clock output from the crystal
oscillator or external clock source must be kept
stable.
RTCCT
User’s Manual
RTC, V1.0
3
rwh
Real-Time Clock Capture Event Trigger
0B
No action
1B
Capture event is triggered immediately
On set, this bit is held for two PCLK clock cycle, then
cleared by hardware.
Reading this bit always return 0.
16-10
V1.1, 2010-09
XC83x
Real-Time Clock
Field
Bits
Type Description
ECRTC
4
rw
Real-Time Clock Compare Interrupt Enable
0B
Disable real-time clock compare interrupt.
1B
Enable real-time clock compare interrupt.
ESRTC
5
rw
Real-Time Clock Second Timing Interrupt Enable
0B
Disable real-time clock interrupt at every second in
Mode 0.
1B
Enable real-time clock interrupt at every second in
Mode 0.
Note: The interrupt function at every second is only
available in Mode 0 and Mode 2.
CFRTC
6
rwh
Real-Time Clock Compare Flag
This bit is set by hardware when there is a compare
match and can only be cleared by software. A wake-up
request is generated only if the XC83x is either in power
down mode 2, 3 or 4.
SFRTC
7
rwh
Real-Time Clock Second Timing Flag
This bit is set by hardware at every second and can only
be cleared by software. It is only available in Mode 0 and
Mode 2.
RTC_RTCON1
Real-Time Clock Control Register 1
RMAP: 0, PAGE: X
7
6
5
(96H)
4
Reset Value: 00H
3
2
1
0
RTYR
r
rw
Field
Bits
Type Description
RTYR
0
rw
Real-Time Clock Year Type
0B
Normal year; 365 days
1B
Leap year; 366 days.
0
[7:1]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
RTC, V1.0
0
16-11
V1.1, 2010-09
XC83x
Real-Time Clock
In Mode 0, CNT0 - CNT5, are used to represent the real time in the range of
milliseconds, seconds, minutes, hours and days of the real-time clock. In Mode 2,
register CNT1 - CNT5 are available and have the same functionality as in Mode 0.
RTC_CNT0 [Mode 0]
Count Clock Register 0
RMAP: 0, PAGE: X
7
6
(E1H)
5
Reset Value: 00H
4
3
2
0
MILLISECONDS
r
rwh
Field
Bits
1
0
Type Description
MILLISECONDS [5:0]
rwh
Real-Time Clock Milliseconds Range Value [5:0]
These bits indicate the range of milliseconds value
of the current timer. It will be reset to zero after a
count of 3FH. At the same time, the CNT1.secs
value is increased by a count.
0
r
Reserved
Returns 0 if read; should be written with 0.
[7:6]
RTC_CNT1 [Mode 0 and Mode 2]
Count Clock Register 1
RMAP: 0, PAGE: X
7
6
5
(E2H)
4
Reset Value: 00H
3
2
0
SECONDS
r
rwh
Field
Bits
Type Description
SECONDS
[5:0]
rwh
User’s Manual
RTC, V1.0
1
0
Real-Time Clock Seconds Value [5:0]
These bits indicate the seconds value of the
current timer. It will be reset to zero at a count of
60D in Mode 0. At the same time, the
CNT2.minutes value is increased by a count. In
Mode 1,
16-12
V1.1, 2010-09
XC83x
Real-Time Clock
Field
Bits
Type Description
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
RTC_CNT2 [Mode 0 and Mode 2]
Count Clock Register 2
RMAP: 0, PAGE: X
7
6
5
(E3H)
4
Reset Value: 00H
3
2
0
MINUTES
r
rwh
1
0
Field
Bits
Type Description
MINUTES
[5:0]
rwh
Real-Time Clock Minutes Value [5:0]
These bits indicate the minutes value of the
current timer. It will be reset to zero at a count of
60D. At the same time, the CNT3.hours value is
increased by a count.
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
RTC_CNT3 [Mode 0 and Mode 2]
Count Clock Register 3
RMAP: 0, PAGE: X
7
6
5
(E4H)
4
Reset Value: 00H
3
0
HOURS
r
rwh
Field
Bits
Type Description
HOURS
[4:0]
rwh
User’s Manual
RTC, V1.0
2
1
0
Real-Time Clock Hours Value [4:0]
These bits indicate the hours value of the
current timer. It will be reset to zero at a count of
24D. At the same time, the days value in CNT4
and CNT5 register is increased by a count.
16-13
V1.1, 2010-09
XC83x
Real-Time Clock
Field
Bits
Type Description
0
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
RTC_CNT4 [Mode 0 and Mode 2]
Count Clock Register 4
RMAP: 0, PAGE: X
7
6
5
(E5H)
4
Reset Value: 00H
3
2
1
0
DAYS
rwh
Field
Bits
Type Description
DAYS
[7:0]
rwh
Real-Time Clock Days Value [7:0]
These bits indicate the lower 8 bits of the days
value of the current timer.
RTC_CNT5 [Mode 0 and Mode 2]
Count Clock Register 5
RMAP: 0, PAGE: X
7
6
5
(E6H)
4
Reset Value: 00H
3
2
1
0
0
DAYS
r
rwh
Field
Bits
Type Description
DAYS
0
rwh
Real-Time Clock Days Value [8]
These bits indicate the MSB of the days value of
the current timer.
0
[7:1]
r
Reserved
Returns 0 if read; should be written with 0.
4 count registers, CNT0 - CNT3 are used to represent the most significant 32 bits of the
41-bits real-time clock timer in Mode 1 and 32-bits timer in Mode 3.
User’s Manual
RTC, V1.0
16-14
V1.1, 2010-09
XC83x
Real-Time Clock
RTC_CNT0 [Mode 1 and Mode 3]
Count Clock Register 0
RMAP: 0, PAGE: X
7
6
5
(E1H)
4
Reset Value: 00H
3
2
1
0
CNT_VAL
rwh
Field
Bits
Type Description
CNT_VAL
[7:0]
rwh
Real-Time Clock Count Value [7:0]
These bits represent counter value [7:0] of the
current real-time clock timer.
RTC_CNT1 [Mode 1 and Mode 3]
Count Clock Register 1
RMAP: 0, PAGE: X
7
6
5
(E2H)
4
Reset Value: 00H
3
2
1
0
CNT_VAL
rwh
Field
Bits
Type Description
CNT_VAL
[7:0]
rwh
Real-Time Clock Count Value [15:8]
These bits represent counter value [15:8] of the
current real-time clock timer.
RTC_CNT2 [Mode 1 and Mode 3]
Count Clock Register 2
RMAP: 0, PAGE: X
7
6
5
(E3H)
4
Reset Value: 00H
3
2
1
0
CNT_VAL
rwh
User’s Manual
RTC, V1.0
16-15
V1.1, 2010-09
XC83x
Real-Time Clock
Field
Bits
Type Description
CNT_VAL
[7:0]
rwh
Real-Time Clock Count Value [23:16]
These bits represent counter value [23:16] of
the current real-time clock timer.
RTC_CNT3 [Mode 1 and Mode 3]
Count Clock Register 3
RMAP: 0, PAGE: X
7
6
5
(E4H)
4
Reset Value: 00H
3
2
1
0
CNT_VAL
rwh
Field
Bits
Type Description
CNT_VAL
[7:0]
rwh
Real-Time Clock Count Value [31:23]
These bits represent counter value [31:23] of
the current real-time clock timer.
In Mode 0, the range of milliseconds, seconds, minutes, hours and days of the real-time
clock timer can be compared with the content of the RTCCR register in order to generate
a compare or wake-up event. When a capture event is triggered by setting RTCCT bit to
1, the content in the RTCCR register will be overwritten with the captured CNT values
after 2 CPU clock cycles. An update of the actual compared value is necessary once a
captured event is triggered. The RTCCR register consists of 6 registers, RTCCR0 RTCCR5.
In Mode 2, the RTCCR0 register is not available for the compare operation.
RTC_RTCCR0 [Mode 0]
Real-Time Clock Compare/Capture Register 0(E7H)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
0
CC_MSECS
r
rwh
User’s Manual
RTC, V1.0
16-16
1
0
V1.1, 2010-09
XC83x
Real-Time Clock
Field
Bits
Type Description
CC_MSECS
[5:0]
rwh
Compare/Capture Milliseconds Range Value [5:0]
These bits indicate the milliseconds value of the
current timer for the compare/capture operation. The
range is from 0H - 3FH.
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
RTCCR1 [Mode 0 and Mode 2]
Real-Time Clock Compare/Capture Register 1(E9H)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
0
CC_SECONDS
r
rwh
1
0
Field
Bits
Type Description
CC_SECONDS
[5:0]
rwh
Compare/Capture Seconds Value [5:0]
These bits indicate the seconds value of the
current timer for the compare/capture operation.
The range is from 0D - 59D. Values out of this
range will be considered as 0D.
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
RTC_RTCCR2 [Mode 0 and Mode 2]
Real-Time Clock Compare/Capture Register 2(EAH)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
0
CC_MINUTES
r
rwh
User’s Manual
RTC, V1.0
16-17
1
0
V1.1, 2010-09
XC83x
Real-Time Clock
Field
Bits
Type Description
CC_MINUTES
[5:0]
rwh
Compare/Capture Minutes Value [5:0]
These bits indicate the minutes value of the
current timer for the compare/capture operation.
The range is from 0D - 59D. Values out of this
range will be considered as 0D.
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
RTC_RTCCR3 [Mode 0 and Mode 2]
Real-Time Clock Compare/Capture Register 3(EBH)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
0
CC_HOURS
r
rwh
1
0
Field
Bits
Type Description
CC_HOURS
[4:0]
rwh
Compare/Capture Hours Value [4:0]
These bits indicate the hours value of the
current timer for the compare/capture operation.
The range is from 0D - 23D. Values out of this
range will be set to 0D.
0
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
RTC_RTCCR4 [Mode 0 and Mode 2]
Real-Time Clock Compare/Capture Register 4(ECH)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
1
0
CC_DAYS
rwh
User’s Manual
RTC, V1.0
16-18
V1.1, 2010-09
XC83x
Real-Time Clock
Field
Bits
Type Description
CC_DAYS
[7:0]
rwh
Compare/Capture Days Value [7:0]
These bits indicate the lower 8 bits of the days
value of the current timer for the
compare/capture operation.
RTC_RTCCR5 [Mode 0 and Mode 2]
Real-Time Clock Compare/Capture Register 5(EDH)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
1
0
0
CC_
DAYS
r
rwh
Field
Bits
Type Description
CC_DAYS
0
rwh
Compare/Capture Days Value [8]
These bits indicate the MSB of the days value of
the current timer for the compare/capture
operation.
0
[7:1]
r
Reserved
Returns 0 if read; should be written with 0.
In Mode 1 and Mode 3, 4 compare and capture registers, RTCCR0 - RTCCR3 are used
to represent 32 bits of compare values that will generate a compare event when it
matches the counter values as specified in CNT register. When a capture event is
triggered by setting RTCCT bit to 1, the content in the RTCCR register will be overwritten
with the captured CNT values after 2 CPU clock cycles. An update of the actual
compared value is necessary once a captured event is triggered.
RTC_RTCCR0 [Mode 1 and Mode 3]
Real-Time Clock Compare/Capture Register 0(E7H)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
1
0
CC_VAL
rwh
User’s Manual
RTC, V1.0
16-19
V1.1, 2010-09
XC83x
Real-Time Clock
Field
Bits
Type Description
CC_VAL
[7:0]
rwh
Compare/Capture Value [7:0]
These bits represent the compare/capture value
[7:0] of the 32-bits value that could generate a
compare interrupt when it matches with the
current counter values.
RTC_RTCCR1 [Mode 1 and Mode 3]
Real-Time Clock Compare/Capture Register 1(E9H)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
1
0
CC_VAL
rwh
Field
Bits
Type Description
CC_VAL
[7:0]
rwh
Compare/Capture Value [15:8]
These bits represent compare/capture value
[15:8] of the 32-bits value that could generate a
compare interrupt when it matches with the
current counter values.
RTC_RTCCR2 [Mode 1 and Mode 3]
Real-Time Clock Compare/Capture Register 2(EAH)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
1
0
CC_VAL
rwh
Field
Bits
Type Description
CC_VAL
[7:0]
rwh
User’s Manual
RTC, V1.0
Compare/Capture Value [23:16]
These bits represent compare/capture value
[23:16] of the 32-bits value that could generate
a compare interrupt when it matches with the
current counter value.
16-20
V1.1, 2010-09
XC83x
Real-Time Clock
RTC_RTCCR3 [Mode 1 and Mode 3]
Real-Time Clock Compare/Capture Register 3(EBH)
RMAP: 0, PAGE: X
7
6
5
4
3
Reset Value: 00H
2
1
0
CC_VAL
rw
Field
Bits
Type Description
CC_VAL
[7:0]
rwh
User’s Manual
RTC, V1.0
Compare/Capture Value [31:23]
These bits represent compare/capture value
[31:23] of the 32-bits value that could generate
a compare interrupt when it matches with the
current counter value.
16-21
V1.1, 2010-09
XC83x
Real-Time Clock
16.7.2
Oscillator Registers
The 32.768 kHz external oscillation is monitored by the XTAL oscillator watchdog to
detect a frequency lower than the threshold. Register OSC_CON control the power down
of the 32.768 kHz oscillation and the control and status monitor of the XTAL oscillator
watchdog. This register is located in SCU.
OSC_CON
OSC Control Register
RMAP: 0, PAGE: 1
(F4H)
7
6
0
INTOSC
_ST
5
XPD
r
rh
rw
4
Reset Value: 30H
3
2
XTALOWD 75KOSC
XTAL2L
RST
2L
rh
rwh
rh
1
0
48MOSC
2L
RCOWD
RST
rh
rwh
Field
Bits
Type Description
XTALOWDRST
3
rwh
32.768 kHz XTAL Oscillator Watchdog Reset
Setting this bit will reset the XTAL2L status flag to 1
and restart the oscillator detection. This bit will be
automatically reset to 0 and thus always be read
back as 0.
0
No effect.
1
Reset XTAL2L flag to 1 and restart the
oscillator watchdog for 32.768 kHz external
oscillation.
XTAL2L
4
rh
32.768 kHz XTAL Too Low Flag
The Oscillator Watchdog monitors the 32.768 kHz
external oscillator
0
fXTAL is above threshold.
1
fXTAL is below threshold.
XPD
5
rw
32.768 MHz XTAL Power Down Control
0
32.768 MHz XTAL is not powered down.
1
32.768 MHz XTAL is powered down.
User’s Manual
RTC, V1.0
16-22
V1.1, 2010-09
XC83x
UART
17
UART
17.1
Overview
The UART provides a full-duplex asynchronous receiver/transmitter, i.e., it can transmit
and receive simultaneously. It is also receive-buffered, i.e., it can commence reception
of a second byte before a previously received byte has been read from the receive
register. However, if the first byte still has not been read by the time reception of the
second byte is complete, one of the bytes will be lost.
UART Feature:
•
•
•
•
Full-duplex asynchronous modes
– 8-bit or 9-bit data frames, LSB first
– fixed or variable baud rate
Receive buffered
Multiprocessor communication
Interrupt generation on the completion of a data transmission or reception
17.2
System Information
This section provides system information relevant to the UART.
17.2.1
Pinning
In mode 0 (the serial port behaves as shift register), data is shifted in through RXD and
out through RXDO, while the TXD line is used to provide a shift clock which can be used
by external devices to clock data in and out. In modes 1, 2 and 3, the port behaves as
an UART. Data is transmitted on TXD and received on RXD.
Note: XC83x does not support mode 0 operation and therefore, RXDO line is not
connected to any general purpose I/O port.
The UART I/O pins are generally assigned as alternate functions to general purpose I/O
ports. Bit URRIS in register MODPISEL1 is used to select one of the RXD input function.
The UART pin assignment for XC83x is shown in Table 1-1.
Table 17-1
Pin
UART Pin Functions in XC83x
Function Desciption
Selected By
P0.5 RXD_0
UART Receive Data Input 0
MODPISEL1.URRIS = 000B
P0.6 RXD_1
UART Receive Data Input 1
MODPISEL1.URRIS = 001B
P1.0 RXD_2
UART Receive Data Input 2
MODPISEL1.URRIS = 010B
User’s Manual
UART, V 1.6
17-1
V1.1, 2010-09
XC83x
UART
Table 17-1
Pin
UART Pin Functions in XC83x
Function Desciption
Selected By
P3.2 RXD_3
UART Receive Data Input 3
MODPISEL1.URRIS = 011B
P3.1 RXD_4
UART Receive Data Input 4
MODPISEL1.URRIS = 100B
P2.1 RXD_5
UART Receive Data Input 5
MODPISEL1.URRIS = 101B
P2.7 RXD_6
UART Receive Data Input 6
MODPISEL1.URRIS = 110B
P0.6 TXD_0
UART Transmit Data Output 0
P0_ALTSEL0.P6 = 1B
P0_ALTSEL1.P6 = 1B
P0_ALTSEL2.P6 = 0B
P1.0 TXD_1
UART Transmit Data Output 1
P1_ALTSEL0.P0 = 1B
P1_ALTSEL1.P0 = 1B
P1.1 TXD_2
UART Transmit Data Output 2
P1_ALTSEL0.P1 = 1B
P1_ALTSEL1.P1 = 1B
P3.2 TXD_3
UART Transmit Data Output 3
P3_ALTSEL0.P2 = 1B
P3_ALTSEL1.P2 = 0B
P0.5 TXD_4
UART Transmit Data Output 4
P0_ALTSEL0.P5 = 0B
P0_ALTSEL1.P5 = 0B
P0_ALTSEL2.P5 = 1B
P0.7 TXD_5
UART Transmit Data Output 5
P0_ALTSEL0.P7 = 0B
P0_ALTSEL1.P7 = 1B
P0_ALTSEL2.P7 = 0B
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
MODPISEL1 register.
MODPISEL1
Peripheral Input Select Register 1
RMAP: 0, PAGE: 3
7
6
EXINT2IS0 EXINT1IS
r
User’s Manual
UART, V 1.6
rw
5
(F4H)
4
Reset Value: 00H
3
2
1
EXINT0IS
URRIS
rw
rw
17-2
0
V1.1, 2010-09
XC83x
UART
Field
Bits
Type Description
URRIS
[2:0]
rw
17.2.2
UART Receive Input Select
000 UART Receiver Input RXD_0 is selected.
001 UART Receiver Input RXD_1 is selected.
010 UART Receiver Input RXD_2 is selected.
011 UART Receiver Input RXD_3 is selected.
100 UART Receiver Input RXD_4 is selected.
101 UART Receiver Input RXD_5 is selected.
110 UART Receiver Input RXD_6 is selected.
111 Reserved.
Clocking Configuration
The UART runs on the PCLK at a frequency of either 8 MHz or 24 MHz.
17.2.3
Interrupt Events and Assignment
Table 1-2 lists the interrupt event sources from the UART, and the corresponding event
interrupt enable bit and flag bit.
Table 17-2
UART Interrupt Events
Event
Event Interrupt Enable Bit
Event Flag Bit
Data Received
–
SCON.RI
Data Transmitted
SCON.TI
Table 1-3 shows the interrupt node assignment for each UART interrupt source.
Table 17-3
UART Events’ Interrupt Node Control
Event
Interrupt Node
Enable Bit
Interrupt Node Flag Vector
Bit
Address
Data Received
IEN0.ES
–
23H
Data Transmitted
User’s Manual
UART, V 1.6
17-3
V1.1, 2010-09
XC83x
UART
17.3
UART Modes
The UART can be used in four different modes. In mode 0, it operates as an 8-bit shift
register. In mode 1, it operates as an 8-bit serial port. In modes 2 and 3, it operates as a
9-bit serial port. The only difference between mode 2 and mode 3 is the baud rate, which
is fixed in mode 2 but variable in mode 3. The variable baud rate is set by either the
underflow rate on the dedicated baud-rate generator, or by the overflow rate on Timer 1.
The different modes are selected by setting bits SM0 and SM1 to their corresponding
values, as shown in Table 17-4.
Table 17-4
UART Modes
SM0
SM1
Operating Mode
Baud Rate
0
0
Mode 0: 8-bit shift register
fPCLK/2
0
1
Mode 1: 8-bit shift UART
Variable
1
0
Mode 2: 9-bit shift UART
fPCLK/64 or fPCLK/32
1
1
Mode 3: 9-bit shift UART
Variable
17.3.1
Mode 0, 8-Bit Shift Register, Fixed Baud Rate
In mode 0, the serial port behaves as an 8-bit shift register. Data is shifted in through
RXD, and out through RXDO, while the TXD line is used to provide a shift clock which
can be used by external devices to clock data in and out.
The transmission cycle is activated by a write to SBUF. One machine cycle later, the data
has been written to the transmit shift register with a 1 at the 9th bit position. For the next
seven machine cycles, the contents of the transmit shift register are shifted right one
position and a zero shifted in from the left so that when the MSB of the data byte is at the
output position, it has a 1 and a sequence of zeros to its left. The control block then
executes one last shift beforesetting the TI bit.
Reception is started by the condition REN = 1 and RI = 0. At the start of the reception
cycle, 11111110B is written to the receive shift register. In each machine cycle that
follows, the contents of the shift register are shifted left one position and the value
sampled on the RXD line in the same machine cycle is shifted in from the right. When
the 0 of the initial byte reaches the leftmost position, the control block executes one last
shift, loads SBUF and sets the RI bit.
The baud rate for the transfer is fixed at fPCLK/2 where fPCLK is the input clock frequency,
i.e. one bit per machine cycle.
17.3.2
Mode 1, 8-Bit UART, Variable Baud Rate
In mode 1, the UART behaves as an 8-bit serial port. A start bit (0), 8 data bits, and a
stop bit (1) are transmitted on TXD or received on RXD at a variable baud rate.
User’s Manual
UART, V 1.6
17-4
V1.1, 2010-09
XC83x
UART
The transmission cycle is activated by a write to SBUF. The data is transferred to the
transmit register and a 1 is loaded to the 9th bit position (as in mode 0). At phase 1 of
the machine cycle after the next rollover in the divide-by-16 counter, the start bit is copied
to TXD, and data is activated one bit time later. One bit time after the data is activated,
the data starts getting shifted right with zeros shifted in from the left. When the MSB gets
to the output position, the control block executes one last shift and sets the TI bit.
Reception is started by a high to low transition on RXD (sampled at 16 times the baud
rate). The divide-by-16 counter is then reset and 1111 1111B is written to the receive
register. If a valid start bit (0) is then detected (based on two out of three samples), it is
shifted into the register followed by 8 data bits. If the transition is not followed by a valid
start bit, the controller goes back to looking for a high to low transition on RXD. When the
start bit reaches the leftmost position, the control block executes one last shift, then
loads SBUF with the 8 data bits, loads RB8 (SCON.2) with the stop bit, and sets the
RI bit, provided RI = 0, and either SM2 = 0 (see Section 17.4) or the received stop
bit = 1. If none of these conditions is met, the received byte is lost.
The associated timings for transmit/receive in mode 1 are illustrated in Figure 17-1.
User’s Manual
UART, V 1.6
17-5
V1.1, 2010-09
User’s Manual
UART, V 1.6
TI
TXD
Shift
Data
TX
Clock
17-6
RI
Shift
Bit Detector
Sample Times
RXD
RX
Clock
Start Bit
D1
Start Bit
reset
D0
D0
D2
D1
D3
D2
D4
D3
D5
D4
D6
D5
D7
D6
Stop Bit
D7
Stop Bit
XC83x
UART
Transmit
Receive
Figure 17-1 Serial Interface, Mode 1, Timing Diagram
V1.1, 2010-09
XC83x
UART
17.3.3
Mode 2, 9-Bit UART, Fixed Baud Rate
In mode 2, the UART behaves as a 9-bit serial port. A start bit (0), 8 data bits plus a
programmable 9th bit and a stop bit (1) are transmitted on TXD or received on RXD. The
9th bit for transmission is taken from TB8 (SCON.3) while for reception, the 9th bit
received is placed in RB8 (SCON.2).
The transmission cycle is activated by a write to SBUF. The data is transferred to the
transmit register and TB8 is copied into the 9th bit position. At phase 1 of the machine
cycle following the next rollover in the divide-by-16 counter, the start bit is copied to TXD
and data is activated one bit time later. One bit time after the data is activated, the data
starts shifting right. For the first shift, a stop bit (1) is shifted in from the left and for
subsequent shifts, zeros are shifted in. When the TB8 bit gets to the output position, the
control block executes one last shift and sets the TI bit.
Reception is started by a high to low transition on RXD (sampled at 16 times the baud
rate). The divide-by-16 counter is then reset and 1111 1111B is written to the receive
register. If a valid start bit (0) is then detected (based on two out of three samples), it is
shifted into the register followed by 8 data bits. If the transition is not followed by a valid
start bit, the controller goes back to looking for a high to low transition on RXD. When the
start bit reaches the leftmost position, the control block executes one last shift, then
loads SBUF with the 8 data bits, loads RB8 (SCON.2) with the 9th data bit, and sets the
RI bit, provided RI = 0, and either SM2 = 0 (see Section 17.4) or the 9th bit = 1. If none
of these conditions is met, the received byte is lost.
The baud rate for the transfer is either fPCLK/64 or fPCLK/32, depending on the setting of
the top bit (SMOD) of the PCON (Power Control) register, which acts as a Double Baud
Rate selector.
17.3.4
Mode 3, 9-Bit UART, Variable Baud Rate
Mode 3 is the same as mode 2 in all respects except that the baud rate is variable.
In all modes, transmission is initiated by any instruction that uses SBUF as a destination
register. Reception is initiated in the modes by the incoming start bit if REN = 1.
The serial interface also provides interrupt requests when transmission or reception of
the frames has been completed. The corresponding interrupt request flags are TI or RI,
respectively. If the serial interrupt is not used (i.e., serial interrupt not enabled), TI and
RI can also be used for polling the serial interface.
The associated timings for transmit/receive in modes 2 and 3 are illustrated
in Figure 17-2.
User’s Manual
UART, V 1.6
17-7
V1.1, 2010-09
User’s Manual
UART, V 1.6
TI
TXD
Shift
Data
TX
Clock
17-8
RI
Shift
Bit Detector
Sample Times
RXD
RX
Clock
Start Bit
Start Bit
reset
D0
D1
D0
D2
D1
D3
D2
D4
D3
D5
D4
D6
D5
D7
D6
D7
TB8
RB8
Stop Bit
Stop Bit
XC83x
UART
Transmit
Receive
Figure 17-2 Serial Interface, Modes 2 and 3, Timing Diagram
V1.1, 2010-09
XC83x
UART
17.4
Multiprocessor Communication
Modes 2 and 3 have a special provision for multiprocessor communication using a
system of address bytes with bit 9 = 1 and data bytes with bit 9 = 0. In these modes,
9 data bits are received. The 9th data bit goes into RB8. The communication always
ends with one stop bit. The port can be programmed such that when the stop bit is
received, the serial port interrupt will be activated only if RB8 = 1.
This feature is enabled by setting bit SM2 in SCON. One of the ways to use this feature
in multiprocessor systems is described in the following paragraph.
When the master processor wants to transmit a block of data to one of several slaves, it
first sends out an address byte that identifies the target slave. An address byte differs
from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With
SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will
interrupt all slaves, so that each slave can examine the received byte and see if it is being
addressed. The addressed slave will clear its SM2 bit and prepare to receive the data
bytes that will be coming. The slaves that were not being addressed retain their SM2s
as set and ignore the incoming data bytes.
Bit SM2 has no effect in mode 0. SM2 can be used in mode 1 to check the validity of the
stop bit. In a mode 1 reception, if SM2 = 1, the receive interrupt will not be activated
unless a valid stop bit is received.
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UART, V 1.6
17-9
V1.1, 2010-09
XC83x
UART
17.5
Baud Rate Generation
There are several ways to generate the baud rate clock for the serial ports, depending
on the mode in which they are operating.
The baud rates in modes 0 and 2 are fixed, so they use the
•
Fixed clock, (see Section 17.5.1)
In modes 1 and 3, the variable baud rate is generated using either the
•
•
UART baud-rate generator (see Section 17.5.2); or
Timer 1 (see Section 17.5.3)
This selection between the different variable baud rate sources is performed by bit BGS
in LINST register.
“Baud rate clock” and “baud rate” must be distinguished from each other. The serial
interface requires a clock rate that is 16 times the baud rate for internal synchronization.
Therefore, the UART baud-rate generator and Timer 1 must provide a “baud rate clock”
to the serial interface where it is divided by 16 to obtain the actual “baud rate”. The
abbreviation fPCLK refers to the input clock frequency.
17.5.1
Fixed Clock
The baud rates in modes 0 and 2 are fixed. However, while the baud rate in mode 0 can
only be fPCLK/2, the baud rate in mode 2 can be selected as either fPCLK/64 or fPCLK/32
depending on bit SMOD in the PCON register.
Bit SMOD acts as a double baud rate selector, as shown in Equation (17.1). If
SMOD = 0 (value after reset), the baud rate is 1/64 of the input clock frequency fPCLK. If
SMOD = 1, the baud rate is 1/32 of fPCLK.
(17.1)
SMOD
2
Mode 2 baud rate = --------------------- × f PCLK
64
17.5.2
UART Baud-rate Generator
The UART baud-rate generator is used to generate the variable baud rate for the UART
in modes 1 and 3. It has programmable 11-bit reload value, 3-bit prescaler and 5-bit
fractional divider.
The baud-rate generator is clocked derived via a prescaler (fDIV) from the input clock
fPCLK. The baud rate timer counts downwards and can be started or stopped through the
baud rate control run bit BCON.R. Each underflow of the timer provides one clock pulse
to the serial channel. The timer is reloaded with the 11-bit BR_VALUE stored in its reload
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UART, V 1.6
17-10
V1.1, 2010-09
XC83x
UART
register BG each time it underflows. The duration between underflows depends on the
‘n’ value in the fractional divider, which can be selected by the bits BGL.FD_SEL. ‘n’
times out of 32, the timer counts one cycle more than specified by BR_VALUE. The
prescaler is selected by the bits BCON.BRPRE.
Register BG is the dual-function Baud-rate Generator/Reload register. Reading BG
returns the contents of the timer, while writing to BG (low byte) always updates the reload
register.
The BG should be written only when BCON.R is 0. An auto-reload of the timer with the
contents of the reload register is performed one instruction cycle after the next time
BCON.R is set. Any write to BG, while BCON.R is set, will be ignored.
The baud rate of the baud-rate generator depends on the following bits and register
values:
•
•
•
•
Input clock fPCLK
Value of bit field BCON.BRPRE.
Value of bit field BG.FD_SEL
Value of the 11-bit reload value BG.BR_VALUE
Figure 17-3 shows a simplified block diagram of the baud rate generator.
fPCLK
fDIV
Prescaler
Baud rate timer
with
Fractional Divider
fBR
R
Figure 17-3 Simplifed Baud Rate Generator Block Diagram
The following formula calculate the final baud rate.
(17.2)
f PCLK
Baud rate = ------------------------------------------------------------------------------n-
16 × PRE ×  BR_VALUE + ----32
The value of PRE (prescaler) is chosen by the bit field BCON.BRPRE. BR_VALUE
represents the contents of the reload value, taken as unsigned 11-bit integer from the bit
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UART, V 1.6
17-11
V1.1, 2010-09
XC83x
UART
field BG.BR_VALUE. n/32 is defined by the fractional divider selection in bit field
BG.FDSEL.
The maximum baud rate that can be generated is limited to fPCLK/32. Hence, for module
clocks of 8 MHz and 24 MHz, the maximum achievable baud rate is 0.25 MBaud and
0.75 MBaud respectively.
Table 17-5 and Table 17-6 list various commonly used baud rates together with their
corresponding parameter settings and the deviation errors compared to the intended
baud rate.
Table 17-5
Typical Baud Rates of UART (fPCLK = 8 MHz)
Baud rate
(fPCLK =
8 MHz)
PRE
Reload Value Numerator of BG
(BR_VALUE) Fractional
Register
1)
Value
(FD_NUM)
Deviation
Error
115.2 kBaud 1 (BRPRE = 000) 4 (4H)
11 (BH)
008BH
-0.08%
20 kBaud
1 (BRPRE = 000) 25 (19H)
0 (0H)
0320H
0.00%
19.2 kBaud
1 (BRPRE = 000) 26 (1AH)
1 (1H)
0341H
+0.04%
9600 Baud
2 (BRPRE = 001) 26 (1AH)
1 (1H)
0341H
+0.04%
4800 Baud
4 (BRPRE = 010) 26 (1AH)
1 (1H)
0341H
+0.04%
2400 Baud
8 (BRPRE = 011) 26 (1AH)
1 (1H)
0341H
+0.04%
1) The value of the 16-bit BG register is obtained by concantenating the 11-bit BRVALUE and 5-bit FD_NUM into
a 16-bit value.
Table 17-6
Typical Baud Rates of UART (fPCLK = 24 MHz)
Baud rate
(fPCLK =
24 MHz)
PRE
Reload Value Numerator of BG
(BR_VALUE) Fractional
Register
1)
Value
(FD_NUM)
Deviation
Error
115.2 kBaud 1 (BRPRE = 000) 13 (0DH)
1 (01H)
01A1H
-0.08%
20 kBaud
1 (BRPRE = 000) 75 (4BH)
0 (00H)
0960H
+0.00%
19.2 kBaud
1 (BRPRE = 000) 78 (4EH)
4 (04H)
09C4H
+0.00%
9600 Baud
2 (BRPRE = 001) 78 (4EH)
4 (04H)
09C4H
+0.00%
4800 Baud
4 (BRPRE = 010) 78 (4EH)
4 (04H)
09C4H
+0.00%
2400 Baud
8 (BRPRE = 011) 78 (4EH)
4 (04H)
09C4H
+0.00%
1) The value of the 16-bit BG register is obtained by concantenating the 11-bit BRVALUE and 5-bit FD_NUM into
a 16-bit value.
User’s Manual
UART, V 1.6
17-12
V1.1, 2010-09
XC83x
UART
17.5.3
Timer 1
In modes 1 and 3 of UART, Timer 1 can also be used for generating the variable baud
rates. In theory, this timer could be used in any of its modes. But in practice, it should be
set into auto-reload mode (Timer 1 mode 2), with its high byte set to the appropriate
value for the required baud rate. The baud rate is determined by the Timer 1 overflow
rate and the value of SMOD bit in the PCON register as follows:
(17.3)
SMOD
2
× f PCLK
Mode 1, 3 baud rate = ---------------------------------------------------32 × 2 × ( 256 – TH1 )
Alternatively, for a given baud rate, the value of Timer 1 high byte can be derived:
(17.4)
SMOD
2
× f PCLK
TH1 = 256 – --------------------------------------------------------------------32 × 2 × Mode 1, 3 baud rate
Note: Timer 1 can neither indicate an overflow nor generate an interrupt if Timer 0 is in
mode 3; Timer 1 is halted while Timer 0 takes over the use of its control bits and
overflow flag. Hence, the baud rate supplied to the UART is defined by Timer 0
and not Timer 1. User should avoid using Timer 0 and Timer 1 in mode 3 for baud
rate generation.
User’s Manual
UART, V 1.6
17-13
V1.1, 2010-09
XC83x
UART
17.6
LIN Support in UART
The UART module can be used to support the Local Interconnect Network (LIN) protocol
for both master and slave operations. The LIN baud rate detection feature, which
consists of the hardware logic for Break and Synch Field detection, provides the
capability to detect the baud rate within LIN protocol using Timer 2. This allows the UART
module to be synchronized to the LIN baud rate for data transmission and reception.
17.6.1
LIN Protocol
LIN is a holistic communication concept for local interconnected networks in vehicles.
The communication is based on the SCI (UART) data format, a single-master/multipleslave concept, a clock synchronization for nodes without stabilized time base. An
attractive feature of LIN is self-synchronization of the slave nodes without a crystal or
ceramic resonator, which significantly reduces the cost of hardware platform. Hence, the
baud rate must be calculated and returned with every message frame.
The structure of a LIN frame is shown in Figure 17-4. The frame consists of the:
•
•
•
•
header, which comprises a Break (13-bit time low), Synch Byte (55H), and ID field
response time
data bytes (according to UART protocol)
checksum
Frame slot
Frame
Header
Synch
Response
space
Protected
identifier
Interframe
space
Response
Data 1
Data 2
Data N Checksum
Figure 17-4 The Structure of LIN Frame
Each byte field is transmitted as a serial byte, as shown in Figure 17-5. The LSB of the
data is sent first and the MSB is sent last. The start bit is encoded as a bit with value zero
(dominant) and the stop bit is encoded as a bit with value one (recessive).
User’s Manual
UART, V 1.6
17-14
V1.1, 2010-09
XC83x
UART
Byte field
Start
Bit
LSB
(bit 0)
MSB
(bit 7)
Stop
Bit
Figure 17-5 The Structure of Byte Field
The break is used to signal the beginning of a new frame. It is the only field that does not
comply with Figure 17-5. A break is always generated by the master task (in the master
mode) and it must be at least 13 bits of dominant value, including the start bit, followed
by a break delimiter, as shown in Figure 17-6. The break delimiter will be at least one
nominal bit time long.
A slave node will use a break detection threshold of 11 nominal bit times.
Start
Bit
Break
delimit
Figure 17-6 The Break Field
Synch Byte is a specific pattern for determination of time base. The byte field is with the
data value 55H, as shown in Figure 17-7.
A slave task is always able to detect the Break/Synch sequence, even if it expects a byte
field (assuming the byte fields are separated from each other). If this happens, detection
of the Break/Synch sequence will abort the transfer in progress and processing of the
new frame will commence.
Start
Bit
Stop
Bit
Figure 17-7 The Synch Byte Field
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UART, V 1.6
17-15
V1.1, 2010-09
XC83x
UART
The slave task will receive and transmit data when an appropriate ID is sent by the
master:
1.
2.
3.
4.
5.
Slave waits for Synch Break
Slave synchronizes on Synch Byte
Slave snoops for ID
According to ID, slave determines whether to receive or transmit data, or do nothing
When transmitting, the slave sends 2, 4 or 8 data bytes, followed by check byte
17.6.2
LIN Header Transmission
LIN header transmission is only applicable in master mode. In the LIN communication,
a master task decides when and which frame is to be transferred on the bus. It also
identifies a slave task to provide the data transported by each frame. The information
needed for the handshaking between the master and slave tasks is provided by the
master task through the header portion of the frame.
The header consists of a break and synch pattern followed by an identifier. Among these
three fields, only the break pattern cannot be transmitted as a normal 8-bit UART data.
The break must contain a dominant value of 13 bits or more to ensure proper
synchronization of slave nodes.
In the LIN communication, a slave task is required to be synchronized at the beginning
of the protected identifier field of frame. For this purpose, every frame starts with a
sequence consisting of a break field followed by a synch byte field. This sequence is
unique and provides enough information for any slave task to detect the beginning of a
new frame and be synchronized at the start of the identifier field.
17.6.2.1 Automatic Synchronization to the Host
Upon entering LIN communication, a connection is established and the transfer speed
(baud rate) of the serial communication partner (host) is automatically synchronized in
the following steps that are to be included in user software:
STEP 1: Initialize interface for reception and timer for baud rate measurement
STEP 2: Wait for an incoming LIN frame from host
STEP 3: Synchronize the baud rate to the host
STEP 4: Enter for Master Request Frame or for Slave Response Frame
The next section, Section 17.6.2.2, provides some hints on setting up the
microcontroller for baud rate detection of LIN.
Note: Re-synchronization and setup of baud rate are always done for every Master
Request Header or Slave Response Header LIN frame.
User’s Manual
UART, V 1.6
17-16
V1.1, 2010-09
XC83x
UART
17.6.2.2 Initialization of Break/Synch Field Detection Logic
The LIN baud rate detection feature provides the capability to detect the baud rate within
the LIN protocol using Timer 2. Initialization consists of:
•
•
•
•
•
•
•
Serial port of the microcontroller set to Mode 1 (8-bit UART, variable baud rate) for
communication.
Provide the baud rate range via bit field BCON.BGSEL.
Toggle BCON.BRDIS bit (set the bit to 1 before clearing it back to 0) to initialize the
Break/Synch detection logic.
Clear all status flags LINST.BRK, LINST.EOFSYN and LINST.ERRSYN to 0.
Timer 2 is set to capture mode with falling edge trigger at pin T2EX. Bit
T2MOD.EDGESEL is set to 0 by default and bit T2CON.CP/RL2 is set to 1.
Timer 2 external events are enabled. T2CON. EXEN2 is set to 1. (EXF2 flag is set
when a negative transition occurs at pin T2EX)
fT2 can be configured by bit field T2MOD.T2PRE.
Note: It is also recommended to toggle the BCON.BRDIS bit after the reception of each
complete LIN frame to avoid a wrong Break field detection in noisy environments
(i.e. spikes on the LIN bus).
17.6.2.3 Baud Rate Range Selection
The Break/Synch Field detection logic supports a maximum number of bits in the Break
field as defined by Equation (17.5).
(17.5)
4095
Maximum number of bits = Baud Rate × -------------------------------------------Sample Frequency
The sample frequency is given by Equation (17.6).
(17.6)
PCLK Sample Frequency = --------------------------BGSEL
8×2
If the maximum number of bits in the Break field is exceeded, the internal counter will
overflow, which results in a baudrate detection error. Therefore, an appropriate BGSEL
value has to be selected for the required baudrate detection range.
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UART, V 1.6
17-17
V1.1, 2010-09
XC83x
UART
The baud rate range defined by different BGSEL settings is shown in Table 17-7.
Table 17-7
BGSEL Bit Field Definition for Different Input Frequencies
fPCLK
BGSEL
Baud Rate Select for Detection
fpclk/(2184*2^BGSEL) to fpclk/(72*2^BGSEL)
24 MHz
00B
11 kHz to 333.3 kHz
01B
5.5 kHz to 166.7 kHz
10B
2.8 kHz to 83.3 kHz
11B
1.4 kHz to 41.7 kHz
00B
3.7 kHz to 111.1 kHz
01B
1.8 kHz to 55.6 kHz
10B
0.92 kHz to 27.8 kHz
11B
0.46 kHz to 13.9 kHz
8 MHz
Each BGSEL setting supports a range of baud rate for detection. If the baud rate used
is outside the defined range, the baud rate may not be detected correctly.
When fpclk = 24 MHz, the baud rate range between 1.4 kHz to 333.3 kHz can be
detected. The following examples serve as a guide to select BGSEL value:
•
•
•
•
If the baud rate falls in the range of 1.4 kHz to 2.8 kHz, selected BGSEL value is
“11B”.
If the baud rate falls in the range of 2.8 kHz to 5.5 kHz, selected BGSEL value is
“10B”.
If the baud rate falls in the range of 5.5 kHz to 11 kHz, selected BGSEL value is “01B”.
If the baud rate falls in the range of 11 kHz to 333.3 kHz, selected BGSEL value is
“00B”. If the baud rate is 20 kHz, the possible values of BGSEL that can be selected
are “00B”, “01B”, “10B”, and “11B”. However, it is advisable to select “00B” for better
detection accuracy.
The baud rate can also be detected when fpclk = 8 MHz, for which the baud rate range
that can be detected is between 0.46 kHz to 111.1 kHz.
User’s Manual
UART, V 1.6
17-18
V1.1, 2010-09
XC83x
UART
17.6.2.4 LIN Baud Rate Detection
The baud rate detection for LIN is shown in Figure 17-8, the Header LIN frame consists
of the:
•
•
•
SYN Break (13 bit times low)
SYN byte (55H)
Protected ID field
1st negative transition,
set T2RHEN bit
T2 automatically
starts
Last captured value of T2
upon negative transition
EOFSYN bit is set,
T2 is stopped
SYN CHAR (55H)
SYN BREAK
Start
Bit
Check the break field
flag bit BRK is set or not
Stop
Bit
Captured Value (8 bits)
Figure 17-8 LIN Auto Baud Rate Detection
With the first falling edge:
•
The Timer 2 External Start Enable bit (T2MOD.T2RHEN) is set. The falling edge at
pin T2EX is selected by default for Timer 2 External Start (bit T2MOD.T2REGS is 0).
With the second falling edge:
•
Start Timer 2 by the hardware.
With the third falling edge:
•
•
Timer 2 captures the timing of 2 bits of SYN byte.
Check the Break Field Flag bit LINST.BRK.
If the Break Field Flag LINST.BRK is set, software may continue to capture 4/6/8 bits of
SYN byte. Finally, the End of SYN Byte Flag (LINST.EOFSYN) is set, Timer 2 is stopped.
T2 Reload/Capture register (RC2H/L) is the time taken for 2/4/6/8 bits according to the
implementation. Then the LIN routine calculates the actual baud rate, sets the PRE and
BG values if the UART module uses the baud-rate generator for baud rate generation.
After the third falling edge, the software may discard the current operation and continue
to detect the next header LIN frame if the following conditions were detected:
•
•
•
The Break Field Flag LINST.BRK is not set, or
The SYN Byte Error Flag LINST.ERRSYN is set, or
The Break Field Flag LINST.BRK is set, but the End of SYN Byte Flag
LINST.EOFSYN and the SYN Byte Error Flag LINST.ERRSYN are not set.
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UART, V 1.6
17-19
V1.1, 2010-09
XC83x
UART
17.7
Registers Description
Besides the SCON and SBUF registers, which can be accessed from both the standard
(non-mapped) and mapped SFR area, the rest of the UART’s SFRs are located in SCU
page 5 of the standard area. The bit field PAGE of SCU_PAGE register must be
programmed before accessing these registers.
Table 17-8 lists the addresses of these SFRs.
Table 17-8
Register Map
Address
Register
98H
SCON
99H
SBUF
F2H
BCON
F3H
BGL
F4H
BGH
F5H
LINST
User’s Manual
UART, V 1.6
17-20
V1.1, 2010-09
XC83x
UART
17.7.1
UART Registers
UART contains the two Special Function Registers (SFRs), SCON and SBUF. SCON is
the control register and SBUF is the data register. On reset, both SCON and SBUF return
00H. The serial port control and status register is the SFR SCON. This register contains
not only the mode selection bits, but also the 9th data bit for transmit and receive (TB8
and RB8) and the serial port interrupt bits (TI and RI).
SBUF is the receive and transmit buffer of the serial interface. Writing to SBUF loads the
transmit register and initiates transmission. This register is used for both transmit and
receive data. Transmit data is written to this location and receive data is read from this
location, but the two paths are independent.
Reading out SBUF accesses a physically separate receive register.
SBUF
Serial Data Buffer
RMAP: X, PAGE: X
7
6
(99H)
5
4
Reset Value: 00H
3
2
1
0
VAL
rwh
Field
Bits
Type Description
VAL
[7:0]
rwh
Serial Interface Buffer Register
SCON
Serial Channel Control Register
RMAP: X, PAGE: X
(98H)
Reset Value: 00H
7
6
5
4
3
2
1
0
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
rw
rw
rw
rw
rw
rwh
rwh
rwh
Field
Bits
Type Description
RI
0
rwh
User’s Manual
UART, V 1.6
Receive Interrupt Flag
This is set by hardware at the end of the 8th bit on
mode 0, or at the half point of the stop bit in modes
1, 2, and 3. Must be cleared by software.
17-21
V1.1, 2010-09
XC83x
UART
Field
Bits
Type Description
TI
1
rwh
Transmit Interrupt Flag
This is set by hardware at the end of the 8th bit in
mode 0, or at the beginning of the stop bit in modes
1, 2, and 3. Must be cleared by software.
RB8
2
rwh
Serial Port Receiver Bit 9
In modes 2 and 3, this is the 9th data bit received.
In mode 1, this is the stop bit received.
In mode 0, this bit is not used.
TB8
3
rw
Serial Port Transmitter Bit 9
In modes 2 and 3, this is the 9th data bit sent.
REN
4
rw
Enable Receiver of Serial Port
0B
Serial reception is disabled.
1B
Serial reception is enabled.
SM2
5
rw
Enable Serial Port Multiprocessor Communication in
Modes 2 and 3
In mode 2 or 3, if SM2 is set to 1, RI will not be
activated if the received 9th data bit (RB8) is 0.
In mode 1, if SM2 is set to 1, RI will not be activated
if a valid stop bit (RB8) was not received.
In mode 0, SM2 should be 0.
SM1
6
rw
Serial Port Operating Mode Selection
See definition for SM0.
SM0
7
rw
Serial Port Operating Mode Selection [SM0, SM1]
00B Mode 0: 8-bit shift register, fixed baud rate
(fPCLK/2).
01B Mode 1: 8-bit UART, variable baud rate.
10B Mode 2: 9-bit UART, fixed baud rate (fPCLK/64
or fPCLK/32).
11B Mode 3: 9-bit UART, variable baud rate.
User’s Manual
UART, V 1.6
17-22
V1.1, 2010-09
XC83x
UART
17.7.2
Baud-rate Generator Control and Status Registers
PCON
Power Control Register
RMAP: X, PAGE: X
7
6
(87H)
5
4
Reset Value: 00H
3
2
1
0
SMOD
0
GF1
GF0
0
IDLE
rw
r
rw
rw
r
rw
Field
Bits
Type Description
SMOD
7
rw
0
1,[6:4] r
Double Baud Rate Enable
0B
Do not double the baud rate of serial interface
in modes 1, 2 and 3.
1B
Double the baud rate of serial interface in mode
2, and in modes 1 and 3 only if Timer 1 is used
as variable baud rate source.
Reserved
Returns 0 if read; should be written with 0.
BCON
Baud Rate Control Register
RMAP: 0, PAGE: 5
7
6
(F2H)
Reset Value: 00H
5
4
3
BGSEL
0
BRDIS
BRPRE
R
rw
r
rw
rw
rw
Field
Bits
Type Description
R
0
rw
2
1
0
Baud Rate Generator Run Control Bit
0B
Baud-rate generator disabled.
1B
Baud-rate generator enabled.
Note: BR_VALUE should only be written if R = 0.
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UART, V 1.6
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V1.1, 2010-09
XC83x
UART
Field
Bits
Type Description
BRPRE
[3:1]
rw
Prescaler Bit
Selects the input clock for fDIV which is derived from
the peripheral clock.
000B fDIV = fPCLK
001B fDIV = fPCLK/2
010B fDIV = fPCLK/4
011B fDIV = fPCLK/8
100B fDIV = fPCLK/16
101B fDIV = fPCLK/32
Others: reserved
BRDIS
4
rw
Baud Rate Detection Disable
0B
Break/Synch detection is enabled.
1B
Break/Synch detection is disabled.
BGSEL
[7:6]
rw
Baud Rate Select for Detection
For different values of BGSEL, the baud rate range
for detection is defined by the following formula:
fpclk/(2184*2^BGSEL) < baud rate range <
fpclk/(72*2^BGSEL)
where BGSEL = 00B, 01B, 10B, 11B.
See Table 17-7 for bit field BGSEL definition for
different input frequencies.
LINST
LIN Status Register
RMAP: 0, PAGE: 5
(F5H)
Reset Value: 00H
7
6
5
4
3
BGS
SYNEN
ERRSYN
EOFSYN
BRK
0
rw
rw
rwh
rwh
rwh
r
Field
Bits
Type Description
BRK
3
rwh
User’s Manual
UART, V 1.6
2
1
0
Break Field Flag
This bit is set by hardware and can only be cleared
by software.
0B
Break Field is not detected.
1B
Break Field is detected.
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V1.1, 2010-09
XC83x
UART
Field
Bits
Type Description
EOFSYN
4
rwh
End of SYN Byte Interrupt Flag
This bit is set by hardware and can only be cleared
by software.
0B
End of SYN Byte is not detected.
1B
End of SYN Byte is detected.
ERRSYN
5
rwh
SYN Byte Error Interrupt Flag
This bit is set by hardware and can only be cleared
by software.
0B
Error is not detected in SYN Byte.
1B
Error is detected in SYN Byte.
SYNEN
6
rw
End of SYN Byte and SYN Byte Error Interrupts
Enable
0B
End of SYN Byte and SYN Byte Error
Interrupts are not enabled.
1B
End of SYN Byte and SYN Byte Error
Interrupts are enabled.
BGS
7
rw
Baud Rate Generator Select
0B
Baud-rate generator is selected.
1B
Timer 1 is selected as baud rate generator.
17.7.3
Baud-rate Generator Timer/Reload Registers
The low and high bytes of the baud rate timer/reload register BG contains the 11-bit
reload value for the baud rate timer and the 5-bit fractional divider selection.
Reading the low byte of register BG returns the content of the lower three bits of the baud
rate timer and the FD_SEL setting, while reading the high byte returns the content of the
upper 8 bits of the baud rate timer.
Writing to register BG loads the baud rate timer with the reload and fractional divider
values from the BG register, the first instruction cycle after BCON.R is set.
BG should only be written if R = 0.
BGL
Baud Rate Timer/Reload Register, Low Byte
(F3H)
RMAP: 0, PAGE: 5
7
6
5
4
Reset Value: 00H
3
2
BR_VALUE
FD_SEL
rwh
rw
User’s Manual
UART, V 1.6
17-25
1
0
V1.1, 2010-09
XC83x
UART
Field
Bits
Type Description
FD_SEL
[4:0]
rw
Fractional Divider Selection
Selects the fractional divider to be n/32, where n is
the value of FD_SEL and is in the range of 0 to 31.
For example, writing 0001B to FD_SEL selects the
fractional divider to be 1/32.
Note: Fractional divider has no effect if BR_VALUE
= 000H .
BR_VALUE
[7:5]
rwh
Baud Rate Timer/Reload Value
The lower three bits of the 11-bit Baud Rate
Timer/Reload value.
See also description in BGH register.
BGH
Baud Rate Timer/Reload Register, High Byte
(F4H)
RMAP: 0, PAGE: 5
7
6
5
4
Reset Value: 00H
3
2
1
0
BR_VALUE
rwh
Field
Bits
Type Description
BR_VALUE
[7:0]
rwh
User’s Manual
UART, V 1.6
Baud Rate Timer/Reload Value
The upper 8 bits of the 11-bit Baud Rate
Timer/Reload value.
When the 11-bit BR_VALUE is 000H, baud-rate timer
is bypassed.
17-26
V1.1, 2010-09
XC83x
Inter-IC Bus
18
Inter-IC Bus
18.1
Overview
The IIC provides an interface between the microcontroller and an IIC bus that conforms
to the IIC Bus Protocol.
The IIC can operate in either master or slave mode. It performs arbitration in master
mode to allow it to operate in multi-master systems. The IIC provides communication at
data rates of up to 400 KBaud and features 7-bit addressing as well as 10-bit addressing.
Features:
•
•
•
•
•
•
Operates in Master or slave mode
Supports multi-master systems
Performs arbitration and clock synchronization
Supports 7-bit and10-bit addressing modes
Selectable baud rate generation of up to 400 KBaud (fast mode)
Flexible control via interrupt service routines or polling
18.2
System Information
This section provides system information relevant to the IIC.
18.2.1
Pinning
The IIC pin assignment for XC83x is shown in Table 1-1.
Table 18-1
Pin
IIC Pin Functions in XC83x
Function Desciption
Selected By
P0.4 SCL_0
IIC Clock Input/Output
P0_ALTSEL0.P4 = 0B
P0_ALTSEL1.P4 = 0B
P0_ALTSEL2.P4 = 1B
P0.2 SCL_1
IIC Clock Input/Output
P0_ALTSEL0.P2 = 0B
P0_ALTSEL1.P2 = 1B
P3.0 SCL_2
IIC Clock Input/Output
P3_ALTSEL0.P0 = 1B
P3_ALTSEL1.P0 = 1B
P0.7 SCL_3
IIC Clock Input/Output
P0_ALTSEL0.P7 = 0B
P0_ALTSEL1.P7 = 0B
P0_ALTSEL2.P7 = 1B
User’s Manual
IIC, V1.1
18-1
V1.1, 2010-09
XC83x
Inter-IC Bus
Table 18-1
Pin
IIC Pin Functions in XC83x
Function Desciption
Selected By
P0.6 SDA_0
IIC Data Input/Output
P0_ALTSEL0.P6 = 0B
P0_ALTSEL1.P6 = 0B
P0_ALTSEL2.P6 = 1B
P0.3 SDA_1
IIC Data Input/Output
P0_ALTSEL0.P3 = 0B
P0_ALTSEL1.P3 = 1B
P3.2 SDA_2
IIC Data Input/Output
P3_ALTSEL0.P2 = 1B
P3_ALTSEL1.P2 = 1B
Since SCL and SDA have input and output functions within the same set of pin selected,
the input and output signal selection is done using just the Px_ALTSELn signals from the
GPIO module. No separate input selection control (PISEL) is required..
If more than 1 set of input/output are selected via Px_ALTSELn register, the set with the
lower set number has the highest priority. For example, if output signal SDA_0 and
SDA_1 are selected at the same time, the input will only come from SDA_0.
18.2.1.1 Output Pin Configuration
The pin drivers that are assigned to the IIC lines provide open drain outputs. This
ensures that the IIC does not put any load on the IIC bus lines while the IIC is not
powered. Therefore, it is necessary to have external pull-up resistors (approximately
10 KΩ for operation at 100 KBaud, 2 KΩ for operation at 400 KBaud) on the IIC bus lines.
All pins of the IIC that are to be used for IIC bus communication must be switched to
output and their alternate function must be enabled, before any communication can be
established.
If not driven by the IIC module, the pins will switch off their drivers (i.e. driving 1 to an
open drain output). Due to the external pull-up devices, the respective bus levels will
then be 1, which is idle.
18.2.2
Clocking Configuration
The IIC runs on the PCLK at a frequency of either 8 MHz or 24 MHz.
If the IIC functionality is not required at all, it can be completely disabled by gating off its
clock input for maximal power reduction. This is done by setting bit IIC_DIS in register
PMCON1 as described below.
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
PMCON1 register.
User’s Manual
IIC, V1.1
18-2
V1.1, 2010-09
XC83x
Inter-IC Bus
PMCON1
Peripheral Management Control Register 1(EFH)
RMAP: 0, PAGE: 1
7
6
5
IIC_DIS
LTS_DIS
rw
rw
4
CDC_DIS MDU_DIS
rw
3
2
1
0
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
rw
rw
rw
rw
rw
Field
Bits
Type Description
IIC_DIS
7
rw
18.2.3
Reset Value: FFH
IIC Disable Request. Active high.
0
IIC is in normal operation.
1
Request to disable the IIC. (default)
Interrupt Events and Assignment
Table 1-2 lists the interrupt event source from the IIC, and the corresponding event
interrupt enable bit and flag bit.
Table 18-2
IIC Interrupt Events
Event
Event Interrupt Enable Bit
Event Flag Bit
IIC interrupt
CNTR.IEN
CNTR.IFLG
Table 1-3 shows the interrupt node assignment for the IIC interrupt source.
Table 18-3
IIC Events’ Interrupt Node Control
Event
Interrupt Node
Enable Bit
Interrupt Node Flag Vector
Bit
Address
IIC interrupt
IEN1.EX2
–
User’s Manual
IIC, V1.1
18-3
43H
V1.1, 2010-09
XC83x
Inter-IC Bus
18.3
Status Code
The state of the IIC is defined by the 5-bit status code in STAT register.
When STAT contains the status code F8H, no relevant status information is available, no
interrupt is generated and the IFLG bit in the CNTR register is not set. All other status
codes correspond to a defined state of the IIC. When any of these states is entered, the
corresponding status code appears in this register and the IFLG bit in the CNTR register
is set. When the IFLG bit is cleared, the status code returns to F8H.
Table 18-4
Status Code
Value of
Status
STAT register
00H
Bus error
08H
START condition transmitted
10H
Repeated START condition transmitted
18H
Address and write bit transmitted, ACK received
20H
Address and write bit transmitted, ACK not received
28H
Data byte transmitted in master mode, ACK received
30H
Data byte transmitted in master mode, ACK not received
38H
Arbitration lost in address or data byte
40H
Address and read bit transmitted, ACK received
48H
Address and read bit transmitted, ACK not received
50H
Data byte received in master mode, ACK transmitted
58H
Data byte received in master mode, ACK not transmitted
60H
Slave address and write bit received, ACK transmitted
68H
Arbitration lost in address as master, slave address and write bit
received, ACK transmitted
70H
General call address received, ACK transmitted
78H
Arbitration lost in address as master, general call address received,
ACK transmitted
80H
Data byte received after slave address received, ACK transmitted
88H
Data byte received after slave address received, ACK not transmitted
90H
Data byte received after general call address received, ACK
transmitted
98H
Data byte received after general call address received, ACK not
transmitted
User’s Manual
IIC, V1.1
18-4
V1.1, 2010-09
XC83x
Inter-IC Bus
Table 18-4
Status Code
Value of
Status
STAT register
A0H
STOP or repeated START mode received in slave mode
A8H
Slave address and read bit received, ACK transmitted
B0H
Arbitration lost in address as master, slave address and read bit
received, ACK transmitted
B8H
Data byte transmitted in slave mode, ACK received
C0H
Data byte transmitted in slave mode, ACK not received
C8H
Last byte transmitted in slave mode, ACK received
D0H
Second address byte and write bit transmitted, ACK received
D8H
Second address byte and write bit transmitted, ACK not received
E0H
Unused
E8H
Unused
F0H
Unused
F8H
No relevant status information, IFLG = 0
If an illegal condition occurs on the IIC bus, the bus error state is entered (status code
00H). To recover from this state, the STP bit in the CNTR register must be set and the
IFLG bit cleared. The IIC will then return to idle state (status code F8H): no STOP
condition will be transmitted on the IIC bus.
To request resumption of transmission, set the STA bit to 1 at the same time as the STP
bit is set. The IIC will then send a START on recovery from the bus error.
18.4
Baud Rate Generation
To support a wide range of input clock frequencies (fIIC), two dividers are implemented
to generate the required baud rate on the IIC bus in master mode. The two dividers are
defined by the PREDIV and BRP bits in BRCR register.
The baud rate is calculated by the formulae:
(18.1)
f PCLK
f OSCL = -----------------------------------------------------------------2 PREDIV × ( BRP + 1 ) × 10
Table 18-5 shows various commonly used baud rates together with the required dividers
setting.
User’s Manual
IIC, V1.1
18-5
V1.1, 2010-09
XC83x
Inter-IC Bus
Table 18-5
Baud Rate Selection
Baud Rate = 100 KBaud
Baud Rate = 400 KBaud
fPCLK
PREDIV
BRP+1
PREDIV
BRP+1
8 MHz
1 (1H)
4 (4H)
1 (1H)
1 (1H)
24 MHz
1 (1H)
12 (CH)
1 (1H)
3 (3H)
The frequency at which the IIC bus is sampled is calculated by the formulae:
(18.2)
f PCLK
f SAMP = --------------------PREDIV
2
To ensure correct detection of START and STOP conditions on the bus, the IIC must
sample the IIC bus at least ten times faster than the bus clock speed of the fastest master
on the bus. The sampling frequency should therefore be at least 1 MHz in standard
mode or 4 MHz in fast mode to guarantee correct operation with other bus masters.
18.5
Clock Synchronization
If another device on the IIC bus drives the clock line when the IIC is in master mode, the
IIC will synchronize its clock to the IIC bus clock. The high period of the clock will be
determined by the device that generates the shortest high clock period. The low period
of the clock will be determined by the device that generates the longest low clock period.
When the IIC is in master mode and is communicating with a slow slave, the slave may
stretch each bit period by holding the SCL line low until it is ready for the next bit. The
IIC will automatically re-synchronize as described above.
When the IIC is in slave mode, it will hold the SCL line low after each byte has been
transferred until IFLG has been cleared in the CNTR register.
18.6
Bus Arbitration
In master mode, the IIC will check that each transmitted logic 1 appears on the IIC bus
as a logic 1. If another device on the bus over-rules and pulls the SDA line low, arbitration
is lost. If arbitration is lost during the transmission of a data byte or a Not-Acknowledge
bit, the IIC will return to idle state. If arbitration is lost during the transmission of an
address, the IIC will switch to slave mode so that it can recognize its own slave address
or the general call address.
User’s Manual
IIC, V1.1
18-6
V1.1, 2010-09
XC83x
Inter-IC Bus
18.7
Software Reset
A software reset may be applied to the IIC module by writing any value to register SRST
(address DFH). This sets the IIC back to idle (STAT set to F8H) and sets the STP, STA
and IFLG bits of the CNTR register to 0.
18.8
Operating Modes
All operating modes of the IIC module require the ENAB bit of register CNTR to be set
to 1.
18.8.1
Master Transmit
In the master transmit mode, the IIC transmits a number of bytes to a slave receiver.
The master transmit mode is entered by setting the STA bit in register CNTR to ‘1’. The
IIC will then test the IIC bus and will transmit a START condition when the bus is free.
When a START condition has been transmitted, the IFLG bit will be set and the status
code in the STAT register will be 08H. Before this interrupt is serviced, the DATA register
must be loaded with either a 7-bit slave address or the first part of a 10-bit slave address,
with the LSB cleared to ‘0’ (i.e. with an added Write bit) to specify transmit mode. The
IFLG bit should now be cleared to ‘0’ to prompt the transfer to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the Write bit have
been transmitted, IFLG will be set again. A number of status codes are possible in the
STAT register:
User’s Manual
IIC, V1.1
18-7
V1.1, 2010-09
XC83x
Inter-IC Bus
Table 18-6
Status Code after Address is Transmitted in Master Transmit Mode
Code
IIC State
CPU Response
18H
Addr + W,
ACK received
For 7-bit address:
Next IIC Action
Write byte to DATA, clear
IFLG
Transmit data byte,
receives ACK
Or Set STA, clear IFLG
Transmit repeated START
Or Set STP, clear IFLG
Transmit STOP
Or Set STA and STP, clear Transmit STOP then
IFLG
START
For 10-bit address:
Write extended address
byte to DATA, clear IFLG
Transmit extended data
byte
20H
Addr + W,
ACK not received
Same as for code 18H
Same as for code 18H
38H
Arbitration lost
Clear IFLG
Return to idle state
Or set STA, clear IFLG
Transmit START when bus
is free
Clear IFLG, AAK = 0
Receive data byte, transmit
not ACK
Or clear IFLG, AAK = 1
Receive data byte, transmit
ACK
68H
Arbitration lost,
SLA + W received,
ACK transmitted
78H
Arbitration lost,
Same as for code 68H
general call address
received, ACK
transmitted
Same as for code 68H
B0H
Arbitration lost,
SLA + R received,
ACK transmitted
Write byte to DATA, clear
IFLG, AAK = 0
Transmit last byte, receive
ACK
Or write byte to DATA,
clear IFLG, AAK = 1
Transmit data byte, receive
ACK
User’s Manual
IIC, V1.1
18-8
V1.1, 2010-09
XC83x
Inter-IC Bus
If 10-bit addressing is being used, then after the first part of a 10-bit address plus the
Write bit have been successfully transmitted, the status code will be 18H or 20H.
After this interrupt has been serviced and the second part of the address transmitted, the
STAT register will contain one of the following codes:
Table 18-7
Status Code after Second Address Byte (for 10-bit Addressing) is
Transmitted in Master Transmit Mode
Code
IIC State
CPU Response
Next IIC Action
38H
Arbitration lost
Clear IFLG
Return to idle state
Or set STA, clear IFLG
Transmit START when bus
is free
Clear IFLG, AAK = 0
Receive data byte, transmit
not ACK
Or clear IFLG, AAK = 1
Receive data byte, transmit
ACK
Write byte to DATA, clear
IFLG, AAK = 0
Transmit last byte, receive
ACK
Or write byte to DATA,
clear IFLG, AAK = 1
Transmit data byte, receive
ACK
Write byte to DATA, clear
IFLG
Transmit data byte,
receives ACK
Or set STA, clear IFLG
Transmit repeated START
Or set STP, clear IFLG
Transmit STOP
68H
B0H
D0H
Arbitration lost,
SLA + W received,
ACK transmitted
Arbitration lost,
SLA + R received,
ACK transmitted
Second address
byte + W
transmitted, ACK
received
Or set STA and STP, clear Transmit STOP then
IFLG
START
D8H
Second address
Same as for code D0H
byte + W
transmitted, ACK not
received
Same as for code D0H
If a repeated START condition has been transmitted, the status code will be 10H instead
of 08H.
After each data byte has been transmitted, IFLG will be set and one of three status codes
will be in the STAT register:
User’s Manual
IIC, V1.1
18-9
V1.1, 2010-09
XC83x
Inter-IC Bus
Table 18-8
Status Code after Data is Transmited in Master Transmit Mode
Code
IIC State
CPU Response
Next IIC Action
28H
Data byte
transmitted,
ACK received
Write byte to DATA, clear
IFLG
Transmit data byte,
receives ACK
Or set STA, clear IFLG
Transmit repeated START
Or set STP, clear IFLG
Transmit STOP
Or set STA and STP, clear Transmit STOP then
IFLG
START
30H
Data byte
transmitted,
ACK not received
Same as for code 28H
Same as for code 28H
38H
Arbitration lost
Clear IFLG
Return to idle state
Or set STA, clear IFLG
Transmit START when bus
is free
When all bytes have been transmitted, the STP bit should be set by writing a 1 to this bit
in the CNTR register. The IIC will then transmit a STOP condition, clear the STP bit and
return to idle state (status code F8H).
18.8.2
Master Receive
In the master receive mode, the IIC will receive a number of bytes from a slave
transmitter.
After the START condition has been transmitted, the IFLG bit will be set and status code
08H will be in the STAT register. The DATA register should now be loaded with the slave
address (or the first part of a 10-bit slave address), with the LSB set to ‘1’ to signify a
Read. The IFLG bit should now be cleared to ‘0’ to prompt the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read bit have
been transmitted, the IFLG bit will be set again. A number of status codes are possible
in the STAT register:
User’s Manual
IIC, V1.1
18-10
V1.1, 2010-09
XC83x
Inter-IC Bus
Table 18-9
Status Code after Address is Transmitted in Master Receive Mode
Code
IIC State
CPU Response
Next IIC Action
40H
Addr + R
transmitted, ACK
received
Clear IFLG, AAK = 0
Receive data byte, transmit
not ACK
Or clear IFLG, AAK = 1
Receive data byte, transmit
ACK
Addr + R
Set STA, clear IFLG
transmitted, ACK not
received
Or set STP, clear IFLG
Transmit repeated START
48H
Transmit STOP
Or set STA and STP, clear Transmit STOP then
IFLG
START
38H
68H
Arbitration lost
Arbitration lost,
SLA + W received,
ACK transmitted
Clear IFLG
Return to idle state
Or set STA, clear IFLG
Transmit START when bus
is free
Clear IFLG, AAK = 0
Receive data byte, transmit
not ACK
Or clear IFLG, AAK = 1
Receive data byte, transmit
ACK
78H
Arbitration lost,
Same as for code 68H
general call address
received, ACK
transmitted
Same as for code 68H
B0H
Arbitration lost,
SLA + R received,
ACK transmitted
Write byte to DATA, clear
IFLG, AAK = 0
Transmit last byte, receive
ACK
Or write byte to DATA,
clear IFLG, AAK = 1
Transmit data byte, receive
ACK
If 10-bit addressing is being used, the slave is first addressed using the full 10-bit
address plus the Write bit. The master then issues a restart followed the first part of the
10-bit address again, but plus the Read bit – after which the status code will be 40H or
48H. It is the responsibility of the slave to remember that it had been selected prior to the
restart.
If a repeated START condition has been transmitted, the status code will be 10H instead
of 08H.
User’s Manual
IIC, V1.1
18-11
V1.1, 2010-09
XC83x
Inter-IC Bus
After each data byte has been received, IFLG will be set and one of three status codes
will be in the STAT register:
Table 18-10 Status Code after Data is Received in Master Receive Mode
Code
IIC State
CPU Response
Next IIC Action
50H
Data byte received,
ACK transmitted
Read DATA, clear IFLG,
AAK = 0
Receive data byte, transmit
not ACK
Or read DATA, clear IFLG, Receive data byte, transmit
AAK = 1
ACK
58H
38H
Data byte received, Read DATA, set STA, clear Transmit repeated START
not ACK transmitted IFLG
Or read DATA, set STP,
clear IFLG
Transmit STOP
Or read DATA, set STA
and STP, clear IFLG
Transmit STOP then
START
Arbitration lost in not Clear IFLG
ACK bit
Or set STA, clear IFLG
Return to idle state
Transmit START when bus
is free
When all bytes have been received, a not ACK should be transmitted then the STP bit
should be set by writing a ‘1’ to this bit in the CNTR register. The IIC will transmit a STOP
condition, clear the STP bit and return to idle state (status code F8H).
18.8.3
Slave Transmit
In the slave transmit mode, a number of bytes are transmitted to a master receiver. For
the IIC to respond, the AAK bit in the CNTR register needs to be set.
The IIC will enter slave transmit mode when it receives its own slave address and a Read
bit after a START condition. The IIC will then transmit an acknowledge bit and set the
IFLG bit in the CNTR register. The STAT register will contain the status code A8H.
Note: Where the IIC has an extended slave address (signified by 11110B in ADDR[7:3]),
it will first be selected, then there will be a restart followed by another address byte. If
this address byte matches the value stored in ADDR, the IIC will transmit an
acknowledge after this address byte is received. An interrupt will be generated, IFLG will
be set and the status will be A8H. No second address byte will be sent by the master: it
is up to the slave to remember that it had been selected prior to the restart.
User’s Manual
IIC, V1.1
18-12
V1.1, 2010-09
XC83x
Inter-IC Bus
Slave transmit mode can also be entered directly from a master mode if arbitration is lost
in master mode during the transmission of an address and the slave address and Read
bit are received. The status code in the STAT register will then be B0H.
The data byte to be transmitted should then be loaded into the DATA register and IFLG
cleared. When the IIC has transmitted the byte and received an acknowledge, IFLG will
be set and the STAT register will contain B8H. Once the last byte to be transmitted has
been loaded into the DATA register, the AAK bit should be cleared when IFLG is cleared.
After the last byte has been transmitted, IFLG will be set and the STAT register will
contain C8H. The IIC will then return to idle state (status code F8H). The AAK bit must be
set to 1 before slave mode can be entered again.
If no acknowledge is received after transmitting a byte, IFLG will be set and the STAT
register will contain C0H. The IIC will then return to idle state.
If the STOP condition is detected after an acknowledge bit, the IIC will return to idle state.
18.8.4
Slave Receive
In the slave receive mode, a number of data bytes are received from a master
transmitter.
The IIC will enter slave receive mode when it receives its own slave address and a Write
bit (LSB=0) after a START condition. The IIC will then transmit an acknowledge bit and
set the IFLG bit in the CNTR register: the STAT register will then contain status code 60H.
The IIC will also enter slave receive mode when it receives the general call address 00H
(if the GCE bit in the ADDR register is set). The status code will then be 70H.
Note: Where the IIC has an extended slave address (signified by 11110B in ADDR[7:3]),
it will transmit an acknowledge after the first address byte is received but no interrupt will
be generated, IFLG will not be set and the status will not change. Only after the second
address byte has been received will the IIC generate an interrupt, set the IFLG bit and
the status code as described above.
Slave receive mode can also be entered directly from a master mode if arbitration is lost
in master mode during the transmission of an address and the slave address and Write
bit (or the general call address if bit GCE in the ADDR register is set to 1) are received.
The status code in the STAT register will then be 68H if the slave address was received
or 78H if the general call address was received. The IFLG bit must be cleared to ‘0’ to
allow the data transfer to continue.
If the AAK bit in the CNTR register is set to 1, then after each byte is received, an
acknowledge bit (low level on SDA) is transmitted and the IFLG bit is set: the STAT
register will then contain status code 80H (or 90H if slave receive mode was entered with
the general call address). The received data byte can be read from the DATA register
and the IFLG bit must be cleared to allow the transfer to continue. When the STOP
condition or a repeated START condition is detected after the acknowledge bit, then the
IFLG bit is set and the STAT register will contain status code A0H.
User’s Manual
IIC, V1.1
18-13
V1.1, 2010-09
XC83x
Inter-IC Bus
If the AAK bit is cleared to 0 during a transfer, the IIC will transmit a not acknowledge bit
(high level on SDA) after the next byte is received, and set the IFLG bit. The STAT
register will contain status code 88H (or 98H if slave receive mode was entered with the
general call address). When the IFLG bit has been cleared to 0, the IIC will return to idle
state (status code F8H).
User’s Manual
IIC, V1.1
18-14
V1.1, 2010-09
XC83x
Inter-IC Bus
18.9
Registers Description
The IIC Special Function Registers are accessed from the standard (non-mapped) SFR
area. Table 18-11 lists the IIC registers with their addresses.
Table 18-11 Register Map
Address
Register
Description
DAH
IIC_ADDR
Slave Address Register
DBH
IIC_DATA
Data Byte Register
DCH
IIC_CNTR
Control Register
DDH
IIC_STAT
Status Register (read only)
DDH
IIC_BRCR
Clock Control Register (write only)
DEH
IIC_ADDRX
Extended Slave Address Register
DFH
IIC_SRST
Software Reset Register
User’s Manual
IIC, V1.1
18-15
V1.1, 2010-09
XC83x
Inter-IC Bus
18.9.1
Slave Address Registers
The ADDR register contains the bit to enable the general call address option and the
device address of the IIC in 7-bit addressing mode. For 10-bit addressing, part of the
address bits is located in ADDRX register.
IIC_ADDR
Slave Address Register
RMAP: 0, PAGE: X
7
6
(DAH)
5
4
Reset Value: 00H
3
2
1
0
SLA
GCE
rw
rw
Field
Bits
Type Description
GCE
0
rw
General Call Address Enable
0B
General call address option is disabled.
1B
General call address option is enabled.
SLA
[7:1]
rw
Slave Address
For 7-bit addressing, SLA contains the 7-bit address
of the IIC when in slave mode.
For 10-bit addressing, the uppermost five bits
SLA[6:2] are fixed at 11110B, while SLA[1:0]
contains the uppermost two bits of the 10-bit slave
address. The remaining lower 8 bits are located in
IIC_ADDRX register.
User’s Manual
IIC, V1.1
18-16
V1.1, 2010-09
XC83x
Inter-IC Bus
The ADDRX register contains the lower 8-bit slave address of the device in 10-bit
addressing mode.
IIC_ADDRX
Extended Slave Address Register
RMAP: 0, PAGE: X
7
6
5
(DEH)
4
Reset Value: 00H
3
2
1
0
SLAX
rw
Field
Bits
Type Description
SLAX
[7:0]
rw
18.9.2
Data Register
Extended Slave Address
For 10-bit addressing, SLAX contains the lower 8-bit
address of the IIC when in slave mode.
The DATA register contains the data byte or slave address to be transmitted or the data
byte that has just been received.
IIC_DATA
Data Register
RMAP: 0, PAGE: X
7
6
(DBH)
5
4
Reset Value: 00H
3
2
1
0
DATA
rw
Field
Bits
Type Description
DATA
[7:0]
rw
User’s Manual
IIC, V1.1
Data Byte
Data to be sent or received.
18-17
V1.1, 2010-09
XC83x
Inter-IC Bus
18.9.3
Control Register
The CNTR register is used to configure the IIC and generate START and STOP
conditions. It also contains the interrupt status flag.
IIC_CNTR
Control Register
RMAP: 0, PAGE: X
(DCH)
Reset Value: 00H
7
6
5
4
3
2
IEN
ENAB
STA
STP
IFLG
AAK
0
rw
rw
rwh
rwh
rwh
rw
r
Field
Bits
Type Description
AAK
2
rw
1
0
Assert Acknowledge
0B
A NACK is sent when a data byte is received
in master or slave mode.
1B
An ACK is sent if one of the following has been
received: 1) a matching 7-bit or either byte of
the 10-bit slave address; 2) general call
address; 3) a data byte in master or slave
mode.
Note: If the AAK bit is cleared to 0 in slave
transmitter mode, the byte in the DATA
register is assumed to be the last byte.
IFLG
User’s Manual
IIC, V1.1
3
rwh
Interrupt Flag
The IFLG bit is set by hardware and can only be
cleared by software.
0B
No interrupt event has occurred.
1B
An interrupt event has occurred.
18-18
V1.1, 2010-09
XC83x
Inter-IC Bus
Field
Bits
Type Description
STP
4
rwh
Master Mode Stop
When the STP bit is set to 1, the IIC will transmit a
STOP condition.
If the STP bit is set while the IIC is in slave mode, no
STOP condition will be transmitted on the IIC bus but
the IIC behaves as if a STOP condition has been
received.
If both STA and STP bits are set, the IIC will first
transmit a STOP condition (if in master mode) before
transmitting a START condition.
0B
The IIC does not transmit any STOP condition.
1B
The IIC transmits a STOP condition on the IIC
bus.
Note: The STP bit is cleared automatically after the
STOP condition has been sent ; writing 0 to
this bit has no effect.
STA
5
rwh
Master Mode Start
When the STA bit is set to 1, the IIC will enter master
mode and transmit a START condition once the IIC
bus is free.
If the IIC is already in master mode and one or more
bytes have been transmitted, a repeated START
condition will be transmitted.
If the IIC is still being accessed in slave mode, the IIC
will complete the data transfer in slave mode and
enter master mode once the IIC bus has been
released.
0B
The IIC does not enter master mode.
1B
The IIC enters master mode and transmits a
START condition on the IIC bus.
Note: The STA bit is cleared automatically after the
START condition has been sent ; writing 0 to
this bit has no effect.
ENAB
6
rw
IIC Enable
0B
The IIC is disabled.
1B
The IIC is enabled.
IEN
7
rw
Interrupt Enable
0B
The interrupt is disabled.
1B
The interrupt is enabled.
User’s Manual
IIC, V1.1
18-19
V1.1, 2010-09
XC83x
Inter-IC Bus
Field
Bits
Type Description
0
[1:0]
r
18.9.4
Reserved
Returns 0 if read; should be written with 0.
Status Register
The read-only STAT register stores the 5-bit status code of the IIC.
IIC_STAT
Status Register [Read Mode]
RMAP: 0, PAGE: X
7
6
5
(DDH)
4
Reset Value: F8H
3
2
1
STAT
0
r
r
0
Field
Bits
Type Description
STAT
[7:3]
r
Status Code
5-bit status code (see Table 18-4).
0
[2:0]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
IIC, V1.1
18-20
V1.1, 2010-09
XC83x
Inter-IC Bus
18.9.5
Baud Rate Control Register
The write-only BRCR register controls the sampling frequency of the IIC and the baud
rate of the IIC in master mode.
IIC_BRCR
Baud Rate Control Register [Write Mode]
(DDH)
RMAP: 0, PAGE: X
7
6
5
4
Reset Value: 00H
3
2
1
0
0
BRP
PREDIV
w
w
w
Field
Bits
Type Description
PREDIV
[2:0]
w
Predivider for Baud Rate Generation
000B Predivider factor of 1 is used.
001B Predivider factor of 2 is used.
010B Predivider factor of 4 is used.
011B Predivider factor of 8 is used.
100B Predivider factor of 16 is used.
101B Predivider factor of 32 is used.
110B Predivider factor of 64 is used.
111B Predivider factor of 128 is used.
BRP
[6:3]
w
Baud Rate Prescaler
Determines the baud rate for the IIC in master mode.
0
7
w
Reserved
Should be written with 0.
18.9.6
Software Reset Register
The SRST register provides for a software reset on the IIC.
IIC_SRST
Software Reset Register
RMAP: 0, PAGE: X
7
6
(DFH)
5
4
Reset Value: XXH
3
2
1
0
SRST
w
User’s Manual
IIC, V1.1
18-21
V1.1, 2010-09
XC83x
Inter-IC Bus
Field
Bits
Type Description
SRST
[7:0]
w
User’s Manual
IIC, V1.1
Software Reset
Writing any value to the SRST bit field triggers a soft
reset on the IIC.
18-22
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
19
High-Speed Synchronous Serial Interface
19.1
Overview
The High-Speed Synchronous Serial Interface (SSC) supports both full-duplex and
half-duplex serial synchronous communication. The serial clock signal can be generated
by the SSC itself (Master Mode) through its own 16-bit baud rate generator, or can be
received from an external master (Slave Mode). Data width, shift direction, clock polarity,
and phase are programmable. This allows communication with SPI-compatible devices
using other synchronous serial interfaces. Transmission and reception of data is doublebuffered.
Features
•
•
•
•
•
•
Master and Slave Mode operation
– Full-duplex or half-duplex operation
Transmit and receive buffered
Flexible data format
– Programmable number of data bits: 2 to 8 bits
– Programmable shift direction: Least Significant Bit (LSB) or Most Significant Bit
(MSB) shift first
– Programmable clock polarity: idle low or high state for the shift clock
– Programmable clock/data phase: data shift with leading or trailing edge of the shift
clock
Variable baud rate
Compatible with Serial Peripheral Interface (SPI)
Interrupt generation
– On a transmitter empty condition
– On a receiver full condition
– On an error condition (receive, phase, baud rate, transmit error)
Figure 17-1 shows the block diagram of the SSC.
User’s Manual
SSC, V1.4
19-1
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
PCLK
Baud-rate
Generator
SS_CLK
MS_CLK
Clock
Control
Shift
Clock
RIR
SSC Control Block
Register CON
Status
Receive Int. Request
TIR
Transmit Int. Request
EIR
Error Int. Request
Control
TXD(Master)
Pin
Control
16-Bit Shift
Register
RXD(Slave)
TXD(Slave)
RXD(Master)
Transmit Buffer
Register TB
Receive Buffer
Register RB
Internal Bus
Figure 19-1 SSC Block Diagram
19.2
System Information
This section provides system information relevant to the SSC.
19.2.1
Pinning
The SSC pin assignment for XC83x is shown in Table 17-1.
User’s Manual
SSC, V1.4
19-2
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
Table 19-1
Pin
SSC Pin Functions in XC83x
Function Desciption
Selected By
P0.4 SCK_0
SSC Clock Input/Output
For Input:
MODPISEL.CIS = 00B
For Output:
P0_ALTSEL0.P4 = 0B
P0_ALTSEL1.P4 = 1B
P0_ALTSEL2.P4 = 0B
P3.0 SCK_1
SSC Clock Input/Output
For Input:
MODPISEL.CIS = 01B
For Output:
P3_ALTSEL0.P0 = 0B
P3_ALTSEL1.P0 = 1B
P2.6 SCK_2
SSC Clock Input
For Input:
MODPISEL.CIS = 10B
P2.2 SCK_3
SSC Clock Input
For Input:
MODPISEL.CIS = 11B
P0.5 MTSR_0
SSC Master Transmit Output
/Slave Receive Input
For Input:
MODPISEL.SIS = 000B
For Output:
P0_ALTSEL0.P5 = 0B
P0_ALTSEL1.P5 = 1B
P0_ALTSEL2.P5 = 0B
P0.6 MTSR_1
SSC Slave Receive Input
For Input:
MODPISEL.SIS = 001B
P0.0 MTSR_2
SSC Master Transmit Output
/Slave Receive Input
For Input:
MODPISEL.SIS = 010B
For Output:
P0_ALTSEL0.P0 = 0B
P0_ALTSEL1.P0 = 1B
P0.1 MTSR_3
SSC Slave Receive Input
For Input:
MODPISEL.SIS = 011B
P3.1 MTSR_4
SSC Master Transmit Output
/Slave Receive Input
For Input:
MODPISEL.SIS = 100B
For Output:
P3_ALTSEL0.P1 = 0B
P3_ALTSEL1.P1 = 1B
User’s Manual
SSC, V1.4
19-3
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
Table 19-1
Pin
SSC Pin Functions in XC83x
Function Desciption
Selected By
P3.2 MTSR_5
Slave Receive Input
For Input:
MODPISEL.SIS = 101B
P2.1 MTSR_6
Slave Receive Input
For Input:
MODPISEL.SIS = 110B
P2.7 MTSR_7
Slave Receive Input
For Input:
MODPISEL.SIS = 111B
P0.6 MRST_0
SSC Master Receive Input
/Slave Transmit Output
For Input:
MODPISEL.MIS = 000B
For Output:
P0_ALTSEL0.P6 = 0B
P0_ALTSEL1.P6 = 1B
P0_ALTSEL2.P6 = 0B
P0.5 MRST_1
SSC Master Receive Input
For Input:
MODPISEL.MIS = 001B
P0.1 MRST_2
SSC Master Receive Input
/Slave Transmit Output
For Input:
MODPISEL.MIS = 010B
For Output:
P0_ALTSEL0.P1 = 0B
P0_ALTSEL1.P1 = 1B
P0.0 MRST_3
SSC Master Receive Input
For Input:
MODPISEL.MIS = 011B
P3.1 MRST_4
SSC Master Receive Input
For Input:
MODPISEL.MIS = 100B
P3.2 MRST_5
SSC Master Receive Input
/Slave Transmit Output
For Input:
MODPISEL.MIS = 101B
For Output:
P3_ALTSEL0.P2 = 0B
P3_ALTSEL1.P2 = 1B
The SSC uses three lines to communicate with the external world. Pin SCK serves as
the clock line, while pins MRST (Master Receive/Slave Transmit) and MTSR (Master
Transmit/Slave Receive) serve as the serial data input/output lines.
Each of the input lines can be selected from one of several different sources. The
selection is done in the MODPISEL register. Similarly, each of the output lines can be
also selected from several different sources. However, the selection is done at the
respective Ports’ ALTSELx registers.
User’s Manual
SSC, V1.4
19-4
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
MODPISEL register.
MODPISEL
Peripheral Input Select Register
RMAP: 0, PAGE: 3
7
6
5
(F3H)
4
Reset Value: 00H
3
2
1
CIS
SIS
MIS
rw
rw
rw
0
Field
Bits
Type Description
MIS
[2:0]
rw
Master Mode Receive Input Select
000 SSC Master Receiver Input 0 is selected.
001 SSC Master Receiver Input 1 is selected.
010 SSC Master Receiver Input 2 is selected.
011 SSC Master Receiver Input 3 is selected.
100 SSC Master Receiver Input 4 is selected.
101 SSC Master Receiver Input 5 is selected.
110 Reserved.
111 Reserved.
SIS
[5:3]
rw
Slave Mode Receive Input Select
000 SSC Slave Receiver Input 0 is selected.
001 SSC Slave Receiver Input 1 is selected.
010 SSC Slave Receiver Input 2 is selected.
011 SSC Slave Receiver Input 3 is selected.
100 SSC Slave Receiver Input 4 is selected.
101 SSC Slave Receiver Input 5 is selected.
110 SSC Slave Receiver Input 6 is selected.
111 SSC Slave Receiver Input 7 is selected.
CIS
[7:6]
rw
Slave Mode Clock Input Select
00
SSC Slave Clock Input 0 is selected.
01
SSC Slave Clock Input 1 is selected.
10
SSC Slave Clock Input 2 is selected.
11
SSC Slave Clock Input 3 is selected.
User’s Manual
SSC, V1.4
19-5
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
19.2.2
Clocking Configuration
The SSC runs on the PCLK at a frequency of either 8 MHz or 24 MHz.
If the SSC functionality is not required at all, it can be completely disabled by gating off
its clock input for maximal power reduction.
The bit field PAGE of register SCU_PAGE must be programmed before accessing the
PMCON1 register.
PMCON1
Peripheral Management Control Register 1(EFH)
RMAP: 0, PAGE: 1
7
6
5
IIC_DIS
LTS_DIS
rw
rw
4
CDC_DIS MDU_DIS
rw
3
2
1
0
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
rw
rw
rw
rw
rw
Field
Bits
Type Description
SSC_DIS
1
rw
19.2.3
Reset Value: FFH
SSC Disable Request. Active high.
0
SSC is in normal operation.
1
Request to disable the SSC. (default)
Interrupt Events and Assignment
Table 17-2 lists the interrupt event sources from the SSC, and the interrupt node
assignment for each SSC interrupt source.
Note: All SSC interrupt enable bits and flags are located at the node level.
Table 19-2
SSC Events’ Interrupt Node Control
Event
Interrupt Node
Enable Bit
Interrupt Node Flag Vector
Bit
Address
Start-of-Transmission
MODIEN.TIREN;
IEN1.ESSC
IRCON1.TIR
3BH
End-of-Transmission
MODIEN.RIREN;
IEN1.ESSC
IRCON1.RIR
3BH
Occurrence-of-Error
MODIEN.EIREN;
IEN1.ESSC
IRCON1.EIR
3BH
User’s Manual
SSC, V1.4
19-6
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
The three interrupt events of SSC module are of interrupt structure 2 and register
MODIEN is used to enable the interrupt. The bit field PAGE of register SCU_PAGE must
be programmed before accessing the MODIEN register.
MODIEN
Peripheral Interrupt Enable Register (F7H)
RMAP: 0, PAGE: 3
7
6
5
4
CCU6SR3 CCU6SR2
EN
EN
rw
r
rw
Reset Value: 07H
3
2
1
0
0
RIREN
TIREN
EIREN
r
rw
rw
rw
Field
Bits
Type Description
EIREN
0
rw
SSC Error Interrupt Enable
0
Error interrupt is disabled
1
Error interrupt is enabled
TIREN
1
rw
SSC Transmit Interrupt Enable
0
Transmit interrupt is disabled
1
Transmit interrupt is enabled
RIREN
2
rw
SSC Receive Interrupt Enable
0
Receive interrupt is disabled
1
Receive interrupt is enabled
0
[5:3]
r
Reserved
Returns 0 if read; should be written with 0.
19.3
General Operation
The SSC supports full-duplex and half-duplex synchronous communication up to
12 MBaud (@ 24 MHz module clock). The serial clock signal can be generated by the
SSC itself (Master Mode) or can be received from an external master (Slave Mode). Data
width, shift direction, clock polarity, and phase are programmable. This allows
communication with SPI-compatible devices. Transmission and reception of data is
double-buffered. A 16-bit baud-rate generator provides the SSC with a separate serial
clock signal.
The SSC can be configured in a very flexible way, so it can be used with other
synchronous serial interfaces, can serve for master/slave or multimaster
interconnections or can operate compatible with the popular SPI interface. Thus, the
SSC can be used to communicate with shift registers (I/O expansion), peripherals (e.g.
EEPROMs, etc.) or other controllers (networking). The SSC supports half-duplex and
User’s Manual
SSC, V1.4
19-7
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
full-duplex communication. Data is transmitted or received on lines TXD and RXD,
normally connected with pins MTSR (Master Transmit/Slave Receive) and MRST
(Master Receive/Slave Transmit). The clock signal is output via line MS_CLK (Master
Serial Shift Clock) or input via line SS_CLK (Slave Serial Shift Clock). Both lines are
normally connected to pin SCLK.
19.3.1
Operating Mode Selection
The operating mode of the serial channel SSC is controlled by its control register CON.
This register serves two purposes:
•
•
During programming (SSC disabled by CON.EN = 0), it provides access to a set of
control bits
During operation (SSC enabled by CON.EN = 1), it provides access to a set of status
flags.
The shift register of the SSC is connected to both the transmit lines and the receive lines
via the pin control logic. Transmission and reception of serial data are synchronized and
take place at the same time, i.e. the same number of transmitted bits is also received.
Transmit data is written into the Transmit Buffer (TB) and is moved to the shift register
as soon as this is empty. An SSC master (CON.MS = 1) immediately begins
transmitting, while an SSC slave (CON.MS = 0) will wait for an active shift clock. When
the transfer starts, the busy flag CON.BSY is set and the Transmit Interrupt Request line
TIR will be activated to indicate that register TB may be reloaded again. When the
programmed number of bits (2 … 8) has been transferred, the contents of the shift
register are moved to the Receive Buffer RB and the Receive Interrupt Request line RIR
will be activated. If no further transfer is to take place (TB is empty), CON.BSY will be
cleared at the same time. Software should not modify CON.BSY, as this flag is hardware
controlled.
Note: The SSC starts transmission and sets CON.BSY minimum two clock cycles after
transmit data is written into TB. Therefore, it is not recommended to poll CON.BSY
to indicate the start and end of a single transmission. Instead, interrupt service
routine should be used if interrupts are enabled, or the interrupt flags IRCON1.TIR
and IRCON1.RIR should be polled if interrupts are disabled.
Note: Only one SSC (etc.) can be master at a given time.
The transfer of serial data bits can be programmed in many respects:
•
•
•
•
•
The data width can be specified from 2 bits to 8 bits
A transfer may start with either the LSB or the MSB
The shift clock may be idle low or idle high
The data bits may be shifted with the leading edge or the trailing edge of the shift
clock signal
The baud rate may be set from 183.11 Baud up to 12 MBaud (@ 24 MHz module
clock)
User’s Manual
SSC, V1.4
19-8
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
•
The shift clock can be generated (MS_CLK) or can be received (SS_CLK)
These features allow the adaptation of the SSC to a wide range of applications requiring
serial data transfer.
The Data Width Selection supports the transfer of frames of any data length, from 2-bit
“characters” up to 8-bit “characters”. Starting with the LSB (CON.HB = 0) allows
communication with SSC devices in Synchronous Mode or with 8051 like serial
interfaces for example. Starting with the MSB (CON.HB = 1) allows operation compatible
with the SPI interface.
Regardless of the data width selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right-aligned in registers TB and RB, with the LSB of the
transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the
internal shift register logic. The unselected bits of TB are ignored; the unselected bits of
RB will not be valid and should be ignored by the receiver service routine.
The Clock Control allows the adaptation of transmit and receive behavior of the SSC to
a variety of serial interfaces. A specific shift clock edge (rising or falling) is used to shift
out transmit data, while the other shift clock edge is used to latch in receive data. Bit
CON.PH selects the leading edge or the trailing edge for each function. Bit CON.PO
selects the level of the shift clock line in the idle state. Thus, for an idle-high clock, the
leading edge is a falling one, a 1-to-0 transition (see Figure 19-2).
CON.
PO
CON.
PH
0
0
0
1
1
0
1
1
Shift Clock
MS_CLK/SS_CLK
Pins
MTSR/MRST
First
Bit
Transmit Data
Last
Bit
Latch Data
Shift Data
Figure 19-2 Serial Clock Phase and Polarity Options
User’s Manual
SSC, V1.4
19-9
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
19.3.2
Full-Duplex Operation
The various devices are connected through three lines. The definition of these lines is
always determined by the master: the line connected to the master’s data output line
TXD is the transmit line; the receive line is connected to its data input line RXD; the shift
clock line is either MS_CLK or SS_CLK. Only the device selected for master operation
generates and outputs the shift clock on line MS_CLK. Since all slaves receive this clock,
their pin SCLK must be switched to input mode. The output of the master’s shift register
is connected to the external transmit line, which in turn is connected to the slaves’ shift
register input. The output of the slaves’ shift register is connected to the external receive
line in order to enable the master to receive the data shifted out of the slave. The external
connections are hard-wired, the function and direction of these pins is determined by the
master or slave operation of the individual device.
Note: The shift direction shown in the figure applies for MSB-first operation as well as for
LSB-first operation.
When initializing the devices in this configuration, one device must be selected for
master operation while all other devices must be programmed for slave operation.
Initialization includes the operating mode of the device’s SSC and also the function of
the respective port lines.
User’s Manual
SSC, V1.4
19-10
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
Master
Device #1
Device #2
Clock
Slave
Shift Register
Shift Register
MTSR
Transmit
MTSR
MRST
Receive
MRST
CLK
Clock
CLK
Clock
Device #3
Slave
Shift Register
MTSR
MRST
CLK
Clock
Figure 19-3 SSC Full-Duplex Configuration
The data output pins MRST of all slave devices are connected together onto the one
receive line in the configuration shown in Figure 19-3. During a transfer, each slave
shifts out data from its shift register. There are two ways to avoid collisions on the receive
line due to different slave data:
•
•
Only one slave drives the line, i.e. enables the driver of its MRST pin. All the other
slaves must have their MRST pins programmed as input so only one slave can put
its data onto the master's receive line. Only receiving data from the master is
possible. The master selects the slave device from which it expects data either by
separate select lines, or by sending a special command to this slave. The selected
slave then switches its MRST line to output until it gets a de-selection signal or
command. This option is applicable only if pin has output driver disabling capability.
The slaves use open drain output on MRST. This forms a wired-AND connection. The
receive line needs an external pull-up in this case. Corruption of the data on the
receive line sent by the selected slave is avoided when all slaves not selected for
transmission to the master only send ones (1s). Because this high level is not actively
driven onto the line, but only held through the pull-up device, the selected slave can
pull this line actively to a low-level when transmitting a zero bit. The master selects
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XC83x
High-Speed Synchronous Serial Interface
the slave device from which it expects data either by separate select lines or by
sending a special command to this slave.
After performing the necessary initialization of the SSC, the serial interfaces can be
enabled. For a master device, the alternate clock line will now go to its programmed
polarity. The alternate data line will go to either 0 or 1 until the first transfer starts. After
a transfer, the alternate data line will always remain at the logic level of the last
transmitted data bit.
When the serial interfaces are enabled, the master device can initiate the first data
transfer by writing the transmit data into register TB. This value is copied into the shift
register (assumed to be empty at this time), and the selected first bit of the transmit data
will be placed onto the TXD line on the next clock from the baud-rate generator
(transmission starts only if CON.EN = 1). Depending on the selected clock phase, a
clock pulse will also be generated on the MS_CLK line. At the same time, with the
opposite clock edge, the master latches and shifts in the data detected at its input line
RXD. This “exchanges” the transmit data with the receive data. Because the clock line
is connected to all slaves, their shift registers will be shifted synchronously with the
master’s shift register — shifting out the data contained in the registers, and shifting in
the data detected at the input line. After the preprogrammed number of clock pulses (via
the data width selection), the data transmitted by the master is contained in all the slaves’
shift registers, while the master’s shift register holds the data of the selected slave. In the
master and all slaves, the contents of the shift register are copied into the receive buffer
RB and the receive interrupt line RIR is activated.
A slave device will immediately output the selected first bit (MSB or LSB of the transfer
data) at line RXD when the contents of the transmit buffer are copied into the slave's shift
register. Bit CON.BSY is not set until the first clock edge at SS_CLK appears. The slave
device will not wait for the next clock from the baud-rate generator, as the master does.
The reason for this is that, depending on the selected clock phase, the first clock edge
generated by the master may already be used to clock in the first data bit. Thus, the
slave’s first data bit must already be valid at this time.
Note: On the SSC, a transmission and a reception takes place at the same time,
regardless of whether valid data has been transmitted or received.
Note: The initialization of the CLK pin on the master requires some attention in order to
avoid undesired clock transitions, which may disturb the other devices. Before the
clock pin is switched to output mode, the clock output level will be selected in the
control register CON and the alternate output be prepared via the related ALTSEL
register, or the output latch must be loaded with the clock idle level.
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SSC, V1.4
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V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
19.3.3
Half-Duplex Operation
In a Half-Duplex Mode, only one data line is necessary for both receiving and
transmitting of data. There are two port configuration options for Half-Duplex Mode. The
first option uses all the three pins but with the data exchange line connected to both the
MTSR and MRST pins of each device; the shift clock line is connected to the SCLK pin.
The second option uses two pins and requires the MTSR and MRST lines to be selected
for the same GPIO pin, thus establishing also only a single data exchange line. The shift
clock line is connected to the SCLK pin as before.
The master device controls the data transfer by generating the shift clock, while the slave
devices receive it. Due to the fact that all transmit and receive pins are connected to the
one data exchange line, serial data may be moved between arbitrary stations.
Similar to Full-Duplex Mode, there are two ways to avoid collisions on the data exchange
line:
•
•
Only the transmitting device may enable its transmit pin driver. This option is
applicable only if pin has output driver disabling capability.
The non-transmitting devices use open drain output and send only ones.
Because the data inputs and outputs are connected together, a transmitting device will
clock in its own data at the input pin (MRST for a master device, MTSR for a slave). By
this method, any corruptions on the common data exchange line are detected if the
received data is not equal to the transmitted data.
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SSC, V1.4
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High-Speed Synchronous Serial Interface
The Half-Duplex Mode port configuration using three pins is shown in Figure 19-4.
Master
Device #1
Shift Register
Clock
Transmit
Device #2
MTSR
MTSR
MRST
MRST
CLK
Clock
Slave
Shift Register
CLK
Common
Transmit/
Receive Device #3
Line
Clock
Slave
Shift Register
MTSR
MRST
CLK
Clock
Figure 19-4 SSC Half-Duplex Configuration
19.3.4
Continuous Transfers
When the transmit interrupt request flag is set, it indicates that the transmit buffer TB is
empty and ready to be loaded with the next transmit data. If TB has been reloaded by
the time the current transmission is finished, the data is immediately transferred to the
shift register and the next transmission will start without any additional delay. On the data
line, there is no gap between the two successive frames. For example, two byte transfers
would look the same as one word transfer. This feature can be used to interface with
devices that can operate with or require more than 8 data bits per transfer. It is just a
matter of software, how long a total data frame length can be. This option can also be
used to interface to byte-wide and word-wide devices on the same serial bus, for
instance.
Note: Of course, this can happen only in multiples of the selected basic data width,
because it would require disabling/enabling of the SSC to reprogram the basic
data width on-the-fly.
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SSC, V1.4
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XC83x
High-Speed Synchronous Serial Interface
19.3.5
Baud Rate Generation
The serial channel SSC has its own dedicated 16-bit baud-rate generator with 16-bit
reload capability, allowing baud rate generation independent of the timers. Figure 19-5
shows the baud-rate generator.
16-Bit Reload Register
fPCLK
.. 2
16-Bit Counter
f MS_CLK/SS_CLK
fMS_CLK max in Master Mode< fPCLK /2
fSS_CLK max in Slave Mode < fPCLK /4
Figure 19-5 SSC Baud-rate Generator
The baud-rate generator is clocked with the module clock fhw_clk. The timer counts
downwards. Register BR is the dual-function Baud-rate Generator/Reload register.
Reading BR, while the SSC is enabled, returns the contents of the timer. Reading BR,
while the SSC is disabled, returns the programmed reload value. In this mode, the
desired reload value can be written to BR.
Note: Never write to BR while the SSC is enabled.
The formulas below calculate either the resulting baud rate for a given reload value, or
the required reload value for a given baud rate:
Baud rate =
fhw_clk
2 * (<BR> + 1)
BR =
fhw_clk
2 * Baud rate
-1
(19.1)
<BR> represents the contents of the reload register, taken as an unsigned 16-bit integer,
while baud rate is equal to fMS_CLK/SS_CLK as shown in Figure 19-5.
The maximum baud rate that can be achieved when using a module clock of 24 MHz is
12 MBaud in Master Mode (with <BR> = 0000H) or 6 MBaud in Slave Mode (with
<BR> = 0001H).
Table 19-3 lists some possible baud rates together with the required reload values and
the resulting bit times, assuming a module clock of 24 MHz.
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XC83x
High-Speed Synchronous Serial Interface
Typical Baud Rates of the SSC (fhw_clk = 24 MHz)
Table 19-3
Reload Value
Baud Rate (= fMS_CLK/SS_CLK)
Deviation
0000H
12 MBaud (only in Master Mode)
0.0%
0001H
6 MBaud
0.0%
0005H
2 MBaud
0.0%
000BH
1 MBaud
0.0%
0017H
500 kBaud
0.0%
0077H
100 kBaud
0.0%
FFFFH
183.11 Baud
0.0%
19.3.6
Error Detection Mechanisms
The SSC is able to detect four different error conditions. Receive Error and Phase Error
are detected in all modes; Transmit Error and Baud Rate Error apply only to Slave Mode.
When an error is detected, the respective error flag is/can be set and an error interrupt
request will be generated by activating the EIR line (see Figure 19-6) if enabled. The
error interrupt handler may then check the error flags to determine the cause of the error
interrupt. The error flags are not reset automatically but rather must be cleared by
software after servicing. This allows servicing of some error conditions via interrupt,
while the others may be polled by software.
Note: The error interrupt handler must clear the associated (enabled) error flag(s) to
prevent repeated interrupt requests.
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XC83x
High-Speed Synchronous Serial Interface
Bits in Register
CON
TEN
&
Transmit
TE
Error
REN
&
RE
Receive
>1
Error
Error Interrupt
EIR
PEN
Phase
Error
PE
BEN
Baud rate
Error
&
&
BE
Figure 19-6 SSC Error Interrupt Control
A Receive Error (Master or Slave Mode) is detected when a new data frame is
completely received but the previous data was not read out of the receive buffer register
RB. This condition sets the error flag CON.RE and the error interrupt request line EIR,
when enabled via CON.REN. The old data in the receive buffer RB will be overwritten
with the new value and is irretrievably lost.
A Phase Error (Master or Slave Mode) is detected when the incoming data at pin MRST
(Master Mode) or MTSR (Slave Mode), sampled with the same frequency as the module
clock, changes between one cycle before and two cycles after the latching edge of the
shift clock signal SCLK. This condition sets the error flag CON.PE and, when enabled
via CON.PEN, the error interrupt request line EIR.
Note: When receiving and transmitting data in parallel, phase errors occur if the baud
rate is configured to fhw_clk / 2.
A Baud Rate Error (Slave Mode) is detected when the incoming clock signal deviates
from the programmed baud rate by more than 100%, i.e. it is either more than double or
less than half the expected baud rate. This condition sets the error flag CON.BE and,
when enabled via CON.BEN, the error interrupt request line EIR. Using this error
detection capability requires that the slave’s baud-rate generator is programmed to the
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V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
same baud rate as the master device. This feature detects false additional, or missing
pulses on the clock line (within a certain frame).
Note: If this error condition occurs and bit CON.AREN = 1, an automatic reset of the
SSC will be performed in case of this error. This is done to re-initialize the SSC if
too few or too many clock pulses have been detected.
Note: This error can occur after any transfer if the communication is stopped. This is the
case due to the fact that the SSC module supports back-to-back transfers for
multiple transfers. In order to handle this, the baud rate detector expects after a
finished transfer immediately a next clock cycle for a new transfer.
A Transmit Error (Slave Mode) is detected when a transfer was initiated by the master
(SS_CLK gets active) but the transmit buffer TB of the slave was not updated since the
last transfer. This condition sets the error flag CON.TE and the error interrupt request
line EIR, when enabled via CON.TEN. If a transfer starts while the transmit buffer is not
updated, the slave will shift out the ‘old’ contents of the shift register, which normally is
the data received during the last transfer. This may lead to corruption of the data on the
transmit/receive line in half-duplex mode (open drain configuration) if this slave is not
selected for transmission. This mode requires that slaves not selected for transmission
only shift out ones; that is, their transmit buffers must be loaded with ‘FFFFH’ prior to any
transfer.
Note: In order to avoid possible conflicts or misinterpretations, it is recommended to
always load the slave's transmit buffer prior to any transfer.
The cause of an error interrupt request (receive, phase, baud rate, transmit error) can be
identified by the error status flags in control register CON.
Note: In contrast to the error interrupt request line EIR, the error status flags CON.TE,
CON.RE, CON.PE, and CON.BE, are not reset automatically upon entry into the
error interrupt service routine, but must be cleared by software.
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SSC, V1.4
19-18
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
19.4
Interrupts
The three SSC interrupts can be separately enabled or disabled by setting or clearing
their corresponding enable bits in SFR SCU_MODIEN.
For a detailed description of the various interrupts see Section 19.3. An overview is
given in Table 19-4.
Table 19-4
Interrupt
SSC Interrupt Sources
Signal
Description
Transmission TIR
starts
Indicates that the transmit buffer can be reloaded with new
data.
Transmission RIR
ends
The configured number of bits have been transmitted and
shifted to the receive buffer.
Receive
Error
EIR
This interrupt occurs if a new data frame is completely
received and the last data in the receive buffer was not
read.
Phase Error
EIR
This interrupt is generated if the incoming data changes
between one cycle before and two cycles after the latching
edge of the shift clock signal SCLK.
Baud Rate
Error (Slave
Mode only)
EIR
This interrupt is generated when the incoming clock signal
deviates from the programmed baud rate by more than
100%.
Transmit
Error (Slave
Mode only)
EIR
This interrupt is generated when TB was not updated since
the last transfer if a transfer is initiated by a master.
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V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
19.5
Register Description
The SSC Special Function Registers are accessed from the standard (non-mapped)
SFR area. The addresses of the SFRs are listed in Table 19-5..
Table 19-5
Register Map
Address
Register
AAH
CONL
ABH
CONH
ACH
TBL
ADH
RBL
AEH
BRL
AFH
BRH
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V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
19.5.1
Configuration Register
The operating mode of the serial channel SSC is controlled by the control register CON.
This register contains control bits for mode and error check selection, and status flags
for error identification. Depending on bit EN, either control functions or status flags and
master/slave control are enabled.
CON.EN = 0: Programming Mode
SSC_CONL
Control Register Low [Programming Mode]
(AAH)
RMAP: 0, PAGE: X
Reset Value: 00H
7
6
5
4
3
LB
PO
PH
HB
BM
rw
rw
rw
rw
rw
Field
Bit
Type Description
BM
[3:0]
rw
2
1
0
Data Width Selection
0000B Reserved. Do not use this combination.
0001B 0111B Transfer Data Width is 2 … 8 bits (<BM>+1).
Note: The most significant bit of BM field is always
fixed at 0. Thus the transfer and receive data
width is restricted at maximum 8 bits. Transfer
Data Width is 2...8 bits (<BM>+1).
HB
4
rw
Heading Control
0B
Transmit/Receive LSB First.
Transmit/Receive MSB First.
1B
PH
5
rw
Clock Phase Control
Shift transmit data on the leading clock edge,
0B
latch on trailing edge.
1B
Latch receive data on leading clock edge, shift
on trailing edge.
PO
6
rw
Clock Polarity Control
Idle clock line is low, leading clock edge is low0B
to-high transition.
1B
Idle clock line is high, leading clock edge is highto-low transition.
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XC83x
High-Speed Synchronous Serial Interface
Field
Bit
Type Description
LB
7
rw
Loop Back Control
0B
Normal output.
Receive input is connected with transmit output
1B
(half-duplex mode).
SSC_CONH
Control Register High [Programming Mode]
(ABH)
RMAP: 0, PAGE: X
Reset Value: 00H
7
6
5
4
3
2
1
0
EN
MS
0
AREN
BEN
PEN
REN
TEN
rw
rw
r
rw
rw
rw
rw
rw
Field
Bit
Type Description
TEN
0
rw
Transmit Error Enable
Ignore transmit errors.
0B
Check transmit errors.
1B
REN
1
rw
Receive Error Enable
0B
Ignore receive errors.
1B
Check receive errors.
PEN
2
rw
Phase Error Enable
0B
Ignore phase errors.
Check phase errors.
1B
BEN
3
rw
Baud Rate Error Enable
Ignore baud rate errors.
0B
1B
Check baud rate errors.
AREN
4
rw
Automatic Reset Enable
0B
No additional action upon a baud rate error.
1B
The SSC is automatically reset upon a baud rate
error.
MS
6
rw
Master Select
Slave Mode. Operate on shift clock received via
0B
SCLK.
1B
Master Mode. Generate shift clock and output it
via SCLK.
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V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
Field
Bit
Type Description
EN
7
rw
Enable Bit = 0
Transmission and reception disabled. Access to
control bits.
0
5
r
Reserved
Returns 0 if read; should be written with 0.
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SSC, V1.4
19-23
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
CON.EN = 1: Operating Mode
SSC_CONL
Control Register Low [Operating Mode]
(AAH)
RMAP: 0, PAGE: X
7
6
5
4
Reset Value: 00H
3
2
1
0
BC
r
rh
Field
Bit
Type Description
BC
[3:0]
rh
0
Bit Count Field
Shift counter is updated with every shift bit.
Note: This bit field is not to be written to.
0
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
SSC_CONH
Control Register High [Operating Mode]
(ABH)
RMAP: 0, PAGE: X
Reset Value: 00H
7
6
5
4
3
2
1
0
EN
MS
0
BSY
BE
PE
RE
TE
rw
rw
r
rh
rwh
rwh
rwh
rwh
Field
Bit
Type Description
TE
0
rwh
Transmit Error Flag
No error.
0B
1B
Transfer starts with the slave’s transmit buffer
not being updated.
RE
1
rwh
Receive Error Flag
0B
No error.
Reception completed before the receive buffer
1B
was read.
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XC83x
High-Speed Synchronous Serial Interface
Field
Bit
Type Description
PE
2
rwh
Phase Error Flag
No error.
0B
Received data changes around sampling clock
1B
edge.
BE
3
rwh
Baud Rate Error Flag
0B
No error.
1B
More than factor 2 or 0.5 between slave’s actual
and expected baud rate.
BSY
4
rh
Busy Flag
Set while a transfer is in progress.
Note: This bit is not to be written to.
MS
6
rw
Master Select Bit
Slave Mode. Operate on shift clock received via
0B
SCLK.
Master Mode. Generate shift clock and output it
1B
via SCLK.
EN
7
rw
Enable Bit = 1
Transmission and reception enabled. Access to status
flags and M/S control.
0
5
r
Reserved
Returns 0 if read; should be written with 0.
Note: The target of an access to CON (control bits or flags) is determined by the state of
CON.EN prior to the access; that is, writing C057H to CON in programming mode
(CON.EN = 0) will initialize the SSC (CON.EN was 0) and then turn it on
(CON.EN = 1). When writing to CON, ensure that reserved locations receive
zeros.
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19-25
V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
19.5.2
Baud Rate Timer Reload Register
The SSC baud rate timer reload register BR contains the 16-bit reload value for the baud
rate timer.
SSC_BRL
Baud Rate Timer Reload Register Low (AEH)
RMAP: 0, PAGE: X
7
6
5
4
Reset Value: 00H
3
2
1
0
BR_VALUE
rw
Field
Bit
Type Description
BR_VALUE
[7:0]
rw
Baud Rate Timer/Reload Register Value
Reading BR returns the 16-bit contents of the
baud rate timer. Writing BR loads the baud rate
timer reload register with BR_VALUE.
SSC_BRH
Baud Rate Timer Reload Register High (AFH)
RMAP: 0, PAGE: X
7
6
5
4
Reset Value: 00H
3
2
1
0
BR_VALUE
rw
Field
Bit
Type Description
BR_VALUE
[7:0]
rw
19.5.3
Baud Rate Timer/Reload Register Value
Reading BR returns the 16-bit contents of the
baud rate timer. Writing BR loads the baud rate
timer reload register with BR_VALUE.
Transmitter Buffer Register
The SSC transmitter buffer register TB contains the transmit data value.
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V1.1, 2010-09
XC83x
High-Speed Synchronous Serial Interface
SSC_TBL
Transmitter Buffer Register Low
RMAP: 0, PAGE: X
7
6
5
(ACH)
4
Reset Value: 00H
3
2
1
0
TB_VALUE
rw
Field
Bit
Type Description
TB_VALUE
[7:0]
rw
19.5.4
Transmit Data Register Value
TB_VALUE is the data value to be transmitted.
Unselected bits of TB are ignored during
transmission.
Receiver Buffer Register
The SSC receiver buffer register RB contains the receive data value.
SSC_RBL
Receiver Buffer Register Low
RMAP: 0, PAGE: X
7
6
5
(ADH)
4
Reset Value: 00H
3
2
1
0
RB_VALUE
rh
Field
Bit
Type Description
RB_VALUE
[7:0]
rh
User’s Manual
SSC, V1.4
Receive Data Register Value
RB contains the received data value RB_VALUE.
Unselected bits of RB will be not valid and should
be ignored.
19-27
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20
LED and Touch-Sense Controller
This chapter describes the LEDTSCU.
20.1
Overview
The LED and Touch-sense control unit (LEDTSCU) provides for up to eight line pins and
up to eight column pins, time-multiplexed control for LED driving and touchpad sensing
on single pin.
LEDTSCU provides optimized HW control for column enabling and function selection.
Software handling is required for line enabling per column time slice.
Features
For the LED driving function, LEDTSCU provides features:
•
•
•
•
•
•
Selection of up to 8 LED columns; Up to 7 LED columns in case touch-sense function
is enabled also
Time slice and active duration within time slice configurable for LED column
Possibility to drive up to 8 LEDs per time slice (column), common-cathode or
common-anode
Shadow transfer of line pattern for LED column time slice
Interrupt for each time slice
Line and column pins controlled by SFR setting
For the touchpad sensing function, LEDTSCU provides features:
•
•
•
•
•
•
•
Up to 8 touchpad input turns
Input pad turn controllable by software or fully by hardware round-robin
Pad oscillation control circuit with flexible configuration, such as oscillation frequency
and duration control
8-bit counter: For counting oscillations at pin.
Share configuration of time slice duration with LED function, with configurable active
duration within time slice
Interrupt for each time slice, time frame
Pin overrule control for active touch-sense function
Note: This chapter in several instances refer to the LED or touch-sense pins, e.g. ‘pin
COL[x]’, ‘pin TSIN[x]’. In all instances, it refers to the user-configured pin(s) where
the alternate function (bit-field ALTSEL) selects the LED/touch-sense function.
Refer to Section 20.7 for more elaboration.
User’s Manual
LEDTSCU, V 1.2.2
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V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.2
System Information
This section provides system information relevant to the LEDTSCU.
20.2.1
Pinning
Table 20-1 describes how to enable/select the particular LED or touch-sense pin
function for XC83x.
Table 20-1
XC83x Pin Functions and Selection
Pin
Function
Desciption
Selected By
P0.0
TSIN0/LINE0
Touch-sense input 0/
LED line 0
P0_ALTSEL0.P0 = 1B
P0_ALTSEL1.P0 = 0B
P0.1
TSIN1/LINE1
Touch-sense input 1/
LED line 1
P0_ALTSEL0.P1 = 1B
P0_ALTSEL1.P1 = 0B
P0.2
TSIN2/LINE2
Touch-sense input 2/
LED line 2
P0_ALTSEL0.P2 = 1B
P0_ALTSEL1.P2 = 0B
P0.3
TSIN3/LINE3
Touch-sense input 3/
LED line 3
P0_ALTSEL0.P3 = 1B
P0_ALTSEL1.P3 = 0B
P0.4
TSIN4/LINE4
Touch-sense input 4/
LED line 4
P0_ALTSEL0.P4 = 1B
P0_ALTSEL1.P4 = 0B
P0_ALTSEL2.P4 = 0B
P0.5
TSIN5/LINE5
Touch-sense input 5/
LED line 5
P0_ALTSEL0.P5 = 1B
P0_ALTSEL1.P5 = 0B
P0_ALTSEL2.P5 = 0B
P0.6
TSIN6/LINE6
Touch-sense input 6/
LED line 6
P0_ALTSEL0.P6 = 1B
P0_ALTSEL1.P6 = 0B
P0_ALTSEL2.P6 = 0B
P0.7
TSIN7/LINE7
Touch-sense input 7/
LED line 7
P0_ALTSEL0.P7 = 1B
P0_ALTSEL1.P7 = 0B
P0_ALTSEL2.P7 = 0B
P1.0
COL0_0
LED column 0
P1_ALTSEL0.P0 = 1B
P1_ALTSEL1.P0 = 0B
P0.4
COL0_1
LED column 0
P0_ALTSEL0.P4 = 1B
P0_ALTSEL1.P4 = 0B
P0_ALTSEL2.P4 = 1B
P1.1
COL1_0
LED column 1
P1_ALTSEL0.P1 = 1B
P1_ALTSEL1.P1 = 0B
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LEDTSCU, V 1.2.2
20-2
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
Table 20-1
XC83x Pin Functions and Selection
Pin
Function
Desciption
Selected By
P0.5
COL1_1
LED column 1
P0_ALTSEL0.P5 = 1B
P0_ALTSEL1.P5 = 0B
P0_ALTSEL2.P5 = 1B
P1.2
COL2_0
LED column 2
P1_ALTSEL0.P2 = 1B
P1_ALTSEL1.P2 = 0B
P0.6
COL2_1
LED column 2
P0_ALTSEL0.P6 = 1B
P0_ALTSEL1.P6 = 0B
P0_ALTSEL2.P6 = 1B
P1.3
COL3_0
LED column 3
P1_ALTSEL0.P3 = 1B
P1_ALTSEL1.P3 = 0B
P0.7
COL3_1
LED column 3
P0_ALTSEL0.P7 = 1B
P0_ALTSEL1.P7 = 0B
P0_ALTSEL2.P7 = 1B
P0.4
COL3_2
LED column 3
P0_ALTSEL0.P4 = 0B
P0_ALTSEL1.P4 = 1B
P0_ALTSEL2.P4 = 1B
P1.4
COL4
LED column 4
P1_ALTSEL0.P4 = 1B
P1_ALTSEL1.P4 = 0B
P1.5
COL5
LED column 5
P1_ALTSEL0.P5 = 1B
P1_ALTSEL1.P5 = 0B
P3.0
COL6
LED column 6
P3_ALTSEL0.P0 = 1B
P3_ALTSEL1.P0 = 0B
P3.1
COLA_0
Touch-sense external pull-up /
LED column A
P3_ALTSEL0.P1 = 1B
P3_ALTSEL1.P1 = 0B
P1.5
COLA_1
Touch-sense external pull-up /
LED column A
P1_ALTSEL0.P5 = 1B
P1_ALTSEL1.P5 = 1B
P0.6
COLA_2
Touch-sense external pull-up /
LED column A
P0_ALTSEL0.P6 = 0B
P0_ALTSEL1.P6 = 1B
P0_ALTSEL2.P6 = 1B
P0.7
COLA_3
Touch-sense external pull-up /
LED column A
P0_ALTSEL0.P7 = 0B
P0_ALTSEL1.P7 = 1B
P0_ALTSEL2.P7 = 1B
P0.4
COLA_4
Touch-sense external pull-up /
LED column A
P0_ALTSEL0.P4 = 1B
P0_ALTSEL1.P4 = 1B
P0_ALTSEL2.P4 = 1B
User’s Manual
LEDTSCU, V 1.2.2
20-3
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.2.2
Clocking Configuration
There are two constant clocks provided to the LED&TSCU kernel: FPCLK (48 MHz) and
SPCLK (8 MHz). The kernel is mainly running on FPCLK (48 MHz). The LEDTS-counter
can be configured to run on pre-scaled clock generated from FPCLK or SPCLK. The
touch-sense counter and corresponding logic is counting and processing pad
oscillations on FPCLK.
If the LEDTSCU functionality is not required at all, it can be completely disabled by gating
off its clock input for maximal power reduction. This is done by setting bit LTS_DIS in
register PMCON1 as described below.
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
PMCON1 register.
PMCON1
Peripheral Management Control Register 1(EFH)
RMAP: 0, PAGE: 1
7
6
5
IIC_DIS
LTS_DIS
rw
rw
4
CDC_DIS MDU_DIS
rw
3
2
1
0
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
rw
rw
rw
rw
rw
Field
Bits
Type Description
LTS_DIS
6
rw
20.2.3
Reset Value: FFH
LEDTSCU Disable Request. Active high.
0
LEDTSCU is in normal operation.
1
Request to disable the LEDTSCU. (default)
Interrupt Events and Assignment
Table 20-2 lists the interrupt event sources from the LEDTSCU, and the corresponding
event interrupt enable bit and flag bit.
Table 20-2
LEDTSCU Interrupt Events
Event
Event Interrupt Enable Bit
Event Flag Bit
Start of Time Slice
GLOBCTL1.ITS_EN
GLOBCTL1.TSF
Start of Time Frame
GLOBCTL1.ITF_EN
GLOBCTL1.TFF
Table 20-3 shows the interrupt node assignment for each LEDTSCU interrupt source.
User’s Manual
LEDTSCU, V 1.2.2
20-4
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
Table 20-3
LEDTSCU Events’ Interrupt Node Control
Event
Interrupt Node
Enable Bit
Interrupt Node Flag Vector
Bit
Address
Start of Time Slice
IEN1.ECCIP3
–
6BH
Start of Time Frame
IEN1.ECCIP1
–
5BH
20.2.4
IP Interconnection
The LEDTSCU has interconnection to other peripherals enabling higher level of
automation without requiring software.
Table 20-4
LEDTSCU Interconnections
LEDTSCU Function/Signal
Connected Other Module Function/Signal
Compare match (o): LEDTS_CM
ADC external trigger (i): REQTR0G, REQTR1G
Time slice interrupt (o): LEDTS_TSI
ADC external trigger (i): REQTR0H, REQTR1H
20.2.5
Debug Suspend Control
The LEDTSCU timers/counters, LEDTS-counter and TS-counter, can be enabled
(together) for suspend operation when debug Monitor Mode becomes active. The debug
suspend control is configurable using register MODSUSP. Chapter 10.2.4 contain the
detailed description of the this register.
By debug suspend, these counters stop counting (retains the last value) during the
duration of the device in Monitor Mode.
20.3
Time-Multiplexed LED & Touch-Sense Functions On Pin
A single pin supports LED & touch-sense functions in time-multiplexed mode. The
hardware provides the enabling for LED mode or touch-sense mode for respective
function control.
In each time frame, there are maximum eight time slices configurable – up to one for
touch-sense function, up to eight for LED function. Provided touch-sense function is
enabled, the last time slice is reserved for touch-sense function where the pad oscillator
circuit will be enabled for pin with active pad turn. Provided LED function is enabled, the
rest of the time slices within the time frame are used for LED function by enabling each
LED column one at a time.
As only one time slice per time frame is used for touch-sense function, depending on the
number of touchpad sense inputs (pad turns) configured, by default the hardware
automatically enables each pad oscillator (pad_turn_x) and sense the respective pins in
round-robin fashion. Otherwise it is possible to enable for software control where the
User’s Manual
LEDTSCU, V 1.2.2
20-5
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
active pad turn is fully under user control. If touch-sense function is disabled, no pad turn
is active in the last time slice of time frame.
A time frame comprises of several time slices whose duration and number is
configurable. When touch-sense function is enabled for automatic hardware pad turn
control, several time frames make up one time period where all pad_turns are
completed. The time slice duration is configured centrally for the LED and/or touchsense functions, using the LEDTS-counter. Refer to the description in Section 20.4,
Section 20.8 and Figure 20-2.
If enabled, a time slice interrupt is triggered on overflow of LEDTS-counter 8LSB for each
new time slice started. A time frame interrupt may also be enabled, which is triggered on
overflow of the whole LEDTS-counter.
To allow flexible duration of activation of LED columns and/or touch-sense oscillation
counting, the duty cycle of column enable and pad oscillation enable can be adjusted for
each time slice.
Figure 20-1 shows an example for a LED matrix configuration with touch pads. The
configuration in this example is 8 X 4 LED matrix with 4 touch pad turns (here: 6 touch
pads) enabled in sequence by hardware. Here, four time frames complete a time period.
In the time slice interrupt, software can:
•
•
set up line value for next time slice
set up compare value for next time slice
Refer to Section 20.7 for Interpretation of Bit Field FNCOL to determine the currently
active time slice.
A time frame interrupt indicates one touch input line has been sensed, application-level
software can, for example:
•
•
start touch-sense analysis routines and update status
enable LED display update
User’s Manual
LEDTSCU, V 1.2.2
20-6
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
One complete period
Frame 0
Frame 1
Frame 2
Frame 3
5.3*5 us 2.01*5 ms
C3
C 2 C1
C0
TS
C3
C2
C1 C 0
TS
C3 C2
C1
C 0 TS
C3
C 2 C1
C0
TS
LTS_fn
COLA
COLLEV = 0
pad _turn_0
pad _turn_1
pad _turn_2
pad _turn_3
COL3
COL2
COL1
COL0
LED function
LED first column active SW: With time- slice interrupt, write
next column line pattern and
compare value to shadow registers.
SW: Analyze & actions on pad
oscillat ion count
HW: On compare match, LED
column is de-activated.
HW: On counter 8LSB overflow,
shadow transfer line pattern&
compare value for next column.
LED function
LED last column active SW: With time-slice interrupt, write
touch-sense compare value to
shadow register.
HW: On compare match, LED
column is de-activated.
HW: On counter 8LSB overflow,
shadow transfer (line pattern &)
compare value for touch-sense
function.
Touch-sense function
Pad oscillator active on pad with
active turn SW: With time-slice interrupt , write
LED 1st column line pattern and
compare value to shadow registers.
HW: LED columns at inactive level.
HW: On compare match, enable
pad oscillation . Oscillations are
counted.
HW: On counter 8LSB overflow,
shadow transfer line pattern&
compare value for 1st column.
Disable pad oscillation & update bit
PADT for next pad turn.
...
Figure 20-1 Time-Multiplexed LEDTSCU Functions on Pin (Example)
User’s Manual
LEDTSCU, V 1.2.2
20-7
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.4
LED Driving
The control provided for LED driving is mainly for LED column selection – where one
column is enabled at a time. It is required for interrupt-based software handling to control
LED enabling per selected column. Up to eight LED columns are supported, and up to
eight LEDs can be enabled per column.
With direct LED drive, it is supported for adjust of luminence for different types of LEDs
with different forward voltages. A compare register for LEDTS-counter is provided so that
the duty cycle for column enabling per time slice can be adjusted. The LED column is
enabled from the beginning of the time slice until compare match event. For 100% duty
cycle for LED column enable in time slice, the compare value should be set to FFH. If the
compare value is set to 00H, the LED column will stay at passive level during the time
slice. Update of the compare register for each time slice is by shadow transfer which
takes place automatically at the beginning of each time slice.
A shadow transfer mechanism for update of LED enabling (LED line pattern) per column
(time slice) is also provided. This shadow transfer takes place automatically at the
beginning of each new time slice.
When the LEDTS-counter is first started (enable input clock by CLK_PS), a shadow
transfer of line pattern and compare value is activated for the first column.
A time slice interrupt can be enabled, which occurs on overflow of the 8LSB of LEDTScounter which indicates the start of a new time slice.
Figure 20-2 shows the LED function control circuit, which also provides the pad
oscillator enable control. The clock source for the control circuit is selectable from the
constant FPCLK of 48 MHz or SPCLK of 8 MHz. A 6-bit divider provides pre-scale
possibilities to flexibly configure the internal LEDTS-counter count rate, which overflows
in one time frame. In the duration of one time frame comprising of configurable number
of time slices, the configured number of LED columns are activated in sequence. In the
last time slice of the time frame, touch-sense function is activated if enabled. The time
frame is divided into equal time slices of duration ranging from 5.3 us to 2.01 ms
configurable.
The LEDTS-counter is started when bit CLK_PS is set to any other value from 0 and at
least one of the LED function or the touch-sense function is/are enabled. It does not run
when both functions are disabled. To avoid over-write of function enable which disturbs
the hardware control during LEDTS-counter running, the TS_EN and LD_EN bits can
only be modified when bit CLK_PS = 0. It is nonetheless possible to set the bits TS_EN
and LD_EN in one single write to SFR GLOBCTL0 when setting CLK_PS from 0 to 1, or
from 1 to 0.
When started, the counter starts running from a reset/reload value based on enabled
function(s): 1) the number of columns (bit-field NR_LEDCOL) when LED function is
enabled, 2) add one time slice at end of time frame when touch-sense function is
enabled. The counter always counts up and overflows from 7FFH to the reload value
User’s Manual
LEDTSCU, V 1.2.2
20-8
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
which is equal to the reset value. Within each time frame, the sequence of LED column
enabling always start from the most-significant enabled column (column with higher
numbering). Example in case of four LED columns enabled, in ordered sequence:
•
•
•
•
Start with COL3,
followed by COL2,
followed by COL1,
then COL0.
If the touch-sense function is not enabled, COLA is always available for LED function as
the last LED column time slice of a time frame. Example in case of four LED columns
enabled, in ordered sequence:
•
•
•
•
Start with COL2,
followed by COL1,
followed by COL0,
then COLA.
FPCLK
(48 MHz)
No. time s lice per time frame =
No. LE D Column & & LD_E N + 1 Touc h-s ens e & & TS _E N
NR_LE DCOL : LE DTS counter reset/reload v alue (in cas e of TS _E N = 0)
Prescaler
6-bit
LEDTS Counter
CLK_PS
0: No clock
1: /1
n: /n
...
63: /63
000 B : 700 H 010 B: 500 H 100 B: 300 H 110 B: 100 H
001 B : 600 H 011 B: 400 H 101 B: 200 H 111 B: 000 H
8-bit compare
reg.
On c ompare
matc h
&
111 B
demux
110 B
101 B
100 B
011 B
010 B
001 B
000 B
On 8-bit
overflow
Enable pad oscillator *
&
^
&
^
&
^
&
^
&
^
&
^
&
^
&
^
COLA *
COL0
OR
SPCLK
(8MHz)
COL1
COL2
COL3
COL4
COL5
COL6
COLLEV = 1
Shadow transfer 8-bit compare
value & LED line pattern
Time-slice
Interrupt
C6
C5
C4
C3
C2
C1
C0
CA/
TS*
* If touch-sense function is enabled , this time
slice is reserved for pad osc . enabling and
LED column control is not available .
For touch-sense function , pin COLA may be
configured to enable external pull -up – not
shown here .
Time-frame
Interrupt
Figure 20-2 LED Function Control Circuit (also provides pad oscillator enable)
In Section 20.8, the time slice duration and formulations for LEDTSCU related timings
are provided.
User’s Manual
LEDTSCU, V 1.2.2
20-9
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.4.1
LED Pin Assignment and Current Capability
One LED column pin is enabled at a time within each configured time slice duration to
control up to eight LEDs. The assignment of COL[x] to pins is configurable to suit various
use cases. High-current pins with increased current capability are defined – refer to
product data-sheet for the current capability of assigned pin/s. For example, some pins
can sink 40 mA nominal. This means per LED drive capability is limited to 5 mA when
direct drive eight LEDs by column assigned on high-current pin.
In all usage, the total current to direct drive (source or sink) all eight LEDs at one time
must not exceed the specified maximum current for all pins (ΣIM). For stronger LED drive
capability, use of external transistors will be required.
User’s Manual
LEDTSCU, V 1.2.2
20-10
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.5
Touchpad Sensing
Figure 20-3 shows the pin oscillation control unit, which is actually integrated with the
standard GPIO pad. An active pad turn (pad_turn_x) is defined for the touch-sense input
pin TSIN[x] as the duration within the touch-sense time slice where the TS-counter is
counting.
COLA
enable external pull-up
enable pad oscillator
&
pad_turn_num
pad_turn_x
counter reset
TSIN[x]
8-bit TS-counter
activeextend
Sensor Pad
“ts_extended”
standard IO pad
Figure 20-3 Touch-Sense Oscillator Control Circuit
The 8-bit TS-counter counts the number of oscillations. It can only be written when there
is no active pad turn. The counter may be enabled for automatic reset (to 00H) on each
start of a new pad turn. Bit TSCTROVF indicates that the counter has overflowed.
Alternatively, it can be configured such that the TS-counter stops counting in current time
slice when the count value saturates, i.e. does not overflow & stops at FFH. In this case,
the TS-counter starts running again only on a new pad turn.
A configurable pin-low-level active extension is provided for adjustment of oscillation per
user system. The extension is active during the discharge phase of oscillation, and is
configurable to extend by one or four FPCLK. Figure 20-4 illustrates this function.
The pad configuration of the active touch-sense pin TSIN[x] is over-ruled by hardware in
the active duration to enable oscillations, reference Section 20.9. In particular, the weak
internal pull-up can be optionally disabled (GPIO pin SFR setting for pull applies instead)
such as when the user system utilize external resistor for pull-up instead. In the whole
duration of the touch-sense time slice, COLA is activated high. This activates a pull-up
via an external resistor connected to pin COLA. This configuration provides some
flexibility to adjust the pad oscillation rate for adaptation to user system.
The touch-sense function is time-multiplexed with the LED function on enabled
LINE[x]/TSIN[x] pins. During the touch-sense time slice for the other TSIN pins which are
not on active pad turn, the corresponding LINE output remains active. Software should
take care to set the line bits to 1 to avoid current sink from pin COLA.
User’s Manual
LEDTSCU, V 1.2.2
20-11
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
The touch-sense function is active in the last time slice of a time frame. Refer to
Section 20.3, and Section 20.4 for more details on time slice allocation and
configuration.
TS-counter input
Input high
threshold
“ts_extended”
Input high
threshold
pin oscillation
Input high
threshold
Input low
threshold
Figure 20-4 Pin-Low-Level Extension Function
The pad oscillation is enabled on pad with valid turn for configurable duration. A compare
value provides to adjust the duty cycle within the time slice when the pad oscillation is
enabled (TS-counter is counting). The pad oscillation is enabled only on compare match
till the end of the time slice. For 100% duty cycle pad oscillation enable in time slice, the
compare value shall be set to 00H. Setting the compare value to FFH results in no pad
oscillation in time slice.
The time slice interrupt and/or time frame interrupt may be enabled as required for touchsense control.
User’s Manual
LEDTSCU, V 1.2.2
20-12
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.5.1
Finger Sensing
When a finger is placed on the sensor pad, it increases the pad capacitance and
frequency of oscillation on pad is reduced. The pad oscillation frequency without finger
is typically expected in the approximate range 0.25 MHz to 0.5 MHz. With finger on the
sensor, the pad oscillation frequency is typically expected in the approximate range
0.125 MHz to 0.25 MHz. As described in above section, some flexibility is provided to
adjust the oscillation in the user system: 1) Configurable pin low-level active extension,
2) Alternative enabling of external pull-up with resistance selectable by user. With a time
slice duration configurable ranging from 5.3 us (0.18 MHz) to 2.01 ms (496 Hz), the
software can configure the duration of the pad turn (adjustable within time slice using
compare function) and set a count threshold for oscillations to detect if finger control is
available.
User’s Manual
LEDTSCU, V 1.2.2
20-13
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.6
Time-Multiplexed LED and Touch-Sense Function on Pin
Some hints are provided regarding the time-multiplexed usage of a pin for LED and
touch-sense function:
•
•
•
•
•
The maximum number of LED columns = 7 when touch-sense function is also
enabled.
If enabled by pin, COLA outputs HIGH to enable external R (resistor) as pull-up for
touch-sense function.
During touch-sense time slice, recommend to set LED lines to output HIGH.
During LED time slice, COLA outputs LOW and will sink current if connected lines
output HIGH.
The effective capacitance for each TSIN line depends largely on what is connected
to the line and the application board layout. All touch-pads for the application should
be calibrated for robust touch-detection.
User’s Manual
LEDTSCU, V 1.2.2
20-14
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.7
Function Enabling and Control Hints
It is recommended to set up all configuration for the LEDTSCU in all SFRs before write
LTS_GLOBCTL0 SFR to enable and start LED and/or touch-sense function(s).
Note: SFR bits especially affecting the LEDTS-counter configuration for LED/touchsense function can only be written when the counter is not running i.e.
CLK_PS = 0. Refer to SFR bit description Section 20.11.
Enable LED Function Only
To enable LED function only: set LD_EN, clear TS_EN.
Initialization after reset:
MOV LTS_GLOBCTL0, #0b10XXXXXX
;set LD_EN and start LEDTS-counter on prescaled clock
;(CLK_PS != 0)
Re-configuration during run-time:
MOV LTS_GLOBCTL0, #0x00;stop LEDTS-counter by clearing prescaler
MOV LTS_GLOBCTL0, #0b10XXXXXX
Enable Touch-Sense Function Only
To enable touch-sense function only: clear LD_EN, set TS_EN.
Initialization after reset:
MOV LTS_GLOBCTL0, #0b01XXXXXX
;set TS_EN and start LEDTS-counter on prescaled clock
;(CLK_PS != 0)
Re-configuration during run-time:
MOV LTS_GLOBCTL0, #0x00;stop LEDTS-counter by clearing prescaler
MOV LTS_GLOBCTL0, #0b01XXXXXX
Enable Both LED and Touch-Sense Function
To enable both functions: set LD_EN, set TS_EN.
Initialization after reset:
MOV LTS_GLOBCTL0, #0b11XXXXXX
;set TS_EN and start LEDTS-counter on prescaled clock
;(CLK_PS != 0)
Re-configuration during run-time:
MOV LTS_GLOBCTL0, #0x00;stop LEDTS-counter by clearing prescaler
MOV LTS_GLOBCTL0, #0b11XXXXXX
User’s Manual
LEDTSCU, V 1.2.2
20-15
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
Interpretation of Bit Field FNCOL
The handling by software in each time slice includes to update the line value and
compare value to be activated (shadow-transferred) in the next time slice. The FNCOL
bit field provides information on the function/column active in the previous time slice.
With this information, software can determine the active function/column in current time
slice and prepare the necessary values (to be shadow-transferred) valid for the next time
slice.
Following is an example where six time slices are enabled (per time frame), with five LED
columns and touch-sensing enabled:
Table 20-5
Interpretation of FNCOL Bit Field
FNCOL
Active Function / Column in SW Prepare via Shadow Registers for
Current Time Slice
Function / Column of Next Time Slice
111B
LED COL[4]
LED COL[3]
010B
LED COL[3]
LED COL[2]
011B
LED COL[2]
LED COL[1]
100B
LED COL[1]
LED COL[0]
101B
LED COL[0]
Touch-sense TSIN[PADT]
110B
Touch-sense TSIN[PADT]
LED COL[4]
20.8
LEDTSCU Timing Calculations
LEDTSCU main timing or duration formulation are provided in following.
Count-Rate (CR):
(20.1)
CR = ( fCLK ) ÷ ( PREscaler )
Time slice duration (TSD):
(20.2)
TSD =
28
÷ ( CR )
Time frame duration:
(20.3)
TimeFrameDuration = ( Number of time slice ) × TSD
User’s Manual
LEDTSCU, V 1.2.2
20-16
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
LED drive active duration:
(20.4)
LED Drive Active Duration = TSD × Compare_VALUE ÷
28
Touch-sense drive active duration:
(20.5)
Touch-sense Drive Active Duration = TSD × ( 2 8 – Compare_VALUE ) ÷ 2 8
User’s Manual
LEDTSCU, V 1.2.2
20-17
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.9
LEDTSCU Pin Control
The user may flexibly assign pins as provided by GPIO-SFR ALTSEL, for the LEDTSCU
functions:
•
•
COL[x] (for LED column control)
LINE[x]/TSIN[x] (for LED line control or touch-sensing)
Refer also to Section 20.4 for more considerations with regards to which COL[x] and/or
LINE[x]/TSIN[x] will be active based on user configuration.
User code must configure the ALTSEL-assigned LED pin GPIO-SFR setting for the LED
function. For the touch-sense function, it is also required to configure the ALTSEL to
select the TSIN (and COLA) function even as LEDTSCU provides some pin over-rule
controls to the assigned touch-sense pin with active pad turn, see Table 20-6 and
Figure 20-5.
Table 20-6
LEDTSCU Pin Control Signals
Function
LD/TS_e LTS_fn
n
Pin
Control of Assigned Pin
LED
column
LD_EN
=1
0 = LED
Enable COL[x];
Passive level on
COL[the rest].
If TS_EN = 1,
COLA = 0.
GPIO SFR setting
LED line
LD_EN
=1
0 = LED
LINE[x] = shadowtransferred from
LDLINE
GPIO SFR setting
Touchsense
TS_EN
=1
1=
Touchsense
Enable TSIN[x] for
oscillation.
All other TSIN pins
output LINE value.
1)
Hardware over-rule on
pad_turn_x1) for active
duration:
- Enable pull-up (this overrule can be disabled by bit
Passive level on
EPULL)
COL[the rest] except - Enable open-drain
COLA = 1.
For the other pad inputs not on turn, there is no HW over-rule which means the GPIO SFR setting is active.
User’s Manual
LEDTSCU, V 1.2.2
20-18
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
Touch-sense enable over -rule && pad _turn_x
Touch-sense disable pull over -rule
Touch-sense pull -up only
Definition :
1
0
P UDE N&S E L
P ull Control
GP IO func tion
by S FR control
Touch-sense open -drain enable
1
OD
Open Drain
Control
LE DTS output signal
0
lts_fn && pad _ turn_x
ts_ extended [x]
ld_ line [x]
ALTS E Lx
A lternate S elect
x
1
0
Pull
Device
AltDataOut[LED &TS]
AltDataOut[N]
Output
Driver
M
U
X
Data OUT
Pin
LED line /
Touch-sense pad x
Input
Driver
Schmitt
Trigger
Pad
Figure 20-5 Over-rule Control on Pad-Input Pin for Touch-Sense Function
20.10
Interrupt
There are two interrupts triggered by LEDTSCU kernel: 1) time slice event, 2) time frame
event. The flags are set on event or when CLK_PS is set from 0 regardless of whether
the corresponding interrupt is enabled or not. When enabled, the event (including setting
of CLK_PS from 0) activates the corresponding interrupt request from the kernel.
User’s Manual
LEDTSCU, V 1.2.2
20-19
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.11
Registers Description
The LEDTSCU Special Function Registers are accessed from the standard (nonmapped) SFR area. Table 20-7 lists the SFRs and corresponding address.
Table 20-7
Register Map
Address
Register
97H
LTS_GLOBCTL0
D4H
LTS_COMPARE
D5H
LTS_LDLINE
D6H
LTS_LDTSCTL
D7H
LTS_TSCTL
D8H
LTS_GLOBCTL1
D9H
LTS_TSVAL
User’s Manual
LEDTSCU, V 1.2.2
20-20
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.11.1
Global Control and Status
There are three registers for global control and status.
LTS_GLOBCTL0
Global Control Register 0
RMAP: 0, PAGE: X
5
(97H)
4
Reset Value: 00H
7
6
3
2
LD_EN
TS_EN
CLK_PS
rw
rw
rw
1
0
Field
Bits
Type Description
CLK_PS
[5:0]
rw
LEDTS-Counter Clock Pre-Scale Factor
The input clock FPCLK or SPCLK is prescaled
according to setting.
0D
No clock
1D
Divide by 1
Divide by n
nD
63D Divide by 63
This bit can only be set to any other value (from 0)
provided at least one of touch-sense or LED function
is enabled. The LEDTS-counter starts running on the
input clock from reset/reload value based on enabled
function(s) (and NR_LEDCOL). Refer Section 20.4
for details.
When this bit is clear to 0 from other value, the
LEDTS-counter stops running and resets.
TS_EN1)
6
rw
Touch-Sense Function Enable
Set to enable the kernel for touch-sense function
control when CLK_PS is set from 0.
LD_EN
7
rw
LED Function Enable
Set to enable the kernel for LED function control
when CLK_PS is set from 0.
1)
This bit can only be modified when bit CLK_PS = 0.
User’s Manual
LEDTSCU, V 1.2.2
20-21
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
LTS_GLOBCTL1
Global Control Register 1
RMAP: 0, PAGE: X
(D8H)
Reset Value: 00H
7
6
5
4
3
2
1
TSF
ITS_EN
TFF
ITF_EN
CLKSEL
FNCOL
rwh
rw
rwh
rw
rw
rh
0
Field
Bits
Type Description
FNCOL
[2:0]
rh
Previous Active Function/LED Column Status
Shows the active function / LED column in the
previous time slice. Updated on start of new timeslice when LEDTS-counter 8LSB over-flows.
Controlled by latched value of the internal DE-MUX,
see Figure 20-2.
CLKSEL1)
3
rw
LEDTS-Counter Clock Input Select
48 MHz is selected
0B
1B
8 MHz is selected
ITF_EN
4
rw
Enable Time-Frame Interrupt
0B
Disabled
Enabled
1B
TFF
5
rwh
Time-Frame Interrupt Flag
Set on activation of each new time-frame, including
when bit CLK_PS is set from 0. To be cleared by
software.
ITS_EN
6
rw
Enable Time Slice Interrupt
0B
Disabled
Enabled
1B
TSF
7
rwh
Time Slice Interrupt Flag
Set on activation of each new time slice, including
when bit CLK_PS is set from 0. To be cleared by
software.
1)
This bit can only be modified when bit CLK_PS = 0.
User’s Manual
LEDTSCU, V 1.2.2
20-22
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
LTS_COMPARE
Time Slice Compare Shadow Register(D4H)
RMAP: 0, PAGE: X
7
6
5
4
Reset Value: 00H
3
2
1
0
SHD_CMP
rw
Field
Bits
Type Description
SHD_CMP
[7:0]
rw
User’s Manual
LEDTSCU, V 1.2.2
Compare Value for Time Slice to ShadowTransfer
This value is shadow-transferred to the time slice
compare register on start of each new time slice.
A shadow transfer is effected on CLK_PS set from 0.
20-23
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
20.11.2
Function Control Registers
These registers provide controls for the LED drive and touch-sense functions.
LTS_LDTSCTL
LED and Touch-Sense Control Register(D6H)
RMAP: 0, PAGE: X
7
6
5
4
Reset Value: 00H
3
2
1
0
NR_LEDCOL
COLLEV
NR_PADT
TSOEXT
rw
rw
rw
rw
Field
Bits
Type Description
TSOEXT
0
rw
Extension for Touch-Sense Output for Pin-LowLevel
0B
Extend by 1 FPCLK
Extend by 4 FPCLK
1B
NR_PADT1)
[3:1]
rw
Number of Touch-Sense Pad Turns
Defines the number of touch-sense inputs, which is
equal to number of pad turns. Used for the hardware
control of pad turn enabling.
1
0D
nD
n+1
COLLEV
4
rw
Active Level of LED Column
0B
Active low
Active high
1B
User’s Manual
LEDTSCU, V 1.2.2
20-24
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
Field
Bits
Type Description
NR_LEDCOL
[7:5]
rw
Number of LED Columns
Defines the number of LED columns.
000B 1 LED column
001B 2 LED columns
010B 3 LED columns
011B 4 LED columns
100B 5 LED columns
101B 6 LED columns
110B 7 LED columns
111B 8 LED columns (max. LED columns = 7 if bit
TS_EN = 1)
Note: LED column is enabled in sequence starting
from highest column number. If touch-sense
function is not enabled, COLA is activated in
last time slice.
1)
This bit can only be modified when bit CLK_PS = 0.
LTS_LDLINE
LED Line Pattern Shadow Register
RMAP: 0, PAGE: X
7
6
5
(D5H)
4
Reset Value: 00H
3
2
1
0
SHD_LINE
rw
Field
Bits
Type Description
SHD_LINE
[7:0]
rw
User’s Manual
LEDTSCU, V 1.2.2
LED Line Value to Shadow-Transfer
This value is shadow-transferred to the LED lines on
start of each new time slice.
A shadow transfer is effected on CLK_PS set from 0.
20-25
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
LTS_TSCTL
Touch-Sense Control Register
RMAP: 0, PAGE: X
7
6
TSCTROV
TSCTRR
F
rwh
rw
(D7H)
Reset Value: 00H
5
4
3
TSCTRSA
T
2
1
EPULL
PADTSW
PADT
rw
rw
rw
rwh
0
Field
Bits
Type Description
PADT
[2:0]
rwh
Touch-Sense Pad Turn (Input Pin)
This is the next or currently active pad turn (touchsense input pin). When PADTSW = 0, the value is
updated by hardware at the end of touch-sense time
slice. Software write is always possible.
TSIN0
0D
nD
TSIN[n]
PADTSW1)
3
rw
Software Control for Touch-Sense Pad Turn
0B
The hardware automatically enables the
touch-sense inputs round-robin, starting from
TSIN0.
Disable hardware control for software control
1B
only. The active touch-sense input is
configured in bit PADT.
EPULL
4
rw
Enable External Pull-up Configuration on Pin
COLA
When set, the internal pull-up over-rule on active
touch-sense input pin is disabled.
HW over-rule to enable internal pull-up is
0B
active on TSIN[x] for set duration in touchsense time slice. With this setting, it is not
specified to assign the COLA to any pin.
Enable external pull-up: Output 1on pin COLA
1B
for whole duration of touch-sense time slice.
Note: Independent of this setting, COLA always
outputs 1 for whole duration of touch-sense
time slice.
User’s Manual
LEDTSCU, V 1.2.2
20-26
V1.1, 2010-09
XC83x
LED and Touch-Sense Controller
Field
Bits
Type Description
TSCTRSAT
5
rw
Saturation of TS-Counter
0B
Disable
Enable. TS-counter stops counting in the
1B
current time slice when it reaches FFH.
Counter starts to count again on new pad turn,
triggered on compare match.
TSCTRR
6
rw
TS-Counter Auto Reset
Disable TS-counter automatic reset
0B
Enable TS-counter automatic reset to 00H on
1B
new pad turn. Triggered on compare match in
time slice.
TSCTROVF
7
rwh
TS-Counter Overflow Indication
This bit indicates whether a TS-counter overflow has
occurred. This bit is cleared on new pad turn,
triggered on compare match.
No overflow has occurred.
0B
1B
The TS-counter has overflowed at least once.
1)
This bit can only be modified when bit CLK_PS = 0.
LTS_TSVAL
Touch-Sense Counter Value
RMAP: 0, PAGE: X
7
6
5
(D9H)
4
Reset Value: 00H
3
2
1
0
TSCTRVAL
rwh
Field
Bits
Type Description
TSCTRVAL
[7:0]
rwh
User’s Manual
LEDTSCU, V 1.2.2
TS-Counter Value
This shows the actual TS-counter value. It can only
be written when no pad turn is active.
This counter may be enabled for automatic reset on
the start of a new pad turn.
20-27
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21
Capture/Compare Unit 6 (CCU6)
The CCU6 is a high-resolution 16-bit capture and compare unit with application specific
modes, mainly for AC drive control. Special operating modes support the control of
Brushless DC-motors using Hall sensors or Back-EMF detection. Furthermore, block
commutation and control mechanisms for multi-phase machines are supported.
It also supports inputs to start several timers synchronously, an important feature in
devices with several CCU6 modules.
This chapter is structured as follows:
•
•
•
•
•
•
•
•
•
•
Introduction (see Section 21.1)
including the register overview (see Section 21.1.3)
System information (see Section 21.2)
Operating T12 (see Section 21.3)
including T12 related registers (see Section 21.3.8)
and capture/compare control registers (see Section 21.3.9)
Operating T13 (see Section 21.4)
including T13 related registers (see Section 21.4.6)
Trap handling (see Section 21.5)
Multi-Channel mode (see Section 21.6)
Hall sensor mode (see Section 21.7)
Modulation control registers (see Section 21.8)
Interrupt handling (see Section 21.9)
including interrupt registers (see Section 21.9.2)
General module operation (see Section 21.10)
including general registers (see Section 21.10.2)
21.1
Introduction
The CCU6 unit is made up of a Timer T12 Block with three capture/compare channels
and a Timer T13 Block with one compare channel. The T12 channels can independently
generate PWM signals or accept capture triggers, or they can jointly generate control
signal patterns to drive AC-motors or inverters.
A rich set of status bits, synchronized updating of parameter values via shadow
registers, and flexible generation of interrupt request signals provide means for efficient
software-control.
Note: The capture/compare module itself is named CCU6 (capture/compare unit 6).
A capture/compare channel inside this module is named CC6x.
User’s Manual
CCU6, V4.0
21-1
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.1.1
Feature Set Overview
This section gives an overview over the different building blocks and their main features.
Timer 12 Block Features
•
•
•
•
•
•
•
•
•
•
•
Three capture/compare channels, each channel can be used either as capture or as
compare channel
Generation of a three-phase PWM supported (six outputs, individual signals for highside and low-side switches)
16-bit resolution, maximum count frequency = peripheral clock
Dead-time control for each channel to avoid short-circuits in the power stage
Concurrent update of T12 registers
Center-aligned and edge-aligned PWM can be generated
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Many interrupt request sources
Hysteresis-like control mode
Timer 13 Block Features
•
•
•
•
•
•
•
•
One independent compare channel with one output
16-bit resolution, maximum count frequency = peripheral clock
Concurrent update of T13 registers
Can be synchronized to T12
Interrupt generation at period-match and compare-match
Single-shot mode supported
Start can be controlled by external events
Capability of counting external events
Additional Specific Functions
•
•
•
•
•
•
•
•
Block commutation for Brushless DC-drives implemented
Position detection via Hall-sensor pattern
Noise filter supported for position input signals
Automatic rotational speed measurement and commutation control for block
commutation
Integrated error handling
Fast emergency stop without CPU load via external signal (CTRAP)
Control modes for multi-channel AC-drives
Output levels can be selected and adapted to the power stage
User’s Manual
CCU6, V4.0
21-2
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.1.2
Block Diagram
The Timer T12 can operate in capture and/or compare mode for its three channels. The
modes can also be combined (e.g. a channel operates in compare mode, whereas
another channel operates in capture mode). The Timer T13 can operate in compare
mode only. The multi-channel control unit generates output patterns which can be
modulated by T12 and/or T13. The modulation sources can be selected and combined
for the signal modulation.
CCU6 Module Kernel
Compare
1
SR[3:0]
3 +3
2
Trap In put
2
Ou tpu t Select
2
Compare
Trap
Control
Ha ll Inpu t
CC63
Multichannel
Control
Ou tpu t Select
1
Compare
CC62
DeadTime
Control
Compare
1
Start
fCC6
T13
Interrupt
Control
1
CC61
Capture
Clock
Control
CC60
Compare
T12
3
1
CTRAP[D:A]
CCPOS2[D:A]
CCPOS1[D:A]
CC62IN[D:A]
CCPOS0[D:A]
CC62
COUT62
CC61IN[D:A]
CC61
COUT61
CC60IN[D:A]
CC60
COUT60
COUT63
T13HR[H:A]
T12HR[H:A]
Input / Output Control
Port Control
CCU6_MCB05506+
Figure 21-1 CCU6 Block Diagram
User’s Manual
CCU6, V4.0
21-3
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.1.3
Register Overview
For the generation of the overall register table, the prefix “CCU6x_” has to be added to
the register names in this table to identify the registers of different CCU6 modules that
are implemented. In this naming convention, x indicates the module number.
Table 21-1 shows all registers required for programming of a CCU6 module. It
summarizes the CCU6 kernel registers and defines the offset and the reset values.
8-bit short addresses are not available for this module.
T12 related
Registers
Cap/Com
Control Registers
Interrupt Status /
Control Registers
General
Registers
T12L
CMPSTATL
IS L
PISEL0L
T12H
CMPSTATH
IS H
PISEL0H
T12PRL
CMPMODIFL
ISS L
PISEL2
T12PRH
CMPMODIFH
ISS H
T12DTCL
T12MSELL
ISRL
T12DTCH
T12MSELH
ISRH
CC60RL
TCTR0L
INPL
CC60RH
TCTR0H
INPH
CC60SRL
TCTR2L
IENL
CC60SRH
TCTR2H
IENH
CC61RL
TCTR4L
CC61RH
TCTR4H
CC61SRL
CC61SRH
Modulation
Control Registers
CC62RL
MODCTRL
CC62RH
MODCTRH
CC62SRL
TRPCTRL
CC62SRH
TRPCTRH
T13 related
Registers
T13L
T13H
T13PRL
T13PRH
PSLR
MCMCTR
MCMOUTSL
MCMOUTSH
MCMOUTL
MCMOUTH
CC63RL
CC63RH
CC63SRL
CC63SRH
8-Bit_CCU6_regs
Figure 21-2 CCU6 Registers
User’s Manual
CCU6, V4.0
21-4
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Table 21-1
CCU6 Module Register Summary
Short Name Description
Offset Reset
Value
See
Page
9EH
00H
Page 21-127
General Registers
PISEL0L
Port Input Select Register Low
PISEL0H
Port Input Select Register High
9FH
00H
Page 21-128
PISEL2
Port Input Select Register 2
A4H
00H
Page 21-129
Timer T12 related Registers
T12L
Timer 12 Counter Register Low
FAH
00H
Page 21-43
T12H
Timer 12 Counter Register High
FBH
00H
Page 21-43
T12PRL
Timer 12 Period Register Low
9CH
00H
Page 21-44
T12PRH
Timer 12 Period Register High
9DH
00H
Page 21-44
T12DTCL
Dead-Time Control Register for Timer
T12 Low
A4H
00H
Page 21-49
T12DTCH
Dead-Time Control Register for Timer
T12 High
A5H
00H
Page 21-49
CC60RL
Capture/Compare Register Channel
CC60 Low
FAH
00H
Page 21-46
CC60RH
Capture/Compare Register Channel
CC60 High
FBH
00H
Page 21-46
CC61RL
Capture/Compare Register Channel
CC61 Low
FCH
00H
Page 21-46
CC61RH
Capture/Compare Register Channel
CC61 High
FDH
00H
Page 21-46
CC62RL
Capture/Compare Register Channel
CC62 Low
FEH
00H
Page 21-46
CC62RH
Capture/Compare Register Channel
CC62 High
FFH
00H
Page 21-46
CC60SRL
Capture/Compare Shadow Register
Channel CC60 Low
FAH
00H
Page 21-47
CC60SRH
Capture/Compare Shadow Register
Channel CC60 High
FBH
00H
Page 21-47
User’s Manual
CCU6, V4.0
21-5
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Table 21-1
CCU6 Module Register Summary (cont’d)
Short Name Description
Offset Reset
Value
See
Page
CC61SRL
Capture/Compare Shadow Register
Channel CC61 Low
FCH
00H
Page 21-47
CC61SRH
Capture/Compare Shadow Register
Channel CC61 High
FDH
00H
Page 21-47
CC62SRL
Capture/Compare Shadow Register
Channel CC62 Low
FEH
00H
Page 21-47
CC62SRH
Capture/Compare Shadow Register
Channel CC62 High
FFH
00H
Page 21-47
CMPSTATL Compare State Register Low
FEH
00H
Page 21-51
CMPSTATH Compare State Register High
FFH
00H
Page 21-52
CMPMODIF Compare State Modification Register
L
Low
A6H
00H
Page 21-53
CMPMODIF Compare State Modification Register
H
High
A7H
00H
Page 21-54
T12MSELL
T12 Capture/Compare Mode Select
Register Low
9AH
00H
Page 21-55
T12MSELH
T12 Capture/Compare Mode Select
Register High
9BH
00H
Page 21-55
TCTR0L
Timer Control Register 0 Low
A6H
00H
Page 21-57
TCTR0H
Timer Control Register 0 High
A7H
00H
Page 21-59
TCTR2L
Timer Control Register 2 Low
FAH
00H
Page 21-61
TCTR2H
Timer Control Register 2 High
FBH
00H
Page 21-63
TCTR4L
Timer Control Register 4 Low
9CH
00H
Page 21-64
TCTR4H
Timer Control Register 4 High
9DH
00H
Page 21-65
Capture/Compare Control Registers
Timer T13 related Registers
T13L
Timer 13 Counter Register Low
FCH
00H
Page 21-79
T13H
Timer 13 Counter Register High
FDH
00H
Page 21-79
T13PRL
Timer 13 Period Register Low
9EH
00H
Page 21-81
T13PRH
Timer 13 Period Register High
9FH
00H
Page 21-81
User’s Manual
CCU6, V4.0
21-6
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Table 21-1
CCU6 Module Register Summary (cont’d)
Short Name Description
Offset Reset
Value
See
Page
CC63RL
Compare Register for Timer 13 Low
9AH
00H
Page 21-83
CC63RH
Compare Register for Timer 13 High
9BH
00H
Page 21-83
CC63SRL
Compare Shadow Register for Timer 13 9AH
Low
00H
Page 21-84
CC63SRH
Compare Shadow Register for Timer 13 9BH
Low
00H
Page 21-84
FCH
00H
Page 21-98
Modulation Control Registers
MODCTRL
Modulation Control Register Low
MODCTRH
Modulation Control Register High
FDH
00H
Page 21-99
TRPCTRL
Trap Control Register Low
FEH
00H
Page 21-100
TRPCTRH
Trap Control Register High
FFH
00H
Page 21-101
PSLR
Passive State Level Register
A6H
00H
Page 21-103
MCMOUTS
L
Multi-Channel Mode Output Shadow
Register Low
9EH
00H
Page 21-106
MCMOUTS
H
Multi-Channel Mode Output Shadow
Register High
9FH
00H
Page 21-106
MCMOUTL
Multi-Channel Mode Output Register
Low
9AH
00H
Page 21-107
MCMOUTH
Multi-Channel Mode Output Register
High
9BH
00H
Page 21-109
MCMCTR
Multi-Channel Mode Control Register
A7H
00H
Page 21-104
Interrupt Status and Node Registers
ISL
Interrupt Status Register Low
9CH
00H
Page 21-112
ISH
Interrupt Status Register High
9DH
00H
Page 21-113
ISSL
Interrupt Status Set Register Low
A4H
00H
Page 21-116
ISSH
Interrupt Status Set Register High
A5H
00H
Page 21-116
ISRL
Interrupt Status Reset Register Low
A4H
00H
Page 21-118
ISRH
Interrupt Status Reset Register High
A5H
00H
Page 21-118
INPL
Interrupt Node Pointer Register Low
9EH
40H
Page 21-124
INPH
Interrupt Node Pointer Register High
9FH
39H
Page 21-125
User’s Manual
CCU6, V4.0
21-7
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Table 21-1
CCU6 Module Register Summary (cont’d)
Short Name Description
Offset Reset
Value
See
Page
IENL
Interrupt Node Pointer Register Low
9CH
0000H
Page 21-120
IENH
Interrupt Node Pointer Register High
9DH
0000H
Page 21-121
Note: In the case of a write access to addresses inside the address range (that is
covered by the same chip select signal), but that are not the addresses explicitly
mentioned for the module, the write access is not taken into account for the
module. The same principle is valid for read accesses. In case of a read access
to another address, the module does not react.
21.2
System Information
This section provides system information relevant to the CCU6.
21.2.1
Pinning
The CCU6 pin assignment for XC83x is shown in Table 21-2.
Table 21-2
Pin
CCU6 Pin Functions and Selection
Function
Desciption
Selected By
Capture Input Signals
P1.1
CC60_0
P0.3
CC60_1
P1.3
CC61_0
P0.1
CC61_1
P1.5
CC62_0
P0.2
CC62_1
Input signals for capture event CCU6_PISEL0L.ISCC60 = 00B
on channel CC60
CCU6_PISEL0L.ISCC60 = 01B
Input signals for capture event CCU6_PISEL0L.ISCC61 = 00B
on channel CC61
CCU6_PISEL0L.ISCC61 = 01B
Input signals for capture event CCU6_PISEL0L.ISCC62 = 00B
on channel CC62
CCU6_PISEL0L.ISCC62 = 01B
Trap Input Signals
Input signals for CTRAP
MODPISEL3.CTRAPIS = 00B
CCU6_PISEL0L.ISTRP = 00B
P0.3
CTRAP_0
P0.4
CTRAP_1
MODPISEL3.CTRAPIS = 01B
CCU6_PISEL0L.ISTRP = 00B
P2.3
CTRAP_2
MODPISEL3.CTRAPIS = 10B
CCU6_PISEL0L.ISTRP = 00B
Hall Input Signals
User’s Manual
CCU6, V4.0
21-8
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Table 21-2
CCU6 Pin Functions and Selection
Pin
Function
Desciption
Selected By
P0.0
CCPOS0_0 Input signals for CCPOS0
CCU6_PISEL0H.ISPOS0 = 00B
P2.0
CCPOS0_1
CCU6_PISEL0H.ISPOS0 = 01B
P2.3
CCPOS0_2
CCU6_PISEL0H.ISPOS0 = 10B
P0.1
CCPOS1_0 Input signals for CCPOS1
CCU6_PISEL0H.ISPOS1 = 00B
P2.1
CCPOS1_1
CCU6_PISEL0H.ISPOS1 = 01B
P0.2
CCPOS2_0 Input signals for CCPOS2
CCU6_PISEL0H.ISPOS2 = 00B
P2.2
CCPOS2_1
CCU6_PISEL0H.ISPOS2 = 01B
Timer Input Signals
P0.0
T12HR_0
Input signals for T12HR
P2.0
T12HR_2
MODPISEL3.IST12HR1 = 010B
CCU6_PISEL0H.IST12HR = 00B
P2.2
T12HR_3
MODPISEL3.IST12HR1 = 011B
CCU6_PISEL0H.IST12HR = 00B
P2.4
T12HR_5
MODPISEL3.IST12HR1 = 101B
CCU6_PISEL0H.IST12HR = 00B
P2.5
T12HR_7
MODPISEL3.IST12HR1 = 111B
CCU6_PISEL0H.IST12HR = 00B
P0.1
T13HR_0
P0.0
T13HR_1
MODPISEL3.IST13HR1 = 001B
CCU6_PISEL2.IST13HR = 00B
P2.0
T13HR_2
MODPISEL3.IST13HR1 = 010B
CCU6_PISEL2.IST13HR = 00B
P2.2
T13HR_3
MODPISEL3.IST13HR1 = 011B
CCU6_PISEL2.IST13HR = 00B
P2.4
T13HR_5
MODPISEL3.IST13HR1 = 101B
CCU6_PISEL2.IST13HR = 00B
P2.5
T13HR_7
MODPISEL3.IST13HR1 = 111B
CCU6_PISEL2.IST13HR = 00B
Input signals for T13HR
MODPISEL3.IST12HR1 = 000B
CCU6_PISEL0H.IST12HR = 00B
MODPISEL3.IST13HR1 = 000B
CCU6_PISEL2.IST13HR = 00B
Compare Output Signals
User’s Manual
CCU6, V4.0
21-9
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Table 21-2
CCU6 Pin Functions and Selection
Pin
Function
Desciption
Selected By
P1.1
CC60_0
Compare outputs for channel
CC60
P1_ALTSEL0.P1 = 0B
P1_ALTSEL1.P1 = 1B
P0.3
CC60_1
P0_ALTSEL0.P3 = 1B
P0_ALTSEL1.P3 = 1B
P1.0
COUT60_0
P1_ALTSEL0.P0 = 0B
P1_ALTSEL1.P0 = 1B
P1.3
CC61_0
P0.1
CC61_1
P0_ALTSEL0.P1 = 1B
P0_ALTSEL1.P1 = 1B
P1.2
COUT61_0
P1_ALTSEL0.P2 = 0B
P1_ALTSEL1.P2 = 1B
P0.0
COUT61_1
P0_ALTSEL0.P0 = 1B
P0_ALTSEL1.P0 = 1B
P1.5
CC62_0
P0.2
CC62_1
P0_ALTSEL0.P2 = 1B
P0_ALTSEL1.P2 = 1B
P1.4
COUT62_0
P1_ALTSEL0.P4 = 0B
P1_ALTSEL1.P4 = 1B
P0.5
COUT62_1
P0_ALTSEL0.P5 = 1B
P0_ALTSEL1.P5 = 1B
P0_ALTSEL2.P5 = 0B
P0.7
COUT63_0
P1.2
COUT63_1
P1_ALTSEL0.P2 = 1B
P1_ALTSEL1.P2 = 1B
P1.4
COUT63_2
P1_ALTSEL0.P4 = 1B
P1_ALTSEL1.P4 = 1B
User’s Manual
CCU6, V4.0
Compare outputs for channel
CC61
Compare outputs for channel
CC62
Compare outputs for channel
CC63
21-10
P1_ALTSEL0.P3 = 0B
P1_ALTSEL1.P3 = 1B
P1_ALTSEL0.P5 = 0B
P1_ALTSEL1.P5 = 1B
P0_ALTSEL0.P7 = 1B
P0_ALTSEL1.P7 = 1B
P0_ALTSEL2.P7 = 0B
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
MODPISEL3
Peripheral Input Select Register 3
RMAP: 0, PAGE: 3
7
6
5
(EEH)
4
Reset Value: 00H
3
2
1
0
IST13HR1
IST12HR1
CTRAPIS
rw
rw
rw
Field
Bits
Type Description
CTRAPIS
[1:0]
rw
CCU6 CTRAP Input Selection
00
CCU6 CTRAP Input Pin CTRAP_0 is
selected.
01
CCU6 CTRAP Input Pin CTRAP_1 is
selected.
10
CCU6 CTRAP Input Pin CTRAP_2 is
selected.
11
Out of Range Channel 3 event on Input Pin
CTRAP_3 is selected.
IST12HR1
[4:2]
rw
CCU6 T12HR Port Pin Input Select
000 T12HR Input Pin T12HR_0 is selected.
001 Out of Range Channel 0 event on Input
T12HR_1 is selected.
010 T12HR Input Pin T12HR_2 is selected.
011 T12HR Input Pin T12HR_3 is selected.
100 Out of Range Channel 2 event on Input
T12HR_4 is selected.
101 T12HR Input Pin T12HR_5 is selected.
110 Out of Range Channel 4 event on Input
T12HR_6 is selected.
111 T12HR Input Pin T12HR_7 is selected.
Note: To select the port pin to trigger T12HR,
CCU6_PISEL0H.IST12HR must be set to 00B.
User’s Manual
CCU6, V4.0
21-11
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
IST13HR1
[7:5]
rw
CCU6 T13HR Port Pin Input Select
000 T13HR Input Pin T13HR_0 is selected.
001 T13HR Input Pin T13HR_1 is selected.
010 T13HR Input Pin T13HR_2 is selected.
011 T13HR Input Pin T13HR_3 is selected.
100 Out of Range Channel 2 event on Input
T13HR_4 is selected.
101 T13HR Input Pin T13HR_5 is selected.
110 Out of Range Channel 4 event on Input
T13HR_6 is selected.
111 T13HR Input Pin T13HR_7 is selected.
Note: To select the port pin to trigger T13HR,
CCU6_PISEL2.IST13HR must be set to 00B.
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
MODPISEL3 register.
21.2.2
Clocking Configuration
The CCU6 kernel runs on the FPCLK at a fixed frequency of 48 MHz.
If the CCU6 functionality is not required at all, it can be completely disabled by gating off
its clock input for maximal power reduction. This is done by setting bit CCU_DIS in
register PMCON1 as described below.
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
PMCON1 register.
PMCON1
Peripheral Management Control Register 1(EFH)
RMAP: 0, PAGE: 1
7
6
5
IIC_DIS
LTS_DIS
rw
rw
4
CDC_DIS MDU_DIS
rw
3
2
1
0
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
rw
rw
rw
rw
rw
Field
Bits
Type Description
CCU_DIS
2
rw
User’s Manual
CCU6, V4.0
Reset Value: FFH
CCU6 Disable Request. Active high.
0
CCU6 is in normal operation.
1
Request to disable the CCU6. (default)
21-12
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.2.3
Interrupt Events and Assignment
Table 21-3 lists the interrupt event sources from the CCU6, and the corresponding event
interrupt enable bit and flag bit.
Table 21-3
CCU6 Interrupt Events
Event
Event Interrupt Enable Bit Event Flag Bit
Service
Request
Output
See
Section 21.9
See IENL, IENH
SR0, SR1,
SR2, SR3
See ISL, ISH
Table 21-4 shows the interrupt node assignment for each CCU6 interrupt source.
Table 21-4
CCU6 Events’ Interrupt Node Control
Event
Interrupt Node Enable Bit Interrupt Node Flag Vector
Bit
Address
SR0
IEN1.ECCIP0
IRCON2.CCU6SR0
53H
SR1
IEN1.ECCIP1
IRCON2.CCU6SR1
5BH
SR2
IEN1.ECCIP2
MODIEN.CCU6SR2EN
IRCON3.CCU6SR2
63H
SR3
IEN1.ECCIP3
MODIEN.CCU6SR3EN
IRCON3.CCU6SR3
6BH
Beside the event interrupt enable bit as shown in Table 21-3, bit MODIEN.CCU6SR2EN
and MODIEN.CCU6SR3EN must be set to 1B to enable the SR2 and SR3 interrupt
service request. The bit field PAGE of register SCU_PAGE must be programmed before
accessing the MODIEN register.
Note: SR2 and SR3 event of CCU6 module are used as interconnection output signals
to trigger CC6x inputs, T12HR input and T13HR input. If no interrupt service is
required during this type of trigger mode , control bits in register MODIEN can be
disabled. However, for SR2 and SR3 events to be used as interconnection output
signal, the event interrupt enable bit in register IENL and IENH must be enabled.
User’s Manual
CCU6, V4.0
21-13
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
MODIEN
Peripheral Interrupt Enable Register (F7H)
RMAP: 0, PAGE: 3
7
6
5
CCU6SR3 CCU6SR2
EN
EN
rw
r
rw
4
Reset Value: 07H
3
2
1
0
0
RIREN
TIREN
EIREN
r
rw
rw
rw
Field
Bits
Type Description
CCU6SR2EN
6
rw
CCU6 SR2 Enable
0
CCU6 SR2 interrupt service request is disabled
1
CCU6 SR2 interrupt service request is enabled
CCU6SR3EN
7
rw
CCU6 SR3 Enable
0
CCU6 SR3 interrupt service request is disabled
1
CCU6 SR3 interrupt service request is enabled
0
[5:3]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
CCU6, V4.0
21-14
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.2.4
IP Interconnection
The CCU6 has interconnection to other peripherals enabling higher level of automation
without requiring software.
Table 21-5
CCU6 Outputs Interconnection
CCU6 Function/Signal
Connected Other Module Function/Signal
Timer 12 output signals
T12 period match (o): T12PM
ADC Request Source 0/1 Trigger 2 Inputs (i):
REQTR0C, REQTR1C
Timer 13 output signals
T13 compare match (o): T13CM
ADC Request Source 0/1 Trigger 4 Inputs (i):
REQTR0E, REQTR1E
T13 period match (o): T13PM
ADC Request Source 0/1 Trigger 3 Inputs (i):
REQTR0D, REQTR1D
CCU6 service request output signals
Service request output SR2 (o):
CCU6_SR2
ADC Request Source 0/1 Trigger 0 Input (i):
REQTR0A, REQTR1A
Service request output SR3 (o):
CCU6_SR3
ADC Request Source 0/1 Trigger 1 Input (i):
REQTR0B, REQTR1B
Miscellaneous signals
MCM shadow transfer (o): MCM_ST ADC Request Source 0/1Trigger 5 Inputs (i):
REQTR0F, REQTR1F
Table 21-6
CCU6 Inputs Interconnection
CCU6
Function/Signal
Connected Other
Module Function/Signal
Selected By
CCU6 SR2 output (o):
CCU6_SR2
CCU6_PISEL0L.ISCC60 = 10B
Capture Inputs
CCU6 input (i): CC60
ADC boundary event 0 (o): CCU6_PISEL0L.ISCC60 = 11B
ADC_BF0
CCU6 input (i): CC61
CCU6 SR2 output (o):
CCU6_SR2
CCU6_PISEL0L.ISCC61 = 10B
ADC boundary event 1 (o): CCU6_PISEL0L.ISCC61 = 11B
ADC_BF1
User’s Manual
CCU6, V4.0
21-15
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Table 21-6
CCU6 Inputs Interconnection
CCU6
Function/Signal
Connected Other
Module Function/Signal
Selected By
CCU6 input (i): CC62
CCU6 SR2 output (o):
CCU6_SR2
CCU6_PISEL0L.ISCC62 = 10B
ADC boundary event 2 (o): CCU6_PISEL0L.ISCC62= 11B
ADC_BF2
CCU6 input (i): T12HR CCU6 SR2 output (o):
CCU6_SR2
CCU6_PISEL0H.IST12HR = 01B
CCU6 SR3 output (o):
CCU6_SR3
CCU6_PISEL0H.IST12HR = 10B
ADC Channel event (o):
ADC_CHEV
CCU6_PISEL0H.IST12HR = 11B
ORC event 0 (o):
ORCEVENT0
MODPISEL3.IST12HR1 = 001B
CCU6_PISEL0H.IST12HR = 00B
ORC event 2 (o):
ORCEVENT2
MODPISEL3.IST12HR1 = 100B
CCU6_PISEL0H.IST12HR = 00B
ORC event 4(o):
ORCEVENT4
MODPISEL3.IST12HR1 = 110B
CCU6_PISEL0H.IST12HR = 00B
CCU6 input (i): T13HR CCU6 SR2 output (o):
CCU6_SR2
CCU6_PISEL2.IST13HR = 01B
CCU6 SR3 output (o):
CCU6_SR3
CCU6_PISEL2.IST13HR = 10B
ADC Channel event (o):
ADC_CHEV
CCU6_PISEL2.IST13HR = 11B
ORC event 2 (o):
ORCEVENT2
MODPISEL3.IST13HR1 = 100B
CCU6_PISEL2.IST13HR = 00B
ORC event 4(o):
ORCEVENT4
MODPISEL3.IST13HR1 = 110B
CCU6_PISEL2.IST13HR = 00B
CCU6 input (i): CTRAP ORC event 3 (o):
ORCEVENT3
CCU6 input (i):
CCPOS0
User’s Manual
CCU6, V4.0
MODPISEL3.CTRAPIS = 11B
CCU6_PISEL0L.ISTRP = 00B/10B
P1 overcurrent event (o):
P1_OCD
CCU6_PISEL0L.ISTRP = 01B/10B
ADC Channel event 0 (o):
ADC_CHEV0
CCU6_PISEL0L.ISTRP = 11B
ADC boundary event 0 (o): CCU6_PISEL0H.ISPOS0 = 11B
ADC_BF0
21-16
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Table 21-6
CCU6 Inputs Interconnection
CCU6
Function/Signal
Connected Other
Module Function/Signal
CCU6 input (i):
CCPOS1
ADC boundary event 1 (o): CCU6_PISEL0H.ISPOS1 = 11B
ADC_BF1
CCU6 input (i):
CCPOS2
ADC boundary event 2 (o): CCU6_PISEL0H.ISPOS2 = 11B
ADC_BF2
21.2.5
Selected By
Module Suspend Control
When the On-Chip Debug Support (OCDS) is in Monitor Mode (MMCR2.MMODE = 1)
and the Debug-Suspend signal is active (MMCR2.DSUSP = 1), Timer T12 and Timer
T13 of CCU6 module in XC83x can be suspended based on the settings of their
corresponding module suspend bits in register MODSUSP. The definition of this register
is described in Chapter 10.2.4.
When suspended, only the timer stops counting as the counter input clock is gated off.
The module is still clocked so that module registers are accessible.
21.3
Operating Timer T12
The timer T12 block is the main unit to generate the 3-phase PWM signals. A 16-bit
counter is connected to 3 channel registers via comparators, that generate a signal when
the counter contents match one of the channel register contents. A variety of control
functions facilitate the adaptation of the T12 structure to different application needs.
Besides the 3-phase PWM generation, the T12 block offers options for individual
compare and capture functions, as well as dead-time control and hysteresis-like
compare mode.
This section provides information about:
•
•
•
•
•
•
•
•
T12 overview (see Section 21.3.1)
Counting scheme (see Section 21.3.2)
Compare modes (see Section 21.3.3)
Compare mode output path (see Section 21.3.4)
Capture modes (see Section 21.3.5)
Shadow transfer (see Section 21.3.6)
T12 operating mode selection (see Section 21.3.7)
T12 counter register description (see Section 21.3.8)
User’s Manual
CCU6, V4.0
21-17
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
State Bits
Timer T12
Logic
Capture/Compare
Channel CC60
CC60ST
Capture/Compare
Channel CC61
CC61ST
Capture/Compare
Channel CC62
CC62ST
To
Dead-Time
Control
and
Output
Modulation
Input and Control/Status Logic
T12HR
CC6xIN
CCPOSx
CCU6_MCA05507
Figure 21-3 Overview Diagram of the Timer T12 Block
User’s Manual
CCU6, V4.0
21-18
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.1
T12 Overview
Figure 21-4 shows a detailed block diagram of Timer T12. The functions of the timer T12
block are controlled by bits in registers TCTR0L, TCTR0H, TCTR2L, TCTR2H, TCTR4L,
TCTR4H, PISEL0L and PISEL0H.
Timer T12 receives its input clock (fT12) from the module clock fCC6 via a programmable
prescaler and an optional 1/256 divider or from an input signal T12HR. These options
are controlled via bit fields T12CLK and T12PRE (see Table 21-7). T12 can count up or
down, depending on the selected operation mode. A direction flag, CDIR, indicates the
current counting direction.
T 12R SEL
T 12R S
T12 R R
T 12R
C D IR
edge
detection
CTM
T 12ST R
T 12ST D
T 12H R
C lock
Selec tion
fCC 6
ST E12
edge
detection
n
T 12C LK
f T12
T12
C ontrol
& Status
C ounter R egister
T 12
256
T 12R ES
= 0000 H
T12 _Z M
= 0001 H
T 12PR E
R ead from
T 12PR
T 12SSC
T12 _OM
C om p.
=?
T12 _PM
Period R egis ter
T12 _ST
W rite to
T 12PR
Period Shadow
R egis ter
8-BIT_8BIT_CCU6_M CA05508
Figure 21-4 Timer T12 Logic and Period Comparators
Via a comparator, the T12 counter register T12L, T12H is connected to a Period Register
T12PRL, T12PRH. This register determines the maximum count value for T12.
In Edge-Aligned mode, T12 is cleared to 0000H after it has reached the period value
User’s Manual
CCU6, V4.0
21-19
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
defined by T12PR. In Center-Aligned mode, the count direction of T12 is set from ‘up’ to
‘down’ after it has reached the period value (please note that in this mode, T12 exceeds
the period value by one before counting down). In both cases, signal T12_PM (T12
Period Match) is generated. The Period Register receives a new period value from its
Shadow Period Register.
A read access to T12PR delivers the current period value at the comparator, whereas a
write access targets the Shadow Period Register to prepare another period value. The
transfer of a new period value from the Shadow Period Register into the Period Register
(see Section 21.3.6) is controlled via the ‘T12 Shadow Transfer’ control signal, T12_ST.
The generation of this signal depends on the operating mode and on the shadow transfer
enable bit STE12. Providing a shadow register for the period value as well as for other
values related to the generation of the PWM signal allows a concurrent update by
software for all relevant parameters.
Two further signals indicate whether the counter contents are equal to 0000H (T12_ZM
= zero match) or 0001H (T12_OM = one match). These signals control the counting and
switching behavior of T12.
The basic operating mode of T12, either Edge-Aligned mode (Figure 21-5) or CenterAligned mode (Figure 21-6), is selected via bit CTM. A Single-Shot control bit, T12SSC,
enables an automatic stop of the timer when the current counting period is finished (see
Figure 21-7 and Figure 21-8).
The start or stop of T12 is controlled by the Run bit T12R that can be modified by bits in
register TCTR4L, TCTR4H. The run bit can be set/cleared by software via the
associated set/clear bits T12RS or T12RR, it can be set by a selectable edge of the input
signal T12HR (TCTR2H.T12RSEL), or it is cleared by hardware according to
preselected conditions.
The timer T12 run bit T12R must not be set while the applied T12 period value is zero.
Timer T12 can be cleared via control bit T12RES. Setting this write-only bit does only
clear the timer contents, but has no further effects, for example, it does not stop the timer.
The generation of the T12 shadow transfer control signal, T12_ST, is enabled via bit
STE12. This bit can be set or reset by software indirectly through its associated set/clear
control bits T12STR and T12STD.
While Timer T12 is running, write accesses to the count register T12 are not taken into
account. If T12 is stopped and the Dead-Time counters are 0, write actions to register
T12 are immediately taken into account.
User’s Manual
CCU6, V4.0
21-20
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.2
T12 Counting Scheme
This section describes the clocking and counting capabilities of T12.
21.3.2.1 Clock Selection
The input clock fT12 of Timer T12 is derived from the internal module clock fCC6 through
a programmable prescaler and an optional 1/256 divider. The resulting prescaler factors
are listed in Table 21-7. The prescaler of T12 is cleared while T12 is not running
(TCTR0L.T12R = 0) to ensure reproducible timings and delays.
Table 21-7
Timer T12 Input Frequency Options
T12CLK
Resulting Input Clock fT12
Prescaler Off (T12PRE = 0)
Resulting Input Clock fT12
Prescaler On (T12PRE = 1)
000B
fCC6
fCC6 / 2
fCC6 / 4
fCC6 / 8
fCC6 / 16
fCC6 / 32
fCC6 / 64
fCC6 / 128
fCC6 / 256
fCC6 / 512
fCC6 / 1024
fCC6 / 2048
fCC6 / 4096
fCC6 / 8192
fCC6 / 16384
fCC6 / 32768
001B
010B
011B
100B
101B
110B
111B
21.3.2.2 Edge-Aligned / Center-Aligned Mode
In Edge-Aligned Mode (CTM = 0), timer T12 is always counting upwards (CDIR = 0).
When reaching the value given by the period register (period-match T12_PM), the value
of T12 is cleared with the next counting step (saw tooth shape).
User’s Manual
CCU6, V4.0
21-21
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
fT12
Period
Value
T12 Count
Period Zero
Match Match
Zero
Up
Up
Value n+1
Value n+2
CDIR
CC6x
Shadow Transfer
CCU6_MCT05509
Figure 21-5 T12 Operation in Edge-Aligned Mode
As a result, in Edge-Aligned mode, the timer period is given by:
T12PER = <Period-Value> + 1; in T12 clocks (fT12)
(21.1)
In Center-Aligned Mode (CTM = 1), timer T12 is counting upwards or downwards
(triangular shape). When reaching the value given by the period register (period-match
T12_PM) while counting upwards (CDIR = 0), the counting direction control bit CDIR is
changed to downwards (CDIR = 1) with the next counting step.
When reaching the value 0001H (one-match T12_OM) while counting downwards, the
counting direction control bit CDIR is changed to upwards with the next counting step.
As a result, in Center.Aligned mode, the timer period is given by:
T12PER = (<Period-Value> + 1) × 2; in T12 clocks (fT12)
•
•
•
(21.2)
With the next clock event of fT12 the count direction is set to counting up (CDIR = 0)
when the counter reaches 0001H while counting down.
With the next clock event of fT12 the count direction is set to counting down (CDIR = 1)
when the Period-Match is detected while counting up.
With the next clock event of fT12 the counter counts up while CDIR = 0 and it counts
down while CDIR = 1.
User’s Manual
CCU6, V4.0
21-22
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
fT12
<Period Value> + 1
Period
Value
Zero
Match
T12 Count
Period
Match
Period
Match
Zero
Down
Up
Up
Down
Value n
Value n+1
Value n+1
Value n+2
CDIR
CC6x
Shadow Transfer
Shadow Transfer
CCU6_MCT05510
Figure 21-6 T12 Operation in Center-Aligned Mode
Note: Bit CDIR changes with the next timer clock event after the one-match or the
period-match. Therefore, the timer continues counting in the previous direction for
one cycle before actually changing its direction (see Figure 21-6).
User’s Manual
CCU6, V4.0
21-23
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.2.3 Single-Shot Mode
In Single-Shot Mode, the timer run bit T12R is cleared by hardware. If bit T12SSC = 1,
the timer T12 will stop when the current timer period is finished.
In Edge-Aligned mode, T12R is cleared when the timer becomes zero after having
reached the period value (see Figure 21-7).
fT12
Period
Value
Compare
Value
T12 Count
0
T12R
CC6xST
T12SSC
CCU6_MCT05511
Figure 21-7 Single-Shot Operation in Edge-Aligned Mode
In Center-Aligned mode, the period is finished when the timer has counted down to zero
(one clock cycle after the one-match while counting down, see Figure 21-8).
fT12
Period
Value
Compare
Value
T12 Count
1
0
T12R
CC6xST
T12SSC
CCU6_MCT05512
Figure 21-8 Single-Shot Operation in Center-Aligned Mode
User’s Manual
CCU6, V4.0
21-24
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.3
T12 Compare Mode
Associated with Timer T12 are three individual capture/compare channels, that can
perform compare or capture operations with regard to the contents of the T12 counter.
The capture functions are explained in Section 21.3.5.
21.3.3.1 Compare Channels
In Compare Mode (see Figure 21-9), the three individual compare channels CC60
CC61, and CC62 can generate a three-phase PWM pattern.
Counter Register
T12
fT12
Compare
Match CM_60
Comp.
=?
Comp.
=?
Comp.
=?
Compare Register
CC60R
Compare Register
CC61R
Compare Register
CC62R
Compare
Match CM_61
Compare
Match CM_62
T12_ST
Compare Shadow
Register CC60SR
Compare Shadow
Register CC61SR
Compare Shadow
Register CC62SR
CCU6_MCA05513
Figure 21-9 T12 Channel Comparators
Each compare channel is connected to the T12 counter register via its individual equalto comparator, generating a match signal when the contents of the counter matches the
contents of the associated compare register. Each channel consists of the comparator
and a double register structure - the actual compare register CC6xR, feeding the
comparator, and an associated shadow register CC6xSR, that is preloaded by software
and transferred into the compare register when signal T12 shadow transfer, T12_ST,
gets active. Providing a shadow register for the compare value as well as for other values
related to the generation of the PWM signal facilitates a concurrent update by software
for all relevant parameters of a three-phase PWM.
User’s Manual
CCU6, V4.0
21-25
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.3.2 Channel State Bits
Associated with each (compare) channel is a State Bit, CMPSTATL.CC6xST, holding
the status of the compare (or capture) operation (see Figure 21-10). In compare mode,
the State Bits are modified according to a set of switching rules, depending on the current
status of timer T12.
CC60_R
CCPOS0
Compare
Channel
CC60
CM_60
To Interrupt
CC60_F Control
Switching
Rule
Logic
State Bit
CC60ST
MSEL60
To Dead_Time
Counter 0
MCC60S/R
CC61_R
CCPOS1
Compare
Channel
CC61
CM_61
To Interrupt
CC61_F Control
Switching
Rule
Logic
State Bit
CC61ST
MSEL61
To Dead_Time
Counter 1
MCC61S/R
CC62_R
CCPOS2
Compare
Channel
CC62
T12 Counter
CM_62
To Interrupt
CC62_F Control
Switching
Rule
Logic
State Bit
CC62ST
MSEL62
MCC62S/R
CDIR
T12R
To Dead_Time
Counter 2
T12_ZM
CCU6_MCB05514
Figure 21-10 Compare State Bits for Compare Mode
The inputs to the switching rule logic for the CC6xST bits are the timer direction (CDIR),
the timer run bit (T12R), the timer T12 zero-match signal (T12_ZM), and the actual
individual compare-match signals CM_6x as well as the mode control bits,
T12MSELL.MSEL6x.
User’s Manual
CCU6, V4.0
21-26
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
In addition, each state bit can be set or cleared by software via the appropriate set and
reset bits in register CMPMODIFL, CMPMODIFH, MCC6xS and MCC6xR. The input
signals CCPOSx are used in hysteresis-like compare mode, whereas in normal compare
mode, these inputs are ignored.
Note: In Hall Sensor, single shot or capture modes, additional/different rules are taken
into account (see related sections).
A compare interrupt event CC6x_R is signaled when a compare match is detected while
counting upwards, whereas the compare interrupt event CC6x_F is signaled when a
compare match is detected while counting down. The actual setting of a State Bit has no
influence on the interrupt generation in compare mode.
A modification of a State Bit CC6xST by the switching rule logic due to a compare action
is only possible while Timer T12 is running (T12R = 1). If this is the case, the following
switching rules apply for setting and clearing the State Bits in Compare Mode (illustrated
in Figure 21-11 and Figure 21-12):
A State Bit CC6xST is set to 1:
•
•
with the next T12 clock (fT12) after a compare-match when T12 is counting up
(i.e., when the counter is incremented above the compare value);
with the next T12 clock (fT12) after a zero-match AND a parallel compare-match when
T12 is counting up.
A State Bit CC6xST is cleared to 0:
•
•
with the next T12 clock (fT12) after a compare-match when T12 is counting down
(i.e., when the counter is decremented below the compare value in center-aligned
mode);
with the next T12 clock (fT12) after a zero-match AND NO parallel compare-match
when T12 is counting up.
fT12
Period
Value
Compare
Value
Zero
T12 Count
CC6xST
CCU6_MCT05515
Figure 21-11 Compare Operation, Edge-Aligned Mode
Figure 21-13 illustrates some more examples for compare waveforms. It is important to
note that in these examples, it is assumed that some of the compare values are changed
User’s Manual
CCU6, V4.0
21-27
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
while the timer is running. This change is performed via a software preload of the
Shadow Register, CC6xSR. The value is transferred to the actual Compare Register
CC6xR with the T12 Shadow Transfer signal, T12_ST, that is assumed to be enabled.
fT12
Compare-Match
Compare-Match
T12 Count
Period
Value
Compare
Value
Zero
CC6xST
CCU6_MCT05516
Figure 21-12 Compare Operation, Center-Aligned Mode
User’s Manual
CCU6, V4.0
21-28
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
fT12
Period
Value = 5
T12 Count
Zero
Down
Up
Down
Up
Value n
Value n+1
Value n+2
Value n+3
CC6x = 2
CC6x = 2
CC6x = 1
CC6x = 1
CC6x = 1
CC6x = 0
CC6x = 0
CC6x = 0
CC6x = 3
CC6x = 3
CC6x = 3
CC6x = 3
CC6x = 4
CC6x = 4
CC6x = 4
CC6x = 4
CC6x = 5
CC6x = 5
CC6x = 5
CC6x = 5
CC6x = 3
CC6x = 6
CC6x = 6
CC6x = 6
CDIR
CC6x
a)
b)
c)
d)
e)
f)
CCU6_MCT05517
Figure 21-13 Compare Waveform Examples
Example b) illustrates the transition to a duty cycle of 100%. First, a compare value of
0001H is used, then changed to 0000H. Please note that a low pulse with the length of
one T12 clock is still produced in the cycle where the new value 0000H is in effect; this
pulse originates from the previous value 0001H. In the following timer cycles, the State
Bit CC6xST remains at 1, producing a 100% duty cycle signal. In this case, the compare
rule ‘zero-match AND compare-match’ is in effect.
Example f) shows the transition to a duty cycle of 0%. The new compare value is set to
<Period-Value> + 1, and the State Bit CC6ST remains cleared.
Figure 21-14 illustrates an example for the waveforms of all three channels. With the
appropriate dead-time control and output modulation, a very efficient 3-phase PWM
signal can be generated.
User’s Manual
CCU6, V4.0
21-29
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Period
Value
CC61R
CC62R
T12 Count
Down
Up
Down
Up
CC60R
Zero
Down
CDIR
Shadow
Transfer
CC60ST
CC61ST
CC62ST
CCU6_MCT05518
Figure 21-14 Three-Channel Compare Waveforms
User’s Manual
CCU6, V4.0
21-30
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.3.3 Hysteresis-Like Control Mode
The hysteresis-like control mode (T12MSELL.MSEL6x = 1001B) offers the possibility to
switch off the PWM output if the input CCPOSx becomes 0 by clearing the State Bit
CC6xST. This can be used as a simple motor control feature by using a comparator
indicating, e.g., overcurrent. While CCPOSx = 0, the PWM outputs of the corresponding
channel are driving their passive levels, because the setting of bit CC6xST is only
possible while CCPOSx = 1.
As long as input CCPOSx is 0, the corresponding State Bit is held 0. When CCPOSx is
at high level, the outputs can be in active state and are determined by bit CC6xST (see
Figure 21-10 for the state bit logic and Figure 21-15 for the output paths).
The CCPOSx inputs are evaluated with fCC6.
This mode can be used to introduce a timing-related behavior to a hysteresis controller.
A standard hysteresis controller detects if a value exceeds a limit and switches its output
according to the compare result. Depending on the operating conditions, the switching
frequency and the duty cycle are not fixed, but change permanently.
If (outer) time-related control loops based on a hysteresis controller in an inner loop
should be implemented, the outer loops show a better behavior if they are synchronized
to the inner loops. Therefore, the hysteresis-like mode can be used, that combines timerrelated switching with a hysteresis controller behavior. For example, in this mode, an
output can be switched on according to a fixed time base, but it is switched off as soon
as a falling edge is detected at input CCPOSx.
This mode can also be used for standard PWM with overcurrent protection. As long as
there is no low level signal at pin CCPOSx, the output signals are generated in the
normal manner as described in the previous sections. Only if input CCPOSx shows a low
level, e.g. due to the detection of overcurrent, the outputs are shut off to avoid harmful
stress to the system.
User’s Manual
CCU6, V4.0
21-31
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.4
Compare Mode Output Path
Figure 21-15 gives an overview on the signal path from a channel State Bit to its output
pin in its simplest form. As illustrated, a user has a variety of controls to determine the
desired output signal switching behavior in relation to the current state of the State Bit,
CC6xST. Please refer to Section 21.3.4.3 for details on the output modulation.
T12
State Bits
Dead-Time
Generation
CC60ST
CC61ST
CC62ST
T12
State Selection
Output Level
Selection
CC6xPS
PSLy
CC6xST
CC6x_O
Dead-Time
Counters
T12 Output
Modulation
CC6xST
Level
Select
Level
Select
COUT6x
COUT6x_O
COUT6xPS
CC6x
PSLy+1
CCU6_MCA05519
Figure 21-15 Compare Mode Simplified Output Path Diagram
The output path is based on signals that are defined as active or passive. The terms
active and passive are not related to output levels, but to internal actions. This mainly
applies for the modulation, where T12 and T13 signals are combined with the multichannel signals and the trap function. The Output level Selection allows the user to
define the output level at the output pin for the passive state (inverted level for the active
state). It is recommended to configure this block in a way that an external power switch
is switched off while the CCU6 delivers an output signal in the passive state.
21.3.4.1 Dead-Time Generation
The generation of (complementary) signals for the high-side and the low-side switches
of one power inverter phase is based on the same compare channel. For example, if the
high-side switch should be active while the T12 counter value is above the compare
value (State Bit = 1), then the low-side switch should be active while the counter value
is below the compare value (State Bit = 0).
In most cases, the switching behavior of the connected power switches is not
symmetrical concerning the switch-on and switch-off times. A general problem arises if
the time for switch-on is smaller than the time for switch-off of the power device. In this
case, a short-circuit can occur in the inverter bridge leg, which may damage the
complete system. In order to solve this problem by HW, this capture/compare unit
User’s Manual
CCU6, V4.0
21-32
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
contains a programmable Dead-Time Generation Block, that delays the passive to active
edge of the switching signals by a programmable time (the active to passive edge is not
delayed).
The Dead-Time Generation Block, illustrated in Figure 21-16, is built in a similar way for
all three channels of T12. It is controlled by bits in register T12DTCL, T12DTCH. Any
change of a CC6xST State Bit activates the corresponding Dead-Time Counter, that is
clocked with the same input clock as T12 (fT12). The length of the dead-time can be
programmed by bit field DTM. This value is identical for all three channels. Writing
TCTR4L.DTRES = 1 sets all dead-times to passive.
Dead-Time Value
DTM
fT12
DTRES
Dead-Time
Counter 0
DTE0
CC60ST
Dead-Time 0
active / passive
CC60ST
CC60ST
Dead-Time
Counter 1
DTE1
CC61ST
Dead-Time 1
active / passive
CC61ST
CC61ST
Dead-Time
Counter 2
DTE2
CC62ST
Dead-Time 2
active / passive
CC62ST
CC62ST
CCU6_MCB05520
Figure 21-16 Dead-Time Generation Block Diagram
Each of the three dead-time counters has its individual dead-time enable bit, DTEx. An
enabled dead-time counter generates a dead-time delaying the passive-to-active edge
of the channel output signal. The change in a State Bit CC6xST is not taken into account
while the dead-time generation of this channel is currently in progress (active). This
avoids an unintentional additional dead-time if a State Bit CC6xST changes too early.
A disabled dead-time counter is always considered as passive and does not delay any
edge of CC6xST.
Based on the State Bits CC6xST, the Dead-Time Generation Block outputs a direct
signal CC6xST and an inverted signal CC6xST for each compare channel, each masked
with the effect of the related Dead-Time Counters (waveforms illustrated in
Figure 21-17).
User’s Manual
CCU6, V4.0
21-33
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
T12 Counter
Value
Compare
Value
active
State Bit
CC6xST
DeadTime
passive
active
CC6xST
with DeadTime
CC6xST
with DeadTime
active
passive
passive
active
passive
active
passive
CCU6_MCT05521
Figure 21-17 Dead-Time Generation Waveforms
21.3.4.2 State Selection
To support a wide range of power switches and drivers, the state selection offers the
flexibility to define when a an output can be active and can be modulated, especially
useful for complementary or multi-phase PWM signals.
The state selection is based on the signals CC6xST and CC6xST delivered by the deadtime generator (see Figure 21-15). Both signals are never active at the same time, but
can be passive at the same time. This happens during the dead-time of each compare
channel after a change of the corresponding State Bit CC6xST.
The user can select independently for each output signal CC6xO and COUT6xO if it
should be active before or after the compare value has been reached (see register
CMPSTATL, CMPSTATH). With this selection, the active (conducting) phases of
complementary power switches in a power inverter bridge leg can be positioned with
respect to the compare value (e.g. signal CC6xO can be active before, whereas
COUT6xO can be active after the compare value is reached). Like this, the output
modulation, the trap logic and the output level selection can be programmed
independently for each output signal, although two output signals are referring to the
same compare channel.
User’s Manual
CCU6, V4.0
21-34
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.4.3 Output Modulation and Level Selection
The last block of the data path is the Output Modulation block. Here, all the modulation
sources and the trap functionality are combined and control the actual level of the output
pins (controlled by the modulation enable bits T1xMODENy and MCMEN in register
MODCTRL, MODCTRH). The following signal sources can be combined here for each
T12 output signal (see Figure 21-18 for compare channel CC60):
•
•
•
•
A T12 related compare signal CC6x_O (for outputs CC6x) or COUT6x_O (for
outputs COUT6x) delivered by the T12 block (state selection with dead-time) with an
individual enable bit T12MODENy per output signal (y = 0, 2, 4 for outputs CC6x and
y = 1, 3, 5 for outputs COUT6x)
The T13 related compare signal CC63_O delivered by the T13 state selection with
an individual enable bit T13MODENy per output signal (y = 0, 2, 4 for outputs CC6x
and y = 1, 3, 5 for outputs COUT6x)
A multi-channel output signal MCMPy (y = 0, 2, 4 for outputs CC6x and y = 1, 3, 5
for outputs COUT6x) with a common enable bit MCMEN
The trap state TRPS with an individual enable bit TRPENy per output signal (y = 0,
2, 4 for outputs CC6x and y = 1, 3, 5 for outputs COUT6x)
If one of the modulation input signals CC6x_O/COUT6x_O, CC63_O, or MCMPy of an
output modulation block is enabled and is at passive state, the modulated is also in
passive state, regardless of the state of the other signals that are enabled. Only if all
enabled signals are in active state the modulated output shows an active state. If no
modulation input is enabled, the output is in passive state.
If the Trap State is active (TRPS = 1), then the outputs that are enabled for the trap
signal (by TRPENy = 1) are set to the passive state.
The output of each of the modulation control blocks is connected to a level select block
that is configured by register PSLR. It offers the option to determine the actual output
level of a pin, depending on the state of the output line (decoupling of active/passive
state and output polarity) as specified by the Passive State Select bit PSLy. If the
modulated output signal is in the passive state, the level specified directly by PSLy is
output. If it is in the active state, the inverted level of PSLy is output. This allows the user
to adapt the polarity of an active output signal to the connected circuitry.
The PSLy bits have shadow registers to allow for updates without undesired pulses on
the output lines. The bits related to CC6x and COUT6x (x = 0, 1, 2) are updated with the
T12 shadow transfer signal (T12_ST). A read action returns the actually used values,
whereas a write action targets the shadow bits. Providing a shadow register for the PSL
value as well as for other values related to the generation of the PWM signal facilitates
a concurrent update by software for all relevant parameters.
Figure 21-18 shows the output modulation structure for compare channel CC60 (output
signals CC60 and COUT60). A similar structure is implemented for the other two
compare channels CC61 and CC62.
User’s Manual
CCU6, V4.0
21-35
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Trap Handling
Block
TRPS
TRPEN0
T13 Block
CC63_O
T13MODEN0
Output
Modulation
CC60
active
passive
Level
Selection
CC60
CC60_O
T12 Block +
Dead-Time
PSL0
COUT60_O
T12MODEN0
MCMP0
Multi-Channel
Mode
MCMEN
MCMP1
TRPEN1
T13MODEN1
Output
Modulation
COUT60
active
passive
Level
Selection
COUT60
PSL1
T12MODEN1
CCU6_MCA05543
Figure 21-18 Output Modulation for Compare Channel CC60
User’s Manual
CCU6, V4.0
21-36
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.5
T12 Capture Modes
Each of the three channels of the T12 Block can also be used to capture T12 time
information in response to an external signal CC6xIN.
In capture mode, the interrupt event CC6x_R is detected when a rising edge is detected
at the input CC6xIN, whereas the interrupt event CC6x_F is detected when a falling edge
is detected.
There are a number of different modes for capture operation. In all modes, both of the
registers of a channel are used. The selection of the capture modes is done via the
T12MSELL.MSEL6x bit fields and can be selected individually for each of the channels.
Table 21-8
Capture Modes Overview
MSEL6x
Mode
0100B
1
Signal
Active Edge
CC6nSR Stored in
T12 Stored in
CC6xIN Rising
–
CC6xR
CC6xIN Falling
–
CC6xSR
CC6xR
CC6xSR
0101B
2
CC6xIN Rising
0110B
3
CC6xIN Falling
CC6xR
CC6xSR
0111B
4
CC6xIN Any
CC6xR
CC6xSR
Figure 21-19 illustrates Capture Mode 1. When a rising edge (0-to-1 transition) is
detected at the corresponding input signal CC6xIN, the current contents of Timer T12
are captured into register CC6xR. When a falling edge (1-to-0 transition) is detected at
the input signal CC6xIN, the contents of Timer T12 are captured into register CC6xSR.
fT12
Counter Register
T12
MSEL6x
CC6xIN
Edge
Detect
fCC6
Capture
Mode
Selection
Rising
Falling
Set
State Bit
CC6xST
Register CC6xR
Shadow Register
CC6xSR
CC6x_R
CC6x_F
To Interrupt Logic
CCU6_MCB05522
Figure 21-19 Capture Mode 1 Block Diagram
User’s Manual
CCU6, V4.0
21-37
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Capture Modes 2, 3 and 4 are shown in Figure 21-20. They differ only in the active
edge causing the capture operation. In each of the three modes, when the selected edge
is detected at the corresponding input signal CC6xIN, the current contents of the shadow
register CC6xSR are transferred into register CC6xR, and the current Timer T12
contents are captured in register CC6xSR (simultaneous transfer). The active edge is a
rising edge of CC6xIN for Capture Mode 2, a falling edge for Mode 3, and both, a rising
or a falling edge for Capture Mode 4, as shown in Table 21-8. These capture modes are
very useful in cases where there is little time between two consecutive edges of the input
signal.
fT12
Counter Register
T12
MSEL6x
CC6xIN
Edge
Detect
Capture
Mode
Selection
Shadow Register
CC6xSR
Set
fCC6
State Bit
CC6xST
Register CC6xR
CC6x_R
CC6x_F
To Interrupt Logic
CCU6_MCB05523
Figure 21-20 Capture Modes 2, 3 and 4 Block Diagram
User’s Manual
CCU6, V4.0
21-38
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Five further capture modes are called Multi-Input Capture Modes, as they use two
different external inputs, signal CC6xIN and signal CCPOSx.
fT12
Counter Register
T12
MSEL6x
CC6xIN
Edge
Detect
fCC6
Capture
Mode
Selection
Set
State Bit
CC6xST
Register CC6xR
Set
CC6x_R
CC6x_F
CCPOSx
Edge
Detect
Shadow Register
CC6xSR
To Interrupt Logic
Capture
Mode
Selection
MSEL6x
CCU6_MCB05524
Figure 21-21 Multi-Input Capture Modes Block Diagram
In each of these modes, the current T12 contents are captured in register CC6xR in
response to a selected event at signal CC6xIN, and in register CC6xSR in response to
a selected event at signal CCPOSx. The possible events can be opposite input
transitions, or the same transitions, or any transition at the two inputs. The different
options are detailed in Table 21-9.
In each of the various capture modes, the Channel State Bit, CC6xST, is set to 1 when
the selected capture trigger event at signal CC6xIN or CCPOSx has occurred. The State
Bit is not cleared by hardware, but can be cleared by software.
In addition, appropriate signal lines to the interrupt logic are activated, that can generate
an interrupt request to the CPU. Regardless of the selected active edge, all edges
detected at signal CC6xIN can lead to the activation of the appropriate interrupt request
line (see also Section 21.9).
User’s Manual
CCU6, V4.0
21-39
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Table 21-9
Multi-Input Capture Modes Overview
MSEL6x
Mode
Signal
Active Edge
T12 Stored in
1010B
5
CC6xIN
Rising
CC6xR
CCPOSx
Falling
CC6xSR
1011B
6
CC6xIN
Falling
CC6xR
CCPOSx
Rising
CC6xSR
1100B
1101B
7
8
1110B
9
1111B
–
User’s Manual
CCU6, V4.0
CC6xIN
Rising
CC6xR
CCPOSx
Rising
CC6xSR
CC6xIN
Falling
CC6xR
CCPOSx
Falling
CC6xSR
CC6xIN
Any
CC6xR
CCPOSx
Any
CC6xSR
reserved (no capture or compare action)
21-40
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.6
T12 Shadow Register Transfer
A special shadow transfer signal (T12_ST) can be generated to facilitate updating the
period and compare values of the compare channels CC60, CC61, and CC62
synchronously to the operation of T12. Providing a shadow register for values defining
one PWM period facilitates a concurrent update by software for all relevant parameters.
The next PWM period can run with a new set of parameters. The generation of this signal
is requested by software via bit TCTR0L.STE12 (set by writing 1 to the write-only bit
TCTR4L.T12STR, cleared by writing 1 to the write-only bit TCTR4L.T12STD).
Figure 21-22 shows the shadow register structure and the shadow transfer signals, as
well as on the read/write accessibility of the various registers.
Read
Read
Read
Read
Period Register
T12PR
(T12)
PSLy
CC6xPS
COUT6xPS
Period Shadow
Register T12PR
(T12) PSLy
Shadow
CC6xPS
Shadow
COUT6xPS
Shadow
Write
Write
Write
Write
Read
Compare Register
CC6xR
_
>1
T12_ST
Other Modes
(Hall, Capture, etc.)
Compare Shadow
Register CC6xSR
Write
Read
CCU6_MCA05546
Figure 21-22 T12 Shadow Register Overview
User’s Manual
CCU6, V4.0
21-41
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
A T12 shadow register transfer takes place (T12_ST active):
•
•
•
while timer T12 is not running (T12R = 0), or
STE12 = 1 and a Period-Match is detected while counting up, or
STE12 = 1 and a One-Match is detected while counting down
When signal T12_ST is active, a shadow register transfer is triggered with the next cycle
of the T12 clock. Bit STE12 is automatically cleared with the shadow register transfer.
21.3.7
Timer T12 Operating Mode Selection
The operating mode for the T12 channels are defined by the bit fields TCTR4L.MSEL6x,
T12MSELL.MSEL6x.
Table 21-10 T12 Capture/Compare Modes Overview
MSEL6x
Selected Operating Mode
0000B,
1111B
Capture/Compare modes switched off
0001B,
0010B,
0011B
Compare mode, see Section 21.3.3
same behavior for all three codings
01XXB
Double-Register Capture modes, see Section 21.3.5
1000B
Hall Sensor Mode, see Section 21.7
In order to properly enable this mode, all three MSEL6x fields have to be
programmed to Hall Sensor mode.
1001B
Hysteresis-like compare mode, see Section 21.3.3.3
1010B
1011B,
1100B,
1101B
1110B
Multi-Input Capture modes, see Section 21.3.5
The clocking and counting scheme of the timers are controlled by the timer control
registers TCTR0L, TCTR0H and TCTR2L, TCTR2H. Specific actions are triggered by
write operations to register TCTR4L, TCTR4H.
User’s Manual
CCU6, V4.0
21-42
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.8
T12 related Registers
21.3.8.1 T12 Counter Register
Register T12 represents the counting value of timer T12. It can only be written while the
timer T12 is stopped. Write actions while T12 is running are not taken into account.
Register T12 can always be read by SW.
In edge-aligned mode, T12 only counts up, whereas in center-aligned mode, T12 can
count up and down.
T12L
Timer T12 Counter Register Low
RMAP: 0, PAGE: 3
7
6
5
(FAH)
4
Reset Value: 00H
3
2
1
0
T12CVL
rwh
Field
Bits
Type Description
T12CVL
[7:0]
rwh
Timer T12 Counter Value
This register represents lower 8-bits of the 16-bit
counter value of T12.
T12H
Timer T12 Counter Register High
RMAP: 0, PAGE: 3
7
6
5
(FBH)
4
Reset Value: 00H
3
2
1
0
T12CVH
rwh
Field
Bits
Type Description
T12CVH
[7:0]
rwh
User’s Manual
CCU6, V4.0
Timer T12 Counter Value
This register represents upper 8-bits of the 16-bit
counter value of T12.
21-43
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.8.2 Period Register
Register T12PRL/H contains the period value for timer T12. The period value is
compared to the actual counter value of T12 and the resulting counter actions depend
on the defined counting rules. This register has a shadow register and the shadow
transfer is controlled by bit STE12. A read action by SW delivers the value that is
currently used for the compare action, whereas the write action targets a shadow
register. The shadow register structure allows a concurrent update of all T12-related
values.
T12PRL
Timer T12 Period Register Low
RMAP: 0, PAGE: 1
7
6
5
(9CH)
4
Reset Value: 00H
3
2
1
0
T12PVL
rwh
Field
Bits
Type Description
T12PVL
[7:0]
rwh
Timer T12 Period Value
The value T12PVL defines lower 8-bits of the
counter value for T12 leading to a period-match.
When reaching this value, the timerT12 is set to zero
(edge-aligned mode) or changes its count direction
to down counting (center-aligned mode).
T12PRH
Timer T12 Period Register High
RMAP: 0, PAGE: 1
7
6
5
(9DH)
4
Reset Value: 00H
3
2
1
0
T12PVH
rwh
User’s Manual
CCU6, V4.0
21-44
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
T12PVH
[7:0]
rwh
User’s Manual
CCU6, V4.0
Timer T12 Period Value
The value T12PVL defines the upper 8-bits of
counter value for T12 leading to a period-match.
When reaching this value, the timerT12 is set to zero
(edge-aligned mode) or changes its count direction
to down counting (center-aligned mode).
21-45
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.8.3 Capture/Compare Registers
In compare mode, the registers CC6xRL/H (x = 0 - 2) are the actual compare registers
for T12. The values stored in CC6xR are compared (all three channels in parallel) to the
counter value of T12. In capture mode, the current value of the T12 counter register is
captured by registers CC6xRL/H if the corresponding capture event is detected.
CC6xRL (x = 0-2)
Capture/Compare Register for Channel CC6x Low
(FAH + x * 2)
RMAP: 0, PAGE: 1
7
6
5
4
3
Reset Value: 00H
2
1
0
CCVL
rh
Field
Bits
Type Description
CCVL
[7:0]
rh
Capture/Compare Value
In compare mode, the bit fields CCV contain the
values, that are compared to the T12 counter value.
In capture mode, the captured value of T12 can be
read from these registers.
CC6xRH (x = 0-2)
Capture/Compare Register for Channel CC6x High
(FBH + x * 2)
RMAP: 0, PAGE: 1
7
6
5
4
3
Reset Value: 00H
2
1
0
CCVH
rh
Field
Bits
Type Description
CCVH
[7:0]
rh
User’s Manual
CCU6, V4.0
Capture/Compare Value
In compare mode, the bit fields CCV contain the
values, that are compared to the T12 counter value.
In capture mode, the captured value of T12 can be
read from these registers.
21-46
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.8.4 Capture/Compare Shadow Registers
The registers CC6xRL/H can only be read by SW, the modification of the value is done
by a shadow register transfer from register CC6xSRL/H. The corresponding shadow
registers CC6xSRL/H can be read and written by SW. In capture mode, the value of the
T12 counter register can also be captured by registers CC6xSRL/H if the selected
capture event is detected (depending on the selected capture mode).
CC6xSRL (x=0-2)
Capture/Compare Shadow Register for Channel CC6x Low
(FAH + x * 2)
RMAP: 0, PAGE: 0
7
6
5
4
3
2
Reset Value: 00H
1
0
CCSL
rwh
Field
Bits
Type Description
CCSL
[7:0]
rh
Shadow Register for Channel x
Capture/Compare Value
In compare mode, the bit fields contents of CCS are
transferred to the bit fields CCV for the
corresponding channel during a shadow transfer. In
capture mode, the captured value of T12 can be read
from these registers.
Note: The shadow registers can also be written by SW in capture mode. In this case, the
HW capture event wins over the SW write if both happen in the same cycle (the
SW write is discarded).
CC6xSRH (x=0-2)
Capture/Compare Shadow Register for Channel CC6x High
(FBH + x * 2)
RMAP: 0, PAGE: 0
7
6
5
4
3
2
Reset Value: 00H
1
0
CCSH
rh
User’s Manual
CCU6, V4.0
21-47
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
CCSH
[7:0]
rh
Shadow Register for Channel x
Capture/Compare Value
In compare mode, the bit fields contents of CCS are
transferred to the bit fields CCV for the
corresponding channel during a shadow transfer. In
capture mode, the captured value of T12 can be read
from these registers.
Note: The shadow registers can also be written by SW in capture mode. In this case, the
HW capture event wins over the SW write if both happen in the same cycle (the
SW write is discarded).
User’s Manual
CCU6, V4.0
21-48
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.8.5 Dead-time Control Register
Register T12DTCL/H controls the dead-time generation for the timer T12 compare
channels. Each channel can be independently enabled/disabled for dead-time
generation. If enabled, the transition from passive state to active state is delayed by the
value defined by bit field DTM.
The dead time counters are clocked with the same frequency as T12.
This structure allows symmetrical dead-time generation in center-aligned and in edgealigned PWM mode. A duty cycle of 50% leads to CC6x, COUT6x switched on for: 0.5 *
period - dead time.
Note: The dead-time counters are not reset by bit T12RES, but by bit DTRES.
T12DTCL
Dead-Time Control Register for Timer T12 Low
(A4H)
RMAP: 0, PAGE: 1
7
6
5
4
3
Reset Value: 00H
2
1
0
DTM
rw
Field
Bits
Type Description
DTM
[7:0]
rw
Dead-Time
Bit field DTM determines the programmable delay
between switching from the passive state to the
active state of the selected outputs. The switching
from the active state to the passive state is not
delayed.
T12DTCH
Dead-Time Control Register for Timer T12 High
(A5H)
RMAP: 0, PAGE: 1
Reset Value: 00H
7
6
5
4
3
2
1
0
0
DTR2
DTR1
DTR0
0
DTE2
DTE1
DTE0
r
rh
rh
rh
r
rw
rw
rw
User’s Manual
CCU6, V4.0
21-49
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
DTE2,
DTE1,
DTE0
2,
1,
0
rw
Dead Time Enable Bits
Bits DTE0..DTE2 enable and disable the dead time
generation for each compare channel (0, 1, 2) of
timer T12.
0B
Dead-Time Counter x is disabled. The
corresponding outputs switch from the passive
state to the active state (according to the
actual compare status) without any delay.
Dead-Time Counter x is enabled. The
1B
corresponding outputs switch from the passive
state to the active state (according to the
compare status) with the delay programmed in
bit field DTM.
DTR2,
DTR1,
DTR0
6,
5,
4
rw
Dead Time Run Indication Bits
Bits DTR0..DTR2 indicate the status of the dead time
generation for each compare channel (0, 1, 2) of
timer T12.
Dead-Time Counter x is currently in the
0B
passive state.
Dead-Time Counter x is currently in the active
1B
state.
0
7,
3
r
reserved;
returns 0 if read; should be written with 0;
User’s Manual
CCU6, V4.0
21-50
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.9
Capture/Compare Control Registers
21.3.9.1 Channel State Bits
The Compare State Register CMPSTATL/H contains status bits monitoring the current
capture and compare state and control bits defining the active/passive state of the
compare channels.
CMPSTATL
Compare State Register Low
RMAP: 0, PAGE: 3
(FEH)
Reset Value: 00H
7
6
5
4
3
2
1
0
0
CC63ST
CCPOS2
CCPOS1
CCPOS0
CC62ST
CC61ST
CC60ST
r
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
CC60ST,
CC61ST,
CC62ST,
CC63ST
0,
1,
2,
6
rh
Capture/Compare State Bits
Bits CC6xST monitor the state of the
capture/compare channels. Bits CC6xST (x = 0, 1,
2) are related to T12, bit CC63ST is related to T13.
In compare mode, the timer count is less than
0B
the compare value.
In capture mode, the selected edge has not yet
been detected since the bit has been cleared
by SW the last time.
In compare mode, the counter value is greater
1B
than or equal to the compare value.
In capture mode, the selected edge has been
detected.
CCPOS60,
CCPOS61,
CCPOS62
3,
4,
5
rh
Sampled Hall Pattern Bits
Bits CCPOS6x (x = 0, 1, 2) are indicating the value
of the input Hall pattern that has been compared to
the current and expected value. The value is
sampled when the event HCRDY (Hall Compare
Ready) occurs.
The input CCPOS6x has been sampled as 0.
0B
1B
The input CCPOS6x has been sampled as 1.
0
7
r
reserved;
returns 0 if read; should be written with 0;
1)
User’s Manual
CCU6, V4.0
21-51
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
1) These bits are set and cleared according to the T12, T13 switching rules
CMPSTATH
Compare State Register High
RMAP: 0, PAGE: 3
7
T13IM
6
5
COUT63P COUT62P
S
S
rwh
rwh
rwh
(FFH)
Reset Value: 00H
4
3
2
1
0
CC62PS
COUT61P
S
CC61PS
COUT60P
S
CC60PS
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type Description
CC60PS,
CC61PS,
CC62PS,
COUT60PS,
COUT61PS,
COUT62PS,
COUT63PS
0,
2,
4,
1,
3,
5,
6
rwh
Passive State Select for Compare Outputs
Bits CC6xPS, COUT6xPS select the state of the
corresponding compare channel, that is considered
to be the passive state. During the passive state, the
passive level (defined in register PSLR) is driven by
the output pin. Bits CC6xPS, COUT6xPS (x = 0, 1, 2)
are related to T12, bit CC63PS is related to T13.
The corresponding compare signal is in
0B
passive state while CC6xST is 0.
The corresponding compare signal is in
1B
passive state while CC6xST is 1.
In capture mode, these bits are not used.
T13IM2)
15
rwh
T13 Inverted Modulation
Bit T13IM inverts the T13 signal for the modulation of
the CC6x and COUT6x (x = 0, 1, 2) signals.
T13 output CC63_O is equal to CC63ST.
0B
T13 output CC63_O is equal to CC63ST.
1B
1)
1) These bits have shadow bits and are updated in parallel to the capture/compare registers of T12, T13
respectively. A read action targets the actually used values, whereas a write action targets the shadow bits.
2) This bit has a shadow bit and is updated in parallel to the compare and period registers of T13. A read action
targets the actually used values, whereas a write action targets the shadow bit.
User’s Manual
CCU6, V4.0
21-52
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
The Compare Status Modification Register CMPMODIFL/H provides software-control
(independent set and clear conditions) for the channel state bits CC6xST. This feature
enables the user to individually change the status of the output lines by software, for
example when the corresponding compare timer is stopped.
CMPMODIFL
Compare State Modification Register Low
(A6H)
RMAP: 0, PAGE: 0
7
6
5
0
MCC63S
r
w
4
Reset Value: 00H
3
2
1
0
0
MCC62S
MCC61S
MCC60S
r
w
w
w
Field
Bits
Type Description
MCC60S,
MCC61S,
MCC62S,
MCC63S
0,
1,
2,
6
w
Capture/Compare Status Modification Bits
These bits are used to bits to set (MCC6xS) or to
clear (MCC6xR1)) the corresponding bits CC6xST by
SW.
This feature allows the user to individually change
the status of the output lines by SW, e.g. when the
corresponding compare timer is stopped. This allows
a bit manipulation of CC6xST-bits by a single data
write action.
The following functionality of a write access to bits
concerning the same capture/compare state bit is
provided:
[MCC6xR, MCC6xS] =
00B Bit CC6xST is not changed.
01B Bit CC6xST is set.
10B Bit CC6xST is cleared.
11B reserved
0
[5:3],
7
r
reserved;
returns 0 if read; should be written with 0;
1) This bit field is contained in the Compare State Modification Register High
User’s Manual
CCU6, V4.0
21-53
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
CMPMODIFH
Compare State Modification Register High
(A7H)
RMAP: 0, PAGE: 0
7
6
5
0
MCC63R
r
w
4
Reset Value: 00H
3
2
1
0
0
MCC62R
MCC61R
MCC60R
0
rw
w
w
Field
Bits
Type Description
MCC60R,
MCC61R,
MCC62R,
MCC63R
0,
1,
2,
6
w
Capture/Compare Status Modification Bits
These bits are used to bits to set (MCC6xS1)) or to
clear (MCC6xR) the corresponding bits CC6xST by
SW.
This feature allows the user to individually change
the status of the output lines by SW, e.g. when the
corresponding compare timer is stopped. This allows
a bit manipulation of CC6xST-bits by a single data
write action.
The following functionality of a write access to bits
concerning the same capture/compare state bit is
provided:
[MCC6xR, MCC6xS] =
00B Bit CC6xST is not changed.
01B Bit CC6xST is set.
10B Bit CC6xST is cleared.
11B reserved
0
[5:3],
7
r
reserved;
returns 0 if read; should be written with 0;
1) This bit field is contained in the Compare State Modification Register Low
User’s Manual
CCU6, V4.0
21-54
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.9.2 T12 Mode Control Register
Register T12MSELL/H contains control bits to select the capture/compare functionality
of the three channels of Timer T12.
T12MSELL
T12 Mode Select Register Low
RMAP: 0, PAGE: 2
7
6
5
(9AH)
4
3
2
1
MSEL61
MSEL60
rw
rw
Field
Bits
Type Description
MSEL60,
MSEL61
[3:0],
[7:4]
rw
6
5
(9BH)
4
Reset Value: 00H
3
2
1
DBYP
HSYNC
MSEL62
rw
rw
rw
Field
Bits
Type Description
MSEL62
[3:0]
rw
User’s Manual
CCU6, V4.0
0
Capture/Compare Mode Selection
These bit fields select the operating mode of the
three T12 capture/compare channels. Each channel
(x = 0, 1, 2) can be programmed individually for one
of these modes (except for Hall Sensor Mode).
Coding see Table 21-10.
T12MSELH
T12 Mode Select Register High
RMAP: 0, PAGE: 2
7
Reset Value: 00H
0
Capture/Compare Mode Selection
These bit fields select the operating mode of the
three T12 capture/compare channels. Each channel
(x = 0, 1, 2) can be programmed individually for one
of these modes (except for Hall Sensor Mode).
Coding see Table 21-10.
21-55
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
HSYNC
[6:4]
rw
Hall Synchronization
Bit field HSYNC defines the source for the sampling
of the Hall input pattern and the comparison to the
current and the expected Hall pattern bit fields.
Coding see Table 21-15.
DBYP
7
rw
Delay Bypass
DBYP controls whether the source signal for the
sampling of the Hall input pattern (selected by
HSYNC) is delayed by the Dead-Time Counter 0.
The bypass is not active.
0B
Dead-Time Counter 0 is generating a delay
after the source signal becomes active.
The bypass is active.
1B
Dead-Time Counter 0 is not used for a delay.
User’s Manual
CCU6, V4.0
21-56
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.3.9.3 Timer Control Registers
Register TCTR0L/H controls the basic functionality of both timers, T12 and T13.
Note: A write action to the bit fields T12CLK or T12PRE is only taken into account while
the timer T12 is not running (T12R=0). A write action to the bit fields T13CLK or
T13PRE is only taken into account while the timer T13 is not running (T13R=0).
TCTR0L
Timer Control Register 0 Low
RMAP: 0, PAGE: 1
(A6H)
Reset Value: 00H
7
6
5
4
3
2
1
0
CTM
CDIR
STE12
T12R
T12PRE
T12CLK
rw
rh
rh
rh
rw
rw
Field
Bits
Type Description
T12CLK
[2:0]
rw
Timer T12 Input Clock Select
Selects the input clock for timer T12 that is derived
from the peripheral clock according to the equation
fT12 = fCC6 / 2<T12CLK>.
000B fT12 = fCC6
001B fT12 = fCC6 / 2
010B fT12 = fCC6 / 4
011B fT12 = fCC6 / 8
100B fT12 = fCC6 / 16
101B fT12 = fCC6 / 32
110B fT12 = fCC6 / 64
111B fT12 = fCC6 / 128
T12PRE
3
rw
Timer T12 Prescaler Bit
In order to support higher clock frequencies, an
additional prescaler factor of 1/256 can be enabled
for the prescaler for T12.
The additional prescaler for T12 is disabled.
0B
1B
The additional prescaler for T12 is enabled.
User’s Manual
CCU6, V4.0
21-57
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
T12R
4
rh
Timer T12 Run Bit1)
T12R starts and stops timer T12. It is set/cleared by
SW by setting bits T12RR or T12RS or it is cleared
by HW according to the function defined by bit field
T12SSC.
Timer T12 is stopped.
0B
Timer T12 is running.
1B
STE12
5
rh
Timer T12 Shadow Transfer Enable
Bit STE12 enables or disables the shadow transfer
of the T12 period value, the compare values and
passive state select bits and levels from their
shadow registers to the actual registers if a T12
shadow transfer event is detected. Bit STE12 is
cleared by hardware after the shadow transfer.
A T12 shadow transfer event is a period-match while
counting up or a one-match while counting down.
The shadow register transfer is disabled.
0B
1B
The shadow register transfer is enabled.
CDIR
6
rh
Count Direction of Timer T12
This bit is set/cleared according to the counting rules
of T12.
0B
T12 counts up.
1B
T12 counts down.
CTM
7
rw
T12 Operating Mode
0B
Edge-aligned Mode:
T12 always counts up and continues counting
from zero after reaching the period value.
Center-aligned Mode:
1B
T12 counts down after detecting a periodmatch and counts up after detecting a onematch.
1) A concurrent set/clear action on T12R (from T12SSC, T12RR or T12RS) will have no effect. The bit T12R will
remain unchanged.
User’s Manual
CCU6, V4.0
21-58
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
TCTR0H
Timer Control Register 0 High
RMAP: 0, PAGE: 1
7
6
(A7H)
Reset Value: 00H
5
4
3
2
1
0
0
STE13
T13R
T13PRE
T13CLK
r
rh
rh
rw
rw
Field
Bits
Type Description
T13CLK
[2:0]
rw
Timer T13 Input Clock Select
Selects the input clock for timer T13 that is derived
from the peripheral clock according to the equation
fT13 = fCC6 / 2<T13CLK>.
000B fT13 = fCC6
001B fT13 = fCC6 / 2
010B fT13 = fCC6 / 4
011B fT13 = fCC6 / 8
100B fT13 = fCC6 / 16
101B fT13 = fCC6 / 32
110B fT13 = fCC6 / 64
111B fT13 = fCC6 / 128
T13PRE
3
rw
Timer T13 Prescaler Bit
In order to support higher clock frequencies, an
additional prescaler factor of 1/256 can be enabled
for the prescaler for T13.
The additional prescaler for T13 is disabled.
0B
1B
The additional prescaler for T13 is enabled.
T13R
4
rh
Timer T13 Run Bit1)
T13R starts and stops timer T13. It is set/cleared by
SW by setting bits T13RR orT13RS or it is
set/cleared by HW according to the function defined
by bit fields T13SSC, T13TEC and T13TED.
Timer T13 is stopped.
0B
Timer T13 is running.
1B
User’s Manual
CCU6, V4.0
21-59
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
STE13
5
rh
Timer T13 Shadow Transfer Enable
Bit STE13 enables or disables the shadow transfer
of the T13 period value, the compare value and
passive state select bit and level from their shadow
registers to the actual registers if a T13 shadow
transfer event is detected. Bit STE13 is cleared by
hardware after the shadow transfer.
A T13 shadow transfer event is a period-match.
The shadow register transfer is disabled.
0B
The shadow register transfer is enabled.
1B
0
[7: 6]
r
reserved;
returns 0 if read; should be written with 0;
1) A concurrent set/cleared action on T13R (from T13SSC, T13TEC, T13RR or T13RS) will have no effect. The
bit T12R will remain unchanged.
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Capture/Compare Unit 6 (CCU6)
Register TCTR2L/H controls the single-shot and the synchronization functionality of both
timers T12 and T13. Both timers can run in single-shot mode. In this mode they stop their
counting sequence automatically after one counting period with a count value of zero.
The single-shot mode and the synchronization feature of T13 to T12 allow the generation
of events with a programmable delay after well-defined PWM actions of T12.
TCTR2L
Timer Control Register 2 Low
RMAP: 0, PAGE: 2
7
6
5
(FAH)
4
Reset Value: 00H
3
2
1
0
0
T13TED
T13TEC
T13SSC
T12SSC
r
rw
rw
rw
rw
Field
Bits
Type Description
T12SSC
0
rw
Timer T12 Single Shot Control
This bit controls the single shot-mode of T12.
The single-shot mode is disabled, no HW
0B
action on T12R.
The single shot mode is enabled, the bit T12R
1B
is cleared by HW if
- T12 reaches its period value in edge-aligned
mode
- T12 reaches the value 1 while down counting
in center-aligned mode.
In parallel to the clear action of bit T12R, the
bits CC6xST (x=0, 1, 2) are cleared.
T13SSC
1
rw
Timer T13 Single Shot Control
This bit controls the single shot-mode of T13.
No HW action on T13R
0B
The single-shot mode is enabled, the bit T13R
1B
is cleared by HW if T13 reaches its period
value.
In parallel to the clear action of bit T13R, the bit
CC63ST is cleared.
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
T13TEC
[4:2]
rw
T13 Trigger Event Control
bit field T13TEC selects the trigger event to start T13
(automatic set of T13R for synchronization to T12
compare signals) according to following
combinations:
000B no action
001B set T13R on a T12 compare event on channel
0
010B set T13R on a T12 compare event on channel
1
011B set T13R on a T12 compare event on channel
2
100B set T13R on any T12 compare event (ch. 0, 1,
2)
101B set T13R upon a period-match of T12
110B set T13R upon a zero-match of T12 (while
counting up)
111B set T13R on any edge of inputs CCPOSx
T13TED
[6:5]
rw
Timer T13 Trigger Event Direction1)
Bit field T13TED delivers additional information to
control the automatic set of bit T13R in the case that
the trigger action defined by T13TEC is detected.
00B reserved, no action
01B while T12 is counting up
10B while T12 is counting down
11B independent on the count direction of T12
0
7
r
reserved;
returns 0 if read; should be written with 0;
1) Example:
If the timer T13 is intended to start at any compare event on T12 (T13TEC=100) the trigger event direction
can be programmed to
- counting up >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting up
- counting down >> a T12 channel 0, 1, 2 compare match triggers T13R only while T12 is counting down
- independent from bit CDIR >> each T12 channel 0, 1, 2 compare match triggers T13R
The timer count direction is taken from the value of bit CDIR. As a result, if T12 is running in edge-aligned
mode (counting up only), T13 can only be started automatically if bit field T13TED=01 or 11.
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Capture/Compare Unit 6 (CCU6)
TCTR2H
Timer Control Register 2 High
RMAP: 0, PAGE: 2
7
6
5
(FBH)
4
Reset Value: 00H
3
2
1
0
0
T13RSEL
T12RSEL
r
rw
rw
Field
Bits
Type Description
T12RSEL
[1:0]
rw
Timer T12 External Run Selection
Bit field T12RSEL defines the event of signal T12HR
that can set the run bit T12R by HW.
00B The external setting of T12R is disabled.
01B Bit T12R is set if a rising edge of signal T12HR
is detected.
10B Bit T12R is set if a falling edge of signal T12HR
is detected.
11B Bit T12R is set if an edge of signal T12HR is
detected.
T13RSEL
[3:2]
rw
Timer T13 External Run Selection
Bit field T13RSEL defines the event of signal T13HR
that can set the run bit T13R by HW.
00B The external setting of T13R is disabled.
01B Bit T13R is set if a rising edge of signal T13HR
is detected.
10B Bit T13R is set if a falling edge of signal T13HR
is detected.
11B Bit T13R is set if an edge of signal T13HR is
detected.
0
[7:4]
r
reserved;
returns 0 if read; should be written with 0;
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Capture/Compare Unit 6 (CCU6)
Register TCTR4L/H provides software-control (independent set and clear conditions) for
the run bits T12R and T13R. Furthermore, the timers can be reset (while running) and
bits STE12 and STE13 can be controlled by software. Reading these bits always returns
0.
TCTR4L
Timer Control Register 4 Low
RMAP: 0, PAGE: 0
7
6
T12STD
T12STR
w
w
(9CH)
5
4
Reset Value: 00H
3
2
1
0
0
DTRES
T12RES
T12RS
T12RR
r
w
w
w
w
Field
Bits
Type Description
T12RR
0
w
Timer T12 Run Reset
Setting this bit clears the T12R bit.
0B
T12R is not influenced.
1B
T12R is cleared, T12 stops counting.
T12RS
1
w
Timer T12 Run Set
Setting this bit sets the T12R bit.
0B
T12R is not influenced.
T12R is set, T12 starts counting.
1B
T12RES
2
w
Timer T12 Reset
No effect on T12.
0B
1B
The T12 counter register is cleared to zero.
The switching of the output signals is
according to the switching rules. Setting of
T12RES has no impact on bit T12R.
DTRES
3
w
Dead-Time Counter Reset
0B
No effect on the dead-time counters.
The three dead-time counter channels are
1B
cleared to zero.
T12STR
6
w
Timer T12 Shadow Transfer Request
No action
0B
1B
STE12 is set, enabling the shadow transfer.
T12STD
7
w
Timer T12 Shadow Transfer Disable
0B
No action
STE12 is cleared without triggering the
1B
shadow transfer.
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
0
[5:4]
r
reserved;
returns 0 if read; should be written with 0;
Note: A simultaneous write of a 1 to bits that set and clear the same bit will trigger no
action. The corresponding bit will remain unchanged.
TCTR4H
Timer Control Register 4 High
RMAP: 0, PAGE: 0
7
6
5
T13STD
T13STR
w
w
(9DH)
4
Reset Value: 00H
3
2
1
0
0
T13RES
T13RS
T13RR
r
w
w
w
Field
Bits
Type Description
T13RR
0
w
Timer T13 Run Reset
Setting this bit clears the T13R bit.
0B
T13R is not influenced.
T13R is cleared, T13 stops counting.
1B
T13RS
1
w
Timer T13 Run Set
Setting this bit sets the T13R bit.
T13R is not influenced.
0B
T13R is set, T13 starts counting.
1B
T13RES
2
w
Timer T13 Reset
0B
No effect on T13.
The T13 counter register is cleared to zero.
1B
The switching of the output signals is
according to the switching rules. Setting of
T13RES has no impact on bit T13R.
T13STR
6
w
Timer T13 Shadow Transfer Request
No action
0B
1B
STE13 is set, enabling the shadow transfer.
T13STD
7
w
Timer T13 Shadow Transfer Disable
0B
No action
STE13 is cleared without triggering the
1B
shadow transfer.
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Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
0
[5:3]
r
reserved;
returns 0 if read; should be written with 0;
Note: A simultaneous write of a 1 to bits that set and clear the same bit will trigger no
action. The corresponding bit will remain unchanged.
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Capture/Compare Unit 6 (CCU6)
21.4
Operating Timer T13
Timer T13 is implemented similarly to Timer T12, but only with one channel in compare
mode. A 16-bit up-counter is connected to a channel register via a comparator, that
generates a signal when the counter contents match the contents of the channel register.
A variety of control functions facilitate the adaptation of the T13 structure to different
application needs. In addition, T13 can be started synchronously to timer T12 events.
This section provides information about:
•
•
•
•
•
•
T13 overview (see Section 21.4.1)
Counting scheme (see Section 21.4.2)
Compare mode (see Section 21.4.3)
Compare output path (see Section 21.4.4)
Shadow register transfer (see Section 21.4.5)
T13 counter register description (see Section 21.4.6)
State Bit
Timer T13
Logic
Capture/Compare
Channel CC63
CC63ST
To Output
Modulation
Input and Control/Status Logic
T13HR
Synchronization to T12
CCU6_MCA05526
Figure 21-23 Overview Diagram of the Timer T13 Block
21.4.1
T13 Overview
Figure 21-24 shows a detailed block diagram of Timer T13. The functions of the timer
T12 block are controlled by bits in registers TCTR0L, TCTR0H, TCTR2L, TCTR2H,
TCTR4L, TCTR4H, and PISEL2.
Timer T13 receives its input clock, fT13, from the module clock fCC6 via a programmable
prescaler and an optional 1/256 divider or from an input signal T13HR. T13 can only
count up (similar to the Edge-Aligned mode of T12).
Via a comparator, the timer T13 Counter Register T13L, T13His connected to the Period
Register T13PRL, T13PRH. This register determines the maximum count value for T13.
When T13 reaches the period value, signal T13_PM (T13 Period Match) is generated
and T13 is cleared to 0000H with the next T13 clock edge. The Period Register receives
a new period value from its Shadow Period Register, T13PS, that is loaded via software.
The transfer of a new period value from the shadow register into T13PR is controlled via
the ‘T13 Shadow Transfer’ control signal, T13_ST. The generation of this signal depends
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Capture/Compare Unit 6 (CCU6)
on the associated control bit STE13. Providing a shadow register for the period value as
well as for other values related to the generation of the PWM signal facilitates a
concurrent update by software for all relevant parameters (refer to Table 21.4.5).
Another signal indicates whether the counter contents are equal to 0000H (T13_ZM).
A Single-Shot control bit, T13SSC, enables an automatic stop of the timer when the
current counting period is finished (see Figure 21-24).
T 13R SEL
Sy nc. to T12
T 13R S
T13 R R
T 13R
edge
detec tion
T 13ST R
T 13ST D
T 13H R
C loc k
Selec tion
fCC 6
T13
C ontrol
& Status
ST E13
edge
detec tion
n
T 13C LK
f T 13
C ounter R egis ter
T 13
256
T 13R ES
= 0000 H
T 13PR E
R ead from
T 13PR
T 13SSC
T13 _Z M
C om p.
=?
T13 _PM
Period R egis ter
T13 _ST
W rite to
T 13PR
Period Shadow
R egis ter
8BIT_8BIT_CCU6_M CA05527
Figure 21-24 T13 Counter Logic and Period Comparators
The start or stop of T13 is controlled by the Run bit, T13R. This control bit can be set by
software via the associated set/clear bits T13RS or T13RR in register TCTR4L,
TCTR4H, or it is cleared by hardware according to preselected conditions (single-shot
mode).
The timer T13 run bit T13R must not be set while the applied T13 period value is zero.
Bit T13R can be set automatically if an event of T12 is detected to synchronize T13
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Capture/Compare Unit 6 (CCU6)
timings to T12 events, e.g. to generate a programmable delay via T13 after an edge of
a T12 compare channel before triggering an AD conversion (T13 can trigger ADC
conversions).
Timer T13 can be cleared to 0000H via control bit T13RES. Setting this write-only bit only
clears the timer contents, but has no further effects, e.g., it does not stop the timer.
The generation of the T13 shadow transfer control signal, T13_ST, is enabled via bit
STE13. This bit can be set or cleared by software indirectly through its associated
set/reset control bits T13STR and T13STD.
Two bit fields, T13TEC and T13TED, control the synchronization of T13 to Timer T12
events. T13TEC selects the trigger event, while T13TED determines for which T12 count
direction the trigger should be active.
While Timer T13 is running, write accesses to the count register T13 are not taken into
account. If T13 is stopped, write actions to register T13 are immediately taken into
account.
Note: The T13 Period Register and its associated shadow register are located at the
same physical address. A write access to this address targets the Shadow
Register, while a read access reads from the actual period register.
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Capture/Compare Unit 6 (CCU6)
21.4.2
T13 Counting Scheme
This section describes the clocking and the counting capabilities of T13.
21.4.2.1 T13 Counting
The period of the timer is determined by the value in the period Register T13PR
according to the following formula:
T13PER = <Period-Value> + 1; in T13 clocks (fT13)
(21.3)
Timer T13 can only count up, comparable to the Edge-Aligned mode of T12. This leads
to very simple ‘counting rule’ for the T13 counter:
•
The counter is cleared with the next T13 clock edge if a Period-Match is detected.
The counting direction is always upwards.
The behavior of T13 is illustrated in Figure 21-25.
fT13
Period
Value
T13 Count
Period Zero
Match Match
Zero
CC63
Value n+1
Value n+2
Shadow Transfer
CCU6_MCT05528
Figure 21-25 T13 Counting Sequence
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Capture/Compare Unit 6 (CCU6)
21.4.2.2 Single-Shot Mode
In Single-Shot Mode, the timer run bit T13R is cleared by hardware. If bit T13SSC = 1,
the timer T13 will stop when the current timer period is finished.
fT13
Period
Value
Compare
Value
T13 Count
0
T13R
CC63ST
T13SSC
CCU6_MCT05529
Figure 21-26 Single-Shot Operation of Timer T13
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Capture/Compare Unit 6 (CCU6)
21.4.2.3 Synchronization to T12
Timer T13 can be synchronized to a T12 event. Bit fields T13TEC and T13TED select
the event that is used to start Timer T13. The selected event sets bit T13R via HW, and
T13 starts counting. Combined with the Single-Shot mode, this feature can be used to
generate a programmable delay after a T12 event.
Figure 21-27 shows an example for the synchronization of T13 to a T12 event. Here, the
selected event is a compare-match (compare value = 2) while counting up. The clocks
of T12 and T13 can be different (other prescaler factor); the figure shows an example in
which T13 is clocked with half the frequency of T12.
fT12
Compare-Match
Period
Value
T12 Count
Compare
Value
Zero
T13R
T13 Count
fT13
CCU6_MCT05530
Figure 21-27 Synchronization of T13 to T12 Compare Match
Bit field T13TEC selects the trigger event to start T13 (automatic set of T13R for
synchronization to T12 compare signals) according to the combinations shown in
Table 21-11. Bit field T13TED additionally specifies for which count direction of T12 the
selected trigger event should be regarded (see Table 21-12).
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Capture/Compare Unit 6 (CCU6)
Table 21-11 T12 Trigger Event Selection
T13TEC
Selected Event
000B
None
001B
T12 Compare Event on Channel 0 (CM_CC60)
010B
T12 Compare Event on Channel 1 (CM_CC61)
011B
T12 Compare Event on Channel 2 (CM_CC62)
100B
T12 Compare Event on any Channel (0, 1, 2)
101B
T12 Period-Match (T12_PM)
110B
T12 Zero-Match while counting up (T12_ZM and CDIR = 0)
111B
Any Hall State Change
Table 21-12 T12 Trigger Event Additional Specifier
T13TED
Selected Event Specifier
00B
Reserved, no action
01B
Selected event is active while T12 is counting up (CDIR = 0)
10B
Selected event is active while T12 is counting down (CDIR = 1)
11B
Selected event is active independently of the count direction of T12
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Capture/Compare Unit 6 (CCU6)
21.4.3
T13 Compare Mode
Associated with Timer T13 is one compare channel, that can perform compare
operations with regard to the contents of the T13 counter.
Figure 21-23 gives an overview on the T13 channel in Compare Mode. The channel is
connected to the T13 counter register via an equal-to comparator, generating a compare
match signal when the contents of the counter matches the contents of the compare
register.
The channel consists of the comparator and a double register structure - the actual
compare register, CC63RL, CC63RH, feeding the comparator, and an associated
shadow register, CC63SRL, CC63SRH, that is preloaded by software and transferred
into the compare register when signal T13 shadow transfer, T13_ST, gets active.
Providing a shadow register for the compare value as well as for other values related to
the generation of the PWM signal facilitates a concurrent update by software for all
relevant parameters.
Associated with the channel is a State Bit, CMPSTATL.CC63ST, holding the status of
the compare operation. Figure 21-28 gives an overview on the logic for the State Bit.
fT13
Counter Register
T13
T13_ZM
Comp.
=?
CM_63
Compare Register
CC63R
Switching
Rule
Logic
State Bit
CC63ST
T13R
MCC63S/R
To State
Selection and
Output
Modulation
To Interrupt
Control
T13_ST
Compare Shadow
Register CC63SR
CCU6_MCB05532
Figure 21-28 T13 State Bit Block Diagram
A compare interrupt event CM_63 is signaled when a compare match is detected. The
actual setting of a State Bit has no influence on the interrupt generation.
The inputs to the switching rule logic for the CC63ST bit are the timer run bit (T13R), the
timer zero-match signal (T13_ZM), and the actual individual compare-match signal
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Capture/Compare Unit 6 (CCU6)
CM_63. In addition, the state bit can be set or cleared by software via bits MCC63S and
MCC63R in register CMPMODIFL, CMPMODIFH.
A modification of the State Bit CC63ST by hardware is only possible while Timer T13 is
running (T13R = 1). If this is the case, the following switching rules apply for setting and
resetting the State Bit in Compare Mode:
State Bit CC63ST is set to 1
•
•
with the next T13 clock (fT13) after a compare-match (T13 is always counting up)
(i.e., when the counter is incremented above the compare value);
with the next T13 clock (fT13) after a zero-match AND a parallel compare-match.
State Bit CC63ST is cleared to 0
•
with the next T13 clock (fT13) after a zero-match AND NO parallel compare-match.
fT13
Compare-Match
Compare-Match
Period
Value
Compare
Value
T13 Count
Zero
CC63ST
CCU6_MCT05533
Figure 21-29 T13 Compare Operation
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Capture/Compare Unit 6 (CCU6)
21.4.4
Compare Mode Output Path
Figure 21-30 gives an overview on the signal path from the channel State Bit CC63ST
to its output pin COUT63. As illustrated, a user can determine the desired output
behavior in relation to the current state of CC63ST. Please refer to Section 21.3.4.3 for
detailed information on the output modulation for T12 signals.
T13
State Selection
Output
Modulation
Output Level
Selection
T13IM
CC63ST
CC63_O
T13
State Bit
CC63ST
T12 Output
Modulation
T13 Output
Modulation
CC63ST
Level
Select
COUT63
COUT63_O
COUT63PS
ECT13O
PSL63
CCU6_MCA05534
Figure 21-30 Channel 63 Output Path
The output line COUT63_O can generate a T13 PWM at the output pin COUT63. The
signal CC63_O can be used to modulate the T12-related output signals with a T13 PWM.
In order to decouple COUT63 from the internal modulation, the compare state leading to
an active signal can be selected independently by bits T13IM and COUT63PS.
The last block of the data path is the Output Modulation block. Here, the modulation
source T13 and the trap functionality are combined and control the actual level of the
output pin COUT63 (see Figure 21-31):
•
•
The T13 related compare signal COUT63_O delivered by the T13 state selection
with the enable bit MODCTRH.ECT13O
The trap state TRPS with an individual enable bit TRPCTRH.TRPEN13
If the modulation input signal COUT63_O is enabled (ECT13O = 1) and is at passive
state, the modulated is also in passive state. If the modulation input is not enabled, the
output is in passive state.
If the Trap State is active (TRPS = 1), then the output enabled for the trap signal (by
TRPEN13 = 1) is set to the passive state.
The output of the modulation control block is connected to a level select block. It offers
the option to determine the actual output level of a pin, depending on the state of the
output line (decoupling of active/passive state and output polarity) as specified by the
Passive State Select bit PSLR.PSL63. If the modulated output signal is in the passive
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Capture/Compare Unit 6 (CCU6)
state, the level specified directly by PSL63 is output. If it is in the active state, the inverted
level of PSL63 is output. This allows the user to adapt the polarity of an active output
signal to the connected circuitry.
The PSL63 bit has a shadow register to allow for updates with the T13 shadow transfer
signal (T13_ST) without undesired pulses on the output lines. A read action returns the
actually used value, whereas a write action targets the shadow bit. Providing a shadow
register for the PSL value as well as for other values related to the generation of the
PWM signal facilitates a concurrent update by software for all relevant parameters.
Trap Handling
Block
TRPS
TRPEN13
T13 Block
COUT63_O
Output
Modulation
COUT63
active
passive
ECT13O
Level
Selection
COUT63
PSL63
CCU6_MCA05545
Figure 21-31 T13 Output Modulation
21.4.5
T13 Shadow Register Transfer
A special shadow transfer signal (T13_ST) can be generated to facilitate updating the
period and compare values of the compare channel CC63 synchronously to the
operation of T13. Providing a shadow register for values defining one PWM period
facilitates a concurrent update by software for all relevant parameters. The next PWM
period can run with a new set of parameters. The generation of this signal is requested
by software via bit TCTR0H.STE13 (set by writing 1 to the write-only bit
TCTR4H.T13STR, cleared by writing 1 to the write-only bit TCTR4H.T13STD).
When signal T13_ST is active, a shadow register transfer is triggered with the next cycle
of the T13 clock. Bit STE13 is automatically cleared with the shadow register transfer.
A T13 shadow register transfer takes place (T13_ST active):
•
•
while timer T13 is not running (T13R = 0), or
STE13 = 1 and a Period-Match is detected while T13R = 1
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Capture/Compare Unit 6 (CCU6)
Read
Read
Read
Read
Period Register
T13PR
PSL63
CC63PS
T13IM
Period Shadow
Register T13PR
PSL63
Shadow
CC63PS
Shadow
T13IM
Shadow
Write
Write
Write
Write
Read
Compare Register
CC63R
T13_ST
Compare Shadow
Register CC63SR
Write
Read
CCU6_MCA05547
Figure 21-32 T13 Shadow Register Overview
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Capture/Compare Unit 6 (CCU6)
21.4.6
T13 related Registers
21.4.6.1 T13 Counter Register
The generation of the patterns for a single channel pulse width modulation (PWM) is
based on timer T13. The registers related to timer T13 can be concurrently updated (with
well-defined conditions) in order to ensure consistency of the PWM signal. T13 can be
synchronized to several timer T12 events.
Timer T13 only supports compare mode on its compare channel CC63.
Register T13 represents the counting value of timer T13. It can only be written while the
timer T13 is stopped. Write actions while T13 is running are not taken into account.
Register T13 can always be read by SW.
Timer T13 only supports edge-aligned mode (counting up).
T13L
Timer T13 Counter Register Low
RMAP: 0, PAGE: 3
7
6
5
(FCH)
4
Reset Value: 00H
3
2
1
0
T13CVL
rwh
Field
Bits
Type Description
T13CVL
[7:0]
rwh
Timer 13 Counter Value
This register represents the lower 8-bits of 16-bit
counter value of Timer13.
Note: While timer T13 is stopped, the internal clock divider is reset in order to ensure
reproducible timings and delays.
T13H
Timer T13 Counter Register High
RMAP: 0, PAGE: 3
7
6
5
(FDH)
4
Reset Value: 00H
3
2
1
0
T13CVH
rwh
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CCU6, V4.0
21-79
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
T13CVH
[7:0]
rwh
Timer 13 Counter Value
This register represents the upper 8-bits of 16-bit
counter value of Timer13.
Note: While timer T13 is stopped, the internal clock divider is reset in order to ensure
reproducible timings and delays.
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CCU6, V4.0
21-80
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.4.6.2 Period Register
The generation of the patterns for a single channel pulse width modulation (PWM) is
based on timer T13. The registers related to timer T13 can be concurrently updated (with
well-defined conditions) in order to ensure consistency of the PWM signal. T13 can be
synchronized to several timer T12 events.
Timer T13 only supports compare mode on its compare channel CC63.
Register T13 represents the counting value of timer T13. It can only be written while the
timer T13 is stopped. Write actions while T13 is running are not taken into account.
Register T13 can always be read by SW.
Timer T13 only supports edge-aligned mode (counting up).
T13PRL
Timer T13 Period Register Low
RMAP: 0, PAGE: 1
7
6
5
(9EH)
4
Reset Value: 00H
3
2
1
0
T13PVL
rwh
Field
Bits
Type Description
T13PVL
[7:0]
rwh
T13 Period Value
The value T13PV defines the lower 8-bits of counter
value for T13 leading to a period-match. When
reaching this value, the timer T13 is set to zero.
T13PRH
Timer T13 Period Register High
RMAP: 0, PAGE: 1
7
6
5
(9FH)
4
Reset Value: 00H
3
2
1
0
T13PVH
rwh
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CCU6, V4.0
21-81
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
T13PVH
[7:0]
rwh
User’s Manual
CCU6, V4.0
T13 Period Value
The value T13PV defines the upper 8-bits of counter
value for T13 leading to a period-match. When
reaching this value, the timer T13 is set to zero.
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Capture/Compare Unit 6 (CCU6)
21.4.6.3 Compare Register
Registers CC63RL/H is the actual compare register for T13. The values stored in
CC63RL/H is compared to the counter value of T13. The State Bit CC63ST is located in
register CMPSTATL.
CC63RL
Compare Register for T13 Low
RMAP: 0, PAGE: 1
7
6
5
(9AH)
4
Reset Value: 00H
3
2
1
0
CCVL
rh
Field
Bits
Type Description
CCVL
[7:0]
rh
Channel CC63 Compare Value
The bit field CCV contains the lower 8-bits value, that
is compared to the T13 counter value.
CC63RH
Compare Register for T13 High
RMAP: 0, PAGE: 1
7
6
5
(9BH)
4
Reset Value: 00H
3
2
1
0
CCVH
rh
Field
Bits
Type Description
CCVH
[7:0]
rh
Channel CC63 Compare Value
The bit field CCV contains the upper 8-bits value,
that is compared to the T13 counter value.
21.4.6.4 Compare Shadow Register
The register CC63RL/H can only be read by SW, the modification of the value is done
by a shadow register transfer from register CC63SRL/H. The corresponding shadow
register CC63SRL/H can be read and written by SW.
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CCU6, V4.0
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V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
CC63SRL
Compare Shadow Register for T13 Low
(9AH)
RMAP: 0, PAGE: 0
7
6
5
4
Reset Value: 00H
3
2
1
0
CCSL
rw
Field
Bits
Type Description
CCSL
[7:0]
rw
Shadow Register for Channel CC63 Compare
Value
The bit field contents of CCSL is transferred to the
lower 8-bits of bit field CCV during a shadow
transfer.
CC63SRH
Compare Shadow Register for T13 High
(9BH)
RMAP: 0, PAGE: 0
7
6
5
4
Reset Value: 00H
3
2
1
0
CCSH
rw
Field
Bits
Type Description
CCSH
[7:0]
rw
User’s Manual
CCU6, V4.0
Shadow Register for Channel CC63 Compare
Value
The bit field contents of CCSH is transferred to the
upper 8-bits of bit field CCV during a shadow
transfer.
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Capture/Compare Unit 6 (CCU6)
21.5
Trap Handling
The trap functionality permits the PWM outputs to react on the state of the input signal
CTRAP. This functionality can be used to switch off the power devices if the trap input
becomes active (e.g. to perform an emergency stop). The trap handling and the effect
on the output modulation are controlled by the bits in the trap control register TRPCTRL,
TRPCTRH. The trap flags TRPF and TRPS are located in register ISH and can be
set/cleared by SW by writing to registers ISSH and ISRH.
Figure 21-33 gives an overview on the trap function.
The Trap Flag TRPF monitors the trap input and initiates the entry into the Trap State.
The Trap State Bit TRPS determines the effect on the outputs and controls the exit of the
Trap State.
When a trap condition is detected (CTRAP = 0) and the input is enabled (TRPPEN = 1),
both, the Trap Flag TRPF and the Trap State Bit TRPS, are set to 1 (trap state active).
The output of the Trap State Bit TRPS leads to the Output Modulation Blocks (for T12
and for T13) and can there deactivate the outputs (set them to the passive state).
Individual enable control bits for each of the six T12-related outputs and the T13-related
output facilitate a flexible adaptation to the application needs.
There are a number of different ways to exit the Trap State. This offers SW the option to
select the best operation for the application. Exiting the Trap State can be done either
immediately when the trap condition is removed (CTRAP = 1 or TRPPEN = 0), or under
software control, or synchronously to the PWM generated by either Timer T12 or Timer
T13.
RTRPF
Trap
Entry / Exit
Control
CTRAP
TRPPEN
STRPF
TRM2
TRPF
T12_ZM
T13_ZM
Trap Exit
Synchronization
TRPS
To T12,
T13 Output
Modulation
TRM0/1
CCU6_MCB05541
Figure 21-33 Trap Logic Block Diagram
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CCU6, V4.0
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V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Clearing of TRPF is controlled by the mode control bit TRPM2. If TRPM2 = 0, TRPF is
automatically cleared by HW when CTRAP returns to the inactive level (CTRAP = 1) or
if the trap input is disabled (TRPPEN = 0). When TRPM2 = 1, TRPF must be reset by
SW after CTRAP has become inactive.
Clearing of TRPS is controlled by the mode control bits TRPM1 and TRPM0 (located in
the Trap Control Register TRPCTRL/H). A reset of TRPS terminates the Trap State and
returns to normal operation. There are three options selected by TRPM1 and TRPM0.
One is that the Trap State is left immediately when the Trap Flag TRPF is cleared,
without any synchronization to timers T12 or T13. The other two options facilitate the
synchronization of the termination of the Trap State to the count periods of either Timer
T12 or Timer T13. Figure 21-34 gives an overview on the associated operation.
T12 Count
T13 Count
TRPF
CTRAP active
TRPS
Sync. to T12
TRPS
Sync. to T13
TRPS
No sync.
CCU6_MCT05542
Figure 21-34 Trap State Synchronization (with TRM2 = 0)
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CCU6, V4.0
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V1.1, 2010-09
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Capture/Compare Unit 6 (CCU6)
21.6
Multi-Channel Mode
The Multi-Channel mode offers the possibility to modulate all six T12-related output
signals with one instruction. The bits in bit field MCMOUTL.MCMP are used to specify
the outputs that may become active. If Multi-Channel mode is enabled (bit
MODCTRL.MCMEN = 1), only those outputs may become active, that have a 1 at the
corresponding bit position in bit field MCMP.
This bit field has its own shadow bit field MCMOUTSL.MCMPS, that can be written by
software. The transfer of the new value in MCMPS to the bit field MCMP can be triggered
by, and synchronized to, T12 or T13 events. This structure permits the software to write
the new value, that is then taken into account by the hardware at a well-defined moment
and synchronized to a PWM signal. This avoids unintended pulses due to
unsynchronized modulation sources.
SWSYN
SWSEL
STRMCM
CM_CHE
CM_61
T12_PM
T12_OM
Switching
Synchronization
T12_ZM
T13_ZM
Switching
Event
Detection
Shadow Register
MCMOUTS.MCMPS
Shadow Transfer
MCM_ST
IDLE
set
T13_PM
CDIR
R
clear
STR
set
clear
Register
MCMOUT.MCMP
To Interrupt Control
T13_ST
T12_ST
T12/T13
Shadow
Transfer
Control
STE12U
T12 Output Modulation
STE12D
Outputs CC6x/COUT6x
STE13U
CCU6_MCB05535+
Figure 21-35 Multi-Channel Mode Block Diagram
Figure 21-35 shows the functional blocks for the Multi-Channel operation, controlled by
bit fields in register MCMCTR. The event that triggers the update of bit field MCMP is
chosen by SWSEL. In order to synchronize the update of MCMP to a PWM generated
by T12 or T13, bit field SWSYN allows the selection of the synchronization event leading
to the transfer from MCMPS to MCMP. Due to this structure, an update takes place with
a new PWM period. A reminder flag R is set when the selected switching event occurs
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Capture/Compare Unit 6 (CCU6)
(the event is not necessarily synchronous to the modulating PWM), and is cleared when
the transfer takes place. This flag can be monitored by software to check for the status
of this logic block. If the shadow transfer from MCMPS to MCMP takes place, bit
ISH.STR becomes set and an interrupt can be generated.
In addition to the Multi-Channel shadow transfer event MCM_ST, the shadow transfers
for T12 (T12_ST) and T13 (T13_ST) can be generated to allow concurrent updates of
applied duty cycles for T12 and/or T13 modulation and Multi-Channel patterns.
If it is explicitly desired, the update takes place immediately with the occurrence of the
selected event when the direct synchronization mode is selected. The update can also
be requested by software by writing to bit field MCMPS with the shadow transfer request
bit STRMCM = 1. The option to trigger an update by SW is possible for all settings of
SWSEL.
By using the direct mode and bit STRMCM = 1, the update takes place completely under
software control.
The event selection and synchronization options are summarized in Table 21-13 and
Table 21-14.
Table 21-13 Multi-Channel Mode Switching Event Selection
SWSEL
Selected Event (see register MCMCTR)
000B
No automatic event detection
001B
Correct Hall Event (CM_CHE) detected at input signals CCPOSx
without additional delay
010B
T13 Period-Match (T13_PM)
011B
T12 One-Match while counting down (T12_OM and CDIR = 1)
100B
T12 Compare Channel 1 Event while counting up (CM_61 and
CDIR = 0) to support the phase delay function by CC61 for block
commutation mode.
101B
T12 Period-Match while counting up (T12_PM and CDIR = 0)
110B, 111B
Reserved, no action
Table 21-14 Multi-Channel Mode Switching Synchronization
SWSYN
Synchronization Event (see register MCMCTR)
00B
Direct Mode: the trigger event directly causes the shadow transfer
01B
T13 Zero-Match (T13_ZM),
the MCM shadow transfer is synchronized to a T13 PWM
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CCU6, V4.0
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V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Table 21-14 Multi-Channel Mode Switching Synchronization (cont’d)
SWSYN
Synchronization Event (see register MCMCTR)
10B
T12 Zero-Match (T12_ZM),
the MCM shadow transfer is synchronized to a T12 PWM
11B
Reserved, no action
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CCU6, V4.0
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V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.7
Hall Sensor Mode
For Brushless DC-Motors in block commutation mode, the Multi-Channel Mode has
been introduced to provide efficient means for switching pattern generation. These
patterns need to be output in relation to the angular position of the motor. For this, usually
Hall sensors or Back-EMF sensing are used to determine the angular rotor position. The
CCU6 provides three inputs, CCPOS0, CCPOS1, and CCPOS2, that can be used as
inputs for the Hall sensors or the Back-EMF detection signals.
There is a strong correlation between the motor position and the output modulation
pattern. When a certain position of the motor has been reached, indicated by the
sampled Hall sensor inputs (the Hall pattern), the next, pre-determined Multi-Channel
Modulation pattern has to be output. Because of different machine types, the modulation
pattern for driving the motor can vary. Therefore, it is wishful to have a wide flexibility in
defining the correlation between the Hall pattern and the corresponding Modulation
pattern. Furthermore, a hardware mechanism significantly reduces the CPU for blockcommutation.
The CCU6 offers the flexibility by having a register containing the currently assumed Hall
pattern (CURH), the next expected Hall pattern (EXPH) and the corresponding output
pattern (MCMP). A new Modulation pattern is output when the sampled Hall inputs
match the expected ones (EXPH). To detect the next rotation phase (segment for block
commutation), the CCU6 monitors the Hall inputs for changes. When the next expected
Hall pattern is detected, the next corresponding Modulation pattern is output.
To increase for noise immunity (to a certain extend), the CCU6 offers the possibility to
introduce a sampling delay for the Hall inputs. Some changes of the Hall inputs are not
leading to the expected Hall pattern, because they are only short spikes due to noise.
The Hall pattern compare logic compares the Hall inputs to the next expected pattern
and also to the currently assumed pattern to filter out spikes.
For the Hall and Modulation output patterns, a double-register structure is implemented.
While register MCMOUTL, MCMOUTH holds the actually used values, its shadow
register MCMOUTSL, MCMOUTSH can be loaded by software from a pre-defined table,
holding the appropriate Hall and Modulation patterns for the given motor control.
A transfer from the shadow register into register MCMOUT can take place when a
correct Hall pattern change is detected. Software can then load the next values into
register MCMOUTS. It is also possible by software to force a transfer from MCMOUTS
into MCMOUT.
Note: The Hall input signals CCPOSx and the CURH and EXPH bit fields are arranged
in the following order:
CCPOS0 corresponds to CURH.0 (LSB) and EXPH.0 (LSB)
CCPOS1 corresponds to CURH.1 and EXPH.1
CCPOS2 corresponds to CURH.2 (MSB) and EXPH.2 (MSB)
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CCU6, V4.0
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V1.1, 2010-09
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Capture/Compare Unit 6 (CCU6)
21.7.1
Hall Pattern Evaluation
The Hall sensor inputs CCPOSx can be permanently monitored via an edge detection
block (with the module clock fCC6). In order to suppress spikes on the Hall inputs due to
noise in rugged inverter environment, two optional noise filtering methods are supported
by the Hall logic (both methods can be combined).
•
•
Noise filtering with delay:
For this function, the mode control bit fields MSEL6x for all T12 compare channels
must be programmed to 1000B and DBYP = 0. The selected event triggers DeadTime Counter 0 to generate a programmable delay (defined by bit field DTM). When
the delay has elapsed, the evaluation signal HCRDY becomes activated.
Output modulation with T12 PWM signals is not possible in this mode.
Noise filtering by synchronization to PWM:
The Hall inputs are not permanently monitored by the edge detection block, but
samples are taken only at defined points in time during a PWM period. This can be
used to sample the Hall inputs when the switching noise (due to PWM) does not
disturb the Hall input signals.
CCPOS 0..2
If neither the delay function of Dead-Time Counter 0 is not used for the Hall pattern
evaluation nor the Hall mode for Brushless DC-Drive control is enabled, the timer T12
block is available for PWM generation and output modulation.
Hall
Compare
Logic
Hall
Inputs
HCRDY
Hall Pattern Evaluation
Edge
Detect
fCC6
Dead-Time
Counter 0
CM_63
T13_PM
T12_PM
Event
Selection
Delay
Bypass
CDIR
T12_OM
CM_61
HSYNC
DBYP
CCU6_MCB05553
Figure 21-36 Hall Pattern Evaluation
If the evaluation signal HCRDY (Hall Compare Ready, see Figure 21-37) becomes
activated, the Hall inputs are sampled and the Hall compare logic starts the evaluation
of the Hall inputs.
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CCU6, V4.0
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V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Figure 21-36 illustrates the events for Hall pattern evaluation and the noise filter logic,
Table 21-15 summarizes the selectable trigger input signals.
Table 21-15 Hall Sensor Mode Trigger Event Selection
HSYNC
Selected Event (see register T12MSELL, T12MSELH)
000B
Any edge at any of the inputs CCPOSx, independent from any PWM
signal (permanent check).
001B
A T13 Compare-Match (CM_63).
010B
A T13 Period-Match (T13_PM).
011B
Hall sampling triggered by HW sources is switched off.
100B
A T12 Period-Match while counting up (T12_PM and CDIR = 0).
101B
A T12 One-Match while counting down (T12_OM and CDIR = 1).
110B
A T12 Compare-Match of compare channel CC61 while counting up
(CM_61 and CDIR = 0).
111B
A T12 Compare-Match of compare channel CC61 while counting down
(CM_61 and CDIR = 1).
User’s Manual
CCU6, V4.0
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V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.7.2
Hall Pattern Compare Logic
Figure 21-37 gives an overview on the double-register structure and the pattern
compare logic. Software writes the next modulation pattern (MCMPS) and the
corresponding current (CURHS) and expected (EXPHS) Hall patterns into the shadow
register MCMOUTS. Register MCMOUT holds the actually used values CURH and
EXPH. The modulation pattern MCMP is provided to the T12 Output Modulation block.
The current (CURH) and expected (EXPH) Hall patterns are compared to the sampled
Hall sensor inputs (visible in register CMPSTATL, CMPSTATH). Sampling of the inputs
and the evaluation of the comparator outputs is triggered by the evaluation signal
HCRDY (Hall Compare Ready), that is detailed in the next section.
Multi-Channel Mode Logic
SW Write
SW Write
CURHS
EXPHS
HP_ST
CURH
Hall Pattern
Evaluation
SW Write
MCMPS
MCM_ST
EXPH
HCRDY
MCMP
clear
T12 Output
Modulation
Sample
CCPOS0..2
Hall
Inputs
CM_CHE
Pattern Compare
CM_WHE
IDLE
Hall Compare Logic
CCU6_MCA05536
Figure 21-37 Hall Pattern Compare Logic
•
•
•
If the sampled Hall pattern matches the value programmed in CURH, the detected
transition was a spike (no Hall event) and no further actions are necessary.
If the sampled Hall pattern matches the value programmed in EXPH, the detected
transition was the expected event (correct Hall event CM_CHE) and the MCMP value
has to change.
If the sampled Hall pattern matches neither CURH nor EXPH, the transition was due
to a major error (wrong Hall event CM_CWE) and can lead to an emergency shut
down (IDLE).
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Capture/Compare Unit 6 (CCU6)
At every correct Hall event (CM_CHE), the next Hall patterns are transferred from the
shadow register MCMOUTS into MCMOUT (Hall pattern shadow transfer HP_ST), and
a new Hall pattern with its corresponding output pattern can be loaded (e.g. from a
predefined table in memory) by software into MCMOUTS. For the Modulation patterns,
signal MCM_ST is used to trigger the transfer.
Loading this shadow register can also be done by writing MCMOUTS.STRHP = 1 (for
EXPH and CURH) or MCMOUTS.STRMCMP = 1 (for MCMP).
21.7.3
Hall Mode Flags
Depending on the Hall pattern compare operation, a number of flags are set in order to
indicate the status of the module and to trigger further actions and interrupt requests.
Flag ISH.CHE (Correct Hall Event) is set by signal CM_CHE when the sampled Hall
pattern matches the expected one (EXPH). This flag can also be set by SW by setting
bit ISSH.SCHE = 1. If enabled by bit IENH.ENCHE = 1, the set signal for CHE can also
generate an interrupt request to the CPU. Bit field INPL.INPCHE defines which service
request output becomes activated in case of an interrupt request.To clear flag CHE, SW
needs to write ISRH.RCHE = 1.
Flag IS.WHE indicates a Wrong Hall Event. Its handling for flag setting and resetting as
well as interrupt request generation are similar to the mechanism for flag CHE.
The implementation of flag STR is done in the same way as for CHE and WHE. This flag
is set by HW by the shadow transfer signal MCM_ST (see also Figure 21-35).
Please note that for flags CHE, WHE, and STR, the interrupt request generation is
triggered by the set signal for the flag. That means, a request can be generated even if
the flag is already set. There is no need to clear the flag in order to enable further
interrupt requests.
The implementation for the IDLE flag is different. It is set by HW through signal CM_WHE
if enabled by bit ENIDLE. Software can also set the flag via bit SIDLE. As long as bit IDLE
is set, the modulation pattern field MCMP is cleared to force the outputs to the passive
state. Flag IDLE must be cleared by software by writing RIDLE = 1 in order to return to
normal operation. To fully restart from IDLE mode, the transfer requests for the bit fields
in register MCMOUTS to register MCMOUT have to be initiated by software via bits
STRMCM and STRHP in register MCMOUTS. In this way, the release from IDLE mode
is under software control, but can be performed synchronously to the PWM signal.
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Capture/Compare Unit 6 (CCU6)
Clear
RCHE
SCHE
CHE
INPCHE
To SR0
Set
_
>1
To SR1
To SR2
CM_CHE
To SR3
ENCHE
Hall Compare
Logic
CM_WHE
Clear
RWHE
SWHE
WHE
INPERR
To SR0
Set
_
>1
To SR1
To SR2
To SR3
ENWHE
ENIDLE
SIDLE
_
>1
Set
IDLE
Clear
MCMP
Clear
RIDLE
CCU6_MCA05540
Figure 21-38 Hall Mode Flags
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CCU6, V4.0
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V1.1, 2010-09
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Capture/Compare Unit 6 (CCU6)
21.7.4
Hall Mode for Brushless DC-Motor Control
The CCU6 provides a mode for the Timer T12 Block especially targeted for convenient
control of block commutation patterns for Brushless DC-Motors. This mode is selected
by setting all T12MSELL/T12MSELH.MSEL6x bit fields of the three T12 Channels to
1000B.
In this mode, illustrated in Figure 21-39, channel CC60 is placed in capture mode to
measure the time elapsed between the last two correct Hall events, channel CC61 in
compare mode to provide a programmable phase delay between the Hall event and the
application of a new PWM output pattern, and channel CC62 also in compare mode as
first time-out criterion. A second time-out criterion can be built by the T12 period match
event.
fT12
Counter Register
T12
Clear
Hall Compare
Logic
CM_CHE
CM_61
Capture Register
CC60R
Comp.
=?
Comp.
=?
Compare Register
CC61R
Compare Register
CC62R
Compare Shadow
Register CC61SR
Compare Shadow
Register CC62SR
CM_62
CCU6_MCA05538
Figure 21-39 T12 Block in Hall Sensor Mode
The signal CM_CHE from the Hall compare logic is used to transfer the new compare
values from the shadow registers CC6xSR into the actual compare registers CC6xR,
performs the shadow transfer for the T12 period register, to capture the current T12
contents into register CC60R, and to clear T12.
Note: In this mode, the shadow transfer signal T12_ST is not generated. Not all shadow
bits, such as the PSLy bits, will be transferred to their main registers. To program
the main registers, SW needs to write to these registers while Timer T12 is
stopped. In this case, a SW write actualizes both registers.
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CCU6, V4.0
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V1.1, 2010-09
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Capture/Compare Unit 6 (CCU6)
CC62 Compare
for Time-Out
Hall Event captures
and resets T12
CC62 Comp.
T12 Count
CC61 Compare
for Phase Delay
CC61 Comp.
0000 H
CCPOS0
1
1
1
0
0
CCPOS1
0
0
1
1
1
CCPOS2
1
0
0
0
1
CURH
= 101
= 001
= 011
= 010
= 110
EXPH
= 001
= 011
= 010
= 110
= 100
MCMP
Phase Delay
CC6x
COUT6y
CCU6_MCT05539
Figure 21-40 Brushless DC-Motor Control Example (all MSEL6x = 1000B)
After the detection of an expected Hall pattern (CM_CHE active), the T12 count value is
captured into channel CC60 (representing the actual rotor speed by measuring the
elapsed time between the last two correct Hall events), and T12 is reset. When the timer
reaches the compare value in channel CC61, the next multi-channel state is switched by
triggering the shadow transfer of bit field MCMP. This trigger event can be combined with
the synchronization of the next multi-channel state to the PWM source (to avoid spikes
on the output lines, see Section 21.6). This compare function of channel CC61 can be
used as a phase delay from the position sensor input signals to the switching of the
output signals, that is necessary if a sensorless back-EMF technique or Hall sensors are
used. The compare value in channel CC62 can be used as a time-out trigger (interrupt),
indicating that the actual motor speed is far below the desired destination value. An
abnormal load change can be detected with this feature and PWM generation can be
disabled.
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XC83x
Capture/Compare Unit 6 (CCU6)
21.8
Modulation Control Registers
21.8.1
Modulation Control
This register contains bits enabling the modulation of the corresponding output signal by
PWM pattern generated by the timers T12 and T13. Furthermore, the multi-channel
mode can be enabled as additional modulation source for the output signals.
MODCTRL
Modulation Control Register Low
RMAP: 0, PAGE: 2
5
(FCH)
4
Reset Value: 00H
7
6
3
2
MCMEN
0
T12MODEN
rw
r
rw
1
0
Field
Bits
Type Description
T12MODEN
[5:0]
rw
T12 Modulation Enable
These bits enable the modulation of the
corresponding output signal by a PWM pattern
generated by timer T12.
T12MODEN0 = MODCTR.0 for output CC60
T12MODEN1 = MODCTR.1 for output COUT60
T12MODEN2 = MODCTR.2 for output CC61
T12MODEN3 = MODCTR.3 for output COUT61
T12MODEN4 = MODCTR.4 for output CC62
T12MODEN5 = MODCTR.5 for output COUT62
The modulation of the corresponding output
0B
signal by a T12 PWM pattern is disabled.
The modulation of the corresponding output
1B
signal by a T12 PWM pattern is enabled.
MCMEN
7
rw
Multi-Channel Mode Enable
0B
The modulation of the corresponding output
signal by a multi-channel pattern according to
bit field MCMOUT is disabled.
The modulation of the corresponding output
1B
signal by a multi-channel pattern according to
bit field MCMOUT is enabled.
0
6
r
reserved;
returns 0 if read; should be written with 0;
User’s Manual
CCU6, V4.0
21-98
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
MODCTRH
Modulation Control Register High
RMAP: 0, PAGE: 2
5
(FDH)
4
Reset Value: 00H
7
6
3
2
ECT13O
0
T13MODEN
rw
r
rw
1
0
Field
Bits
Type Description
T13MODEN
[5:0]
rw
T13 Modulation Enable
These bits enable the modulation of the
corresponding output signal by the PWM pattern
CC63_O generated by timer T13.
T13MODEN0 = MODCTR.8 for output CC60
T13MODEN1 = MODCTR.9 for output COUT60
T13MODEN2 = MODCTR.10 for output CC61
T13MODEN3 = MODCTR.11 for output COUT61
T13MODEN4 = MODCTR.12 for output CC62
T13MODEN5 = MODCTR.13 for output COUT62
The modulation of the corresponding output
0B
signal by a T13 PWM pattern is disabled.
The modulation of the corresponding output
1B
signal by a T13 PWM pattern is enabled.
ECT13O
7
rw
Enable Compare Timer T13 Output
0B
The output COUT63 is in the passive state.
The output COUT63 is enabled for the PWM
1B
signal generated by T13.
0
6
r
reserved;
returns 0 if read; should be written with 0;
User’s Manual
CCU6, V4.0
21-99
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.8.2
Trap Control Register
The register TRPCTRL/H controls the trap functionality. It contains independent enable
bits for each output signal and control bits to select the behavior in case of a trap
condition. The trap condition is a low level on the CTRAP input pin, that is monitored
(inverted level) by bit ISH.TRPF. While TRPF=1 (trap input active), the trap state bit
IS.TRPS is set to 1.
TRPCTRL
Trap Control Register Low
RMAP: 0, PAGE: 2
7
6
5
(FEH)
4
3
2
1
0
0
TRPM2
TRPM1
TRPM0
r
rw
rw
rw
Field
Bits
Type Description
TRPM1,
TRPM0
1,
0
rw
User’s Manual
CCU6, V4.0
Reset Value: 00H
Trap Mode Control Bits 1, 0
These two bits define the behavior of the selected
outputs when leaving the trap state after the trap
condition has become inactive again.
A synchronization to the timer driving the PWM
pattern avoids unintended pulses when leaving the
trap state.
The combination [TRPM1, TRPM0] leads to:
00B The trap state is left (return to normal
operation) after TRPF has become 0 again
when a zero-match of T12 (while counting up)
is detected (synchronization to T12).
01B The trap state is left (return to normal
operation) after TRPF has become 0 again
when a zero-match of T13 is detected
(synchronization to T13).
10B reserved
11B The trap state is left (return to normal
operation) immediately after TRPF has
become 0 again without any synchronization
to T12 or T13.
21-100
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
TRPM2
2
rw
Trap Mode Control Bit 2
This bit defines how the trap flag TRPF can be
cleared after the trap input condition (CTRAP = 0
and TRPPEN = 1) is no longer valid (either by
CTRAP = 1 or by TRPPEN = 0).
Automatic Mode:
0B
Bit TRPF is cleared by HW if the trap input
condition is no longer valid.
Manual Mode:
1B
Bit TRPF stays 0 after the trap input condition
is no longer valid. It has to be cleared by SW
by writing ISR.RTRPF = 1.
0
[7:3]
r
reserved;
returns 0 if read; should be written with 0;
TRPCTRH
Trap Control Register High
RMAP: 0, PAGE: 2
4
Reset Value: 00H
7
6
TRPPEN
TRPEN13
TRPEN
rw
rw
rw
User’s Manual
CCU6, V4.0
5
(FFH)
3
21-101
2
1
0
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
TRPEN
[5:0]
rw
Trap Enable Control
Setting a bit enables the trap functionality for the
following corresponding output signals:
TRPEN0 = TRPCTR.8 for output CC60
TRPEN1 = TRPCTR.9 for output COUT60
TRPEN2 = TRPCTR.10 for output CC61
TRPEN3 = TRPCTR.11 for output COUT61
TRPEN4 = TRPCTR.12 for output CC62
TRPEN5 = TRPCTR.13 for output COUT62
The trap functionality of the corresponding
0B
output signal is disabled. The output state is
independent from bit IS.TRPS.
The trap functionality of the corresponding
1B
output signal is enabled. The output state is
set to the passive while IS.TRPS=1.
TRPEN13
6
rw
Trap Enable Control for Timer T13
The trap functionality for output COUT63 is
0B
disabled. The output state is independent from
bit IS.TRPS.
The trap functionality for output COUT63 is
1B
enabled. The output state is set to the passive
while IS.TRPS=1.
TRPPEN
7
rw
Trap Pin Enable
This bit enables the input (pin) function for the trap
generation. An interrupt can only be generated if a
falling edge is detected at pin CTRAP while
TRPPEN = 1.
The CCU6 trap functionality based on the input
0B
CTRAP is disabled. A CCU6 trap can only be
generated by SW by setting bit TRPF.
The CCU6 trap functionality based on the input
1B
CTRAP is enabled. A CCU6 trap can be
generated by SW by setting bit TRPF or by
CTRAP=0.
User’s Manual
CCU6, V4.0
21-102
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.8.3
Passive State Level Register
Register PSLR defines the passive state level of the PWM outputs of the module. The
passive state level is the value that is driven during the passive state of the output.
During the active state, the corresponding output pin drives the active state level, that is
the inverted passive state level. The passive state level permits to adapt the driven
output levels to the driver polarity (inverted, not inverted) of the connected power stage.
The bits in this register have shadow bit fields to permit a concurrent update of all PWMrelated parameters (bit field PSL is updated with T12_ST, whereas PSL63 is updated
with T13_ST). The actually used values can be read (attribute “rh”), whereas the shadow
bits can only be written (attribute “w”).
PSLR
Passive State Level Register
RMAP: 0, PAGE: 2
5
(A6H)
4
Reset Value: 00H
7
6
3
2
PSL63
0
PSL
rwh
r
rwh
1
0
Field
Bits
Type Description
PSL
[5:0]
rwh
Compare Outputs Passive State Level
These bits define the passive level driven by the
module outputs during the passive state.
PSL0 = PSLR.0 for output CC60
PSL1 = PSLR.1 for output COUT60
PSL2 = PSLR.2 for output CC61
PSL3 = PSLR.3 for output COUT61
PSL4 = PSLR.4 for output CC62
PSL5 = PSLR.5 for output COUT62
The passive level is 0.
0B
The passive level is 1.
1B
PSL63
7
rwh
Passive State Level of Output COUT63
This bit defines the passive level driven by the
module output COUT63 during the passive state.
The passive level is 0.
0B
1B
The passive level is 1.
0
6
r
reserved;
returns 0 if read; should be written with 0;
User’s Manual
CCU6, V4.0
21-103
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.8.4
Multi-Channel Mode Registers
Register MCMCTR contains control bits for the multi-channel functionality.
MCMCTR
Multi-Channel Mode Control Register (A7H)
RMAP: 0, PAGE: 2
7
6
5
4
Reset Value: 00H
3
2
1
0
SWSYN
0
SWSEL
r
rw
r
rw
Field
Bits
Type Description
SWSEL
[2:0]
rw
User’s Manual
CCU6, V4.0
0
Switching Selection
Bit field SWSEL selects one of the following trigger
request sources (next multi-channel event) for the
shadow transfer MCM_ST from MCMPS to MCMP.
The trigger request is stored in the reminder flag R
until the shadow transfer is done and flag R is
cleared automatically with the shadow transfer. The
shadow transfer takes place synchronously with an
event selected in bit field SWSYN.
000B No trigger request will be generated
001B Correct Hall pattern detected (CM_CHE)
010B T13 period-match detected (while counting up)
011B T12 one-match (while counting down)
100B T12 channel 1 compare-match detected
(phase delay function)
101B T12 period match detected (while counting up)
110B reserved, no trigger request will be generated
111B reserved, no trigger request will be generated
21-104
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
SWSYN
[5:4]
rw
Switching Synchronization
Bit field SWSYN defines the synchronization
mechanism of the shadow transfer event MCM_ST if
it has been requested before (flag R set by an event
selected by SWSEL) and if MCMEN = 1. This
feature permits the synchronization of the outputs to
the PWM source, that is used for modulation (T12 or
T13).
00B Direct; the trigger event immediately leads to
the shadow transfer
01B A T13 zero-match triggers the shadow transfer
10B A T12 zero-match (while counting up) triggers
the shadow transfer
11B reserved; no action
0
[7:6],
3
r
reserved;
returns 0 if read; should be written with 0;
User’s Manual
CCU6, V4.0
21-105
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Register MCMOUTSL/H contains bits used as pattern input for the multi-channel mode
and the Hall mode. This register is a shadow register (that can be read and written) for
register MCMOUT, indicating the currently active signals.
MCMOUTSL
Multi-Channel Mode Output Shadow Register Low
(9EH)
RMAP: 0, PAGE: 0
7
6
5
4
3
STRMCM
0
MCMPS
w
r
rw
Reset Value: 00H
2
1
0
Field
Bits
Type Description
MCMPS
[5:0]
rw
Multi-Channel PWM Pattern Shadow
Bit field MCMPS is the shadow bit field for bit field
MCMP. The multi-channel shadow transfer is
triggered by MCM_ST according to the transfer
conditions defined by register MCMCTR.
STRMCM
7
w
Shadow Transfer Request for MCMPS
Writing STRMCM = 1 leads to an immediate
activation of MCM_ST to update bit field MCMP by
the value of MCMPS.
When read, this bit always delivers 0.
No action.
0B
1B
Bit field MCMP is updated.
0
6
r
reserved;
returns 0 if read; should be written with 0;
MCMOUTSH
Multi-Channel Mode Output Shadow Register High
(9FH)
RMAP: 0, PAGE: 0
7
6
STRHP
0
CURHS
EXPHS
rw
r
rw
rw
User’s Manual
CCU6, V4.0
5
4
3
Reset Value: 00H
21-106
2
1
0
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
EXPHS
[2:0]
rw
Expected Hall Pattern Shadow
Bit field EXPHS is the shadow bit field for bit field
EXPH. The shadow transfer takes place when a
correct Hall event is detected (CM_CHE).
CURHS
[5:3]
rw
Current Hall Pattern Shadow
Bit field CURHS is the shadow bit field for bit field
CURH. The shadow transfer takes place when a
correct Hall event is detected (CM_CHE).
STRHP
7
w
Shadow Transfer Request for the Hall Pattern
Writing STRHP = 1 leads to an immediate activation
of HP_ST to update bit fields EXPH and CURH by
EXPHS and CURHS.
When read, this bit always delivers 0.
No action.
0B
Bit fields EXPH and CURH are updated.
1B
0
6
r
reserved;
returns 0 if read; should be written with 0;
MCMOUTL
Multi-Channel Mode Output Register Low
(9AH)
RMAP: 0, PAGE: 3
7
6
0
R
MCMP
r
rh
rw
User’s Manual
CCU6, V4.0
5
4
Reset Value: 00H
3
21-107
2
1
0
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
MCMP
[5:0]
rh
Multi-Channel PWM Pattern
Bit field MCMP defines the output pattern for the
multi-channel mode. If this mode is enabled by
MODCTR.MCMEN = 1, the output state of all T12
related PWM outputs can be modified.
This bit field is 0 while IS.IDLE = 1.
MCMP0 = MCMOUT.0 for output CC60
MCMP1 = MCMOUT.1 for output COUT60
MCMP2 = MCMOUT.2 for output CC61
MCMP3 = MCMOUT.3 for output COUT61
MCMP4 = MCMOUT.4 for output CC62
MCMP5 = MCMOUT.5 for output COUT62
The output is set to the passive state. A PWM
0B
generated by T12 or T13 are not taken into
account.
The output can be in the active state,
1B
depending on the enabled PWM modulation
signals generated by T12, T13 and the trap
state.
R
6
rh
Reminder Flag
This flag indicates that the shadow transfer from
MCMPS to MCMP has been requested by the
selected trigger source. It is cleared when the
shadow transfer takes place or while MCMEN=0.
A shadow transfer MCM_ST is not requested.
0B
A shadow transfer MCM_ST is requested, but
1B
has not yet been executed, because the
selected synchronization condition has not yet
occurred.
0
6
r
reserved;
returns 0 if read; should be written with 0;
User’s Manual
CCU6, V4.0
21-108
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
MCMOUTH
Multi-Channel Mode Output Register High
(9BH)
RMAP: 0, PAGE: 3
7
6
5
4
Reset Value: 00H
3
2
1
0
CURH
EXPH
r
rw
rw
0
Field
Bits
Type Description
EXPH
[10:8]
rh
Expected Hall Pattern
Bit field EXPH is updated by a shadow transfer
HP_ST from bit field EXPHS.
If HCRDY = 1, EXPH is compared to the sampled
CCPOSx inputs in order to detect the occurrence of
the next desired (=expected) hall pattern or a wrong
pattern.
If the sampled hall pattern at the hall input pins is
equal to bit field EXPH, a correct Hall event has been
detected (CM_CHE).
CURH
[13:11]
rh
Current Hall Pattern
Bit field CURH is updated by a shadow transfer
HP_ST from bit field CURHS.
If HCRDY = 1, CURH is compared to the sampled
CCPOSx inputs in order to detect a spike.
If the sampled Hall pattern at the Hall input pins is
equal to bit field CURH, no Hall event has been
detected.
If the sampled Hall input pattern is neither equal to
CURH nor equal to EXPH, the Hall event was not the
desired one and may be due to a fatal error (e.g.
blocked rotor, etc.). In this case, a wrong Hall event
has been detected (CM_WHE).
0
[7:6]
r
reserved;
returns 0 if read; should be written with 0;
User’s Manual
CCU6, V4.0
21-109
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.9
Interrupt Handling
This section describes the interrupt handling of the CCU6 module.
21.9.1
Interrupt Structure
The HW interrupt event or the SW setting of the corresponding interrupt set bit (in
register ISS) sets the event indication flags (in register IS) and can trigger the interrupt
generation. The interrupt pulse is generated independently from the interrupt status flag
in register IS (it is not necessary to clear the related status bit to be able to generate
another interrupt). The interrupt flag can be cleared by SW by writing to the
corresponding bit in register ISR.
If enabled by the related interrupt enable bit in register IEN, an interrupt pulse can be
generated on one of the four service request outputs (SR0 to SR3) of the module. If more
than one interrupt source is connected to the same interrupt node pointer (in register
INP), the requests are logically OR-combined to one common service request output
(see Figure 21-41).
SW Requests
Clear
Interrupt
Clear
Interrupt
Status
Set
Interrupt
Enable
Interrupt
Node Pointer
Set Interrupt
To SR0
_
>1
To SR1
To SR2
To SR3
HW Interrupt
Event
CCU6_MCA05549
Figure 21-41 General Interrupt Structure
The available interrupt events in the CCU6 are shown in Figure 21-42.
User’s Manual
CCU6, V4.0
21-110
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
T12_PM
T12 Counter
T12_OM
CDIR
T12 Capture
Compare
Channels CC6x
T13 Counter
T13 Compare
Channel CC63
SR0
Interrupt Request
Reg. CC6x_0IC
SR1
Interrupt Request
Reg. CC6x_1IC
SR2
Interrupt Request
Reg. CC6x_2IC
SR3
Interrupt Request
Reg. CC6x_3IC
CC6x_R
CC6x_F
T13_PM
CM_63
Interrupt
Control Logic
Interrupt Set
Register ISS
Interrupt Status
Register IS
Multi-Channel
Mode Logic
STR
Interrupt Reset
Register ISR
CM_CHE
Hall Compare
Logic
CM_WHE
Trap Handling
TRPS
Interrupt Enable
Register IEN
TRPF
Node Pointer
Register INP
CCU6_MCA05548
Figure 21-42 Interrupt Sources and Events
User’s Manual
CCU6, V4.0
21-111
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.9.2
Interrupt Registers
21.9.2.1 Interrupt Status Register
Register ISL/H contains the individual interrupt request bits. This register can only be
read, write actions have no impact on the contents of this register. The SW can set or
clear the bits individually by writing to the registers ISSL/H (to set the bits) or to register
ISRL/H (to clear the bits).
The interrupt generation is independent from the value of the bits in register ISL/H, e.g.
the interrupt will be generated (if enabled) even if the corresponding bit is already set.
The trigger for an interrupt generation is the detection of a set condition (by HW or SW)
for the corresponding bit in register ISL/H.
In compare mode (and hall mode), the timer-related interrupts are only generated while
the timer is running (T1xR=1). In capture mode, the capture interrupts are also generated
while the timer T12 is stopped.
Note: Not all bits in register ISL/H can generate an interrupt. Other status bits have been
added, that have a similar structure for their set and clear actions. It is
recommended that SW checks the interrupt bits bit-wisely (instead of common OR
over the bits).
ISL
Interrupt Status Register Low
RMAP: 0, PAGE: 3
(9CH)
Reset Value: 00H
7
6
5
4
3
2
1
0
T12PM
T12OM
ICC62F
ICC62R
ICC61F
ICC61R
ICC60F
ICC60R
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
ICC60R,
ICC61R,
ICC62R
0,
2,
4
rh
User’s Manual
CCU6, V4.0
Capture, Compare-Match Rising Edge Flag
This bit indicates that event CC6x_R has been
detected. This event occurs in compare mode when
a compare-match is detected while T12 is counting
up (CM_6x and CDIR = 0) and in capture mode
when a rising edge is detected at the related input
CC6xIN.
The event has not yet been detected.
0B
The event has been detected.
1B
21-112
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
ICC60F,
ICC61F,
ICC62F
1,
3,
5
rh
Capture, Compare-Match Falling Edge Flag
This bit indicates that event CC6x_F has been
detected. This event occurs in compare mode when
a compare-match is detected while T12 is counting
down (CM_6x and CDIR = 1) and in capture mode
when a falling edge is detected at the related input
CC6xIN.
The event has not yet been detected.
0B
The event has been detected.
1B
T12OM
6
rh
Timer T12 One-Match Flag
This bit indicates that a timer T12 one-match while
counting down (T12_OM and CDIR = 1) has been
detected.
The event has not yet been detected.
0B
1B
The event has been detected.
T12PM
7
rh
Timer T12 Period-Match Flag
This bit indicates that a timer T12 period-match while
counting up (T12_PM and CDIR = 0) has been
detected.
0B
The event has not yet been detected.
The event has been detected.
1B
ISH
Interrupt Status Register High
RMAP: 0, PAGE: 3
(9DH)
Reset Value: 00H
7
6
5
4
3
2
1
0
STR
IDLE
WHE
CHE
TRPS
TRPF
T13PM
T13CM
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
T13CM
0
rh
User’s Manual
CCU6, V4.0
Timer T13 Compare-Match Flag
This bit indicates that a timer T13 compare-match
(CM_63) has been detected.
0B
The event has not yet been detected.
1B
The event has been detected.
21-113
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
T13PM
1
rh
Timer T13 Period-Match Flag
This bit indicates that a timer T13 period-match
(T13_PM) has been detected.
The event has not yet been detected.
0B
1B
The event has been detected.
TRPF
2
rh
Trap Flag
This bit indicates if a trap condition (input CTRAP = 0
or by SW) is / has been detected. If TRM2= 0, it
becomes cleared automatically if CTRAP = 1 or
TRPPEN = 0, whereas if TRM2 = 1, it has to be
cleared by writing RTRPF = 1.
The trap condition has not been detected.
0B
The trap condition is / has been detected.
1B
TRPS
3
rh
Trap State1)
This bit indicates the actual trap state. It is set if
TRPF = 1 and becomes cleared according to the
mode selected in register TRPCTR.
The trap state is not active.
0B
The trap state is active.
1B
CHE
4
rh
Correct Hall Event
This bit indicates that a correct Hall event (CM_CHE)
has been detected.
The event has not yet been detected.
0B
The event has been detected.
1B
WHE
5
rh
Wrong Hall Event
This bit indicates that a wrong Hall event (CM_WHE)
has been detected.
The event has not yet been detected.
0B
The event has been detected.
1B
IDLE
6
rh
IDLE State
If enabled by ENIDLE = 1, this bit is set together with
bit WHE and it has to be cleared by SW.
No action.
0B
Bit field MCMP is cleared, the selected outputs
1B
are set to passive state.
User’s Manual
CCU6, V4.0
21-114
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
STR
7
rh
Multi-Channel Mode Shadow Transfer Request
This bit indicates that a shadow transfer from
MCMPS to MCMP (MCM_ST) has taken place.
The event has not yet been detected.
0B
1B
The event has been detected.
1) During the trap state, the selected outputs are set to the passive state. The logic level driven during the passive
state is defined by the corresponding bit in register PSLR. Bits TRPS=1 and TRPF=0 can occur if the trap
condition is no longer active but the selected synchronization has not yet taken place.
User’s Manual
CCU6, V4.0
21-115
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.9.2.2 Interrupt Status Set Register
Register ISSL/H contains individual interrupt request set bits to generate a CCU6
interrupt request by software. Writing a 1 sets the bit(s) in register ISL/H at the
corresponding bit position(s) and can generate an interrupt event (if available and
enabled).
All bit positions read as 0.
ISSL
Interrupt Status Set Register Low
RMAP: 0, PAGE: 2
(A4H)
Reset Value: 00H
7
6
5
4
3
2
1
0
ST12PM
ST12OM
SCC62F
SCC62R
SCC61F
SCC61R
SCC60F
SCC60R
w
w
w
w
w
w
w
w
Field
Bits
Type Description
SCC60R,
SCC61R,
SCC62R
0,
2,
4
w
Set Capture, Compare-Match Rising Edge Flag
0B
No action
Bit CC6xR will be set.
1B
SCC60F,
SCC61F,
SCC62F
1,
3,
5
w
Set Capture, Compare-Match Falling Edge Flag
No action
0B
1B
Bit CC6xF will be set.
ST12OM
6
w
Set Timer T12 One-Match Flag
0B
No action
Bit T12OM will be set.
1B
ST12PM
7
w
Set Timer T12 Period-Match Flag
0B
No action
Bit T12PM will be set.
1B
ISSH
Interrupt Status Set Register High
RMAP: 0, PAGE: 2
(A5H)
Reset Value: 00H
7
6
5
4
3
2
1
0
SSTR
SIDLE
SWHE
SCHE
SWHC
STRPF
ST13PM
ST13CM
w
w
w
w
w
w
w
w
User’s Manual
CCU6, V4.0
21-116
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
ST13CM
0
w
Set Timer T13 Compare-Match Flag
0B
No action
Bit T13CM will be set.
1B
ST13PM
1
w
Set Timer T13 Period-Match Flag
No action
0B
Bit T13PM will be set.
1B
STRPF
2
w
Set Trap Flag
0B
No action
1B
Bits TRPF and TRPS will be set.
SWHC
3
w
Software Hall Compare
0B
No action
The Hall compare action is triggered.
1B
SCHE
4
w
Set Correct Hall Event Flag
No action
0B
1B
Bit CHE will be set.
SWHE
5
w
Set Wrong Hall Event Flag
0B
No action
Bit WHE will be set.
1B
SIDLE
6
w
Set IDLE Flag
0B
No action
Bit IDLE will be set.
1B
SSTR
7
w
Set STR Flag
No action
0B
1B
Bit STR will be set.
User’s Manual
CCU6, V4.0
21-117
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.9.2.3 Status Reset Register
Register ISRL/H contains bits to individually clear the interrupt event flags by software.
Writing a 1 clears the bit(s) in register IS at the corresponding bit position(s).
All bit positions read as 0.
ISRL
Interrupt Status Reset Register Low
RMAP: 0, PAGE: 0
(A4H)
Reset Value: 00H
7
6
5
4
3
2
1
0
RT12PM
RT12OM
RCC62F
RCC62R
RCC61F
RCC61R
RCC60F
RCC60R
w
w
w
w
w
w
w
w
Field
Bits
Type Description
RCC60R,
RCC61R,
RCC62R
0,
2,
4
w
Reset Capture, Compare-Match Rising Edge Flag
No action
0B
1B
Bit CC6xR will be cleared.
RCC60F,
RCC61F,
RCC62F
1,
3,
5
w
Reset Capture, Compare-Match Falling Edge
Flag
0B
No action
Bit CC6xF will be cleared.
1B
RT12OM
6
w
Reset Timer T12 One-Match Flag
No action
0B
1B
Bit T12OM will be cleared.
RT12PM
7
w
Reset Timer T12 Period-Match Flag
0B
No action
Bit T12PM IS will be cleared.
1B
ISRH
Interrupt Status Reset Register High (A5H)
RMAP: 0, PAGE: 0
Reset Value: 00H
7
6
5
4
3
2
1
0
RSTR
RIDLE
RWHE
RCHE
0
RTRPF
RT13PM
RT13CM
w
w
w
w
r
w
w
w
User’s Manual
CCU6, V4.0
21-118
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
RT13CM
0
w
Reset Timer T13 Compare-Match Flag
0B
No action
Bit T13CM will be cleared.
1B
RT13PM
1
w
Reset Timer T13 Period-Match Flag
No action
0B
Bit T13PM will be cleared.
1B
RTRPF
2
w
Reset Trap Flag
0B
No action
1B
Bit TRPF will be cleared (not taken into
account while input CTRAP=0 and
TRPPEN=1.
RCHE
4
w
Reset Correct Hall Event Flag
0B
No action
Bit CHE will be cleared.
1B
RWHE
5
w
Reset Wrong Hall Event Flag
1B
No action
Bit WHE will be cleared.
0B
RIDLE
6
w
Reset IDLE Flag
No action
0B
1B
Bit IDLE will be cleared.
RSTR
7
w
Reset STR Flag
0B
No action
Bit STR will be cleared.
1B
0
3
r
reserved;
returns 0 if read; should be written with 0;
User’s Manual
CCU6, V4.0
21-119
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.9.2.4 Interrupt Enable Register
Register IENL/H contains the interrupt enable bits and a control bit to enable the
automatic idle function in the case of a wrong hall pattern.
IENL
Interrupt Enable Register Low
RMAP: 0, PAGE: 2
7
6
5
(9CH)
4
Reset Value: 00H
3
2
1
0
ENT12PM ENT12OM ENCC62F ENCC62R ENCC61F ENCC61R ENCC60F ENCC60R
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
ENCC60R,
ENCC61R,
ENCC62R
0,
2,
4
rw
Capture, Compare-Match Rising Edge Interrupt
Enable for Channel CC6x
0B
No interrupt will be generated if the set
condition for bit CC6xR in register IS occurs.
1B
An interrupt will be generated if the set
condition for bit CC6xR in register IS occurs.
The service request output that will be
activated is selected by bit field INPCC6x.
ENCC60F,
ENCC61F,
ENCC62F
1,
3,
5
rw
Capture, Compare-Match Falling Edge Interrupt
Enable for Channel CC6x
No interrupt will be generated if the set
0B
condition for bit CC6xF in register IS occurs.
An interrupt will be generated if the set
1B
condition for bit CC6xF in register IS occurs.
The service request output that will be
activated is selected by bit field INPCC6x.
ENT12OM
6
rw
Enable Interrupt for T12 One-Match
0B
No interrupt will be generated if the set
condition for bit T12OM in register IS occurs.
An interrupt will be generated if the set
1B
condition for bit T12OM in register IS occurs.
The service request output that will be
activated is selected by bit field INPT12.
User’s Manual
CCU6, V4.0
21-120
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
ENT12PM
7
rw
Enable Interrupt for T12 Period-Match
0B
No interrupt will be generated if the set
condition for bit T12PM in register IS occurs.
An interrupt will be generated if the set
1B
condition for bit T12PM in register IS occurs.
The service request output that will be
activated is selected by bit field INPT12.
IENH
Interrupt Enable Register High
RMAP: 0, PAGE: 2
(9DH)
Reset Value: 00H
7
6
5
4
3
2
ENSTR
ENIDLE
ENWHE
ENCHE
0
ENTRPF
rw
rw
rw
rw
r
rw
1
0
ENT13PM ENT13CM
rw
rw
Field
Bits
Type Description
ENT13CM
0
rw
Enable Interrupt for T13 Compare-Match
No interrupt will be generated if the set
0B
condition for bit T13CM in register IS occurs.
1B
An interrupt will be generated if the set
condition for bit T13CM in register IS occurs.
The service request output that will be
activated is selected by bit field INPT13.
ENT13PM
1
rw
Enable Interrupt for T13 Period-Match
No interrupt will be generated if the set
0B
condition for bit T13PM in register IS occurs.
An interrupt will be generated if the set
1B
condition for bit T13PM in register IS occurs.
The service request output that will be
activated is selected by bit field INPT13.
User’s Manual
CCU6, V4.0
21-121
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
ENTRPF
2
rw
Enable Interrupt for Trap Flag
0B
No interrupt will be generated if the set
condition for bit TRPF in register IS occurs.
An interrupt will be generated if the set
1B
condition for bit TRPF in register IS occurs.
The service request output that will be
activated is selected by bit field INPERR.
ENCHE
4
rw
Enable Interrupt for Correct Hall Event
0B
No interrupt will be generated if the set
condition for bit CHE in register IS occurs.
An interrupt will be generated if the set
1B
condition for bit CHE in register IS occurs.
The service request output that will be
activated is selected by bit field INPCHE.
ENWHE
5
rw
Enable Interrupt for Wrong Hall Event
No interrupt will be generated if the set
0B
condition for bit WHE in register IS occurs.
1B
An interrupt will be generated if the set
condition for bit WHE in register IS occurs.
The service request output that will be
activated is selected by bit field INPERR.
ENIDLE
6
rw
Enable Idle
This bit enables the automatic entering of the idle
state (bit IDLE will be set) after a wrong hall event
has been detected (bit WHE is set). During the idle
state, the bit field MCMP is automatically cleared.
The bit IDLE is not automatically set when a
0B
wrong hall event is detected.
The bit IDLE is automatically set when a wrong
1B
hall event is detected.
ENSTR
7
rw
Enable Multi-Channel Mode Shadow Transfer
Interrupt
No interrupt will be generated if the set
0B
condition for bit STR in register IS occurs.
An interrupt will be generated if the set
1B
condition for bit STR in register IS occurs.
The service request output that will be
activated is selected by bit field INPCHE.
User’s Manual
CCU6, V4.0
21-122
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
0
3
r
User’s Manual
CCU6, V4.0
reserved;
returns 0 if read; should be written with 0;
21-123
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.9.2.5 Interrupt Node Pointer Register
Register INPL/H contains the interrupt node pointers allowing a flexible interrupt
handling. These bit fields define which service request output will be activated if the
corresponding interrupt event occurs and the interrupt generation for this event is
enabled.
INPL
Interrupt Node Pointer Register Low (9EH)
RMAP: 0, PAGE: 2
7
6
5
4
Reset Value: 40H
3
2
1
0
INPCHE
INPCC62
INPCC61
INPCC60
rw
rw
rw
rw
Field
Bits
Type Description
INPCC60,
INPCC61,
INPCC62
[1:0],
[3:2],
[5:4]
rw
Interrupt Node Pointer for Channel CC6x
Interrupts
This bit field defines the service request output
activated due to a set condition for bit CC6xR (if
enabled by bit ENCC6xR) or for bit CC6xF (if
enabled by bit ENCC6xF).
00B Service request output SR0 is selected.
01B Service request output SR1 is selected.
10B Service request output SR2 is selected.
11B Service request output SR3 is selected.
INPCHE
[7:6]
rw
Interrupt Node Pointer for the CHE Interrupt
This bit field defines the service request output
activated due to a set condition for bit CHE (if
enabled by bit ENCHE) of for bit STR (if enabled by
bit ENSTR).
Coding see INPCC6x.
User’s Manual
CCU6, V4.0
21-124
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
INPH
Interrupt Node Pointer Register High (9FH)
RMAP: 0, PAGE: 2
7
6
5
4
Reset Value: 39H
3
2
1
0
0
INPT13
INPT12
INPERR
r
rw
rw
rw
Field
Bits
Type Description
INPERR
[1:0]
rw
Interrupt Node Pointer for Error Interrupts
This bit field defines the service request output
activated due to a set condition for bit TRPF (if
enabled by bit ENTRPF) or for bit WHE (if enabled by
bit ENWHE).
Coding see INPCC6x.
INPT12
[3:2]
rw
Interrupt Node Pointer for Timer12 Interrupts
This bit field defines the service request output
activated due to a set condition for bit T12OM (if
enabled by bit ENT12OM) or for bit T12PM (if
enabled by bit ENT12PM).
Coding see INPCC6x.
INPT13
[5:4]
rw
Interrupt Node Pointer for Timer13 Interrupt
This bit field defines the service request output
activated due to a set condition for bit T13CM (if
enabled by bit ENT13CM) or for bit T13PM (if
enabled by bit ENT13PM).
Coding see INPCC6x.
0
[7:6]
r
reserved;
returns 0 if read; should be written with 0;
User’s Manual
CCU6, V4.0
21-125
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.10
General Module Operation
This section provides information about the:
•
•
Input selection (see Section 21.10.1)
General register description (see Section 21.10.2)
21.10.1
Input Selection
Each CCU6 input signal can be selected from a vector of four or eight possible inputs by
programming the port input select registers PISEL0L, PISEL0H and PISEL2. This
permits to adapt the pin functionality of the device to the application requirements.
The output pins for the module output signals are chosen in the ports.
Naming convention:
The input vector CC60IN[D:A] for input signal CC60IN is composed of the signals
CC60INA to CC60IND.
Note: All functional inputs of the CCU6 are synchronized to fCC6 before they affect the
module internal logic. The resulting delay of 2/fCC6 and for asynchronous signals
an additional uncertainty of 1/fCC6 have to be taken into account for precise timing
calculation. An edge of an input signal can only be correctly detected if the high
phase and the low phase of the input signal are both longer than 1/fCC6.
User’s Manual
CCU6, V4.0
21-126
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.10.2
General Registers
21.10.2.1 Port Input Select Registers
Registers PISEL0L and PISEL0H contain bit fields selecting the actual input signal for
the module inputs.
PISEL0L
Port Input Select Register Low
RMAP: 0, PAGE: 3
7
6
(9EH)
5
4
Reset Value: 00H
3
2
1
0
ISTRP
ISCC62
ISCC61
ISCC60
rw
rw
rw
rw
Field
Bits
Type Description
ISCC60
[1:0]
rw
Input Select for CC60
This bit field defines the port pin or that is used for the
CC60 capture input.
00B Input pin CC60_0.
01B Input pin CC60_1.
10B CCU6 SR2 event.
11B ADC channel 0 boundary limit check event.
ISCC61
[3:2]
rw
Input Select for CC61
This bit field defines the port pin that is used for the
CC61 capture input signal.
00B Input pin CC61_0.
01B Input pin CC61_1.
10B CCU6 SR2 event.
11B ADC channel 1 boundary limit check event.
ISCC62
[5:4]
rw
Input Select for CC62
This bit field defines the port pin that is used for the
CC62 capture input signal.
00B Input pin CC62_0.
01B Input pin CC62_1.
10B CCU6 SR2 event.
11B ADC channel 2 boundary limit check event.
User’s Manual
CCU6, V4.0
21-127
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
ISTRP
[7:6]
rw
Input Select for CTRAP
This bit field defines the options that is used for the
CTRAP input signal. MODPISEL3.CPTRAPIS is
concurrently to select the 8 type of sources to trigger
CTRAP.
00B One of the input pin for CTRAP_0, CTRAP_1,
CTRAP_2 and CTRAP_3 is selected. Bit
CTRAPIS bit in MODPISEL3 register are used
for the indicidual selection.
01B Port 1 overcurrent detection output is selected.
10B Any input source from above option 00 or 01 is
selected to trigger a CTRAP.
11B ADC channel event is selected.
PISEL0H
Port Input Select Register 0 High
RMAP: 0, PAGE: 3
7
6
5
(9FH)
4
Reset Value: 00H
3
2
1
0
IST12HR
ISPOS2
ISPOS1
ISPOS0
rw
rw
rw
rw
Field
Bits
Type Description
ISPOS0
[1:0]
rw
Input Select for CCPOS0
This bit field defines the input signal used as
CCPOS0 input.
00B Input pin for CCPOS0_0.
01B Input pin for CCPOS0_1.
10B Input pin for CCPOS0_2.
11B ADC channel 0 boundary limit check event.
ISPOS1
[3:2]
rw
Input Select for CCPOS1
This bit field defines the input signal used as
CCPOS1 input.
00B Input pin for CCPOS1_0.
01B Input pin for CCPOS1_1.
10B Unused.
11B ADC channel 1 boundary limit check event.
User’s Manual
CCU6, V4.0
21-128
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
ISPOS2
[5:4]
rw
Input Select for CCPOS2
This bit field defines the the port pin that is used for
the CCPOS2 input signal.
00B Input pin for CCPOS2_0.
01B Input pin for CCPOS2_1.
10B Unused.
11B ADC channel 2 boundary limit check event.
IST12HR
[7:6]
rw
Input Select for T12HR
This bit field defines the input signal used as T12HR
input.
00B Any of the input pin for T12HR[7:0]1).
01B CCU6 SR2 output.
10B CCU6 SR3 output.
11B ADC channel event.
1) The selection of T12HR[7:0] can be done by bit IST12HR1 in MODIPISEL3 register from SCU module.
PISEL2
Port Input Select Register 2
RMAP: 0, PAGE: 3
7
6
(A4H)
5
4
Reset Value: 00H
3
2
1
0
0
IST13HR
r
rw
Field
Bits
Type Description
IST13HR
[1:0]
rw
Input Select for T13HR
This bit field defines the input signal used as T13HR
input.
00B Any of the input pin for T13HR[7:0]1).
01B CCU6 SR2 output.
10B CCU6 SR3 output.
11B ADC channel event.
0
[7:2]
r
reserved;
returns 0 if read; should be written with 0;
1) The selection of T13HR[7:0] can be done by bit IST13HR1 in MODIPISEL3 register from SCU module.
User’s Manual
CCU6, V4.0
21-129
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
21.11
Register Mapping
The CCU6 SFRs are located in the standard memory area (RMAP = 0) and are
organized into 4 pages. The CCU6_PAGE register is located at address A3H. It contains
the page value and the page control information.
CCU6_PAGE
Page Register for CCU6
RMAP: 0, PAGE: X
7
6
(F1H)
5
4
Reset Value: 00H
3
2
1
OP
STNR
0
PAGE
w
w
r
rwh
0
Field
Bits
Type Description
PAGE
[3:0]
rwh
Page Bits
When written, the value indicates the new page address.
When read, the value indicates the currently active page
= addr [y:x+1]
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the target
of the operation defined by bit OP.
If OP = 10B,
the contents of PAGE are saved in CCU6_STx before
being overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the contents of
CCU6_STx. The value written to the bit positions of
PAGE is ignored.
00
CCU6_ST0 is selected.
01
CCU6_ST1 is selected.
10
CCU6_ST2 is selected.
11
CCU6_ST3 is selected.
User’s Manual
CCU6, V4.0
21-130
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Field
Bits
Type Description
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is ignored
and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the former contents of
PAGE are saved in the storage bit field CCU6_STx
indicated by STNR.
11
Automatic restore page action. The value written
to the bit positions PAGE is ignored and instead,
PAGE is overwritten by the contents of the storage
bit field CCU6_STx indicated by STNR.
The addresses (non-mapped) of the kernel SFRs are listed in Table 21-16.
All CCU6 register names described in the following sections are referenced in other
chapters of this document with the module name prefix “CCU6_”, e.g.,
CCU6_CC63SRL.
Table 21-16 SFR Address List for CCU6 Pages 0 – 3
Address
Page 0
Page 1
Page 2
Page 3
9AH
CC63SRL
CC63RL
T12MSELL
MCMOUTL
9BH
CC63SRH
CC63RH
T12MSELH
MCMOUTH
9CH
TCTR4L
T12PRL
IENL
ISL
9DH
TCTR4H
T12PRH
IENH
ISH
9EH
MCMOUTSL
T13PRL
INPL
PISEL0L
9FH
MCMOUTSH
T13PRH
INPH
PISEL0H
A4H
ISRL
T12DTCL
ISSL
PISEL2
A5H
ISRH
T12DTCH
ISSH
A6H
CMPMODIFL
TCTR0L
PSLR
A7H
CMPMODIFH
TCTR0H
MCMCTR
FAH
CC60SRL
CC60RL
TCTR2L
T12L
FBH
CC60SRH
CC60RH
TCTR2H
T12H
FCH
CC61SRL
CC61RL
MODCTRL
T13L
FDH
CC61SRH
CC61RH
MODCTRH
T13H
User’s Manual
CCU6, V4.0
21-131
V1.1, 2010-09
XC83x
Capture/Compare Unit 6 (CCU6)
Table 21-16 SFR Address List for CCU6 Pages 0 – 3
Address
Page 0
Page 1
Page 2
Page 3
FEH
CC62SRL
CC62RL
TRPCTRL
CMPSTATL
FFH
CC62SRH
CC62RH
TRPCTRH
CMPSTATH
User’s Manual
CCU6, V4.0
21-132
V1.1, 2010-09
XC83x
Analog to Digital Converter
22
Analog to Digital Converter
The Analog to Digital Converter module (ADC) of the XC83x uses the successive
approximation method to convert analog input values (voltages) to discrete digital
values.
One ADC kernel (ADC0) operate on a user-selectable number of input channels.
The input channels can be selected and arbitrated flexibly.
ADC kernel 0
...
analog
inputs
AD
converter
data (result)
handling
conversion
control
request
control
bus
interface
AD C_ 1_kernels
Figure 22-1 ADC Module Block Diagram
This section gives an overview about the feature of the ADC module and introduces the
general structure which is described in the below fromat:
•
•
•
•
•
•
•
•
“Introduction and Basic Structure” on Page 22-7
“Configuration of General Functions” on Page 22-13
“Conversion Request Generation” on Page 22-17
“Request Source Arbitration” on Page 22-38
“Analog Input Channel Configuration” on Page 22-45
“Conversion Result Handling” on Page 22-64
“Interrupt Request Handling” on Page 22-83
“Register Mapping” on Page 22-90
User’s Manual
ADC, V2.2
22-1
V1.1, 2010-09
XC83x
Analog to Digital Converter
The following features describe the functionality of an ADC kernel:
•
•
•
•
•
•
•
•
•
•
Input voltage range from 0 V up to analog supply voltage (VDDP = 3.0 V to 5.5 V)
Three internal reference voltage source selectable for each channel to support
ratiometric measurements and different signal scales, which are:
– Internal VDDP and VSSP
– Internal 1.2Vref and CH0 used as ADC voltage reference ground1)
– Internal 1.2Vref and VSSP1)
Up to 8 analog input channels
Conversion speed and sample time adjustable to adapt to sensors and reference
Conversion time below 1 µs (depending on result width and sample time)
Flexible source selection and arbitration
– Single-channel conversion (single or repeated)
– Configurable auto scan conversions (single or repeated)
– Programmable arbitrary conversion sequence (single or repeated)
– Conversions triggered by software, timer events, or external events
– Wait-for-start mode for maximum throughput or
Cancel-inject-restart mode for reduced conversion delay
Powerful result handling
– Selectable result width of 8 to 10 bits
– 4 independent result registers
– Configurable limit checking against programmable border values
– Data rate reduction through adding a selectable number of conversion results
– First order digital low pass filter through averaging of the conversion results
Flexible interrupt generation based on selectable events
Support of power saving modes
Additional features
– Out of range (ORC) voltage comparator detection for each input channel that is
able to trigger other modules
– Configurable limit checker able to trigger other modules
1) A setup time is needed between conversions when using this mode. Refer to Data Sheet for the required setup
time.
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ADC, V2.2
22-2
V1.1, 2010-09
XC83x
Analog to Digital Converter
22.1
System Information
This section provides system information relevant to the ADC.
22.1.1
Pinning
The ADC pin assignment for XC83x is shown in Table 22-1.
Table 22-1
ADC Pin Functions and Selection
Pin
Function
Desciption
Selected By
P2.0
CH0
Analog input channel 0
P2_EN.P0 = 1B
P2.1
CH1
Analog input channel 1
P2_EN.P1 = 1B
P2.2
CH2
Analog input channel 2
P2_EN.P2 = 1B
P2.3
CH3
Analog input channel 3
P2_EN.P3 = 1B
P2.4
CH4
Analog input channel 4
P2_EN.P4 = 1B
P2.5
CH5
Analog input channel 5
P2_EN.P5 = 1B
P2.6
CH6
Analog input channel 6
P2_EN.P6 = 1B
P2.7
CH7
Analog input channel 7
P2_EN.P7 = 1B
22.1.2
Clocking Configuration
The ADC kernel runs on the FPCLK at a fixed frequency of 48 MHz. See Section 22.5.1
If the ADC functionality is not required at all, it can be completely disabled by gating off
its clock input for maximal power reduction. This is done by setting bit ADC_DIS in
register PMCON1 as described below.
The bit field PAGE of SCU_PAGE register must be programmed before accessing the
PMCON1 register.
PMCON1
Peripheral Management Control Register 1(EFH)
RMAP: 0, PAGE: 1
7
6
IIC_DIS
LTS_DIS
rw
rw
User’s Manual
ADC, V2.2
5
4
CDC_DIS MDU_DIS
rw
rw
22-3
Reset Value: FFH
3
2
1
0
T2_DIS
CCU_DIS
SSC_DIS
ADC_DIS
rw
rw
rw
rw
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
ADC_DIS
0
rw
22.1.3
ADC Disable Request. Active high.
0
ADC is in normal operation.
1
Request to disable the ADC. (default)
Interrupt Events and Assignment
Table 22-2 lists the interrupt event sources from the ADC, and the corresponding event
interrupt enable bit and flag bit.
Table 22-2
ADC Interrupt Events
Event
Event Interrupt Enable Bit Event Flag Bit
Service
Request
Output
Request Source
Event Interrupts
ADC_Q0R0.ENSI
SR0
Channel Event
Interrupts
ADC_GLOBCTR.CLCIEN
ADC_CHINFR.CHINFx SR0
Result Event
Interrupts
ADC_RCRx (x = 0 - 3).IEN
ADC_EVINFR.EVINFx
SR0
Out of Range
Comparator
Event Interrupts
ADC_GLOBCTR.ORCIEN
ADC_LORE.LOREx
SR1
ADC_EVINFR.EVINFx
ADC_QBUR0.ENSI
Table 22-3 shows the interrupt node assignment for each ADC interrupt source.
Table 22-3
ADC Events’ Interrupt Node Control
Event
Interrupt Node
Enable Bit
Interrupt Node Flag Vector
Bit
Address
SR0
IEN1.EADC
IRCON1.ADCSR0
SR1
22.1.4
33H
IRCON1.ADCSR1
IP Interconnection
The ADC has interconnection to other peripherals enabling higher level of automation
without requiring software. Table 22-4 describes the interconnection from ADC outputs,
channel events and out of range comparator events, to CCU6 and Timer 2 inputs.
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
Table 22-5 describes the interconnection from CCU6 and LEDTSCU outputs to the
external request trigger input of ADC.
Table 22-4
ADC Output Interconnections
ADC Function/Signal
Connected Other
Module Inputs
Selected By
CCU6 input (i): T12HR
CCU6_PISEL0H.IST12HR = 11B
Channel Events
ADC channel event (o):
ADC_CHEV
CCU6 input (i): T13HR
CCU6_PISEL2.IST13HR = 11B
ADC channel event 0 (o):
ADC_CHEV0
CCU6 input (i): CTRAP
CCU6_PISEL0L.ISTRP = 11B
ADC channel event 1 (o):
ADC_CHEV1
No connection
-
ADC channel event 2 (o):
ADC_CHEV2
No connection
-
ADC boundary event 0 (o): CCU6 input (i): CC60
CCU6_PISEL0L.ISCC60 = 11B
ADC_BF0
CCU6 input (i): CCPOS0 CCU6_PISEL0H.ISPOS0 = 11B
ADC boundary event 1 (o): CCU6 input (i): CC61
CCU6_PISEL0L.ISCC61 = 11B
ADC_BF1
CCU6 input (i): CCPOS1 CCU6_PISEL0H.ISPOS1 = 11B
ADC boundary event 2 (o): CCU6 input (i): CC62
CCU6_PISEL0L.ISCC62= 11B
ADC_BF2
CCU6 input (i): CCPOS2 CCU6_PISEL0H.ISPOS2= 11B
Out of Range Comparator (ORC)
ORC event 0 (o):
ORCEVENT0
CCU6 input (i): T12HR
MODPISEL3.IST12HR1 = 001B
CCU6_PISEL0H.IST12HR = 00B
Timer 2 input (i): T2EX
MODPISEL2.T2EXIS = 100B
ORC event 1 (o):
ORCEVENT1
Timer 2 input (i): T2EX
MODPISEL2.T2EXIS = 101B
ORC event 2 (o):
ORCEVENT2
CCU6 input (i): T12HR
MODPISEL3.IST12HR1 = 100B
CCU6_PISEL0H.IST12HR = 00B
CCU6 input (i): T13HR
MODPISEL3.IST13HR1 = 100B
CCU6_PISEL2.IST13HR = 00B
CCU6 input (i): CTRAP
MODPISEL3.CTRAPIS = 11B
CCU6_PISEL0L.ISTRP = 00/10B
ORC event 3 (o):
ORCEVENT3
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
Table 22-4
ADC Output Interconnections
ADC Function/Signal
Connected Other
Module Inputs
Selected By
ORC event 4 (o):
ORCEVENT4
CCU6 input (i): T12HR
MODPISEL3.IST12HR1 = 110B
CCU6_PISEL0H.IST12HR = 00B
CCU6 input (i): T13HR
MODPISEL3.IST13HR1 = 110B
CCU6_PISEL2.IST13HR = 00B
Table 22-5
ADC Input Interconnection
ADC Function/Signal
Connected Other Module Function/Signal
Request Source x (x = 0,1)
Request Source x Trigger 0 Input (i):
REQTRxA
CCU6 service request output SR2 (o):
CCU6_SR2
Request Source x Trigger 1 Input (i):
REQTRxB
CCU6 service request output SR3 (o):
CCU6_SR3
Request Source x Trigger 2 Input (i):
REQTRxC
CCU6 T12 period match (o): T12PM
Request Source x Trigger 3 Input (i):
REQTRxD
CCU6 T13 period match (o): T13PM
Request Source x Trigger 4 Input (i):
REQTRxE
CCU6 T13 compare match (o): T13CM
Request Source x Trigger 5 Input (i):
REQTRxF
CCU6 MCM shadow transfer (o): MCM_ST
Request Source x Trigger 6 Input (i):
REQTRxG
LEDTSCU Compare match (o): LEDTS_CM
Request Source x Trigger 7 Input (i):
REQTRxH
LEDTSCU Time slice interrupt (o): LEDTS_TSI
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ADC, V2.2
22-6
V1.1, 2010-09
XC83x
Analog to Digital Converter
22.2
Introduction and Basic Structure
A set of functional units can be configured according to the requirements of a given
application. These units build a path from the input signals to the digital results.
Vddp V 1.2 VREF
va_altref
va_ref
ADC kernel
va_gnd
va_altgnd
Vssp
analog input
channel CH0
...
analog input
channel CH3 / 7
interrupt
generation
AD
converter
result
handling
conversion
control
request
control
ADC _kernel _ overv3
Figure 22-2 ADC Kernel Block Diagram
Request Source Control
Concurrent conversion requests can be generated by up to 2 request sources:
•
•
A linear sequence source requests auto scan conversions of a configurable
sequence of up to 8 channels
An arbitrary sequence source requests queued conversions of up to 4 arbitrarily
selectable channels
Each source can requests its selected conversion sequence once or repeatedly. Each
source can be enabled separately and can be triggered by external events, such as
edges of PWM or timer signals, or pin transitions.
An arbiter resolves concurrent conversion requests from different sources. Requests
with higher priority can either cancel a running lower-priority conversion (cancel-injectrepeat mode) or be converted immediately after the currently running conversion (waitfor-start mode). If the target result register has not been read, a conversion can be
deferred (wait-for-read mode).
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V1.1, 2010-09
XC83x
Analog to Digital Converter
Input Channel Selection
The analog input multiplexer selects one of up to 8 analog inputs (CH0 - CH7) to be
converted. Two sources can select a linear sequence or an arbitrary sequence. The
priorities of these sources can be configured.
Note: Not all analog input channels are necessarily available in all packages, due to pin
limitations. Please refer to the implementation description in Section 22.1.
Conversion Control
Conversion parameters, such as sample phase duration, can be configured in the input
classes.
The input channels can, thus, be adjusted to the type of sensor (or other analog sources)
connected to the ADC.
Analog/Digital Converter
The selected input channel is converted to a digital value by first sampling the voltage
on the selected input and then generating the selected number of result bits.
Result Handling
The conversion results of each analog input channel can be directed to one of 4 result
registers to be stored there. A result register can be used by a group of channels or by
a single channel.
The wait-for-read mode avoids data loss due to result overwrite by blocking a conversion
until the previous result has been read.
Data reduction (e.g. for digital anti-aliasing filtering) can automatically add up to 2
conversion results before interrupting the CPU.
Also, result registers can be concatenated to build FIFO structures that store a number
of conversion results without overwriting previous data. This increases the allowed CPU
latency for retrieving conversion data from the ADC.
A digital first order low pass filter is implemented that can continously filter the
conversion results before it is written to the result register.
Interrupt Generation
Several ADC events can issue interrupt requests to the CPU:
•
•
Source events indicate the completion of a conversion sequence in the
corresponding request source. This event can be used to trigger the setup of a new
sequence.
Channel events indicate the completion of a conversion for a certain channel. This
can be combined with limit checking, so interrupt are generated only if the result is
within a defined range of values.
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V1.1, 2010-09
XC83x
Analog to Digital Converter
•
•
Result events indicate the availability of new result data in the corresponding result
register. If data reduction or digital low pass filter mode is active, events are
generated only after a complete accumulation sequence.
Out of range comparator events indicate that a voltage higher or lower than Vddp is
detected at the ADC input channels.
All interrupt request is assigned to two interrupt nodes.
Additional Features
Detect and trigger mechanisms are supported with two mechanisms to ensure a fast
response without CPU intervention.
Out of Range Comparator (ORC) is build into every ADC channel which will trigger
other modules or an interrupt when voltage out of range condition occurs. This happens
when voltage at the input channel rises to above Vddp level or when the input channel
falls to a voltage below Vddp level.
The out of range comparator is connected to other modules e.g CCU6, timer such that it
is able to trigger the start or stop of other modules. All out of range comparator events is
assigned to one interrupt node.
Configurable Limit Checker checks the conversion results against programmed values
which will trigger other modules or an interrupt when the trigger condition is fulfilled.
The configurable limit checker is conected to other module i.e CCU6 such that is is able
to trigger the start or stop of the other module.
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ADC, V2.2
22-9
V1.1, 2010-09
XC83x
Analog to Digital Converter
22.3
Electrical Models
Each conversion of an analog input voltage to a digital value consists of two consecutive
phases:
•
•
During the sample phase, the input voltage is sampled and stored.
The input signal path is a simplified model for this.
During the conversion phase the stored voltage is converted to a digital result.
The reference voltage path is a simplified model for this.
Input Signal Path
The ADC of the XC83x uses a switched capacitor field represented by CAIN (small
parasitic capacitances are present at each input pin). During the sample phase, the
capacitor field CAIN is connected to the selected analog input CHx via the input
multiplexer (modeled by ideal switches and series resistors RAIN).
The switch to CHx is closed during the sample phase and connects the capacitor field to
the input voltage VAINx.
CH3/7
...
R EXT
...
VS
C EXT
ADC kernel
C Hx
C H0
V AINx
R AIN
C AIN
VC
V AGND
ADC_signal _ path _ m odel 3
Figure 22-3 Signal Path Model
A simplified model for the analog input signal path is given in Figure 22-3. An analog
voltage source (value VS) with an internal impedance of REXT delivers the analog input
that should be converted.
During the sample phase the corresponding switch is closed and the capacitor field CAIN
is charged. Due to the low-pass behavior of the resulting RC combination, the voltage
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
VC to be actually converted does not immediately follow VS. The value REXT of the analog
voltage source and the desired precision of the conversion strongly define the required
length of the sample phase.
To reduce the influence of REXT and to filter input noise, it is recommended to introduce
a fast external blocking capacitor CEXT at the analog input pin of the ADC. Like this,
mainly CEXT delivers the charge during the sample phase. This structure allows a
significantly shorter sample phase than without a blocking capacitor, because the lowpass time constant defining the sample time is mainly given by the values of RAIN and
CAIN.
Additionally, the capacitor CAIN is automatically precharged to a voltage of approximately
the half of the standard reference voltage VAREF to minimize the average difference
between VAINx and VC at the beginning of a sample phase. Due to varying parameters
and parasitic effects, the precharge voltage of CAIN is typically smaller than VAREF / 2.
On the other hand, the charge redistribution between CEXT and CAIN leads to a voltage
change of VAINx during the sample phase. In order to keep this voltage change lower than
1 LSBn, it is recommended to use an external blocking capacitor CEXT in the range of at
least 2n × CAIN.
The resulting low-pass filter of REXT and CEXT should be dimensioned in a way to allow
VAINx to follow VS between two sample phases of the same analog input channel.
Please note that, especially at high temperatures, the analog input structure of an ADC
can lead to a leakage current and introduces an error due to a voltage drop over REXT.
The ADC input leakage current increases if the input voltage level is close to the analog
supply ground VSS or to the analog power supply VDDP. It is recommended to use an
operating range for the input voltage between approximately 3% and 97% of VDDP to
reduce the input leakage current of the respective ADC channel.
Furthermore, the leakage is influenced by an overload condition at adjacent analog
inputs. During an overload condition, an input voltage exceeding the supply range is
applied at an input and the built-in protection circuit limits the resulting input voltage. This
leads to an overload current through the protection circuit that is translated (by a coupling
factor) into an additional leakage at adjacent inputs.
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
22.4
Transfer Characteristics and Error Definitions
The transfer characteristic of the ADC describes the association of analog input voltages
to the 2n discrete digital result values (n bits resolution). Each digital result value (in the
range of 0 to 2n-1) represents an input voltage range defined by the reference voltage
range divided by 2n. This range (called quantization step or code width) represents the
granularity (called LSBn) of the ADC. The discrete character of the digital result
generates a system-inherent quantization uncertainty of ±0.5 LSBn for each conversion
result.
The ideal transfer curve has the first digital transition (between 0 and 1) when the analog
input reaches 0.5 LSBn. The quantization steps are equally distributed over the input
voltage range.
Analog input voltages below or above the reference voltage limits lead to a saturation of
the digital result at 0 or 2n-1.
The real transfer curve can exhibit certain deviations from the ideal transfer curve:
•
•
•
•
•
The offset error is the deviation of the real transfer line from the ideal transfer line at
the lowest code. This refers to best-fit lines through all possible codes, for both cases.
The gain error is the deviation of the slope of the real transfer line from the slope of
the ideal transfer line. This refers to best-fit lines through all possible codes, for both
cases.
The differential non-linearity error (DNL) is the deviation of the real code width
(variation of the analog input voltage between two adjacent digital conversion results)
from the ideal code width. A DNL value of -1 LSBn indicates a missing code.
The integral non-linearity error (INL) is the deviation of the real transfer curve from
an adjusted ideal transfer curve (same offset and gain error as the real curve, but
equal code widths).
The total unadjusted error (TUE) describes the maximum deviation between a real
conversion result and the ideal transfer characteristics over a given measurement
range. Since some of these errors noted above can compensate each other, the TUE
value generally is much less than the sum of the individual errors.
The TUE also covers production process variations and internal noise effects (if
switching noise is generated by the system, this generally leads to an increased TUE
value).
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
22.5
Configuration of General Functions
While many parameters can be selected individually for each channel, source, etc, some
adjustments are valid for the whole ADC kernel.
22.5.1
General Clocking Scheme and Control
The different parts of an ADC kernel are driven by clock signals that are based on the
clock fADC of the bus that is used to access the ADC module. The ADC in the XC83x
device are connected to the system clock, so fADC = fSYS.
•
•
•
The analog clock fADCI is used as internal clock for the converter and defines the
conversion length and the sample time.
See Section 22.8.6.
The digital clock fADCD is used for the arbiter and defines the duration of an arbiter
round
All other digital structures (such as interrupts, etc.) are directly driven by the module
clock fADC.
Timing parameters are programmed in register ADC_GLOBCTR.
clock generation
unit (in SCU)
fSYS
ADC kernel
module clock f ADC
divider for
fADCI
analog clock
fADCI
interrupts,
etc.
converter
digital clock
fADCD
arbiter
ADC8 _clocking 2
Figure 22-4 Clocking Scheme
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
Note: If the clock generation for the converter of the ADC falls below a minimum value
or is stopped during a running conversion, the conversion result can be corrupted.
For correct ADC results, the frequency of fADCI must not exceed the defined range.
Please, refer to the range indicated in the respective Data Sheet.
The Global Control Register defines the basic timing parameters and the basic operating
mode of the converter unit, it contains bits for:
•
•
•
•
•
Enabling/Disabling of the analog converter
Defining the result bits resolution, 8/10bits wide
Defining the divider ratio CTC for fADCI , internal clock frequency for the analog part
Enabling/Disabling of the Out of range comparator interrupt
Enabling/Disabling of the Channel limit checking interrupt
ADC_GLOBCTR
Global Control Register
RMAP: 0, PAGE: 0
7
6
ANON
DW
rw
rw
(CAH)
5
4
Reset Value: 30H
3
2
1
0
CTC
ORCIEN
CLCIEN
0
rw
rw
rw
r
Field
Bits
Type Description
CLCIEN
2
rw
Channel Limit Checking Interrupt Enable
This bit enables the channel event interrupt related
to the limit checking, see Figure 22-15. A channel
event interrupt is generated when this interrupt
enable is set to ”1”, there is new result in buffer and
result triggers the limit check unit.
The event interrupt is disabled.
0B
1B
The event interrupt is enabled.
ORCIEN
3
rw
Out of Range Comparator Interrupt Enable
0B
Out of range comparator interrupt disabled.
1B
Out of range comparator interrupt enabled.
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V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
CTC
[5:4]
rw
Conversion Time Control
This bit field defines the divider ratio for the divider
stage of the internal analog clock fADCI. This clock
provides the internal time base for the conversion
and sample time calculations.
00B fADCI = 1/3 × fADCA
01B fADCI = 1/4 × fADCA
10B Reserved
11B fADCI = 1/6 × fADCA (default)
DW
6
rw
Data Width
This bit field defines how many bits are converted for
the result.
The result is 10-bits wide (default).
0B
The result is 8-bits wide.
1B
ANON
7
rw
Analog Part Switched On
This bit enables the analog part of the ADC module
and defines its operation mode.
The analog part is switched off and
0B
conversions are not possible.
To achieve minimal power consumption, the
internal analog circuitry is in its power-down
state and the generation of fADCI is stopped.
1B
The analog part of the ADC module is
switched on and conversions are possible.
The automatic power-down capability of the
analog part is disabled.
0
[1:0]
r
Reserved
Returns 0 if read; should be written with 0.
The Global Status Register indicates the current status of a conversion
ADC_GLOBSTR
Global Status Register
RMAP: 0, PAGE: 0
7
6
(CBH)
5
4
Reset Value: 00H
3
2
1
0
0
CHNR
0
SAMPLE
BUSY
r
rh
r
rh
rh
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V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
BUSY
0
rh
Analog Part Busy
This bit indicates that a conversion is currently
active.
The analog part is idle.
0B
1B
A conversion is currently active.
SAMPLE
1
rh
Sample Phase
This bit indicates that an analog input signal is
currently sampled.
The analog part is not in the sampling phase.
0B
1B
The analog part is in the sampling phase.
CHNR
[5:3]
rh
Channel Number
This bit field indicates which analog input channel is
currently converted. This information is updated
when a new conversion is started.
Note: Bit 5 is only applicable for devices that have 8
ADC channels. For channels not implemented, these
bits should be treated as Reserved bits of type ‘r’
which returns ‘0’ if read and should be written with 0.
0
2, [7:6]
r
Reserved
Returns 0 if read; should be written with 0.
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XC83x
Analog to Digital Converter
22.6
Conversion Request Generation
The conversion request unit of each ADC kernel autonomously handles the generation
of conversion requests. Two request sources can generate requests for the conversion
of an analog channel. The arbiter resolves concurrent requests and selects the channel
to be converted next.
Upon a trigger event, the request source requests the conversion of a certain analog
input channel or a sequence of channels.
•
•
Software triggers directly activate the respective request source.
External triggers synchronize the request source activation with external events,
such as a trigger pulse from a timer generating a PWM signal or from a port pin.
Application software selects the trigger, the channel(s) to be converted, and the request
source priority. A request source can also be activated directly by software without
requiring an external trigger.
The arbiter regularly scans the request sources for pending conversion requests and
selects the conversion request with the highest priority. This conversion request is then
forwarded to the converter to start the conversion of the requested channel.
Each request source can operate in single-shot or in continuous mode:
•
•
In single-shot mode, the programmed conversion (sequence) is requested once
after being triggered. A subsequent conversion (sequence) must be triggered again.
In continuous mode, the programmed conversion (sequence) is automatically
requested repeatedly after being triggered once.
For each request source, external triggers are generated from one of 8 selectable trigger
inputs (REQTRx[H:A]).
request control
request
source 0
AD C kernel
(4 -stage queue )
C CU6
request
source
arbiter
request
source 1
external
request(s)
(4 /81 ) -ch scan )
analog part
Note:
1) 8 channel scan are for devices with 8 ADC channels and
4 channel scan are for devices with 4 ADC channels.
AD C _request _ handling 2
Figure 22-5 Conversion Request Unit
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XC83x
Analog to Digital Converter
Two types of requests sources are available:
•
•
A channel scan source can issue conversion requests for a coherent sequence of
input channels. This sequence begins with the highest enabled channel number and
continues towards lower channel numbers. Up to 8 channels can be enabled for the
scan sequence. Each channel is converted once per sequence.
A scan source converts a series of input channels permanently or on a regular time
base. For example, if programmed with low priority, some input channels can be
scanned in a background task to update information that is not time-critical.
Request source 1 is a channel scan source.
A queued source can issue conversion requests for an arbitrary sequence of input
channels. The channel numbers for this sequence can be freely programmed. This
supports application-specific conversion sequences that cannot be covered by a
channel scan source. Also, multiple conversions of the same channel within a
sequence are supported.
A queued source converts a series of input channels permanently or on a regular
time base. For example, if programmed with medium priority, some input channels
can be converted upon a specified event (e.g. synchronized to a PWM). Conversions
of lower priority sources are suspended in the meantime.
Request source 0 is a 4-stage queued source.
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XC83x
Analog to Digital Converter
22.6.1
Channel Scan Request Source Handling
Each analog input channel can be included in or excluded from the scan sequence (see
bits in register ADC_CRCR1). The programmed register value remains unchanged by
an ongoing scan sequence. The scan sequence starts with the highest enabled channel
number and continues towards lower channel numbers.
Upon a load event, the request pattern is transferred to the pending bits (see register
ADC_CRCR1). The pending conversion requests indicate which input channels are to
be converted in an ongoing scan sequence. Each conversion start that was triggered by
the scan request source, automatically clears the corresponding pending bit. If the last
conversion triggered by the scan source is finished and all pending bits are cleared, the
current scan sequence is considered finished and a request source event is generated.
A conversion request is only issued to the request source arbiter if at least one pending
bit is set.
If the arbiter aborts a conversion triggered by the scan request source due to higher
priority requests, the corresponding pending bit is automatically set. This ensures that
an aborted conversion is not lost but takes part in the next arbitration round.
The trigger unit generates load events from the selected external (outside the ADC)
trigger signals. For example, a timer unit can issue a request signal to synchronize
conversions to PWM events.
Load events start a scan sequence and can be generated either via software or via the
selected hardware triggers.
trigger inputs
REQTRx_[7:0]
conversion request
control
REQTRx
trigger &
gating unit
load event
conversion
requests pending
request
request
source event
request handling
scan request source x
status
request
source
arbiter
ADC_ scan _reqsrc
Figure 22-6 Scan Request Source
User’s Manual
ADC, V2.2
22-19
V1.1, 2010-09
XC83x
Analog to Digital Converter
Scan Source Operation
Configure the scan request source by executing the following actions:
•
•
•
•
Select the input channels for the sequence by programming ADC_CRCR1
If hardware trigger is desired, select the appropriate trigger inputs by programming
ADC_ETRCR. Enable the trigger by programming ADC_CRMR1.
Define the load event operation (handling of pending bits, autoscan mode) by
programming ADC_CRMR1.
A load event with bit LDM = 0 copies the content of ADC_CRCR1 to ADC_CRPR1
(overwrite mode). This starts a new scan sequence and aborts any pending
conversions from a previous scan sequence.
A load event with bit LDM = 1 OR-combines the content of ADC_CRCR1 to
ADC_CRPR1 (combine mode). This starts a scan sequence that includes pending
conversions from a previous scan sequence.
Enable the corresponding arbitration slot (1) to accept conversion requests from the
channel scan source (see register ADC_PRAR).
Start a channel scan sequence by generating a load event:
•
•
•
If a hardware trigger is selected and enabled, generate the configured transition at
the selected input signal, e.g. from a timer or an input pin.
Generate a software load event by setting ADC_CRMR1.LDEV = 1.
Generate a load event by writing the scan pattern directly to the pending bits in
ADC_CRPR1. The pattern is copied to ADC_CRCR1 and a load event is generated
automatically.
In this case, a scan sequence can be defined and started with a single data write
action.
Note: If autoscan is enabled, a load event is generated automatically each time a
request source event occurs when the scan sequence has finished. This
permanently repeats the defined scan sequence (autoscan).
Stop or abort an ongoing scan sequence by executing the following actions:
•
•
•
If external gating is enabled, switch the gating signal to the defined inactive level. This
does not modify the conversion pending bits, but only prevents issuing conversion
requests to the arbiter.
Disable the corresponding arbitration slot (1) in the arbiter. This does not modify the
contents of the conversion pending bits, but only prevents the arbiter from accepting
requests from the request handling block.
Disable the channel scan source by clearing bitfield ENGT = 0B. Clear the pending
request bits by setting bit ADC_CRMR1.CLRPND = 1.
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ADC, V2.2
22-20
V1.1, 2010-09
XC83x
Analog to Digital Converter
Scan Request Source Events and Interrupts
A request source event of a scan source occurs if the last conversion of a scan sequence
is finished (all pending bits = 0). A request source event interrupt can be generated
based on a request source event according to the structure shown in Figure 22-7. If a
request source event is detected, it sets the corresponding indication flag in register
ADC_EVINFR. The indication flags can be cleared by SW by writing a 1 to the
corresponding bit position in register ADC_EVINCR.
The service request output SRx becomes activated each time the related request source
event is detected (and enabled by CRMRx.ENSI).
The request source events and the result events share the same registers. The request
source event is located at the bit position in register ADC_EVINFR:
•
Event 1: Request source event of the channel scan source 1 (in arbitration slot 1)
request source
event
indication flag
request source
event
interrupt enable
EVIN FR.
EVINF 1
C RMR1.
ENSI
set
scan
sequence
finished
request
source event
to SR0
ADC_scan _source _ int
Figure 22-7 Interrupt Generation of a Scan Request Source
The conversion request mode registers contains bits used to set the request source in
the desired mode.
ADC_CRMR1
Conversion Request Mode Register 1 (CCH)
RMAP: 0, PAGE: 6
Reset Value: 00H
7
6
5
4
3
2
1
0
0
LDEV
CLRPND
SCAN
ENSI
ENTR
0
ENGT
r
w
w
rw
rw
rw
r
rw
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ADC, V2.2
22-21
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
ENGT
0
rw
Enable Gate
This bit enables the gating functionality for the
request source.
The gating line is permanently 0. The source is
0B
switched off.
The gating line is permanently 1. The source is
1B
switched on.
ENTR
2
rw
Enable External Trigger
This bit enables the external trigger possibility. If
enabled, the load event takes place if a rising edge
is detected at the external trigger input REQTR.
0B
The external trigger is disabled.
The external trigger is enabled.
1B
ENSI
3
rw
Enable Source Interrupt
This bit enables the request source interrupt. This
interrupt can be generated when the last pending
conversion is completed for this source (while PND
= 0).
The source interrupt is disabled.
0B
1B
The source interrupt is enabled.
SCAN
4
rw
Autoscan Enable
This bit enables the autoscan functionality. If
enabled, the load event is automatically generated
when a conversion (requested by this source) is
completed and PND = 0.
The autoscan functionality is disabled.
0B
The autoscan functionality is enabled.
1B
CLRPND
5
w
Clear Pending Bits
No action
0B
1B
The bits in register CRPR1 are reset.
LDEV
6
w
Generate Load Event
0B
No action
1B
The load event is generated.
0
7,[1:0]
r
Reserved
Returns 0 if read; should be written with 0.
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ADC, V2.2
22-22
V1.1, 2010-09
XC83x
Analog to Digital Converter
The Conversion Request 1 Control Register selects the channels to be converted by
request source 1 (channel scan source). Its bits are used to update the pending register
CRPR1, when the load event occurs.
Note: Writes to register CRPR1 also update CRCR1 and generate a load event.
ADC_CRCR1
Conversion Request Control Register 1(CAH)
RMAP: 0, PAGE: 6
Reset Value: 00H
7
6
5
4
3
2
1
0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type Description
CHx
(x = 0 - 7)
x
rwh
User’s Manual
ADC, V2.2
Channel Bit x
Each bit corresponds to one analog channel, the
channel number x is defined by the bit position in the
register. The corresponding bit x in the conversion
request pending register will be overwritten by this bit
when the load event occurs.
The analog channel x will not be requested for
0B
conversion by the parallel request source.
1B
The analog channel x will be requested for
conversion by the parallel request source.
Note: Bits 4-7 are only applicable for devices that
have 8 ADC channels. For channels not
implemented, these bits should be treated as
Reserved bits of type ‘r’ which returns ‘0’ if read and
should be written with 0.
22-23
V1.1, 2010-09
XC83x
Analog to Digital Converter
The Conversion Request Pending Register indicates which channels of request source
1 (channel scan source) are requesting a conversion. Its bits are updated from pending
register CRCR1, when the load event occurs.
Note: Writes to register CRPR1 also update CRCR1 and generate a load event.
ADC_CRPR1
Conversion Request Pending Register 1(CBH)
RMAP: 0, PAGE: 6
Reset Value: 00H
7
6
5
4
3
2
1
0
CHP7
CHP6
CHP5
CHP4
CHP3
CHP2
CHP1
CHP0
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type Description
CHPx
(x = 0 - 7)
x
rwh
Channel Pending Bit x
Write view:
A write to this address targets the bits in register
CRCR1.
Read view:
Each bit corresponds to one analog channel; the
channel number x is defined by the bit position in the
register.
The arbiter automatically resets (at start of
conversion) or sets it again (at abort of conversion)
for the corresponding analog channel.
The analog channel x is not requested for
0B
conversion by the parallel request source.
The analog channel x is requested for
1B
conversion by the parallel request source.
Note: Bits 4-7 are only applicable for devices that
have 8 ADC channels. For channels not
implemented, these bits should be treated as
Reserved bits of type ‘r’ which returns ‘0’ if read and
should be written with 0.
0
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
Note: The bits that can be read from this register location are generally ‘rh’. They cannot
be modified directly by a write operation. A write operation modifies the bits in
User’s Manual
ADC, V2.2
22-24
V1.1, 2010-09
XC83x
Analog to Digital Converter
CRCR1 (that is why they are marked ‘rwh’) and leads to a load event one clock
cycle later.
22.6.2
Queued Request Source Handling
A queued request source supports short conversion sequences of arbitrary channels
(contrary to a scan request source with a fixed conversion order for the enabled
channels). The programmed sequence is stored in a queue buffer (based on a FIFO
mechanism). The requested channel numbers are entered via the queue input, while
queue stage 0 defines the channel to be converted next.
A conversion request is only issued to the request source arbiter if a valid entry is stored
in queue stage 0.
If the arbiter aborts a conversion triggered by a queued request source due to higher
priority requests, the corresponding conversion parameters are automatically saved in
the backup stage. This ensures that an aborted conversion is not lost but takes part in
the next arbitration round (before stage 0).
The trigger and gating unit generates trigger events from the selected external (outside
the ADC) trigger. For example, a timer unit can issue a request signal to synchronize
conversions to PWM events.
Trigger events start a queued sequence and can be generated either via software or via
the selected hardware triggers. The occurrence of a trigger event is indicated by bit
QSRx.EV. This flag is cleared when the corresponding conversion is started or by writing
to bit QMRx.CEV.
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ADC, V2.2
22-25
V1.1, 2010-09
XC83x
Analog to Digital Converter
trigger inputs
REQTRx_[7:0]
request
source
event
REQTR x
queue input
trigger &
gating unit
intermediate
queue stages
E
V
queue stage 0
w ait for
trigger
refill
request
request handling
abort
sequential
request source
restart
status
request
source
arbiter
backup stage
AD C_seq _ reqsrc
Figure 22-8 Queued Request Source
A sequence is defined by entering conversion requests into the queue input register
(ADC_QINR0). Each entry selects the channel to be converted and can enable an
external trigger, generation of an interrupt, and an automatic refill (i.e. keep this entry in
the queue after conversion). The entries are stored in the queue buffer stages.
The content of stage 0 (ADC_Q0R0) selects the channel to be converted next. When the
requested conversion is started, the contents of this queue stage is invalidated and
copied to the backup stage. Then the next queue entry can be handled (if available).
Note: The contents of the queue stages cannot be modified directly, but only by writing
to the queue input or by flushing the queue.
If all queue entries have automatic refill selected, the defined conversion
sequence can be repeated without re-programming.
Properties of the Queued Request Source
The ADC kernels of the XC83x provide one queued request source with buffer size:
•
Queued request source 0 provides 4 buffer stages and can handle sequences of up
to 4 input channel entries. It supports short application-specific conversion
sequences, especially for timing-critical sequences containing also multiple
conversions of the same channel.
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ADC, V2.2
22-26
V1.1, 2010-09
XC83x
Analog to Digital Converter
Queued Source Operation
Configure the queued request source by executing the following actions:
•
•
•
Define the sequence by writing the entries to the queue input ADC_QINR0. Initialize
the complete sequence before enabling the request source, because with enabled
refill feature, software writes to QINRx are not allowed.
If hardware trigger is desired, select the appropriate trigger inputs by programming
ADC_ETRCR.
Enable the trigger by programming bitfield ENGT in register ADC_QMR0.
Enable the corresponding arbitration slot (0) to accept conversion requests from the
queued source (see register ADC_PRAR).
Start a queued sequence by generating a trigger event:
•
•
•
If a hardware trigger is selected and enabled, generate the configured transition at
the selected input signal, e.g. from a timer or an input pin.
Generate a software trigger event by setting QMRx.TREV = 1.
Write a new entry to the queue input of an empty queue. This leads to a (new) valid
queue entry that is forwarded to queue stage 0 and starts a conversion request (if
enabled by QMRx.ENGT and without waiting for an external trigger).
Note: If the refill mechanism is activated, a processed entry is automatically reloaded
into the queue. This permanently repeats the respective sequence (autoscan).
In this case, do not write to the queue input while the queued source is running.
Write operations to a completely filled queue are ignored.
Stop or abort an ongoing queued sequence by executing the following actions:
•
•
Disable the corresponding arbitration slot (0) in the arbiter. This does not modify the
queue entries, but only prevents the arbiter from accepting requests from the request
handling block.
Disable the queued source by clearing bitfield ENGT = 0B.
– Invalidate the next pending queue entry by setting bit QMRx.CLRV = 1.
If the backup stage contains a valid entry, this one is invalidated, otherwise stage 0
is invalidated.
– Remove all entries from the queue by setting bit QMRx.FLUSH = 1.
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ADC, V2.2
22-27
V1.1, 2010-09
XC83x
Analog to Digital Converter
Queue Request Source Events and Interrupts
A request source event of a queued source occurs when a conversion is finished. A
request source event interrupt can be generated based on a request source event
according to the structure shown in Figure 22-9. If a request source event is detected, it
sets the corresponding indication flag in register ADC_EVINFR. The indication flags can
be cleared by SW by writing a 1 to the corresponding bit position in register
ADC_EVINCR.
The interrupt enable bit is taken from stage 0 for a normal sequential conversion, or from
the backup stage for a repeated conversion after an abort.
The service request output line SRx becomes activated each time the related request
source event is detected (and enabled by Q0Rx.ENSI, or QBURx.ENSI respectively).
The request source events and the result events share the same registers. The request
source event is located at the bit position in register ADC_EVINFR:
•
Event 0: Request source event of queued source 0 (in arbitration slot 0)
request source
event
indication flag
request source
event
interrupt enable
EVINF R.
EVIN F0
Q 0R 0.
ENSI
set
conversion
finished
triggered by
request
source
request source
event
0
to SR0
1
QBUR 0.
ENSI
QBU R0.
V
ADC_ seq _source _int
Figure 22-9 Interrupt Generation of a Queued Request Source
User’s Manual
ADC, V2.2
22-28
V1.1, 2010-09
XC83x
Analog to Digital Converter
The Queue Mode Register configures the operating mode of a queued request source.
ADC_QMR0
Queue Mode Register
RMAP: 0, PAGE: 6
(CDH)
Reset Value: 00H
7
6
5
4
3
2
1
0
CEV
TREV
FLUSH
CLRV
0
ENTR
0
ENGT
w
w
w
w
r
rw
r
rw
Field
Bits
Type Description
ENGT
0
rw
Enable Gate
This bit enables the gating functionality for the
request source.
0B
The gating line is permanently 0. The source is
switched off.
The gating line is permanently 1. The source is
1B
switched on.
ENTR
2
rw
Enable External Trigger
This bit enables the external trigger possibility. If
enabled, bit EV is set if a rising edge is detected at
the external trigger input REQTR when at least one
V bit is set in register Q0R0 or QBUR0.
The external trigger is disabled.
0B
The external trigger is enabled.
1B
CLRV
4
w
Clear V Bits
No action
0B
1B
The bit V in register Q0R0 or QBUR0 is reset.
If QBUR0.V = 1, then QBUR0.V is reset. If
QBUR0.V = 0, then Q0R0.V is reset.
FLUSH
5
w
Flush Queue
No action
0B
1B
All bits V in the queue registers and bit EV are
reset. The queue contains no more valid entry.
TREV
6
w
Trigger Event
0B
No action
1B
A trigger event is generated by software. If the
source waits for a trigger event, a conversion
request is started.
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ADC, V2.2
22-29
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
CEV
7
w
Clear Event Bit
No action
0B
Bit EV is cleared.
1B
0
1, 3
r
Reserved
Returns 0 if read; should be written with 0.
Note: Before SW modifies the queue content by QMR.CLRV or QMR.FLUSH, all HW
actions related to this queue have to be finished. Therefore, the arbitration slot has
to be disabled and SW has to wait for at least two arbitration rounds (to be sure
that this request source can no longer be an arbitration winner). Then, it has to
check ADC_GLOBCTR.BUSY to be sure that a conversion triggered by this
request source is no longer running. Then SW can read QBURx and Q0Rx and
can start modification of the queue content.
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
The Queue Status Register indicates the current status of the queued source. The filling
level and the empty information refer to the queue intermediate stages (if available) and
to the queue register 0. An aborted conversion stored in the backup stage is not
indicated by these bits (therefore, see QBURx.V).
ADC_QSR0
Queue Status Register
RMAP: 0, PAGE: 6
7
6
(CEH)
Reset Value: 20H
5
4
3
2
1
0
0
EMPTY
EV
0
FILL
r
rh
rh
r
rh
Field
Bits
Type Description
FILL
[1:0]
rh
Filling Level
This bit field indicates how many entries are valid in
the sequential-sourced queue. It is incremented
each time a new entry is written to QINR0,
decremented each time a requested conversion has
been finished. A new entry is ignored if the filling
level has reached its maximum value. If EMPTY bit
= 1, there are no valid entries in the queue.
00B If EMPTY bit = 0, there is 1 valid entry in the
queue.
01B If EMPTY bit = 0, there are 2 valid entries in the
queue.
10B If EMPTY bit = 0, there is 3 valid entry in the
queue.
11B If EMPTY bit = 0, there are 4 valid entries in the
queue.
EV
4
rh
Event Detected
This bit indicates that an event has been detected
while V = 1. Once set, this bit is reset automatically
when the requested conversion is started.
An event has not been detected.
0B
An event has been detected.
1B
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ADC, V2.2
22-31
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
EMPTY
5
rh
Queue Empty
This bit indicates if the sequential source contains
valid entries. A new entry is ignored if the queue is
filled (EMPTY = 0).
The queue is filled with 'FILL+1' valid entries in
0B
the queue.
The queue is empty, no valid entries are
1B
present in the queue.
0
[3:2],
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
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ADC, V2.2
22-32
V1.1, 2010-09
XC83x
Analog to Digital Converter
The Queue Input Register is the entry point for conversion requests of a queued request
source.
ADC_QINR0
Queue Input Register 0
RMAP: 0, PAGE: 6
(D2H)
4
Reset Value: 00H
7
6
5
3
2
1
0
EXTR
ENSI
RF
0
REQCHNR
w
w
w
r
w
Field
Bits
Type Description
REQCHNR
[2:0]
w
Request Channel Number
This bit field defines the requested channel number.
Note: Bit 2is only applicable for devices that have 8
ADC channels. For channels not implemented, these
bits should be treated as Reserved bits of type ‘r’
which returns ‘0’ if read and should be written with 0.
RF
5
w
Refill
This bit defines the refill functionality.
ENSI
6
w
Enable Source Interrupt
This bit defines the source interrupt functionality.
EXTR
7
w
External Trigger
This bit defines the external trigger functionality.
0
[4:3]
r
Reserved
Returns 0 if read; should be written with 0.
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
The queue registers 0 monitor the status of the pending request (queue stage 0).
ADC_Q0R0
Queue 0 Register 0
RMAP: 0, PAGE: 6
(CFH)
Reset Value: 00H
7
6
5
4
3
2
1
0
EXTR
ENSI
RF
V
0
REQCHNR
rh
rh
rh
rh
r
rh
Field
Bits
Type Description
REQCHNR
[2:0]
rh
Request Channel Number
This bit field indicates the channel number that will
be or is currently requested.
Note: Bit 2is only applicable for devices that have 8
ADC channels. For channels not implemented, these
bits should be treated as Reserved bits of type ‘r’
which returns ‘0’ if read and should be written with 0.
V
4
rh
Request Channel Number Valid
This bit indicates if the data in REQCHNR, RF, ENSI
and EXTR is valid. Bit V is set when a valid entry is
written to the queue input register QINR0 (or by an
update by intermediate queue registers).
The data is not valid.
0B
The data is valid.
1B
RF
5
rh
Refill
This bit indicates if the pending request is discarded
after being executed (conversion start) or if it is
automatically refilled in the top position of the
request queue.
The request is discarded after conversion
0B
start.
The request is refilled in the queue after
1B
conversion start.
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
ENSI
6
rh
Enable Source Interrupt
This bit indicates if a source interrupt will be
generated when the conversion is completed. The
interrupt trigger becomes activated if the conversion
requested by the source has been completed and
ENSI = 1.
The source interrupt generation is disabled.
0B
1B
The source interrupt generation is enabled.
EXTR
7
rh
External Trigger
This bit defines if the conversion request is sensitive
to an external trigger event.
The event flag (bit EV) indicates if an external event
has taken place and a conversion can be requested.
Bit EV is not used to start conversion request.
0B
1B
Bit EV is used to start conversion request.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
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ADC, V2.2
22-35
V1.1, 2010-09
XC83x
Analog to Digital Converter
The Queue Backup Registers monitor the status of an aborted queued request.
ADC_QBUR0
Queue Backup Register 0
RMAP: 0, PAGE: 6
(D2H)
Reset Value: 00H
7
6
5
4
3
2
1
0
EXTR
ENSI
RF
V
0
REQCHNR
rh
rh
rh
rh
r
rh
Field
Bits
Type Description
REQCHNR
[2:0]
rh
Request Channel Number
This bit field is updated by bit field Q0R0.REQCHNR
when the conversion requested by Q0R0 is started.
Note: Bit 2 is only applicable for devices that have 8
ADC channels. For channels not implemented, these
bits should be treated as Reserved bits of type ‘r’
which returns ‘0’ if read and should be written with 0.
V
4
rh
Request Channel Number Valid
This bit indicates if the data in REQCHNR, RF, ENSI,
and EXTR is valid. Bit V is set if a running conversion
is aborted. It is reset when the conversion is started.
The backup register does not contain valid
0B
data, because the conversion described by
this data has not been aborted.
The data is valid. The aborted conversion is
1B
requested before taking into account what is
requested by Q0R0.
RF
5
rh
Refill
This bit is updated by bit Q0R0.RF when the
conversion requested by Q0R0 is started.
ENSI
6
rh
Enable Source Interrupt
This bit is updated by bit Q0R0.ENSI when the
conversion requested by Q0R0 is started.
EXTR
7
rh
External Trigger
This bit is updated by bit Q0R0.EXTR when the
conversion requested by Q0R0 is started.
0
3
r
Reserved
Returns 0 if read; should be written with 0.
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
Note: Registers QBURx share addresses with registers QINRx.
Read operations return the status bits from register QBURx. Write operations
target the control bits in register QINRx.
22.6.3
Hardware Trigger Selection
Each request source can be activated either by software or by a hardware trigger signal.
The hardware triggers can be derived from several module signals or port inputs.
The external trigger control register contains bits to select the external trigger input signal
source.
ADC_ETRCR
External Trigger Control Register
RMAP: 0, PAGE: 4
7
6
5
(D3H)
4
Reset Value: 00H
3
2
1
0
0
ETRSEL1
ETRSEL0
r
rw
rw
Field
Bits
Type Description
ETRSEL0,
ETRSEL1
[2:0],
[5:3]
rw
External Trigger Selection for Request Source x
This bit field defines which external trigger input
signal is selected.
000B The trigger input REQTRxA is selected.
001B The trigger input REQTRxB is selected.
010B The trigger input REQTRxC is selected.
011B The trigger input REQTRxD is selected.
100B The trigger input REQTRxE is selected.
101B The trigger input REQTRxF is selected.
110B The trigger input REQTRxG is selected.
111B The trigger input REQTRxH is selected.
0
[7:6]
r
Reserved
Returns 0 if read; should be written with 0.
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ADC, V2.2
22-37
V1.1, 2010-09
XC83x
Analog to Digital Converter
22.7
Request Source Arbitration
The request source arbiter regularly polls the request sources, one after the other, for
pending conversion requests. Each request source is assigned to a certain time slot
within an arbitration round, called arbitration slot.
The priority of each request source is user-configurable via register ADC_PRAR, so the
arbiter can select the next channel to be converted, in the case of concurrent requests
from multiple sources, according to the application requirements.
A disabled or unused arbitration slot is considered empty and does not take part in the
arbitration. After reset, all slots are disabled and must be enabled (register ADC_PRAR)
to take part in the arbitration process.
Figure 22-10 summarizes the arbitration sequence. An arbitration round consists of one
arbitration slot for each available request source. The synchronization source is always
evaluated in the last slot and has a higher priority than all other sources. Additional
arbitration slots can be inserted to adjust the timing to other products (not required for
the XC83x). At the end of each arbitration round, the arbiter has determined the highest
priority conversion request.
If a conversion is started in an arbitration round, this arbitration round does not deliver
an arbitration winner.
In the XC83x, the following request sources are available:
•
•
•
Arbitration slot 0: 4-stage sequential source, 4-stage sequences in arbitrary order
Arbitration slot 1: 4/8-channel scan source, sequences in defined order
Last arbitration slot: Synchronization source, synchronized conversion requests
from another ADC kernel (always handled with the highest priority in a
synchronization slave kernel).
arbitration round
arbitration
slot 0
arbitration
slot 1
polling of
request
source 0
polling of
request
source 1
arbitration
slot 2
arbitration
slot 3
Not used
check for
synchronized
start request
arbitration
winner
found
conversion
can be
started
ADC_ arbiter _round
Figure 22-10 Arbitration Round
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Analog to Digital Converter
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Analog to Digital Converter
22.7.1
Arbiter Timing
The timing of the arbiter (i.e. of an arbitration round) is determined by the number of
arbitration slots within an arbitration round and by the duration of an arbitration slot.
An arbitration round consist of 4arbitration slots
The duration of an arbitration slot is configurable tSlot = fADC.
The duration of an arbitration round, therefore, is tARB = N × tSlot (N = number of slots).
The period of the arbitration round introduces a timing granularity to detect an incoming
conversion request signal and the earliest point to start the related conversion. This
granularity can introduce a jitter of maximum one arbitration round. The jitter can be
reduced by minimizing the period of an arbitration round.
To achieve a reproducible reaction time (constant delay without jitter) between the
trigger event of a conversion request (e.g. by a timer unit or due to an external event)
and the start of the related conversion, mainly the following two options exist. For both
options, the converter has to be idle and other conversion requests must not be pending
for at least one arbiter round before the trigger event occurs:
•
•
If bit ADC_PRAR.ARBM = 0, the arbiter runs permanently.
The trigger for the conversion triggers has to be generated synchronously to the
arbiter timing. Incoming triggers should have exactly n-times the granularity of the
arbiter (n = 1, 2, 3,...). In order to allow some flexibility, the duration of an arbitration
slot can be programmed in cycles of fADC.
If bit ADC_PRAR.ARBM = 1, the arbiter stops after an arbitration round when no
conversion request have been found pending any more. The arbiter is started again
if at least one enabled request source indicates a pending conversion request. The
trigger of a conversion request does need not to be synchronous to the arbiter timing.
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XC83x
Analog to Digital Converter
22.7.2
Request Source Priority and Conversion Start Mode
Each request source has a configurable priority, so the arbiter can resolve concurrent
conversion requests from different sources. The request with the highest priority is
selected for conversion. These priorities can be adapted to the requirements of a given
application (see register ADC_PRAR).
The Conversion Start Mode determines the handling of the conversion request that has
won the arbitration.
The Priority and Arbitration Register defines the request source priority, the conversion
start mode for each request source and enables/disables the arbitration slots to control
whether or not conversion requests are considered.
Note: Only change priority and conversion start mode settings of a request source while
this request source is disabled, and a currently running conversion requested by
this source is finished.
ADC_PRAR
Priority and Arbitration Register
RMAP: 0, PAGE: 0
(CCH)
Reset Value: 00H
7
6
5
4
3
2
1
0
ASEN1
ASEN0
0
ARBM
CSM1
PRIO1
CSM0
PRIO0
rw
rw
r
rw
rw
rw
rw
rw
Field
Bits
Type Description
PRIO0
0
rw
Priority of Request Source 0
This bit defines the priority of the sequential request
source 0.
0B
Low priority
High priority
1B
CSM0
1
rw
Conversion Start Mode of Request Source 0
This bit defines the conversion start mode of the
sequential request source 0.
0B
The wait-for-start mode is selected.
1B
The cancel-inject-repeat mode is selected.
PRIO1
2
rw
Priority of Request Source 1
This bit defines the priority of the parallel request
source 1.
0B
Low priority
High priority
1B
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XC83x
Analog to Digital Converter
Field
Bits
Type Description
CSM1
3
rw
Conversion Start Mode of Request Source 1
This bit defines the conversion start mode of the
parallel request source 1.
The wait-for-start mode is selected.
0B
1B
The cancel-inject-repeat mode is selected.
ARBM
4
rw
Arbitration Mode
This bit defines which arbitration mode is selected.
0B
Permanent arbitration (default).
Arbitration started by pending conversion
1B
request
ASEN0,
ASEN1
6,
7
rw
Arbitration Slot x Enable
Each bit enables an arbitration slot of the arbiter
round. ASEN0 enables arbitration slot 0, ASEN1
enables slot 1.
If an arbitration slot is disabled, a pending
conversion request of a request source connected to
this slot is not taken into account for arbitration.
The corresponding arbitration slot is disabled.
0B
The corresponding arbitration slot is enabled.
1B
0
5
r
Reserved
Returns 0 if read; should be written with 0.
Note: If the arbiter shall not be running continuously (ARBM = 1), no conversion request
of the request source for arbitration slot x must be active. Clear conversion
requests of the related request source before disabling an arbitration slot.
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XC83x
Analog to Digital Converter
Conversion Start Mode
When the arbiter has selected the request to be converted next, the handling of this
channel depends on the current activity of the converter:
•
•
•
Converter is currently idle: the conversion of the arbitration winner is started
immediately.
Current conversion has same or higher priority: the current conversion is completed,
the conversion of the arbitration winner is started after that.
Current conversion has lower priority: the action is user-configurable:
– Wait-for-start mode: the current conversion is completed, the conversion of the
arbitration winner is started after that. This mode provides maximum throughput,
but can produce a jitter for the higher priority conversion.
Example in Figure 22-11:
Conversion A is requested (t1) and started (t2). Conversion B is then requested
(t3), but started only after completion of conversion A (t4).
– Cancel-inject-repeat mode: the current conversion is aborted, the conversion of
the arbitration winner is started after the abortion (1 … 3 fADCI cycles).
The aborted conversion request is restored in the corresponding request source
and takes part again in the next arbitration round. This mode provides minimum
jitter for the higher priority conversions, but reduces the overall throughput.
Example in Figure 22-11:
Conversion A is requested (t6) and started (t7). Conversion B is then requested
(t8) and started (t9), while conversion A is aborted but requested again. When
conversion B is complete (t10), conversion A is restarted.
Exception: If both requests target the same result register with wait-for-read mode
active (see Section 22.10), the current conversion cannot be aborted.
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XC83x
Analog to Digital Converter
t1
t3
t6
t8
request
channel B
request
channel A
conversions
A
t2
B
A
t4
t5
w ait-for-start mode
t7
B
t9
A
t10
t11
cancel-inject-repeat mode
ADC_conv _ starts
Figure 22-11 Conversion Start Modes
The conversion start mode can be individually programmed for each request source by
bits in register ADC_PRAR and is applied to all channels requested by the source. In
this example, channel A is issued by a request source with a lower priority than the
request source requesting the conversion of channel B.
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XC83x
Analog to Digital Converter
22.8
Analog Input Channel Configuration
For each analog input channel, a number of parameters can be configured that control
the conversion of this channel. After a channel has won the arbitration, its parameters
are applied to the converter. The channel control registers (CHCTRx on Page 22-48)
define the following parameters:
•
•
•
•
Conversion parameters: The input class defines sample time and data width. All
channels is using the same input class.
Reference selection: Three types of internal reference are available for selection
ranging from internal 1.2V and Vddp 3.3/5V. The reference selection determines the
conversion conversion mode of the ADC, i.e single ended or differential mode. See
Section 22.8.1
Please note that low reference voltages lead to small granularity. As a consequence
the resulting TUE increases due to noise effects.
Result target: The conversion result can be stored in one of 4 result registers.
Channel event handling: Channel events can be restricted to results inside or
outside a defined area of values (limit checking).
In addition to the general channel control, the ADC kernel supports a mechanism
(named alias feature, see Section 22.8.4) to redirect a conversion request to another
channel number.
22.8.1
Reference Selection
The conversion result of the ADC is always reference to a reference voltage. The
maximum digital result value (full scale) is obtained if the analog input voltage equals the
reference voltage. In order to support more than one measurement range with full scale
digital representation, the user can select between three conversion modes which are:
•
•
•
Single ended measurement with ADC reference connected internally to VDDP and
VSSP. See Figure 22-12
Differential like measurement wth ADC reference connected to internal 1.2V voltage
reference and ground reference taken from CH0. See Figure 22-13
Single ended measurement with ADC reference connected to internal 1.2V voltage
reference and VSSP. See Figure 22-14
In single ended ADC conversion with reference to Vddp and Vssp voltage, the ADC
reference voltage is internally connected to Vddp and Vssp voltage. See Figure 22-12
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XC83x
Analog to Digital Converter
Vddp
AD C kernel
va_ref
va_gnd
result
handling
AD
converter
request
control
conversion
control
AIN CH0
AIN CH1
...
Vssp
AIN CH3/7
Interrupt
generation
ADC_single _ended_measurement2.vsd
Figure 22-12 Single ended measurement with Vddp, Vssp
In differential like ADC conversion with internal 1.2V voltage reference and ground
reference taken from CH0. CH0 cannot be used for ADC measurement. CH0 is used as
ground reference for ADC which may be connected externally to increase measurement
accuracy. See Figure 22-13. The digital features of CH0 maybe reused for other
channels with the alias function. See Section 22.8.4. Please note that a setup time is
needed between conversions, when this mode is used. Refer to the Data Sheet for the
value of the setup time.
V 1 .2VREF
ADC kernel
va_altref
va_altgnd
V 1.2VGN D
AD
converter
request
control
conversion
control
AIN CH0
AIN CH1
...
result
handling
AIN CH3/7
Interrupt
generation
ADC_differential_like _1.2Vref_ch0gnd_measurement2.vsd
Figure 22-13 Differential like measurement with internal 1.2V voltage reference,
and CH0 gnd.
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XC83x
Analog to Digital Converter
In single ended ADC conversion with 1.2V voltage reference and Vssp, CH0 can be used
for ADC measurement. See Figure 22-14
V 1.2VREF
ADC kernel
va_altref
va_altgnd
Vssp
AD
converter
request
control
conversion
control
AIN CH0
AIN CH1
...
result
handling
AIN CH3/7
Interrupt
generation
ADC_single _ended_1.2Vref_vssp _measurement2.vsd
Figure 22-14 Single ended measurement with internal 1.2V voltage reference and
Vssp.
The reference selection for each input channel is selected by programming
ADC_CHCTRx.REFSEL bits. Please note that a setup time is needed between
conversions, when this mode is used. Refer to the Data Sheet for the value of the setup
time.
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XC83x
Analog to Digital Converter
22.8.2
Channel Parameters
Each analog input channel is configured by its associated channel control register. The
sample time and the result width are selected via an input class.
The Channel Control Registers select the control parameters for each input channel, it
contain bits to select the targetted result register, selection of internal reference voltages,
controls the limit check mechanism and boundary flags.
ADC_CHCTRx (x = 0 - 2)
Channel x Control Register
RMAP: 0, PAGE: 1
7
6
5
(CAH + x * 1)
4
Reset Value: 00H
3
2
1
0
BFEN
LCC
REFSEL
RESRSEL
rw
rw
rw
rw
Field
Bits
Type Description
RESRSEL
[1:0]
rw
Result Register Selection
This bit field defines which result register will be the
target of a conversion of this channel.
00B The result register 0 is selected.
01B The result register 1 is selected.
10B The result register 2 is selected.
11B The result register 3 is selected.
REFSEL
[3:2]
rw
Reference Input Selection
This bit field defines the reference source for this
channel.
00B Analog to digital conversion is done with
reference to VDDP, VSSP (See Figure 22-12).
01B Analog to digital conversion is done with
internal 1.2V and CH0 as the ground reference
(See Figure 22-13)1).
10B Analog to digital conversion is dones with
internal 1.2V and Vssp (See Figure 22-14)1).
11B Reserved; do not use this combination
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XC83x
Analog to Digital Converter
Field
Bits
Type Description
LCC
[6:4]
rw
Limit Check Control
This bit field defines the behavior of the limit
checking mechanism. See Section 22.8.3
000B Never
001B Result outside area I
010B Result outside area II
011B Result outside area III
100B Always (boundaries disregarded)
101B Result within area I
110B Result within area II
111B Result within area III
BFEN
7
rw
Boundary Flags Enable
This bit is the gating control for the boundary flags
ADC_BF<2:0> signal.
0B
Boundary flag signal is disabled for the
corresponding channel.
Boundary flag signal is enabled for the
1B
corresponding channel.
1) A setup time is needed between conversions when using this mode. Refer to Data Sheet for the required setup
time.
ADC_CHCTRx (x = 3 - 5)
Channel x Control Register
ADC_CHCTRx (x = 6 - 7)
Channel x Control Register
RMAP: 0, PAGE: 1
7
6
5
(CAH + x * 1)
Reset Value: 00H
(CCH + x * 1)
Reset Value: 00H
4
3
2
1
0
0
LCC
REFSEL
RESRSEL
r
rw
rw
rw
Note: ADC_CHCTR4 - 7 are only for devices that have 8 ADC channels. For channels
not implemented, these bits should be treated as Reserved bits of type ‘r’ which
returns ‘0’ if read and should be written with 0.
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XC83x
Analog to Digital Converter
Field
Bits
Type Description
RESRSEL
[1:0]
rw
Result Register Selection
This bit field defines which result register will be the
target of a conversion of this channel.
00B The result register 0 is selected.
01B The result register 1 is selected.
10B The result register 2 is selected.
11B The result register 3 is selected.
REFSEL
[3:2]
rw
Reference Input Selection
This bit field defines the reference source for this
channel.
00B Analog to digital conversion is done with
reference to VDDP, VSSP (See Figure 22-12).
01B Analog to digital conversion is done with
internal 1.2V and CH0 as the ground reference
(See Figure 22-13)1).
10B Analog to digital conversion is dones with
internal 1.2V and Vssp (See Figure 22-14)1).
11B Reserved; do not use this combination
LCC
[6:4]
rw
Limit Check Control
This bit field defines the behavior of the limit
checking mechanism. See Section 22.8.3
000B Never
001B Result outside area I
010B Result outside area II
011B Result outside area III
100B Always (boundaries disregarded)
101B Result within area I
110B Result within area II
111B Result within area III
0
7
r
Reserved
Returns 0 if read; should be written with 0.
1) A setup time is needed between conversions when using this mode. Refer to Data Sheet for the required setup
time.
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Analog to Digital Converter
An input class defines the length of the sample phase and the resolution of the
conversion.
The default settings select the minimum sample phase length of 2 fADCI cycles.
The Input Class Registers select the sample time and the resolution for each input class.
ADC_INPCR0
Input Class 0 Register
RMAP: 0, PAGE: 0
7
6
(CEH)
5
4
Reset Value: 00H
3
2
1
0
STC
r
rw
0
Field
Bits
Type Description
STC
[3:0]
rw
Sample Time Control
This bit field defines the additional length of the
sample time, given in terms of fADCI clock cycles.
A sample time of 2 analog clock cycles is extended
by the programmed value.
0
[7:4]
r
Reserved
Returns 0 if read; should be written with 0.
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Analog to Digital Converter
22.8.3
Limit Checking
The limit checking mechanism automatically compares each conversion result to two
boundary values (boundary A and boundary B). For each channel, the user can select
these boundaries from a set of 2 programmable values (ADC_LCBR0 to ADC_LCBR1).
A channel event is then generated depending on the two comparisons. The conditions
are selected via bitfield LCC in the respective channel control register.
boundaries
A
channel
num ber
analog part
arbiter
conversion
finished
GLOBC T R .
C LC IEN
B
limit
checking
channel
event
conversion result
ADC 8_ channel _events _overv
Figure 22-15 Channel Event Generation
The two selectable boundaries split the conversion result range into three areas:
Area I: Conversion result below or equal to both boundaries.
Area II: Conversion result above one boundary and below/equal to other boundary.
Area III: Conversion result above both boundaries.
conv ersion result range
for n bit res olution
•
•
•
area III
area II
area I
conversion results with
channel events
conversion results without
channel events
conversion results with
channel events
2 n -1
boundary B
boundary A
0
ADC_limit_check
Figure 22-16 Limit Checking
The shown example for limit checking generates channel events only if the conversion
results are outside the normal operating range defined by area II (LCC = 010B).
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Analog to Digital Converter
If only two areas are required, use the same boundary register for boundary A and
boundary B. In this case, area II is empty and two result ranges are available. Avoid
LCC = x10B in this case.
Typical applications for limit checking are monitoring tasks (temperature, pressure,
current, etc.) where the real value of a result is less important than its range. As long as
the measured values are within their defined valid range, no CPU action is required. A
channel event should be generated only if the conversion result is outside the valid range
to indicate a critical condition (over-temperature, loss of pressure, etc.).
The CPU load is minimized if the conversions of the analog input signals to be monitored
are part of an auto-scan sequence autonomously triggered on a regular time base.
Under normal conditions the CPU load here is zero.
Note: In the case of an over-current protection, the channel event can be used to disable
PWM generation to reduce the current (in the XC83x, an interrupt output line of
the ADC module is connected to a corresponding input of the CCU6x units to allow
fast reactions without CPU intervention).
Boundary Flag Control
The limit checking mechanism can be configured to automatically control the boundary
flags. A boundary flag will be set when the conversions result is within area III, and will
be cleared when the conversion result is within area I.
Figure 22-17 Boundary Flag Control
The difference between the two boundary values defines a hysterisis for setting/clearing
the boundary flags.
Using this feature on three channels that onitor linear hall elements can produce signals
to feed the three hall position inputs of a CCU6x unit.
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Analog to Digital Converter
The Limit Check Boundary Registers define compare values (boundaries) for the limit
checking unit.
ADC_LCBR0
Limit Check Boundary Register 0
ADC_LCBR1
Limit Check Boundary Register 1
RMAP: 0, PAGE: 0
7
6
5
(CDH)
Reset Value: 70H
(CFH)
Reset Value: B0H
4
3
2
1
0
BOUNDARY
rw
Field
Bits
Type Description
BOUNDARY
[7:0]
rw
22.8.4
Boundary for Limit Checking
This value is compared to the actual conversion
result.
Alias Feature
The alias feature re-directs conversion requests for channels CH0 to other channel
numbers. This means that CH0 are converted with the channel parameters of the
referenced channel instead of with their own. The re-direction feature serves several
purposes:
•
•
•
•
The same signal can be measured twice and the two results (original and re-directed)
can be stored in separate result registers. This allows triggering both conversions
quickly one after the other while data loss is avoided, independent from the CPU
interrupt latency.
The sensor signal is connected to only one input (instead of two). This can save input
pins in low-cost applications and reduces the input leakage to be considered in the
error calculation.
Even if the analog input CH0 is used as alternate gnd (see Figure 22-18), the internal
trigger and data handling features for channel CH0 can be used.
The channel settings for both conversions (of the same signal) can be different in
terms of boundary values, interrupts, etc.
If a queued conversion request source has been set up, a conversion request for
channels CH0 can be easily re-directed to other input channels without flushing the
queue.
Figure 22-18 shows an example where the sensor signal is connected to one input
channel (CHx) but two conversions are triggered (for CHx and CH0). The alias feature
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Analog to Digital Converter
re-directs the conversion request for CH0 to CHx, but taking into account the settings for
CH0. Although the same analog input (CHx) has been measured, the conversion results
can be stored and retrieved from result registers RESRx (conversion triggered for CHx)
and RESR0 (conversion triggered for CH0). Additionally, different interrupts or limit
boundaries can be selected, enabled or disabled.
sensor
CHx
RESRx
ADC
reference
CH0
PWM
timer
RESR0
trigger CH0
trigger CHx
ADC_alias
Figure 22-18 Alias Feature
In typical low-cost AC-drive applications, only one common current sensor is used to
determine the phase currents. Depending on the applied PWM pattern, the measured
value has different meanings and the sample points have to be precisely located in the
PWM period.
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Analog to Digital Converter
The Alias Register specifies replacement channel numbers for CH0, i.e. CH0 will use the
respective channel numbers when requested.
The programmed alias channel number controls the analog input multiplexer (of the
converter). The original channel number controls all other internal actions and the
synchronization request.
ADC_ALR0
Alias Register 0
RMAP: 0, PAGE: 4
7
6
(CFH)
5
4
Reset Value: 00H
3
2
1
0
ALIAS0
r
rw
0
Field
Bits
Type Description
ALIAS0
[2:0]
rw
Alias Value for CH0 Conversion Requests
The channel indicated in this bit field is converted
instead of channel CH0. The conversion is done with
the settings defined for channel CH0. The default for
this is CH0.
Note: Bit 2 is only applicable for devices that have 8
ADC channels. For channels not implemented, these
bits should be treated as Reserved bits of type ‘r’
which returns ‘0’ if read and should be written with 0.
0
[7:3]
r
Reserved
Returns 0 if read; should be written with 0.
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Analog to Digital Converter
22.8.5
Out of Range Comparator
The out of range comparator mechanism is build into every ADC channels and detects
voltages higher or lower than Vddp. Before using the out of range comparator, it has to
be enabled by setting the bits at ADC_ENORC.ENORCx and configuring it to detect
voltage higher or lower than Vddp by setting bits ADC_CNF.CNFx (See Figure 22-19).
C OR C.
CNFx
AIN C H x
EN OR C .
EN OR C x
Out of R ange
C om parator
LOR C .
LOR Ex
SR 1
OR C EVEN T 0-4
ADC_ out _of _ range _ com parator .vsd
Figure 22-19 Out of range comparator
When a voltage out of range event occurs, the event is latched into ADC_LORE.LOREx,
sets an interrupt request through ADC_SR1and triggers other modules through internal
connections with ORCEVENT0-4. Triggering of other modules is only made availble on
ADC_CH0-4.
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Analog to Digital Converter
The bit fields in these registers enables the out of range comparator in the ADC channel.
ADC_ENORC
Enable Out Of Range Comparator Register(D3H)
RMAP: 0, PAGE: 0
Reset Value: 00H
7
6
5
4
3
2
1
0
ENORC7
ENORC6
ENORC5
ENORC4
ENORC3
ENORC2
ENORC1
ENORC0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
ENORCx
(x = 0 - 7)
x
rw
User’s Manual
ADC, V2.2
Enable Out of Range Comparator x
This bit defines if the out of range comparator is
enabled in the corresponding analog input channel.
0B
Out of range comparator disabled.
Out of range comparator enabled.
1B
Note: Bit 4-7 are only applicable for devices that
have 8 ADC channels. For channels not
implemented, these bits should be treated as
Reserved bits of type ‘r’ which returns ‘0’ if read and
should be written with 0.
22-58
V1.1, 2010-09
XC83x
Analog to Digital Converter
The bit fields in this register selects for detection of voltages higher or lower than Vddp
at each input ADC channels that triggers the out of range comparator.
ADC_CNF
Configure Out Of Range Comparator Register(D2H)
RMAP: 0, PAGE: 4
Reset Value: 00H
7
6
5
4
3
2
1
0
CNF7
CNF6
CNF5
CNF4
CNF3
CNF2
CNF1
CNF0
rw
rw
rw
rw
rw
rw
rw
rw
Field
Bits
Type Description
CNFx
(x = 0 - 7)
x
rw
User’s Manual
ADC, V2.2
Out of Range Comparator Flag x
This bit selects CHx rising edge trigger or falling
edge trigger for out of range comparator flag register.
Falling edge trigger out of range event register.
0B
Rising edge trigger out of range event register.
1B
Note: Bit 4-7 are only applicable for devices that
have 8 ADC channels. For channels not
implemented, these bits should be treated as
Reserved bits of type ‘r’ which returns ‘0’ if read and
should be written with 0.
22-59
V1.1, 2010-09
XC83x
Analog to Digital Converter
The bit fields in these registers indicates if a voltage out of range have occured for the
corresponding analog input channels. If a voltage out of range have occured it will be
latched to 1 in this register. The event flag can be cleared by writing a 0 to this register.
ADC_LORE
Latched Out Of Range Event Register (D2H)
RMAP: 0, PAGE: 0
Reset Value: 00H
7
6
5
4
3
2
1
0
LORE7
LORE6
LORE5
LORE4
LORE3
LORE2
LORE1
LORE0
rwh
rwh
rwh
rwh
rwh
rwh
rwh
rwh
Field
Bits
Type Description
LOREx
(x = 0 - 7)
x
rwh
User’s Manual
ADC, V2.2
Latched Out of Range Event x
This bit defines which analog input channel voltage
out of range event have occured. The LORE bit is set
by hardware and can only be cleared by software.
0B
No voltage out of range event for channel x
has not occured. Writing a “0” clears this
register.
A voltage out of range event for channel x has
1B
occured.
Note: Bit 4-7 are only applicable for devices that
have 8 ADC channels. For channels not
implemented, these bits should be treated as
Reserved bits of type ‘r’ which returns ‘0’ if read and
should be written with 0.
22-60
V1.1, 2010-09
XC83x
Analog to Digital Converter
22.8.6
Conversion Timing
The total time required for a conversion depends on several user-definable factors:
•
•
•
•
The ADC conversion clock frequency, where fADCI = fADC / (CTC+3)
The selected sample time, where tS = (2 + STC) × tADCI
(STC = aditional sample time, see also Section 22.5.1)
The selected result width N (8/10 bits)
Synchronization steps done at module clock speed
The conversion time is the sum of sample time, conversion steps, and synchronization.
It can be computed with the following formula:
tCN = tADC x (1 + r x (3 + n + STC))
r = CTC +3,
CTC = Conversion Time Control (ADC_GLOBCTR.CTC)
STC = Sample Time Control (ADC_INPCR0.STC)
n = 8 or 10 (for 8-bit and 10bit conversion respectively)
tADC = 1/ fADC
The frequency at which conversions are triggered also depends on several configurable
factors:
•
•
•
•
The selected conversion time, according to the input class definitions.
Delays induced by cancelled conversions that must be repeated.
The configured arbitration cycle time.
The frequency of external trigger signals, if enabled.
Example1:
When N=10bit, STC=0000B, fADC=48Mhz, CTC=01B
f ADCI = ( 48Mhz ⁄ ( 1 + 3 ) ) = 12Mhz = 83.33ns
(22.1)
t sample = ( 2 + 0 ) × 83.33ns = 166.67ns
(22.2)
User’s Manual
ADC, V2.2
22-61
V1.1, 2010-09
XC83x
Analog to Digital Converter
Table 22-6
Sample Time
Sample Time ADC_INPCR0.STC
(bin)
2 x tADCI
0000B
3 x tADCI
0001B
...
17 x tADCI
1111B
1 
- × ( 1 + ( 1 + 3 ) × ( 3 + 10 + 0 ) ) = 1.104us
t conv =  ----------------48Mhz
User’s Manual
ADC, V2.2
22-62
(22.3)
V1.1, 2010-09
XC83x
Analog to Digital Converter
22.8.7
Channel Events and Interrupts
A channel event interrupt can be generated based on a channel event according to the
structure shown in Figure 22-20. If a channel event is detected, it sets the corresponding
indication flag in register ADC_CHINFR. The indication flags can be cleared by SW by
writing a 1 to the corresponding bit position in register ADC_CHINCR.
channel
event
to SR 0
channel event
flags C HINFR .
C HINF0
ADC_chev0
C HINF1
ADC_chev1
C HINF2
. ..
channel
number
ADC_chev2
C HINF7
Note:
ADC _chev0-2 are internally connected signals to other
modules and is not triggered by CHINSR set channel
interrupt register
ADC _channel _ events _ routing
Figure 22-20 Channel Event Interrupt Generation
User’s Manual
ADC, V2.2
22-63
V1.1, 2010-09
XC83x
Analog to Digital Converter
22.9
Conversion Result Handling
The conversion results of each analog input channel can be stored in one of 4 conversion
result registers (selected by bitfield RESRSEL in the associated channel control register
CHCTRx). This structure provides different locations for the conversion results of
different groups of channels. Depending on the application needs (data reduction, autoscan, alias feature, etc.), the user can distribute the conversion results to minimize CPU
load or to be more tolerant against interrupt latency.
22.9.1
Storage of Conversion Results
Each result register has an individual data valid flag (VFx) associated with it. This flag
indicates when “new” valid data has been stored in the corresponding result register and
can be read out.
Depending of the result register read view (see below), the corresponding valid flag is
automatically cleared when the result is read or remains set.
•
•
Automatically clearing the valid flag provides an easy handshake between result
generation and retrieval. This also supports wait-for-read mode.
Leaving the valid flag set supports debugging by delivering the result value without
disturbing the handshake with the application.
AD conversion
stage
Pointer to
result registers
0-3
set
condition
data reduction
unit / digital low
pass filter
data valid flags
result events
AD C_ result_ handling
Figure 22-21 Conversion Result Storage
Conversion result handling comprises the following functions:
•
•
•
•
Storage of conversion results to user-configurable registers
Wait-for-read mode to avoid loss of data if several channels share one result register
(see Section 22.10)
Result event interrupts (see Section 22.10.1)
Data reduction or anti-aliasing filtering and Digital low pass fitlering (see
Section 22.10.2)
User’s Manual
ADC, V2.2
22-64
V1.1, 2010-09
XC83x
Analog to Digital Converter
Up to 4 result values can be added in each result register. This reduces the frequency of
interrupts generated by the ADC.
•
•
Standard application read view (RESRxL/H):
– 8bit conversion mode with Data Reduction and Digital Low Pass Filter
disabled. (i.e ADC_GLOBCTR.DW=1, RCRx.DRCTR=0, RCRx.DLPF=0)
When this mode is chosen, the targetted result register in ADC_RESRxL (x=0-3)
and ADC_RESRxH (x=0-3) would be shown as Figure 22-22.
In ADC_RESRxL (x=0-3), bits 2-0 indicate the channel number whose conversion
triggered the result event and in ADC_RESRxH (x=0-3) bits 7-0 returns the
conversion result. Reading the result automatically clears the valid flag. This view
is useful only without data reduction.
– 10bit conversion mode with Data Reduction and Digital Low Pass Filter
disabled. (i.e ADC_GLOBCTR.DW=0, RCRx.DRCTR=0, RCRx.DLPF=0)
When this mode is chosen, the targetted result register in ADC_RESRxL (x=0-3)
and ADC_RESRxH (x=0-3) would be shown as Figure 22-23.
In ADC_RESRxL (x=0-3), bits 2-0 indicate the channel number whose conversion
triggered the result event, bits 7-5 return the last 3bits of the conversion result. In
ADC_RESRxH (x=0-3) bits 6-0 returns bit 9-3 of the conversion result. Reading
the result automatically clears the valid flag. This view is useful only without data
reduction
Accumulated application read view (RESRxL/H):
– 8bit conversion mode with Data Reduction Enabled and Digital Low Pass
Filter disabled. (i.e ADC_GLOBCTR.DW=1, RCRx.DRCTR=1, RCRx.DLPF=0)
When this mode is chosen, the targetted result register in ADC_RESRxL (x=0-3)
and ADC_RESRxH (x=0-3) would be shown as Figure 22-24.
After the 1st conversion, in ADC_RESRxL (x=0-3) result register, bits 2-0 indicate
the channel number whose conversion triggered the result event. In
ADC_RESRxH (x=0-3) bits 7-0 returns the conversion result. This allows the result
to be read in a single read. Reading the result automatically clears the valid flag.
At the 2nd conversion onwards, in ADC_RESRxL (x=0-3) result register, bits 2-0
indicate the channel number whose conversion triggered the result event , bit 7
indicate the last bit of the accumulated result. In ADC_RESRxH (x=0-3) bits 7-0
returns bit 8-1of the accumulated result.
– 10bit conversion mode with Data Reduction Enabled and Digital Low Pass
Filter disabled. (i.e ADC_GLOBCTR.DW=0, RCRx.DRCTR=1, RCRx.DLPF=0)
When this mode is chosen, the targetted result register in ADC_RESRxL (x=0-3)
and ADC_RESRxH (x=0-3) would be shown as Figure 22-25.
After the 1st conversion, in ADC_RESRxL (x=0-3) result register, bits 2-0 indicate
the channel number whose conversion triggered the result event, bits 7-5 returns
bits 2-0 of the conversion results. In ADC_RESRxH (x=0-3) bits 6-0 returns bits 93 of the conversion result. Reading the result automatically clears the valid flag.
At the 2nd conversion onwards, in ADC_RESRxL (x=0-3) result register, bits 2-0
User’s Manual
ADC, V2.2
22-65
V1.1, 2010-09
XC83x
Analog to Digital Converter
•
indicate the channel number whose conversion triggered the result event , bit 7-5
returns bits 2-0 of the accumulated result. In ADC_RESRxH (x=0-3) bits 7-0
returns bit 10-3 of the accumulated result.
Digital low pass filtered application read view (RESRxL/H):
10bit conversion mode with Data Reduction Disabled and Digital Low Pass
Filter enabled. (i.e ADC_GLOBCTR.DW=0, RCRx.DRCTR=0, RCRx.DLPF=1) This
mode is only available for 10bit conversions and the Data Reduction Feature cannot
be turned on when the Digital Low Pass Filter is being used, since there is only one
adder.
When this mode is chosen, the targetted result register in ADC_RESRxL (x=0-3) and
ADC_RESRxH (x=0-3) would be shown as Figure 22-26.
In ADC_RESRxL (x=0-3), bits 2-0 indicate the channel number whose conversion
triggered the result event, bits 7-3 returns bits 4-0 of the filtered result. In
ADC_RESRxH (x=0-3) bits 7-0 returns bits 12-5 of the filtered result.
Result Read View (SFR Page 2)
8 -bit conversion (without accum ulation )
R ESR xH
R ESR xL
7
6
5
4
3
2
1
0
7
6
5
4
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
VF DRC
msb
rh
lsb
3
2
1
0
CHNR
rh
adc _res ult_regis ter _v iew_ he_8bit_drc tr_dlpf= 0.v s d
Figure 22-22 8bit, RCRx.DRCTR=0, RCRx.DLPF=0, Result Register View
Result Read View (SFR Page 2)
10-bit conversion (without accum ulation )
7
6
R ESR xH
5 4 3
0
R9
R8
msb
R7
R6
rh
R ESR xL
4 3 2
2
1
0
7
6
5
R5
R4
R3
R2
R1
R0
VF DRC
1
0
CHNR
rh
lsb
adc _ res ult_ regis ter_v iew _he_10 bit_drc tr= 0_dlpf= 0.v s d
Figure 22-23 10bit, RCRx.DRCTR=0, RCRx.DLPF=0, Result Register View
User’s Manual
ADC, V2.2
22-66
V1.1, 2010-09
XC83x
Analog to Digital Converter
Result Read View (SFR Page 2)
8-bit conversion (with accum ulation , 1 st conversion )
R ESR xH
R ESR xL
7
6
5
4
3
2
1
0
7
6
5
4
R7
R6
R5
R4
R3
R2
R1
R0
0
0
0
VF DRC
msb
rh
lsb
7
6
R8
R7
R6
R5
msb
R4
R3
nd
1
0
CHNR
conversion onwards )
1
0
7
6
5
R2
R1
R0
0
0
rh
2
rh
8-bit conversion (accum ulated 9 -bit, 2
R ESR xH
5 4 3 2
3
R ESR xL
4 3 2
VF DRC
lsb
1
0
CHNR
rh
adc _res ult_regis ter_v iew _he _8bit_drc tr=1_ dlpf=0.v s d
Figure 22-24 8bit, RCRx.DRCTR=1, RCRx.DLPF=0, Result Register View
Result Read View (SFR Page 2)
10 -bit conversion (with accum ulation , 1
7
6
R ESR xH
5 4 3
0
R9
R8
R7
msb
R6
2
1
0
7
6
R4
R3
R2
R1
R0
rh
6
R10 R9
0
7
6
5
R8
R5
R4
R3
R2
R1
R0
rh
0
conversion onwards )
1
R6
1
CHNR
rh
nd
2
msb
VF DRC
lsb
R ESR xH
5 4 3
R7
conversion )
R5
10 -bit conversion (accum ulated 11 -bit, 2
7
st
R ESR xL
5 4 3 2
R ESR xL
4 3
2
VF DRC
lsb
1
0
CHNR
rh
adc _ res ult_ regis ter_v iew _he_10 bit_drc tr= 1_dlpf= 0.v s d
Figure 22-25 10bit, RCRx.DRCTR=1, RCRx.DLPF=0, Result Register View
Result Read View (SFR Page 2)
10 -bit conversion (accum ulated 13 -bit filter with D LPF =1)
7
6
R ESR xH
5 4 3
R12 R11 R10 R9
msb
R8
rh
R ESR xL
4 3
2
1
0
7
6
5
R7
R6
R5
R4
R3
R2
lsb
R1
R0
2
1
0
CHNR
rh
adc _ res ult_ regis ter_v iew _he_10 bit_drc tr= 0_dlpf= 1.v s d
Figure 22-26 10bit, RCRx.DRCTR=0, RCRx.DLPF=1, Result Register View
All conversion results are stored in the result registers, the content of the result register
is available at a single page address and data are aligned according to the different
modes being selected.
User’s Manual
ADC, V2.2
22-67
V1.1, 2010-09
XC83x
Analog to Digital Converter
The standard read views of the result registers consists of ADC_RESRxL and
ADC_RESRxH which delivers the conversion result and the related channel number.
The corresponding valid flag is cleared when register RESRx is read (application view).
ADC_RESRxL (x = 0 - 2)
Result Register x Low, View Std. 8-bit or Acc. 8-bit 1st conv.(CAH + x * 2)
Value: 00H
ADC_RESR3L
Result Register 3 Low, View Std. 8-bit or Acc. 8-bit 1st conv.(D2H)
Value:00H
RMAP: 0, PAGE: 2
7
6
5
4
3
2
1
0
VF
DRC
CHNR
r
rh
rh
rh
Reset
Reset
0
Field
Bits
Type Description
CHNR
[2:0]
rh
Channel Number
This bit field contains the channel number of the
latest register update.
Note: Bit 2 is only applicable for devices that have 8
ADC channels. For channels not implemented, these
bits should be treated as Reserved bits of type ‘r’
which returns ‘0’ if read and should be written with 0.
DRC
3
rh
Data Reduction Counter
This bit field indicates how many conversion results
have still to be accumulated to generate the final
result for data reduction.
The final result is available in the result
0B
register.The valid flag is automatically set
when this bit field is set to 0.
1 more conversion result must be added to
1B
obtain the final result in the result register.The
valid flag is automatically reset when this bit
field is set to 1.
User’s Manual
ADC, V2.2
22-68
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
VF
4
rh
Valid Flag for Result Register x
This bit indicates that the contents of the result
register x are valid.
The result register x does not contain valid
0B
data.
The result register x contains valid data.
1B
0
[7:5]
r
Reserved
Returns 0 if read; should be written with 0.
ADC_RESRxH (x = 0 - 2)
Result Register x High, View Std. 8-bit or Acc. 8-bit 1st conv.(CBH + x * 2) Reset
Value: 00H
ADC_RESR3H
Result Register 3 High, View Std. 8-bit or Acc. 8-bit 1st conv.(D3H) Reset Value:
00H
RMAP: 0, PAGE: 2
7
6
5
4
3
2
1
0
RESULT[7:0]
rh
Field
Bits
Type Description
RESULT[7:0]
[7:0]
rh
Conversion Result
This bit field contains the conversion result or the
result of the data reduction filter.
ADC_RESRxL (x = 0 - 2)
Result Register x Low, View Std. 10-bit(CAH + x * 2)
ADC_RESR3L
Result Register 3 Low, View Std.10-bit(D2H)
RMAP: 0, PAGE: 2
7
6
Reset Value: 00H
4
3
RESULT[2:0]
VF
DRC
CHNR
rh
rh
rh
rh
User’s Manual
ADC, V2.2
5
Reset Value: 00H
22-69
2
1
0
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
CHNR
[2:0]
rh
Channel Number
This bit field contains the channel number of the
latest register update.
Note: Bit 2is only applicable for devices that have 8
ADC channels. For channels not implemented, these
bits should be treated as Reserved bits of type ‘r’
which returns ‘0’ if read and should be written with 0.
DRC
3
rh
Data Reduction Counter
This bit field indicates how many conversion results
have still to be accumulated to generate the final
result for data reduction.
The final result is available in the result
0B
register.The valid flag is automatically set
when this bit field is set to 0.
1 more conversion result must be added to
1B
obtain the final result in the result register.The
valid flag is automatically reset when this bit
field is set to 1.
VF
4
rh
Valid Flag for Result Register x
This bit indicates that the contents of the result
register x are valid.
The result register x does not contain valid
0B
data.
1B
The result register x contains valid data.
RESULT[2:0]
[7:5]
rh
Conversion Result
This bit field contains the conversion result or the
result of the data reduction filter.
ADC_RESRxH (x = 0 - 2)
Result Register x High, View Std. 10-bit(CBH + x * 2)
ADC_RESR3H
Result Register 3 High, View Std. 10-bit(D3H)
RMAP: 0, PAGE: 2
7
6
5
4
3
0
RESULT[9:3]
r
rh
User’s Manual
ADC, V2.2
22-70
Reset Value: 00H
Reset Value: 00H
2
1
0
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
RESULT[9:3]
[6:0]
rh
Conversion Result
This bit field contains the conversion result or the
result of the data reduction filter.
0
7
r
Reserved
Returns 0 if read; should be written with 0.
ADC_RESRxL (x = 0 - 2)
Result Register x Low, View Acc. 8-bit 2nd conv.(CAH + x * 2)
ADC_RESR3L
Result Register 3 Low, View Acc. 8-bit 2nd conv.(D2H)
RMAP: 0, PAGE: 2
7
6
5
4
3
2
Reset Value: 00H
Reset Value: 00H
1
R0
0
VF
DRC
CHNR
rh
r
rh
rh
rh
0
Field
Bits
Type Description
CHNR
[2:0]
rh
Channel Number
This bit field contains the channel number of the
latest register update.
Note: Bit 2is only applicable for devices that have 8
ADC channels. For channels not implemented, these
bits should be treated as Reserved bits of type ‘r’
which returns ‘0’ if read and should be written with 0.
DRC
3
rh
Data Reduction Counter
This bit field indicates how many conversion results
have still to be accumulated to generate the final
result for data reduction.
The final result is available in the result
0B
register.The valid flag is automatically set
when this bit field is set to 0.
1 more conversion result must be added to
1B
obtain the final result in the result register.The
valid flag is automatically reset when this bit
field is set to 1.
User’s Manual
ADC, V2.2
22-71
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
VF
4
rh
Valid Flag for Result Register x
This bit indicates that the contents of the result
register x are valid.
The result register x does not contain valid
0B
data.
The result register x contains valid data.
1B
0
[6:5]
r
Reserved
Returns 0 if read; should be written with 0.
RESULT[0]
7
rh
Conversion Result
This bit field contains the conversion result or the
result of the data reduction filter.
ADC_RESRxH (x = 0 - 2)
Result Register x High, View Acc. 8-bit 2nd conv.(CBH + x * 2)
ADC_RESR3H
Result Register 3 High, View Acc. 8-bit 2nd conv.(D3H)
RMAP: 0, PAGE: 2
7
6
5
4
3
2
Reset Value: 00H
Reset Value: 00H
1
0
RESULT[8:1]
rh
Field
Bits
Type Description
RESULT[8:1]
[7:0]
rh
Conversion Result
This bit field contains the conversion result or the
result of the data reduction filter.
ADC_RESRxL (x = 0 - 2)
Result Register x Low, View Acc. 10-bit 1st conv.(CAH + x * 2)
ADC_RESR3L
Result Register 3 Low, View Acc. 10-bit 1st conv.(D2H)
RMAP: 0, PAGE: 2
7
6
3
RESULT[2:0]
VF
DRC
CHNR
rh
rh
rh
rh
22-72
2
Reset Value: 00H
4
User’s Manual
ADC, V2.2
5
Reset Value: 00H
1
0
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
CHNR
[2:0]
rh
Channel Number
This bit field contains the channel number of the
latest register update.
Note: Bit 2is only applicable for devices that have 8
ADC channels. For channels not implemented, these
bits should be treated as Reserved bits of type ‘r’
which returns ‘0’ if read and should be written with 0.
DRC
3
rh
Data Reduction Counter
This bit field indicates how many conversion results
have still to be accumulated to generate the final
result for data reduction.
The final result is available in the result
0B
register.The valid flag is automatically set
when this bit field is set to 0.
1 more conversion result must be added to
1B
obtain the final result in the result register.The
valid flag is automatically reset when this bit
field is set to 1.
VF
4
rh
Valid Flag for Result Register x
This bit indicates that the contents of the result
register x are valid.
The result register x does not contain valid
0B
data.
The result register x contains valid data.
1B
RESULT[2:0]
[7:5]
rh
Conversion Result
This bit field contains the conversion result or the
result of the data reduction filter.
ADC_RESRxH (x = 0 - 2)
Result Register x High, View Acc. 10-bit 1st conv.(CBH + x * 2)
ADC_RESR3H
Result Register 3 High, View Acc. 10-bit 1st conv.(D3H)
RMAP: 0, PAGE: 2
7
6
5
4
3
0
RESULT[9:3]
r
rh
User’s Manual
ADC, V2.2
22-73
2
Reset Value: 00H
Reset Value: 00H
1
0
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
RESULT[9:3]
[6:0]
rh
Conversion Result
This bit field contains the conversion result or the
result of the data reduction filter.
0
7
r
Reserved
Returns 0 if read; should be written with 0.
ADC_RESRxL (x = 0 - 2)
Result Register x Low, View Acc. 10-bit 2nd conv.(CAH + x * 2)
ADC_RESR3L
Result Register 3 Low, View Acc. 10-bit 2nd conv.(D2H)
RMAP: 0, PAGE: 2
7
6
5
2
Reset Value: 00H
Reset Value: 00H
4
3
1
RESULT[2:0]
VF
DRC
CHNR
rh
rh
rh
rh
0
Field
Bits
Type Description
CHNR
[2:0]
rh
Channel Number
This bit field contains the channel number of the
latest register update.
Note: Bit 2is only applicable for devices that have 8
ADC channels. For channels not implemented, these
bits should be treated as Reserved bits of type ‘r’
which returns ‘0’ if read and should be written with 0.
DRC
3
rh
Data Reduction Counter
This bit field indicates how many conversion results
have still to be accumulated to generate the final
result for data reduction.
The final result is available in the result
0B
register.The valid flag is automatically set
when this bit field is set to 0.
1 more conversion result must be added to
1B
obtain the final result in the result register.The
valid flag is automatically reset when this bit
field is set to 1.
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
VF
4
rh
Valid Flag for Result Register x
This bit indicates that the contents of the result
register x are valid.
The result register x does not contain valid
0B
data.
The result register x contains valid data.
1B
RESULT[2:0]
[7:5]
rh
Conversion Result
This bit field contains the conversion result or the
result of the data reduction filter.
ADC_RESRxH (x = 0 - 2)
Result Register x High, View Acc. 10bit 2nd conv.(CBH + x * 2)
ADC_RESR3H
Result Register 3 High, View Acc. 10bit 2nd conv.(D3H)
RMAP: 0, PAGE: 2
7
6
5
4
3
2
Reset Value: 00H
Reset Value: 00H
1
0
RESULT[10:3]
rh
Field
Bits
RESULT[10:3] [7:0]
Type Description
rh
Conversion Result
This bit field contains the conversion result or the
result of the data reduction filter.
ADC_RESRxL (x = 0 - 2)
Result Register x Low, View LPF. 10-bit(CAH + x * 2)
ADC_RESR3L
Result Register 3 Low, View LPF. 10-bit(D2H)
RMAP: 0, PAGE: 2
7
User’s Manual
ADC, V2.2
6
5
4
3
Reset Value: 00H
Reset Value: 00H
2
1
RESULT
[4:0]
CHNR
rh
rh
22-75
0
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
CHNR
[2:0]
rh
Channel Number
This bit field contains the channel number of the
latest register update.
Note: Bit 2is only applicable for devices that have 8
ADC channels. For channels not implemented, these
bits should be treated as Reserved bits of type ‘r’
which returns ‘0’ if read and should be written with 0.
RESULT[4:0]
[7:3]
rh
Conversion Result
This bit field contains the result of the digital low pass
filter.
ADC_RESRxH (x = 0 - 2)
Result Register x High, View LPF. 10-bit(CBH + x * 2)
ADC_RESR3H
Result Register 3 High, View LPF, 10-bit(D3H)
RMAP: 0, PAGE: 2
7
6
5
4
3
Reset Value: 00H
Reset Value: 00H
2
1
0
RESULT[12:5]
rh
Field
Bits
RESULT[12:5] [7:0]
User’s Manual
ADC, V2.2
Type Description
rh
Conversion Result
This bit field contains the result of the digital low pass
filter.
22-76
V1.1, 2010-09
XC83x
Analog to Digital Converter
The Result Control Registers control the behavior of the result registers and monitor their
status.
ADC_RCRx (x = 0 - 3)
Result Control Register x
RMAP: 0, PAGE: 4
(CAH + x * 1)
Reset Value: 00H
7
6
5
4
3
2
1
0
VFCTR
WFR
0
IEN
0
DLPF
0
DRCTR
rw
rw
r
rw
r
rw
r
rw
Field
Bits
Type Description
DRCTR1)
0
rw
Data Reduction Control
This bit defines how many conversion results are
accumulated for data reduction. It defines the reload
value for bit DRC.
The data reduction filter is disabled. The
0B
reload value for DRC is 0, so the accumulation
is done over 1 conversion.
The data reduction filter is enabled. The reload
1B
value for DRC is 1, so the accumulation is
done over 2 conversions.
DLPF1)
2
rw
Digital Low Pass Filter Control
This bit defines if the conversion results is processed
through the Digital low pass filter.
The digital low pass filter is disabled.
0B
The digital low pass filter is enabled and
1B
previous result register is cleared for the first
time when the bit is changed from 0->1. See
Page 22-82
IEN
4
rw
Interrupt Enable
This bit enables the event interrupt related to the
result register x. An event interrupt can be generated
when DRC is set to 0 (after decrementing or by
reload).
The event interrupt is disabled.
0B
1B
The event interrupt is enabled.
User’s Manual
ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
WFR
6
rw
Wait-for-Read Mode
This bit enables the wait-for-read mode for result
register x.
The wait-for-read mode is disabled.
0B
1B
The wait-for-read mode is enabled.
VFCTR
7
rw
Valid Flag Control
This bit enables the reset of valid flag (by read
access to high byte) for result register x.
VF unchanged by read access to
0B
RESRxH/RESRAxH. (default)
VF reset by read access to
1B
RESRxH/RESRAxH.
0
1,3,5
r
Reserved
Returns 0 if read; should be written with 0.
1) For 10bit conversion, either Data Reduction Filter OR Digital Low Pass Filter can be used. However since
there is only one adder both filter cannot be turned on at the same time. Thus when both filter is turned on at
the same time, DRCTR=1 and DLPF=1, the results would be the same as DRCTR=0 and DLPF=1, digital low
pass filter enabled.
For 8-bit conversion, only Data Reduction Filter can be used. When 8bit resolution mode is chosen and digital
low pass filter is enabled DLPF=1 the results will be the same as DLPF=0,digital low pass filter disabled.
User’s Manual
ADC, V2.2
22-78
V1.1, 2010-09
XC83x
Analog to Digital Converter
The Valid Flag Register summarizes the flags indicating that the corresponding result
register contents are valid.
ADC_VFCR
Valid Flag Clear Register
RMAP: 0, PAGE: 4
7
6
Field
(CEH)
5
3
2
1
0
0
VFC3
VFC2
VFC1
VFC0
r
w
w
w
w
Bits
4
Reset Value: 00H
Type Description
VFCx(x = 0 - 3) x
w
Clear Valid Flag for Result Register x
No action
0B
1B
Bit VF in result register RESRxL is reset.
0
r
Reserved
Returns 0 if read; should be written with 0.
22.10
[7:4]
Wait-for-Read Mode
The wait-for-read mode is a feature to prevent data loss due to overwriting a result
register with a new conversion result before the CPU has read the previous data. For
example, auto-scan conversion sequences or other sequences with “relaxed” timing
requirements are likely to use the same result register. However, the results come from
different input channels, so an overwrite would destroy the result from the previous
conversion1).
Wait-for-read mode automatically suspends the start of a conversion for this channel
until the current result has been read. So a conversion or a conversion sequence can be
requested by a hardware or software trigger, while each conversion is only started after
the previous one has been read. This automatically aligns the conversion sequence with
the CPU capability to read the formerly converted result (interrupt latency).
If wait-for-read mode is enabled for a result register (bit WFR = 1 in the corresponding
result control register), a request source does not generate a conversion request while
the targeted result register contains valid data (indicated by the valid flag VFx = 1) or if
a currently running conversion targets the same result register.
1) Repeated conversions of a single channel that use a sepearate result register will not destroy other results,
but rather update their own previous result value. This way, always the actual signal data is available in the
result register.
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
If two request sources target the same result register with wait-for-read mode selected,
a higher priority source cannot interrupt a lower priority conversion request started
before the higher priority source has requested its conversion. Cancel-inject-repeat
mode does not work in this case. If the higher priority request targets a different result
register, the lower priority conversion can be cancelled and repeated afterwards.
22.10.1
Result Events and Interrupts
A result event interrupt can be generated based on a result event according to the
structure shown in Figure 22-27. If a result event is detected, it sets the corresponding
indication flag in register ADC_EVINFR. These flags can also be set by writing a 1 to the
corresponding bit position at ADC_EVINSR, whereas writing 0 has no effect. The
indication flags can be cleared by SW by writing a 1 to the corresponding bit position in
register ADC_EVINCR.
result event
indication flag
result event
interrupt enable
EVIN FR.
EVINF4-7
RC R0-3.
IEN
set
new data
available
to SR0
result event
ADC _ result_ event _ int
Figure 22-27 Result Event Interrupt Generation
The Request Source Event Interrrupt, Channel Event Interupt and Result Event Interrupt
all share the same service request output line SR0.
The result events and the request source events share the same registers. The result
events are located at the following bit positions in register ADC_EVINFR:
•
•
•
•
Event 4: Result event of result register 0.
Event 5: Result event of result register 1.
...
Event 7: Result event of result register 3.
22.10.2
Data Reduction and Filtering
Data reduction automatically accumulates a series of conversion results before
generating a result interrupt. This can remove some noise from the input signal and
reduces the CPU load required to unload the conversion data from the ADC.
The standard data reduction mode accumulates result values within arbitrary result
registers.
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ADC, V2.2
22-80
V1.1, 2010-09
XC83x
Analog to Digital Converter
The digital low pass filter pre-processes the result values by averaging the previous and
current results to remove any transient noise voltages that is measured.
Standard Data Reduction Mode
The data reduction mode can be used as digital filter for anti-aliasing or decimation
purposes. It accumulates a maximum of 2 conversion results to generate a final result.
Each result register can be individually enabled for data reduction, controlled by bitfield
DRCTR in registers ADC_RCRx (x = 0 - 3). The data reduction counter DRC indicates
the actual status of the accumulation.
Note: Conversions for other result registers can be inserted between conversions to be
accumulated.
conversion
ready
DRCTR = 1
c0
c1
c2
c3
c4
c5
c6
c7
c8
running
conversion
r0
r1
r2
r3
r4
r5
r6
r7
delivered
result
0
1
0
1
0
1
0
1
0
DRC
0
r0
r0 +
r1
r2
r2 +
r3
r4
r4 +
r5
r6
r6 +
r7
content of result register x
valid flag for result register x
VF
Figure 22-28 Standard Data Reduction Filter
This example shows a data reduction sequence of 2 accumulated conversion results.
Eight conversion results (r0 … r7) are accumulated and produce 4 final results.
When a conversion is complete and stores data to a result register that has data
reduction mode enabled, the data handling is controlled by the data reduction counter
DRC:
•
•
If DRC = 0 ( t3, t5, t7, t9in the example), the conversion result is stored to the register.
DRC is loaded with the contents of bitfield RCRx.DRCTR
(i.e. the accumulation begins).
If DRC > 0 (t2, t4, t6, t8in the example), the conversion result is added to the value in
the result register.
DRC is decremented by 1.
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ADC, V2.2
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V1.1, 2010-09
XC83x
Analog to Digital Converter
•
If DRC becomes 0, either decremented from 1 (t2, t4, t6, t8 in the example) or loaded
from DRCTR, the valid bit for the respective result register is set and a result register
event occurs.
The final result must be read before the next data reduction sequence starts (before
t3, t5, t7 or t9in the example). This automatically clears the valid flag.
Digital Low Pass Filter Mode
Alternatively, the data reduction logic can build a digital low-pass filter by adding the
amplified result (factor 4) to the attenuated current value (factor 0.5)
Each result register can be individually enabled for low-pass filtering, controlled by
bitfield LPFEN in registers ADC_RCRx (x = 0 - 3). The data reduction counter DRC is
not used in this case.
Note: For low-pass filtering, the result data must come from one dedicated channel.
Figure 22-29 Low-Pass Filter Operation
Each result is multiplied by 4 and added to half the previous register value. The valid flag
is activated after the addition.
User’s Manual
ADC, V2.2
22-82
V1.1, 2010-09
XC83x
Analog to Digital Converter
22.11
Interrupt Request Handling
Interrupts can be generated by several types of events. Each ADC kernel provides 2
service request output signals (ADCx_SR[1:0]) connected to interrupt nodes. Four types
of events can generate interrupt requests:
•
•
•
•
Request source events: indicate that a request source completed the requested
conversion sequence. For a scan source, the event is generated when the complete
defined set of channels has been arbitrated. For a sequential source, the user can
define where inside a conversion sequence a request source event is generated.
Request source events indicate that a conversion sequence has reached a defined
state and software can access the related set of results.
Channel events: indicate that a conversion is finished. Optionally, channel events
can be generated only for conversion result within a programmable value range.
Channel events preferably indicate analog input values inside or outside a nominal
operating range. This offloads the CPU load from background tasks, i.e. an interrupt
is only required if the specified conversion result range is met or exceeded.
Result events: indicate a new valid result in a result register. Usually, this triggers a
read action by the CPU. Optionally, result events can be generated only at a reduced
rate if data reduction or digital low pass filteris active.
Out of range comparator events: indicate that a voltage higher or lower than Vddp
is detected at the analog input channels.
Each ADC event is indicated by a dedicated flag that can be cleared by software. If an
interrupt is enabled for a certain event, the interrupt is generated for each event,
independent of the status of the corresponding event indication flag. This ensures
efficient handling of ADC events (the ADC event can generate an interrupt without the
need to clear the indication flag).
The Request source event, Channel event and Result events share a common service
request output, ADC_SR0, while the the Out of range comparator events uses the
ADC_SR1 service request output.
Note: A conversion can lead to three interrupts, one of each type, if all are enabled.
In this case, the ADC module first triggers the request source event interrupt, then
the channel event interrupt, followed by the result event interrupt (all within a few
fADC clock cycles).
User’s Manual
ADC, V2.2
22-83
V1.1, 2010-09
XC83x
Analog to Digital Converter
The Event indication Flag Register ADC_EVINFR monitors both the detected request
source events (flags EVINF0-EVINF1) and the result events (flags EVINF4-EVINF7).
ADC_EVINFR
Event Interrupt Flag Register
RMAP: 0, PAGE: 5
(CEH)
7
6
5
4
EVINF7
EVINF6
EVINF5
EVINF4
rh
rh
rh
rh
Reset Value: 00H
3
2
1
0
0
EVINF1
EVINF0
r
rh
rh
Field
Bits
Type Description
EVINF0,
EVINF1,
EVINF4,
EVINF5,
EVINF6,
EVINF7
0,
1,
4,
5,
6,
7
rh
Interrupt Flag for Event x
This bit monitors the status of the event interrupt x.
An event interrupt for event x has not occurred.
0B
Writing a “0” clears this register.
An event interrupt for event x has occurred.
1B
Writing a “1” sets this register and generates
an interrupt pulse (if interrupt is enabled).
0
[3:2]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
ADC, V2.2
22-84
V1.1, 2010-09
XC83x
Analog to Digital Converter
The Event Interrupt Set Flag Register ADC_EVINSR sets the corresponding bit at
ADC_EVINFR and generates an interrupt request when the associated bit is written.
ADC_EVINSR
Event Interrupt Set Flag Register
RMAP: 0, PAGE: 5
(D2H)
7
6
5
4
EVINS7
EVINS6
EVINS5
EVINS4
w
w
w
w
Reset Value: 00H
3
2
1
0
0
EVINS1
EVINS0
r
w
w
Field
Bits
Type Description
EVINS0,
EVINS1,
EVINS4,
EVINS5,
EVINS6,
EVINS7
0,
1,
4,
5,
6,
7
w
Set Interrupt Flag for Event x
No action
0B
1B
Bit EVINFR.x is set.
0
[3:2]
r
Reserved
Returns 0 if read; should be written with 0.
Note: Writing 1 to a bit of the Event Interrupt Set Flag Register ADC_EVINSR sets the
corresponding bit at ADC_EVINFR and generates the associated interrupt
request. Writing a 0 has not effect.
User’s Manual
ADC, V2.2
22-85
V1.1, 2010-09
XC83x
Analog to Digital Converter
Writing a 1 to a bit position in the Event Indication Clear Register ADC_EVINCR clears
the corresponding event indication flag EVINFx in register ADC_EVINFR. If a request
source or result event is detected when the corresponding bit position is written with a 1,
flag EVINFx is cleared.
ADC_EVINCR
Event Interrupt Clear Flag Register
RMAP: 0, PAGE: 5
(CFH)
7
6
5
4
EVINC7
EVINC6
EVINC5
EVINC4
w
w
w
w
Reset Value: 00H
3
2
1
0
0
EVINC1
EVINC0
r
w
w
Field
Bits
Type Description
EVINC0,
EVINC1,
EVINC4,
EVINC5,
EVINC6,
EVINC7
0,
1,
4,
5,
6,
7
w
Clear Interrupt Flag for Event x
No action
0B
Bit EVINFR.x is reset.
1B
0
[3:2]
r
Reserved
Returns 0 if read; should be written with 0.
User’s Manual
ADC, V2.2
22-86
V1.1, 2010-09
XC83x
Analog to Digital Converter
The Channel Event Indication Flag Register CHINFR monitors the detected channel
events for channels 0 … 7
ADC_CHINFR
Channel Interrupt Flag Register
RMAP: 0, PAGE: 5
(CAH)
Reset Value: 00H
7
6
5
4
3
2
1
0
CHINF7
CHINF6
CHINF5
CHINF4
CHINF3
CHINF2
CHINF1
CHINF0
rh
rh
rh
rh
rh
rh
rh
rh
Field
Bits
Type Description
CHINFx
(x = 0 - 7)
x
rh
User’s Manual
ADC, V2.2
Interrupt Flag for Channel x
This bit monitors the status of the channel interrupt x.
A channel interrupt for channel x has not
0B
occurred.
A channel interrupt for channel x has occurred.
1B
Note: Bit 4-7 are only applicable for devices that
have 8 ADC channels. For channels not
implemented, these bits should be treated as
Reserved bits of type ‘r’ which returns ‘0’ if read and
should be written with 0.
22-87
V1.1, 2010-09
XC83x
Analog to Digital Converter
Writing 1 to a bit of the CHINSR register sets the corresponding bit and generates the
associated interrupt request. Writing a 0 has no effect
ADC_CHINSR
Channel Interrupt Set Register
RMAP: 0, PAGE: 5
(CCH)
Reset Value: 00H
7
6
5
4
3
2
1
0
CHINS7
CHINS6
CHINS5
CHINS4
CHINS3
CHINS2
CHINS1
CHINS0
w
w
w
w
w
w
w
w
Field
Bits
Type Description
CHINSx
(x = 0 - 7)
x
w
User’s Manual
ADC, V2.2
Set Interrupt Flag for Channel x
No action
0B
1B
Bit CHINFR.x is set and an interrupt pulse is
generated.
Note: Bit 4-7 are only applicable for devices that
have 8 ADC channels. For channels not
implemented, these bits should be treated as
Reserved bits of type ‘r’ which returns ‘0’ if read and
should be written with 0.
22-88
V1.1, 2010-09
XC83x
Analog to Digital Converter
Writing a 1 to a bit position in the channel indication clear register CHINCR clears the
corresponding channel event indication flag CHINFx in register ADC_CHINFR. If a
channel event is detected when the corresponding bit position is written with a 1, flag
CHINFx is cleared.
ADC_CHINCR
Channel Interrupt Clear Register
RMAP: 0, PAGE: 5
(CBH)
Reset Value: 00H
7
6
5
4
3
2
1
0
CHINC7
CHINC6
CHINC5
CHINC4
CHINC3
CHINC2
CHINC1
CHINC0
w
w
w
w
w
w
w
w
Field
Bits
Type Description
CHINCx
(x = 0 - 7)
x
w
User’s Manual
ADC, V2.2
Clear Interrupt Flag for Channel x
0B
No action
Bit CHINFR.x is reset.
1B
Note: Bit 4-7 are only applicable for devices that
have 8 ADC channels. For channels not
implemented, these bits should be treated as
Reserved bits of type ‘r’ which returns ‘0’ if read and
should be written with 0.
22-89
V1.1, 2010-09
XC83x
Analog to Digital Converter
22.12
Register Mapping
The ADC SFRs are located in the standard memory area (RMAP = 0) and are organized
into 6 pages. The ADC_PAGE register is located at address D1H. It contains the page
value and page control information.
ADC_PAGE
Page Register for ADC
RMAP: 0, PAGE: X
7
6
(F1H)
5
4
Reset Value: 00H
3
2
1
OP
STNR
0
PAGE
w
w
r
rwh
0
Field
Bits
Type Description
PAGE
[3:0]
rwh
Page Bits
When written, the value indicates the new page address.
When read, the value indicates the currently active page
= addr [y:x+1]
STNR
[5:4]
w
Storage Number
This number indicates which storage bit field is the target
of the operation defined by bit OP.
If OP = 10B,
the contents of PAGE are saved in ADC_STx before
being overwritten with the new value.
If OP = 11B,
the contents of PAGE are overwritten by the contents of
ADC_STx. The value written to the bit positions of PAGE
is ignored.
00
ADC_ST0 is selected.
01
ADC_ST1 is selected.
10
ADC_ST2 is selected.
11
ADC_ST3 is selected.
User’s Manual
ADC, V2.2
22-90
V1.1, 2010-09
XC83x
Analog to Digital Converter
Field
Bits
Type Description
OP
[7:6]
w
Operation
0X Manual page mode. The value of STNR is ignored
and PAGE is directly written.
10
New page programming with automatic page
saving. The value written to the bit positions of
PAGE is stored. In parallel, the former contents of
PAGE are saved in the storage bit field ADC_STx
indicated by STNR.
11
Automatic restore page action. The value written
to the bit positions PAGE is ignored and instead,
PAGE is overwritten by the contents of the storage
bit field ADC_STx indicated by STNR.
The addresses of the kernel SFRs are listed in Table 22-7 and Table 22-8.
All ADC register names described in the following sections are referenced in other
chapters of this document with the module name prefix “ADC_”, e.g., ADC_GLOBCTR.
Table 22-7
SFR Address List for Pages 0 – 3
Address
Page 0
Page 1
Page 2
CAH
ADC_GLOBCTR
CHCTR0
RESR0L
CBH
ADC_GLOBSTR
CHCTR1
RESR0H
CCH
ADC_PRAR
CHCTR2
RESR1L
CDH
ADC_LCBR0
CHCTR3
RESR1H
CEH
ADC_INPCR0
CHCTR4
RESR2L
CFH
ADC_LCBR1
CHCTR5
RESR2H
D2H
ADC_LORE
CHCTR6
RESR3L
D3H
ADC_ENORC
CHCTR7
RESR3H
Table 22-8
SFR Address Listing for Pages 4 – 7
Address
Page 4
Page 5
Page 6
CAH
RCR0
ADC_CHINFR
ADC_CRCR1
CBH
RCR1
ADC_CHINCR
ADC_CRPR1
CCH
RCR2
ADC_CHINSR
ADC_CRMR1
CDH
RCR3
CEH
ADC_VFCR
User’s Manual
ADC, V2.2
Page 3
Page 7
ADC_QMR0
ADC_EVINFR
22-91
ADC_QSR0
V1.1, 2010-09
XC83x
Analog to Digital Converter
Table 22-8
SFR Address Listing for Pages 4 – 7
Address
Page 4
Page 5
Page 6
CFH
ADC_ALR0
ADC_EVINCR
ADC_Q0R0
D2H
ADC_CNF
ADC_EVINSR
ADC_QBUR0/
ADC_QINR0
D3H
ADC_ETRCR
User’s Manual
ADC, V2.2
22-92
Page 7
V1.1, 2010-09
XC83x
Boot ROM User Routines
23
Boot ROM User Routines
The Boot ROM User Routines provides a set of useful routines that can be called by user
application. These routines have been developed as part of the Boot ROM functionality
and are provided to the user via a Boot ROM User Routine table. User application would
be able to call these routines provided in Table 23-1.
Table 23-1
Boot ROM User Routine table
Address Name
Description
0xDFDE
BR_FLASH_READ_MODE_
STATUS
Check the Read Mode status of the
selected Flash Bank
0xDFE1
BR_GET_4_BYTES_INFO
Read the 4 bytes of Chip Identification
Number and User Identification Number
(USER_ID)
0xDFE4
BR_PROG_USER_ID
Program 4 bytes of USER_ID
(Option 1 of BR_FEATURE_SETTING)
0xDFE4
BR_CLKMODE_SETTING
Initialize CLKMODE
(Option 0 of BR_FEATURE_SETTING)
0xDFE7
BR_AUTO_BAUD
Automatically detect UART Baud rate
0xDFEA
BR_UART_BSL
Re-enter UART BSL Mode
0xDFED
BR_FLASH_BACKGROUND Program code/data in the background
_PROGRAM
0xDFF0
BR_FLASH_BACKGROUND Erase flash in the background
_ERASE
0xDFF3
BR_FLASH_BACKGROUND Abort Flash Erase (background)
_ERASE_ABORT
0xDFF6
BR_FLASH_PROGRAM
Program code/data into flash
0xDFF9
BR_FLASH_ERASE
Erase flash
The erase and program user routines can be called from XRAM or Flash. Table 23-2
shows the description of how to use and call these routines.
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BootROM User Routines, V1.2
23-1
V1.1, 2010-09
XC83x
Boot ROM User Routines
Table 23-2
Calling Flash User Routines
Name
Device
Called from
Target
BR_FLASH_PROGRAM
XC83x - 8K
XRAM
Flash Bank 0 or
Flash Bank 1
BR_FLASH_ERASE
Flash Bank 0/1 Flash Bank 0/1
XC83x - 4K
BR_FLASH_ERASE
XC83x - 8K
BR_FLASH_BACKGROUND_ XC83x - 8K
PROGRAM
BR_FLASH_BACKGROUND_
ERASE
XC83x - 4K
Flash Bank 0
Flash Bank 0
XRAM
Flash Bank 0
XRAM or Flash Flash Bank 0
Bank 0/1
and 1 at same
time
XRAM
Flash Bank 0 or
Flash Bank 1
Flash Bank 0
Flash Bank 1
Flash Bank 1
Flash Bank 0
XRAM
Flash Bank 0
BR_FLASH_BACKGROUND_
ERASE_ABORT
23.1
Flash Bank Read Mode Status Subroutine
The Read Mode status subroutine allows the checking of ready-to-read Mode status of
the Flash Bank. This routine is especially useful when user uses
BR_FLASH_BACKGROUND_ERASE_ABORT user-routine. After calling the eraseabort routine, user can call this Read Mode Status user-routine to check if erase has
been successfully aborted and the Flash is in Read Mode already.
Before calling this subroutine, the user must ensure that the input R7 is configured to the
selected Flash Bank. The carry flag is clear when Flash is in Read Mode, otherwise it is
set. For wrong input, the carry flag is set.
Table 23-3
Specifications of Flash Bank Read Mode Status subroutine
Subroutine
BR_FLASH_READ_MODE_STATUS
Input
R7 of current Register Bank: Selected Flash Bank
00H Flash Bank 0
01H Flash Bank 11)
Others: Reserved (Invalid options)
Output
C = 0:Selected Flash Bank is in Read Mode
C = 1:Selected Flash Bank is not in Read Mode
C = 1:Invalid option is selected
User’s Manual
BootROM User Routines, V1.2
23-2
V1.1, 2010-09
XC83x
Boot ROM User Routines
Table 23-3
Specifications of Flash Bank Read Mode Status subroutine (cont’d)
Stack size required
6
Resource
used/destroyed
A
1) Available only for XC83x - 8K only. For other configurations, this option is considered invalid.
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BootROM User Routines, V1.2
23-3
V1.1, 2010-09
XC83x
Boot ROM User Routines
23.2
Get 4 Bytes Information
This routine allow the tool chain software or even user code to read out the Chip
Identification Number (see Chapter 1.3) or User Identification Number (USER_ID; see
Chapter 5.1) for device.
Table 23-4
Specifications of BR_GET_4_BYTES_INFO subroutine
Subroutine
BR_GET_4_BYTES_INFO
Input
R7 of current Register Bank: Option
00H Option 0 Chip Idenitification Number
01H Option 1 User Identification Number (USER_ID)
Others: Reserved (Invalid options)
R5 of current Register Bank:
Pointer for the 4-byte IRAM buffer
Output
The IRAM buffer is filled with the following for Option 0:
[R5]: Chip Identification Number (MSB)
[R5+1]:Chip Identification Number
[R5+2]:Chip Identification Number
[R5+3]:Chip Identification Number (LSB)
The IRAM buffer is filled with the following for Option 1:
[R5]: USER_ID (MSB)
[R5+1]:USER_ID
[R5+2]:USER_ID
[R5+3]:USER_ID (LSB)
The IRAM buffer is filled with the following for invalid option:
[R5]: 0x00
[R5+1]:0x00
[R5+2]:0x00
[R5+3]:0x00
C = 0; Fetch is successful
C = 1; Fetch is not successful (Option is invalid)
Stack size required
8
Resource
used/destroyed
A
R1 and R7 of current Register Bank (2 bytes)
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BootROM User Routines, V1.2
23-4
V1.1, 2010-09
XC83x
Boot ROM User Routines
23.3
Feature Setting Subroutine
Feature Setting subroutine is provided in the Boot ROM to initialize some settings.
Currently only 2 options provided, CLKMODE setting (BR_CLKMODE_SETTING) and
programming of USER_ID (BR_PROG_USER_ID). See
The CLKMODE setting sets the frequency to 8MHz or 24MHz while USER_ID
programming programs the 4 bytes user identification (USER_ID) information into
device . These 4 bytes of User Identification Number will consists of BMI, BMI (to
determine entry of Mode) and some initialization like clock frequency setting and
enabling peripherals. This BR_PROG_USER_ID routine will issue a soft reset once
programming is completed. Thus there is no successful indication, except a reset will
occur and device will bootup in the programmed boot-mode. This BR_PROG_USER_ID
routine will also check if NMISR is 0x00. If yes, it will clear NMICON and EA and continue
programming USER_ID. User should take care of their watchdog service routine and to
disable the wdt before calling this routine as there is no return back after calling this
routine.
Table 23-5
Specifications of CLKMODE Setting subroutine
Subroutine
BR_CLKMODE_SETTING
(BR_FEATURE_SETTING - Option 0)
Input
R7 of current Register Bank: Option
00H Option 0 - BR_CLKMODE_SETTING
Others: Reserved (Invalid options)
R5 of current Register Bank:
00 - 8MHz
80 - 24MHz
Others - Reserved
Output
C = 0:Correct option is selected, CLK Mode is set accordingly.
C = 1:Invalid option is selected
Stack size required
9
Resource
used/destroyed
A
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BootROM User Routines, V1.2
23-5
V1.1, 2010-09
XC83x
Boot ROM User Routines
Table 23-6
Specifications of Program USER_ID subroutine
Subroutine
BR_PROG_USER_ID
(BR_FEATURE_SETTING - Option 1)
Input
R7 of current Register Bank: Option
01H Option 1-BR_PROG_USER_ID
Others: Reserved (Invalid options)
R5 of current Register Bank:
IRAM start address for 4-byte User Identification Number
[R5]: USER_ID_3
[R5+1]:USER_ID_2
[R5+2]:USER_ID_1
[R5+3]:USER_ID_0
4-byte User ID Information (in IRAM)
SFR NMISR = 00H
Stack Pointer (SP) Setting:
0x07 <= SP <= 0x60 or
0xC0 <= SP <= 0xE0
Output1)
C = 1:Programming of User ID has failed
C = 1:Routine is exited as NMISR is not 00H - error
Stack size required
10
Resource
used/destroyed
DPTR, A
R0, R1, R3, R5, R6 and R7 of current Register Bank (6 bytes)
IRAM Address 0x80 - 0xBF (64 bytes)
1) Routine is exited and output is observed only when programming of USER_ID has failed. When successful
programming of USER_ID, a soft reset will be triggered and it will boot-up in the programmed Boot-up Mode
depending on BMI.
23.4
UART Auto Baud Subroutine
This routine allows application software to configure UART settings upon reception of a
synchronization byte from the host. User application would block, once this subroutine is
called, throughout reception of synchronization byte, baudrate calculation and
transmission of response byte. The protocol of the auto baud is described in Figure 6-1
while the port pins used in the auto baud are defined in Table 6-1
User has to take care of the clock frequency used and program the BCON.BGSEL SFR
field bit according to their desired auto baud rate.
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BootROM User Routines, V1.2
23-6
V1.1, 2010-09
XC83x
Boot ROM User Routines
Note: Clock Frequency and BGSEL SFR field bit are not modified in this routine. These
field bits can be modified by user first before calling this user-routine for desired
baud rate and clock frequency
Note: SPD setting is not disabled upon entering this user-routine. User must ensure that
there are no conflicts in the port pins used by SPD and auto baud.
Note: It is highly recommended that all interrupts should be disabled before calling this
routine as not to interfere with the auto baud detection and calculation.
Table 23-7
Specifications of BR_AUTO_BAUD subroutine
Subroutine
BR_AUTO_BAUD
Input
BCON.BGSEL SFR field bit to be set accordingly
Output
This subroutine configures port pins (to input/output,
RXD/TXD) and baud rate for UART based on autobaud value
of 005555H, or 0055AAH received. It subsequently transmits
the response character, 55H (acknowledge code) if
initialization is completed successfully.
Stack size required
11
Resource
used/destroyed
Port related SFRs, A, SBUF, SCON, MODPISEL1,
MODPISEL2, TCON, TMOD, TH0, TL0, TR0, BCON, LINST,
T2_T2CON, T2_RC2H/L, T2_T2MOD, T2_T2H/L
IRAM address 0x7F
23.5
UART BSL Routine
This routine allows application software to jump back to UART BSL Mode for various
modes like programming, erasing of XRAM, FLASH..etc. Auto baud detection will be
done in this routine. User has to take care of the clock frequency used and program the
BCON.BGSEL SFR field bit according to their desired auto baud rate. For details of the
feature of UART_BSL Mode, refer to Boot-loader chapter.
Note: Clock Frequency and BGSEL SFR field bit are not modified in this routine. These
field bits can be modified by user first before jumping back to this user-routine for
desired baud rate and clock frequency
Note: This routine will NOT return as it will be always be waiting for any uart bsl
header, therefore an LJMP to this routine should be used (instead of
LCALL).
Note: SPD setting is disabled upon entering this user-routine. And once SPD is disabled,
it cannot be enabled again, unless via reset.
User’s Manual
BootROM User Routines, V1.2
23-7
V1.1, 2010-09
XC83x
Boot ROM User Routines
Table 23-8
Specifications of BR_UART_BSL subroutine
Subroutine
BR_UART_BSL
Input
IEN0.EA = 0
NMICON = 0x00
BCON.BGSEL SFR field bit to be set accordingly
Stack Pointer (SP) Setting:
0x07 <= SP <= 0x60 or
SP = 0xE0
Output
-
Stack size required
-
Resource
used/destroyed
-
Note: Some of IRAM addressess may be destroyed depending on the mode(s) selected
and executed in UART BSL Mode.
23.6
Flash Program Subroutine
Each call of the Flash program subroutine allows the programming of:
•
•
32 of data bytes (WL aligned) into selected Flash wordline.
32 of data bytes (WL aligned) into selected User BSL Flash Sector wordline.1)
Before calling this subroutine, the user must ensure that the Flash content to be
programmed should be buffered in an identically-sized IRAM buffer. Two types of Flash
programing routines will be offered to users. The calling of the erase and program user
routines can be called from XRAM or Flash. Table 23-2 shows the description of how to
use and call these routines.
The
first
type
of
routine
(supports
non-background
programming),
BR_FLASH_PROGRAM, will wait until programming is done before allowing user
program to continue with its execution.This type of routine is necessary for users who
need to program the Flash bank where the user code is in execution, especially when
there will be only one flash bank. The Flash cannot be in both program mode and read
mode at the same time. It is also useful for users who wish to program the Flash Bank
where the interrupt vectors are defined as interrupts cannot be handled when the Flash
Bank is in program mode as the interrupt handler cannot be fetched. For Type 1 program
routine, Boot ROM will control the code, the FNMIFLASH flag is cleared automatically
and therefore need not be handled by users.
1) Supported in XC83x - 8K device only
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BootROM User Routines, V1.2
23-8
V1.1, 2010-09
XC83x
Boot ROM User Routines
Table 23-9
Specifications of FLASH_PROGRAM subroutine
Subroutine
BR_FLASH_PROGRAM
Input
Flash WL aligned address to be programmed
R6 of current Register Bank: DPH
R7 of current Register Bank: DPL1)
R5 of current Register Bank:
IRAM start address for 32-byte Flash data
32-byte Flash data
All interrupts including NMI must be disabled (IEN0.EA=0,
NMICON=00H)
SFR NMISR = 00H
Output
PSW.CY:
0 = Flash programming is successful
1 = Flash programming is not successful
DPTR is incremented by 20H2)
Stack size required
12
Resource
used/destroyed
DPTR, A
R0, R2, R6 and R7 of current Register Bank (4 bytes)
1) The last 5 LSB of the DPL is 0 for an aligned WL address, for e.g. 00H, 20H, 40H, 60H, 80H, A0H, C0H and
E0H.
2) DPTR is only incremented by 20H when PSW.CY is 0
The
second
type
of
routine
(supports
background
programming),
BR_FLASH_BACKGROUND_PROGRAM, allows the user program code to continue
execution after the programming routine is called. User will wait until the Flash NMI event
is generated; bit FNMIFLASH in register NMISR is set, and if enabled via NMIFLASH,
an NMI to the CPU is triggered to enter the Flash NMI service routine. At this point, the
Flash bank is in ready-to-read mode i.e. programming is done.
Table 23-10 Specifications of FLASH_BACKGROUND_PROGRAM subroutine
Subroutine
BR_FLASH_BACKGROUND_PROGRAM
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23-9
V1.1, 2010-09
XC83x
Boot ROM User Routines
Table 23-10 Specifications of FLASH_BACKGROUND_PROGRAM subroutine
Input
Flash WL aligned address to be programmed:
R6 of current Register Bank: DPH
R7 of current Register Bank: DPL1)
R5 of current Register Bank:
IRAM start address for 32-byte Flash data
32-byte Flash data
Flash NMI (NMICON.NMIFLASH) is enabled (1) or disabled (0)
SFR NMISR = 00H
Output
PSW.CY:
0 = Flash programming is in progress
1 = Flash programming is not successful
DPTR is incremented by 20H2)
Stack size required
8
Resource
used/destroyed
DPTR, A
R0, R2, R6 and R7 of current Register Bank (4 bytes)
1) The last 5 LSB of the DPL is 0 for an aligned WL address, for e.g. 00H, 20H, 40H, 60H, 80H, A0H, C0H and
E0H.
2) DPTR is only incremented by 20H when PSW.CY is 0
23.7
Flash Erase Subroutine
Each call of the Flash erase subroutine allows sector(s) erase of the selected Flash
Bank. At any one time, more than one Flash Sectors can be selected for erase. At any
one time, more than one Flash Banks can be selected for erase1) 2). This routine also
support erasing of User BSL Flash Sector1). Erasing of the User BSL Flash Sector can
be done together with the Flash Bank 0/1 flash sector(s).
Before calling this subroutine, the user must ensure that inputs are set accordingly. Two
types of Flash erasing routines will be offered to users. The calling of the erase and
program user routines can be called from XRAM or Flash. Table 23-2 shows the
description of how to use and call these routines.
The first type of routine (supports non-background erasing), BR_FLASH_ERASE, will
wait until erasing is done before allowing user program to continue with its execution.
This routine will be aborted if the FNMIVDDP, FNMIVDD or FNMIPLL flag is set while
1) Valid for XC83x - 8K only
2) Applicable for BR_FLASH_ERASE user-routine. Can be called in Flash or XRAM. To select both Flash banks
for erase for BR_FLASH_BACKGROUND_ERASE user-routine, this user-routine must be called from
XRAM.
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BootROM User Routines, V1.2
23-10
V1.1, 2010-09
XC83x
Boot ROM User Routines
they are being polled for error. This type of routine is necessary for users who need to
erase the Flash bank where the user code is in execution, especially when there is only
one Flash Bank. The Flash cannot be in both erase mode and read mode at the same
time. It is also useful for users who wish to erase the Flash Bank where the interrupt
vectors are defined as interrupts cannot be handled when the Flash is in erase mode as
the interrupt handler cannot be fetched. For Type 1 erase routine, Boot ROM will control
the code, the FNMIFLASH flag is cleared automatically and therefore need not be
handled by users.
Note: As program will return to user code after erasing is completed, customer should
take care that they do not erase their user program code as well.
Note: When invalid/No input(s) is provided for this routine, C flag will be set, and routine
will be exited. Nothing else will be done.
Table 23-11 Specifications of FLASH_ERASE subroutine
Subroutine
BR_FLASH_ERASE
Input1)
R7 of Current Register Bank:
Select sector(s) to be erased for the Flash Bank 0
LSB represents sector 0, MSB represents sector 7.
R6 of Current Register Bank:
Select sector(s) to be erased for the Flash Bank 0
LSB represents sector 8 and bit 1 represents sector 9.
R5 of Current Register Bank2):
Select sector(s) to be erased for the Flash Bank 1
LSB represents sector 0, MSB represents sector 7.
R4 of Current Register Bank2):
Select sector(s) to be erased for the Flash Bank 1
LSB represents sector 8, bit 1 represents sector 9 and bit 2
represents User BSL Flash Sector.
SFR NMISR = 00H
All interrupts including NMI must be disabled (IEN0.EA=0,
NMICON=00H)
Output
PSW.CY:
0 = Flash erasing is successful
1 = Flash erasing is not successful
1 = Invalid/No input(s) is given
Stack size required
12
Resource
used/destroyed
DPTR, A
R2 and R7 of current Register Bank (2 bytes)
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23-11
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XC83x
Boot ROM User Routines
1) The inputs should be set as 0 if the sector(s) of the bank is/are not to be selected for erasing.
2) Valid for XC83x-8K only. For other configurations, this byte is ignored.
The
second
type
of
routine
(supports
background
erasing),
BR_FLASH_BACKGROUND_ERASE, allows the user program code to continue
execution after the erasing routine is called. User will wait until the Flash NMI event is
generated; bit FNMIFLASH in register NMISR is set, and if enabled via NMIFLASH, an
NMI to the CPU is triggered to enter the Flash NMI service routine. At this point, the Flash
bank is in ready-to-read mode i.e. erasing is done.
Note: When invalid/No input(s) is provided for this routine, C flag will be set, and routine
will be exited. Nothing else will be done.
Table 23-12 Specifications of FLASH_BACKGROUND_ERASE subroutine
Subroutine
Input
1)
BR_FLASH_BACKGROUND_ERASE
R7 of Current Register Bank:
Select sector(s) to be erased for the Flash Bank 0
LSB represents sector 0, MSB represents sector 7.
R6 of Current Register Bank:
Select sector(s) to be erased for the Flash Bank 0
LSB represents sector 8 and bit 1 represents sector 9.
R5 of Current Register Bank2):
Select sector(s) to be erased for the Flash Bank 1
LSB represents sector 0, MSB represents sector 7.
R4 of Current Register Bank2):
Select sector(s) to be erased for the Flash Bank 1
LSB represents sector 8, bit 1 represents sector 9 and bit 2
represents User BSL Flash Sector.
SFR NMISR = 00H
Flash NMI (NMICON.NMIFLASH) is enabled (1) or disabled (0)
Output
PSW.CY:
0 = Flash erasing is in progress
1 = Flash erasing is not successful
1 = Invalid/No input(s) is given
Stack size required
8
Resource
used/destroyed
DPTR, A
R2 of current Register Bank (1 bytes)
1) The inputs should be set as 0 if the sector(s) of the bank is/are not to be selected for erasing.
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23-12
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XC83x
Boot ROM User Routines
2) Valid for XC83x-8K only. For other configurations, this byte is ignored.
23.8
Abort Flash Erase Subroutine
Each complete erase operation on a Flash bank requires approximately 100 ms, during
which read and program operations on the Flash bank cannot be performed. For the
XC83x, provision has been made to allow an on-going erase operation (type 2,
BR_FLASH_BACKGROUND_ERASE) to be interrupted so that higher priority tasks
such as reading/programming of critical data from/to the Flash bank can be performed.
Hence, erase operations on selected Flash bank sector(s) may be aborted to allow data
in other sectors to be read or programmed. To minimize the effect of aborted erase on
the Flash data retention/cycling and to guarantee data reliability, the following points
must be noted for each Flash bank:
•
•
•
•
•
An erase operation cannot be aborted earlier than 5 ms after it starts.
Maximum of two consecutive aborted erase (without complete erase in-between) are
allowed on each sector.
Complete erase operation (approximately 100 ms) is required and initiated by userprogram after a single or two consecutive aborted erase as data in relevant sector(s)
is corrupted.
For the specified cycling time, each aborted erase constitutes one program/erase
cycling.
Maximum allowable number of aborted erase for each D-Flash sector during lifetime
is 2500.
The Flash erase abort subroutine call cannot be performed anytime within 5 ms after the
erase operation has started. This is a strict requirement that must be ensured by the
user. Otherwise, the erase operation cannot be aborted. Once exited from this routine,
user can call BR_FLASH_READ_MODE_STATUS user routine to check if the abort
erase operation has been completed. When the selected bank is already in Read Mode,
it indicates that the abort erase operation has been completed.
Table 23-13 Specifications of Flash Erase Abort subroutine
Subroutine
BR_FLASH_BACKGROUND_ERASE_ABORT
Input
Flash Bank is in erase mode1)
Output
C = 0: Flash erase abort is in progress
C = 1: Flash erase abort is not started
Stack size required
3
Resource
used/destroyed
A
1) For XC83x-8K, both Flash Bank 0 and 1 can be in Erase Mode together and thus both flash Banks are aborted
together
User’s Manual
BootROM User Routines, V1.2
23-13
V1.1, 2010-09
XC83x
ROM Library
24
ROM Library
On top of the User routines, a set of useful ROM library routines is also provided to the
user to be used in the user application. The ROM Library provided are:
•
•
•
Fixed Point ROM Library,
LED and Touch-Sense Controller ROM Library,
EEPROM Emulation ROM Library
The user application would be able to call these routines by calling the functions provided
in Table 24-1 for XC83x device. Details of the ROM library are covered in its respective
section.
Table 24-1
XC83x ROM Library function and its Address
Addr
Name
Description
0xD649
_PI_CONTROLLER_G16
FIXEDPOINT ROM Library
0xD64F
_PI_CONTROLLER_G256
FIXEDPOINT ROM Library
0xD655
_P_CONTROLLER_G16
FIXEDPOINT ROM Library
0xD65B
_PI_CONTROLLER_G256
FIXEDPOINT ROM Library
0xD75B
_PT1_24
FIXEDPOINT ROM Library
0xD78A
_PT1_32
FIXEDPOINT ROM Library
0xD7CE
_CLARKE
FIXEDPOINT ROM Library
0xD802
_CARTESIAN_POLAR_POLL
FIXEDPOINT ROM Library
0xD805
_CARTESIAN_POLAR_RET
FIXEDPOINT ROM Library
0xD81E
_VECTOR_ROTATION
FIXEDPOINT ROM Library
0xD821
_INV_VECTOR_ROTATION
FIXEDPOINT ROM Library
0xD859
_SINCOSINE_POLL
FIXEDPOINT ROM Library
0xD85C
_SINCOSINE_RET
FIXEDPOINT ROM Library
0xDFCC
FINDTOUCHEDPAD
LEDTS ROM Library
0xDFCF
SET_LDLINE_CMP
LEDTS ROM Library
0xDFD2
INITEEPROM
EEPROM Emulation ROM Library
0xDFD5
FIXEEPROM
EEPROM Emulation ROM Library
0xDFD8
READEEPROM
EEPROM Emulation ROM Library
0xDFDB
WRITEEEPROM
EEPROM Emulation ROM Library
User’s Manual
ROM Library, V1.4
24-1
V1.1, 2010-09
XC83x
ROM Library
24.1
Fixed Point ROM Library
The Fixed Point Library contains a list of routines that reside in ROM that are accessible
to the user. The definitions and specifications of the library routines are explained in the
following sections.
“Execution Cycles” in the tables does not include the calling instruction “LCALL” which
requires 10 clock cycles if it is executed from FLASH or 8 clock cycles if it is executed
from XRAM.
24.1.1
P Controller Routine
The P controller routine is the implementation of a proportional control algorithm defined
as:
(24.1)
Y(k) = G × Kp × X(k)
where
•
•
•
•
•
Y(k): P controller output
G: Gain factor of16 or 256
Kp: Proportional gain
X: Error = Reference value - Actual value
k: Time or instantaneous time
Table 24-2
Specifications of P Controller Routine
Subroutine
_P_controller_G16 or _P_controller_G256
Routine Address
0xD655: _P_controller_G16
0xD65B: _P_controller_G256
C-Prototype
int P_controller_G16(int Ref_val, int Actual_val, char idata *Kp)
int P_controller_G256(int Ref_val, int Actual_val, char idata *Kp)
Input
R7, R6 (MSB), Ref_val = 16 bit Reference value
R5, R4 (MSB), Acutal_val = 16 bit Actual value
R3 = idata pointer to Kp_H
Output
R7, R6 (MSB) = 16 bit Y(k) value
Execution Cycle
_P_controller_G16: 138 cclks
_P_controller_G256: 112 cclks
Resource
used/destroyed
PSW, A, MDU
User’s Manual
ROM Library, V1.4
R0, R4, R5 of current Register Bank
24-2
V1.1, 2010-09
XC83x
ROM Library
Code Example:
//global
data int
data int
data int
data int
variables
Speed;
Speed_ref;
Speed_kp;
P_Speed;
//program
Speed = 16288
Speed_ref = 4000;
Speed_kp = 4096;
P_Speed = P_controller_G16(Speed_ref, Speed, (char idata *)
&Speed_kp);
//P_speed = 0x7F40
24.1.2
PI Controller Routine
The PI controller routine is the implementation of a proportional-integral control algorithm
defined as:
(24.2)
Y(k) = G × Kp × X(k) + Y(k-1) + Ki × X(k)
where
•
•
•
•
•
•
•
Y(k): PI controller output
Y(k-1): Previous PI controller output
G: Gain factor of16 or 256
Kp: Proportional gain
Ki: Integral gain
X: Error = Reference value - Actual value
k: Time or instantaneous time
Table 24-3
Specifications of PI Controller Routine
Subroutine
_PI_controller_G16 or _PI_controller_G256
Routine Address
0xD649: _PI_controller_G16
0xD64F: _PI_controller_G256
C-Prototype
int PI_controller_G16(int Ref_val, int Actual_val, PI_param *pPI)
int PI_controller_G256(int Ref_val, int Actual_val, PI_param *pPI)
User’s Manual
ROM Library, V1.4
24-3
V1.1, 2010-09
XC83x
ROM Library
Table 24-3
Specifications of PI Controller Routine (cont’d)
Input
R7, R6 (MSB), Ref_val = 16 bit Reference value
R5, R4 (MSB), Acutal_val = 16 bit Actual value
R3 = idata pointer to Y(k-1)_H
Remark
Required structure:
Struct{
Y(k-1)[HLh]
Kp[HL]
Ki[HL]
PI_SAT_HH //high byte of 24 bit saturation value 0xHHFFFF
}
Output
R7, R6 (MSB) = 16 bit Y(k) value
Execution Cycle
_PI_controller_G16: 248 cclks
_PI_controller_G256: 226 cclks
Resource
used/destroyed
PSW, A, MDU
R0, R2, R4, R5 of current Register Bank
Code Example:
//define structure
typedef struct pi_param{
char
yn[3];
int
kp;
int
ki;
unsigned char
PI_SAT_HH;
}PI_param;
//global variables
data int Speed;
data int Speed_ref;
data int PI_Speed;
idata PI_param Speed_control;
//program
Speed = 2048;
Speed_ref = 4000;
Speed_control.yn[0] = 0x01;
Speed_control.yn[1] = 0x4C;
Speed_control.yn[2] = 0x97;
Speed_control.kp = 4096;
Speed_control.ki = 32;
User’s Manual
ROM Library, V1.4
24-4
V1.1, 2010-09
XC83x
ROM Library
Speed_control.PI_SAT_HH = 0x1F;
PI_Speed = PI_controller_G16(Speed_ref, Speed, &Speed_control);
//PI_Speed = 0x108E
24.1.3
PT1_24 Controller Routine
The PT1_24 controller routine is a digital lowpass filter defined as:
(24.3)
Y(k) = Y(k-1) + 2
–Z
× [ X(k) – Y(k-1) ]
where
•
•
•
•
•
Y(k): PT1_24 controller output
Y(k-1): Previous PT1_24 controller output
Z: Division factor of 1/2Z
X(k): 16 bit input
k: Time or instantaneous time
Table 24-4
Specifications of PT1_24 Controller Routine
Subroutine
_PT1_24
Routine Address
0xD75B: _PT1_24
C-Prototype
int PT1_24(int X, char Z, char idata *pY)
Input
R7, R6 (MSB) = 16 bit X value
R5 = 8 bit Z value, number of right shifts (1/2Z)
R3 = idata pointer to Y(k-1)_H
Remark
Y(k-1) = 24 bits [HLh]
X must be within 0xC000 to 0x3FFF
Output
R7, R6 (MSB) = 16 bit Y(k) value
Execution Cycle
76 cclk
Resource
used/destroyed
PSW, A, MDU
R0 of current Register Bank
Code Example:
//declare
data char
data int
data int
variables
Speed[3];
result;
angle_new;
User’s Manual
ROM Library, V1.4
24-5
V1.1, 2010-09
XC83x
ROM Library
data int
angle_old;
//program
Speed[0] = 0xF8;
Speed[1] = 0xF3;
Speed[2] = 0xCB;
angle_new = 0x1800;
angle_old = 0x0800;
result = PT1_24(angle_new - angle_old, 5, &speed);
//result = 0xF9AC;
24.1.4
PT1_32 Controller Routine
The PT1_32 controller routine is an integrator defined as:
(24.4)
Y(k) = Y(k-1) + Z1 × X(k) – Z2 × Y(k-1)
where
•
•
•
•
•
Y(k): PT1_24 controller output
Y(k-1): Previous PT1_24 controller output
Z: Division factor of 1/2Z
X(k): 16 bit input
k: Time or instantaneous time
Table 24-5
Specifications of PT1_32 Controller Routine
Subroutine
_PT1_32
Routine Address
0xD78A: _PT1_32
C-Prototype
int PT1_32(int X, int Z2, int idata *pY)
Input
R7, R6 (MSB) = 16 bit X value
R5, R4 (MSB) = 16bit Z2 value
R3 = idata pointer to Y(k-1)_H
MDU_MD4 = Z1_L
MDU_MD5 = Z1_H
Remark
Y(k-1) = 32 bits [HLhl]
Z1must be within 0x0000 to 0x3FFF or X must be within 0xC000 to
0x3FFF
Output
R7, R6 (MSB) = 16 bit Y(k) value
Execution Cycle
118 cclk
User’s Manual
ROM Library, V1.4
24-6
V1.1, 2010-09
XC83x
ROM Library
Table 24-5
Specifications of PT1_32 Controller Routine (cont’d)
Resource
used/destroyed
PSW, A, MDU
R0 of current Register Bank
Code Example:
//global variables
data int result;
data int Integrator[2];
//program
Integrator[0] = 0xFF12;
Integrator[1] = 0xE828;
MDU_MD4 = 0x1F;//Low byte Z1
MDU_MD5 = 0x00; //High byte Z1
result = PT1_32(X, 0x109, &Integrator);
//result = 0xFF15
24.1.5
Cartesian-Polar Transform Routine
This routine transforms Cartesian coordinates to Polar coordinates and is defined as:
(24.5)
2
2
 X +Y
R = K ×  ------------------------
4


(24.6)
Y
θ = atan  ----
 X
where
•
•
•
•
•
R: Radial distance from the point of origin
θ: Counter-clockwise angle relative to the x-axis
K: Scaling factor of ~ 1.64676
X: x-coordinate
Y: y-coordinate
Table 24-6
Specifications of Cartesian-Polar Transform Routine
Subroutine
_Cartesian_Polar_poll or _Cartesian_Polar_ret
Routine Address
0xD802: _Cartesian_Polar_poll
0xD805: _Cartesian_Polar_ret
User’s Manual
ROM Library, V1.4
24-7
V1.1, 2010-09
XC83x
ROM Library
Table 24-6
Specifications of Cartesian-Polar Transform Routine
C-Prototype
void Cartesian_Polar_poll(int X, int Y)
- Routine will wait for CD_BSY flag before returning. Result is
available in CORDX and CORDZ once it is returned.
void Cartesian_Polar_ret(int X, int Y)
- Routine will return once CORDIC starts. It does not wait for
CD_BSY flag. The user will check CD_BSY flag or wait for
sufficient cycles before reading the result in CORDX and CORDY
Input
R7, R6 (MSB) = 16 bit X value
R5, R4 (MSB) = 16bit Y value
Output
CORDX = R and CORDZ = θ
Execution Cycle
_Cartesian_Polar_poll: 58 cclk
_Cartesian_Polar_ret: 38 cclk
Resource
PSW, A, CORDIC
used/destroyed
Code Example:
//For solving R, set X = x/1.64676, Y = y/1.6476
//i.e. R = Sqrt[sq(X) + sq(Y)]/4
//If X = 300 and Y = 400,
//X = 300/1.64676 = 182.18 = 0xB7
//Y = 400/1.64676 = 242.90 = 0xF3
//program
int R_result, angle_result;
Cartesian_Polar_ret(0xB7, 0xF3);
while(CD_BSY); //wait till conversion is finished
R_result = CD_CORDXLH;
angle_result = CD_CORDZLH;
//R_result = 0x007D, angle_result = 0x25B3
User’s Manual
ROM Library, V1.4
24-8
V1.1, 2010-09
XC83x
ROM Library
24.1.6
Clarke Transform Routine
This routine is used for the transformation of a three phase system into a two phase
orthogonal system. It’s implementation is defined as:
(24.7)
I_alpha = I_phaseA
----------------------2
(24.8)
PhaseA + 2 × PhaseB
I_beta =  -------------------------------------------------------
3×2
where
•
•
•
•
•
Y(k): PT1_24 controller output
Y(k-1): Previous PT1_24 controller output
Z: Division factor of 1/2Z
X(k): 16 bit input
k: Time or instantaneous time
Table 24-7
Specifications of Clarke Transform Routine
Subroutine
_Clarke
Routine Address
0xD7CE: _Clarke
C-Prototype
void Clarke(int idata *I_phaseAB, int idata *I_alphabeta)
Input
R7 = idata pointer to I_phaseA_H
R5 = idata pointer to I_alpha_H
Remark
char idata *I_phaseAB
Expected addreass arrangement in IRAM:
I_phaseA_H (MSB), I_phaseA_L, I_phaseB_H, I_phaseB_L
char idata *I_alphabeta
Expected addreass arrangement in IRAM:
I_alpha_H (MSB), I_alpha_L, I_beta_H, I_beta_L
Output
Result of I_alpha, I_beta saved in address location of 2nd input
parameter
Execution Cycle
84 cclk
Resource
used/destroyed
PSW, A, MDU
User’s Manual
ROM Library, V1.4
R0, R1 of current Register Bank
24-9
V1.1, 2010-09
XC83x
ROM Library
Code Example:
//declare
data int
data int
data int
data int
variables
I_phaseA
I_phaseB
I_alpha
I_beta
_at_
_at_
_at_
_at_
(0x36);
(0x38);
(0x4A);
(0x4C);
//program
I_phaseA = -2048;
I_phaseB = 8192;
Clarke(&I_phaseA, &I_alpha);
//I_alpha = 0xFC00, I_beta = 0x102A
24.1.7
Vector Rotation (Park Transform) Routine
In this routine, the two phases from Clarke Transform in Section 24.1.6 are rotated over
an angle θ:
(24.9)
I_alpha × cos ( θ ) + I_beta × sin ( θ ) )Id = (---------------------------------------------------------------------------------------2
(24.10)
– I_alpha × sin ( θ ) + I_beta × cos ( θ ) )
Iq = (-------------------------------------------------------------------------------------------2
where
•
•
•
•
•
Y(k): PT1_24 controller output
Y(k-1): Previous PT1_24 controller output
Z: Division factor of 1/2Z
X(k): 16 bit input
k: Time or instantaneous time
Table 24-8
Specifications of Vector Rotation Routine
Subroutine
_Vector_Rotation
Routine Address
0xD81E: _Vector_Rotation
C-Prototype
void Vector_Rotation(int Angle, int idata *pInput, int idata *pOutput)
Input
R7, R6 (MSB) = 16 bit angle value
R5 = idata pointer to I_alpha_H
R3 = idata pointer to Iq_H
User’s Manual
ROM Library, V1.4
24-10
V1.1, 2010-09
XC83x
ROM Library
Table 24-8
Specifications of Vector Rotation Routine
Remark
char idata *pInput
Expected addreass arrangement in IRAM:
I_alpha_H (MSB), I_alpha_L, I_beta_H, I_beta_L
char idata *pOutput
Expected addreass arrangement in IRAM:
Iq_H (MSB), Iq_L, Id_H, Id_L
Output
Result of Iq, Id saved in address location of 3rd input parameter
Execution Cycle
92 cclk
Resource
used/destroyed
PSW, A, B, CORDIC
R0 of current Register Bank
Code Example:
//declare
data int
data int
data int
data int
data int
variables
I_alpha
I_beta
I_q
I_d
angle;
_at_
_at_
_at_
_at_
(0x4A);
(0x4C);
(0x4E);
(0x50);
//program
I_alpha = -4096;
I_beta = 8192;
//If the angle of interest is 126o, scale it in radians
angle = 126*32768/180;
Vector_Rotation(angle, &I_alpha, &I_q);
//I_q = 0xFB2C, I_d = 0x1D0F
24.1.8
Inverse Vector Rotation (Inverse Park Transform) Routine
This routine implements the inverse of Vector Rotation in Section 24.1.7 where Id and
Iq is transformed back to I_alpha and I_beta with a rotation over an angle θ:
(24.11)
Id × cos ( θ ) – Iq × sin ( θ ) )I_alpha = (-----------------------------------------------------------------4
(24.12)
Id × sin ( θ ) + Iq × cos ( θ ) )I_beta = (-----------------------------------------------------------------4
where
User’s Manual
ROM Library, V1.4
24-11
V1.1, 2010-09
XC83x
ROM Library
•
•
•
•
•
Y(k): PT1_24 controller output
Y(k-1): Previous PT1_24 controller output
Z: Division factor of 1/2Z
X(k): 16 bit input
k: Time or instantaneous time
Table 24-9
Specifications of Inverse Vector Rotation Routine
Subroutine
_Inv_Vector_Rotation
Routine Address
0xD821: _Inv_Vector_Rotation
C-Prototype
void Inv_Vector_Rotation(int Angle, int idata *pInput, int idata
*pOutput)
Input
R7, R6 (MSB) = 16 bit angle value
R5 = idata pointer to Iq_H
R3 = idata pointer to I_alpha_H
Remark
char idata *pInput
Expected addreass arrangement in IRAM:
Iq_H (MSB), Iq_L, Id_H, Id_L
char idata *pOutput
Expected addreass arrangement in IRAM:
I_alpha_H (MSB), I_alpha_L, I_beta_H, I_beta_L
Output
Result of Iq, Id saved in address location of 3rd input parameter
Execution Cycle
88 cclk
Resource
used/destroyed
PSW, A, B, CORDIC
24.1.9
R0 of current Register Bank
Sine/Cosine Routine
This routine implements the Sine/Cosine function defined as:
(24.13)
K × [ Y × cos ( z ) + X × sin ( z ) -]
Yo = -------------------------------------------------------------------------2
where
•
•
•
•
•
Yo: Output value
K: Scaling factor of ~ 1.64676
Y: Gain factor for cos(z) value
X: Gain factor for sin(z) value
z: Angle of interest (scaled in radians as z * 32768/180o)
User’s Manual
ROM Library, V1.4
24-12
V1.1, 2010-09
XC83x
ROM Library
Table 24-10 Specifications of Sine/Cosine Routine
Subroutine
_SinCos_poll or _SinCos_ret
Routine Address
0xD859: _SinCos_poll
0xD85C: _SinCos_ret
C-Prototype
int SinCos_poll(int X, int Y, int Z)
- Routine will wait for CD_BSY flag before returning the result in R7
and R6.
void SinCos_retl(int X, int Y, int Z)
- Routine will return once CORDIC starts. It does not wait for
CD_BSY flag. The user will check CD_BSY flag or wait for
sufficient cycles before reading the result in CORDY
Input
R7, R6 (MSB) = 16 bit X value for Sine calculation. Input is 0 for
Cosine calculation.
R5, R4 (MSB) = 16 bit Y value for Cosine calculation. Input is 0 for
Sine calculation.
R3, R2 (MSB) = 16 bit Z value
Output
R7, R6 (MSB) = Yo, applicable to routine _SinCos_poll
CORDY = Yo, applicable to routine _SinCos_ret after CD_BSY
flag is set
Execution Cycle
_SinCos_poll: 70 cclk
_SinCos_ret: 42 cclk
Resource
PSW, A, CORDIC
used/destroyed
Code Example:
//Example to calculate Sine value
//Step 1: For sine calculation, Set Y = 0. Equation becomes:
//Yo = K * [X * sin(z)]/2 = 1.64676 * [X * sin(z)]/2
//Step 2: For a gain factor of 1 (Yo = sin(z)),
//set X = 2/1.64676 = 1.214506
//scale X by a factor of 10000 for better accuracy,
//X = 12145.06 = 0x2F72
//Step 3: Scale z in radians. If the angle of interest is 45o,
//z = 45o * 32768/180o = 8192 = 0x2000
//program
int sin_out;
User’s Manual
ROM Library, V1.4
24-13
V1.1, 2010-09
XC83x
ROM Library
sin_out = SinCos_poll(0x2F72, 0, 0x2000);
//sin_out = 0x1B9F, scaling back we get 0.7071
User’s Manual
ROM Library, V1.4
24-14
V1.1, 2010-09
XC83x
ROM Library
24.2
LED and Touch-Sense Controller ROM Library
The LEDTS ROM Library contains two routines that reside in ROM that are accessible
to the user. The definitions and specifications of the library routines are organized into
the following major sections.
•
•
•
SET_LDLINE_CMP Function (LED and Touch-Sense)
FINDTOUCHEDPAD Function (Touch-Sense)
Use of the functions in Interrupts
The call functions for LEDTS are listed in Table 24-11.
Table 24-11 LEDTS ROM Library Routine Table
Address Name
Description
0xDFCF
SET_LDLINE_CMP
Program SFRs LTS_LDLINE and LTS_COMPARE
(LED enabled only).
0xDFCF
SET_LDLINE_CMP
Program SFRs LTS_LDLINE and LTS_COMPARE
(Touch-sense enabled only).
0xDFCF
SET_LDLINE_CMP
Program SFRs LTS_LDLINE and LTS_COMPARE
(LED and Touch-sense are enabled)
0xDFCC
FINDTOUCHEDPAD Get Average, calculate LowTrip and assess whether
pad(s) is being touched or not.
These routines are called from Time Slice or Time Frame Interrupts. This is illustrated in
Section 24.2.3.
User’s Manual
ROM Library, V1.4
24-15
V1.1, 2010-09
XC83x
ROM Library
24.2.1
SET_LDLINE_CMP Function (LED and Touch-Sense)
This function programs SFRs LTS_LDLINE and LTS_COMPARE (brightness/oscillation
window) for LED and/or Touch-sense, based on the user’s input parameters1). The
function takes SFR bits LTS_GLOBCTL1.FNCOL to synchronize which data is to be
programmed into the SFR LTS_LDLINE for implementing an LED display2). Likewise,
the function also updates the SFR LTS_COMPARE for individual LED or Touch-sense
pad turn. Figure 24-1 gives an overview of the usage of this function while Figure 24-2
shows the respective SFR settings used for this function.
TFF
Interrupt Control
time-frame
ITF_EN
ITS_EN
Column
Control
time-slice
TSF
ISR
COL6
COL5
COL4
COL3
COL2
COL1
COL0
COLA
call ROMLIB
LINE7
AND
LINE6
LINE5
ROM Library
LEDLINE[7]
LEDLINE[6]
LEDCMP[7]
LEDLINE[5]
LEDCMP[6]
LEDLINE[4]
LEDCMP[5]
LEDLINE[3]
LEDCMP[4]
LEDLINE[2]
LEDCMP[3]
LEDLINE[1]
LEDCMP[2]
LEDLINE[0]
LEDCMP[1]
LEDCMP[0]
Line
Control
LINE4
LINE3
LINE2
mux
LINE1
LINE0
Figure 24-1 SET_LDLINE_CMP Function Overview
This function can be called at every Time Slice or Time Frame interrupt. Details of how
this function can be called are shown in Section 24.2.3.
The inputs are shown in Section 24.2.1.1, Section 24.2.1.2 and Section 24.2.1.3 for
LED enabled only, Touch-sense enabled only, and both LED and Touch-sense enabled
respectively.
1) The function determines the active function/column in current Time Slice and updates the line value and
compare value (to be shadow transferred) valid for the next Time Slice. This will be transparent to the user.
2) For Touch-sense, LTS_LDLINE parameter can be written as 0xFF.
User’s Manual
ROM Library, V1.4
24-16
V1.1, 2010-09
User’s Manual
ROM Library, V1.4
24-17
TSF
call ROMLIB
ISR
ITS_EN
TFF
CLKSEL
ITF_EN
48MHz
8MHZ
prescaler
LEDLINE[7]
LED
LINE[7]
6]
LEDCMP[
LEDL
INE[5]
]
LEDCMP[6
LEDLI
NE[4]
LEDCMP[5]
LLEDCM
EDLINP[4]
E[3]
LED
LINE[
2]
LEDCMP
[3]
LEDL
INE[1]
]
LEDCMP[2
LEDLI
NE[0]
LEDCMP[1]
LEDCMP[0]
ROM Library
time-slice
time-frame
Interrupt Control
0: no clock
1: clk/1
...
63: clk/63
CLK_PS
mux
demux
3bit
pad osc
enable
XOR
XOR
AND
AND
line value
SHD_LINE
P
O
R
T
0
XOR
AND
Line Control
XOR
AND
XOR
AND
XOR
XOR
AND
AND
XOR
AND
LINE0
LINE1
LINE2
LINE3
LINE4
LINE5
LINE6
LINE7
COLA
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COLLEV
AND
NR_LEDCOL
reload value
shadow transfer
SHD_CMP
comparator
8bit
LEDTS counter
Column Control
XC83x
ROM Library
Figure 24-2 SET_LDLINE_CMP Function - SFR Settings
V1.1, 2010-09
XC83x
ROM Library
24.2.1.1 Inputs for SET_LDLINE_CMP Function (LED only)
If only LED module is enabled, the inputs overview is shown in Table 24-12. Examples
of input parameters for 2, 4, 6 or 8 LED columns enabled are also shown in Figure 24-3.
Table 24-12 Specifications of Setting LDLINE & COMPARE (LED only)
Subroutine
SET_LDLINE_CMP
Address
DFCFH
Input
R7 of current Register Bank:
Start IRAM address of LDLINE parameters
R5 of current Register Bank:
Start IRAM address of COMPARE parameters
LDLINE parameters programmed into IRAM R7 .. R7+(y-1)1)
@R7 = LDLINE parameter for COLA
@R7+1 = LDLINE parameter for COL0
...
@R7+(y-1) = LDLINE parameter for COL(y-2)
COMPARE parameters programmed into IRAM R5.. R5+(y-1)1)
@R5 = COMPARE parameter for COLA
@R5+1 = COMPARE parameter for COL0
...
@R5+(y-1) = COMPARE parameter for COL(y-2)
Output
SFR LTS_LDLINE is programmed.
SFR LTS_COMPARE is programmed.
Stack size required
2
Resource
used/destroyed
A, R0, R1, R2, R3, R4
1) Depending how many LED column(s) is/are enabled; y = number of LED column(s) enabled
User’s Manual
ROM Library, V1.4
24-18
V1.1, 2010-09
XC83x
ROM Library
Eg. 2 LED + No TS enabled
Eg. 4 LED + No TS enabled
Eg. 6 LED + No TS enabled
Eg. 8 LED + No TS enabled
LDLINE(A)
R7
LDLINE(A)
R7
LDLINE(A)
R7
LDLINE(A)
R7
LDLINE(0)
R7 + 1
LDLINE(0)
R7 + 1
LDLINE(0)
R7 + 1
LDLINE(0)
R7 + 1
LDLINE(1)
R7 + 2
LDLINE(1)
R7 + 2
LDLINE(1)
R7 + 2
LDLINE(2)
R7 + 3
LDLINE(2)
R7 + 3
LDLINE(2)
R7 + 3
LDLINE(3)
R7 + 4
LDLINE(3)
R7 + 4
LDLINE(4)
R7 + 5
LDLINE(4)
R7 + 5
LDLINE(5)
R7 + 6
LDLINE(6)
R7 + 7
COMPARE(A)
COMPARE(0)
R5
R5 + 1
COMPARE(A)
R5
COMPARE(0)
R5 + 1
COMPARE(1)
R5 + 2
COMPARE(A)
R5
COMPARE(2)
R5 + 3
COMPARE(0)
R5 + 1
COMPARE(1)
R5 + 2
COMPARE(A)
R5
COMPARE(2)
R5 + 3
COMPARE(0)
R5 + 1
COMPARE(3)
R5 + 4
COMPARE(1)
R5 + 2
COMPARE(4)
R5 + 5
COMPARE(2)
R5 + 3
COMPARE(3)
R5 + 4
COMPARE(4)
R5 + 5
For LED
COMPARE(5)
R5 + 6
For Touch Sense
COMPARE(6)
R5 + 7
Figure 24-3 Input Parameters Example (LED enabled only)
User’s Manual
ROM Library, V1.4
24-19
V1.1, 2010-09
XC83x
ROM Library
24.2.1.2 Inputs for SET_LDLINE_CMP Function (Touch-sense only)
If only Touch-sense module is enabled, the inputs overview is shown in Table 24-13,
Table 24-14 for common and different compare parameters setting (for oscillation
window) respectively. Examples of input parameters are also shown in Figure 24-4.
For flexibility, the user can choose common compare parameter for all pad turns or
choose different compare parameters for individual pad turn. This is also provided to give
better sensitivity for respective pads. If CMP_OPTION (at address R5) is programmed
as 0xFF, it means that different compare value is selected. Then the different compare
parameters are read, at IRAM address R5+1 onwards, for individual pad turn1). If
CMP_OPTION is not programmed as 0xFF, then common compare parameter for all
pad turns is selected, and this value is programmed at address R5 itself2).
In preparing compare value for Touch-sense, quantization effect is taken into
consideration in the function. The respective compare value will be XRL with 2, 4, 8, 16
etc. and finally updating the final value to SFR LTS_COMPARE. Quantization effect
gives better sensitivity and is transparent to the user as all are achieved by the function.
Table 24-13 Specifications of Setting LDLINE & Common COMPARE (TS only)
Subroutine
SET_LDLINE_CMP
Address
DFCFH
Input
R7 of current Register Bank:
Start IRAM address of LDLINE parameter
R5 of current Register Bank:
Start IRAM address of CMP_OPTION & COMPARE parameters
LDLINE parameters programmed into IRAM, address R7
@R7 = LDLINE parameter for COLA (Touch-sense)
COMPARE parameters programmed into IRAM, address R5
@R5 = Common COMPARE parameter1) for all pad turns
Output
SFR LTS_LDLINE is programmed.
SFR LTS_COMPARE is programmed.
Stack size required
2
Resource
used/destroyed
A, R0, R1, R2, R3, R4
1) This common Compare parameter cannot be 0xFF value.
1) See Table 24-14.
2) See Table 24-13.
User’s Manual
ROM Library, V1.4
24-20
V1.1, 2010-09
XC83x
ROM Library
Table 24-14 Specifications of Setting LDLINE & Different COMPARE (TS only)
Subroutine
SET_LDLINE_CMP
Address
DFCFH
Input
R7 of current Register Bank:
Start IRAM address of LDLINE parameter
R5 of current Register Bank:
Start IRAM address of CMP_OPTION & COMPARE
parameters
LDLINE parameters programmed into IRAM, address R7
@R7 = LDLINE parameter for COLA (Touch-sense)
COMPARE parameters programmed into IRAM, R5 .. R5+z1)
@R5 = CMP_OPTION (0xFF value)
@R5+1 = COMPARE parameter for PADT0
@R5+2 = COMPARE parameter for PADT1
...
@R5+z = COMPARE parameter for PADT(z-1)
Output
SFR LTS_LDLINE is programmed.
SFR LTS_COMPARE is programmed.
Stack size required
2
Resource
used/destroyed
A, R0, R1, R2, R3, R4
1) Depending how many Touch-sense pad turn(s) is/are enabled; z = number of pad turn(s) enabled
User’s Manual
ROM Library, V1.4
24-21
V1.1, 2010-09
XC83x
ROM Library
24.2.1.3 Inputs for SET_LDLINE_CMP Function (LED and Touch-Sense)
If both LED and Touch-sense modules are enabled, the inputs overview is shown in
Table 24-15 and Table 24-16 for common and different compare parameters setting (for
oscillation window) respectively. Examples of input parameters are also shown in
Figure 24-4 and Figure 24-5.
For flexibility, the user can choose common compare parameter for all pad turns or
choose different compare parameters for individual pad turn. This is also provided to give
better sensitivity for respective pads. If CMP_OPTION (at address R5) is programmed
as 0xFF, it means that different compare value is selected. Then the different compare
parameters are read, at IRAM address R5+1 onwards, for individual pad turn1). If
CMP_OPTION is not programmed as 0xFF, then common compare parameter for all
pad turns is selected, and this value is programmed at address R5 itself2).
In preparing compare value for Touch-sense, quantization effect is taken into
consideration in the function. The respective compare value will be XRL with 2, 4, 8, 16
etc. and finally updating the final value to SFR LTS_COMPARE. Quantization effect
gives better sensitivity and is transparent to the user as all are achieved by the function.
Table 24-15 Specifications of Setting LDLINE & Common COMPARE (LEDTS)
Subroutine
SET_LDLINE_CMP
Address
DFCFH
Input
R7 of current Register Bank:
Start IRAM address of LDLINE parameters
R5 of current Register Bank:
Start IRAM address of COMPARE parameters
LDLINE parameters programmed into IRAM R7.. R7+y1)
@R7 = LDLINE parameter for COLA (for Touch-sense)
@R7+1 = LDLINE parameter for COL0
...
@R7+y = LDLINE parameter for COL(y-1)
COMPARE parameters programmed into IRAM R5 .. R5+y1)
@R5 = Common COMPARE parameter2) for pad turns (COLA)
@R5+1 = COMPARE parameter for COL0
...
@R5+y = COMPARE parameter for COL(y-1)
Output
SFR LTS_LDLINE is programmed.
SFR LTS_COMPARE is programmed.
1) See Table 24-16.
2) See Table 24-15.
User’s Manual
ROM Library, V1.4
24-22
V1.1, 2010-09
XC83x
ROM Library
Table 24-15 Specifications of Setting LDLINE & Common COMPARE (LEDTS)
Stack size required
2
Resource
used/destroyed
A, R0, R1, R2, R3, R4
1) Depending how many LED column(s) is/are enabled; y = number of LED column(s) enabled. Maximum LED
columns that can be enabled are 7 when Touch-sense is enabled.
2) This common Compare parameter cannot be 0xFF value.
Table 24-16 Specifications of Setting LDLINE & Different COMPARE (LEDTS)
Subroutine
SET_LDLINE_CMP
Address
DFCFH
Input
R7 of current Register Bank:
Start IRAM address of LDLINE parameter
R5 of current Register Bank:
Start IRAM address of CMP_OPTION & COMPARE parameters
LDLINE parameters programmed into IRAM, address R7.. R7+y
@R7 = LDLINE parameter for COLA (for Touch-sense)
@R7+1 = LDLINE parameter for COL0
...
@R7+y = LDLINE parameter for COL(y-1)
COMPARE parameters programmed into IRAM, R5..R5+(y+z)1)
@R5 = CMP_OPTION (0xFF value)
@R5+1 = COMPARE parameter for COL0
@R5+2 = COMPARE parameter for COL1
...
@R5+y = COMPARE parameter for COL(y-1)
@R5+(y+1) = COMPARE parameter for PADT0
@R5+(y+2) = COMPARE parameter for PADT1
...
@R5+(y+z) = COMPARE parameter for PADT(z-1)
Output
SFR LTS_LDLINE is programmed.
SFR LTS_COMPARE is programmed.
Stack size required
2
Resource
used/destroyed
A, R0, R1, R2, R3, R4
1) Depending how many LED column(s) and Touch-sense pad turn(s) is/are enabled; y = number of LED
column(s) enabled, z = number of pad turn(s) enabled
User’s Manual
ROM Library, V1.4
24-23
V1.1, 2010-09
XC83x
ROM Library
Eg. No LED + 8 TS PAD enabled Eg. No LED + 8 TS PAD enabled Eg. 2 LED + 2 TS PAD enabled Eg. 2 LED + 2 TS PAD enabled
TS PADTx has different
TS PADTx has different compare TS PADTx has common
TS PADTx has common
compare value
value
compare value
compare value
LDLINE(A)
R7
LDLINE(A)
R7
CMP_OPTION =
0xFF
R5
Common
COMPARE(PADTx)
R5
LDLINE(A)
R7
LDLINE(A)
R7
LDLINE(0)
R7 + 1
LDLINE(0)
R7 + 1
LDLINE(1)
R7 + 2
LDLINE(1)
R7 + 2
COMPARE
(PADT0)
R5 + 1
COMPARE
(PADT1)
R5 + 2
CMP_OPTION =
0xFF
COMPARE
(PADT2)
R5 + 3
COMPARE (0)
R5 + 1
COMPARE (0)
R5 + 1
COMPARE
(PADT3)
R5 + 4
COMPARE (1)
R5 + 2
COMPARE(1)
R5 + 2
COMPARE
(PADT4)
R5 + 5
COMPARE
(PADT0)
R5 + 3
COMPARE
(PADT5)
R5 + 6
COMPARE
(PADT1)
R5 + 4
COMPARE
(PADT6)
R5 + 7
COMPARE
(PADT7)
R5 + 8
R5
Common
COMPARE(PADTx) R5
For LED
For Touch Sense
Figure 24-4 Input Parameters Examples 1(LED & Touch-Sense enabled)
User’s Manual
ROM Library, V1.4
24-24
V1.1, 2010-09
XC83x
ROM Library
Eg. 4 LED + 5 TS PAD enabled
TS PADTx has different
compare value
Eg. 4 LED + 5 TS PAD enabled Eg. 7 LED + 8 TS PAD enabled
TS PADTx has common
TS PADTx has different
compare value
compare value
Eg. 7 LED + 8 TS PAD enabled
TS PADTx has common
compare value
LDLINE(A)
R7
LDLINE(A)
R7
LDLINE(A)
R7
LDLINE(A)
R7
LDLINE(0)
R7 + 1
LDLINE(0)
R7 + 1
LDLINE(0)
R7 + 1
LDLINE(0)
R7 + 1
LDLINE(1)
R7 + 2
LDLINE(1)
R7 + 2
LDLINE(1)
R7 + 2
LDLINE(1)
R7 + 2
LDLINE(2)
R7 + 3
LDLINE(2)
R7 + 3
LDLINE(2)
R7 + 3
LDLINE(2)
R7 + 3
LDLINE(3)
R7 + 4
LDLINE(3)
R7 + 4
LDLINE(3)
R7 + 4
LDLINE(3)
R7 + 4
LDLINE(4)
R7 + 5
LDLINE(4)
R7 + 5
LDLINE(5)
R7 + 6
LDLINE(5)
R7 + 6
LDLINE(6)
R7 + 7
LDLINE(6)
R7 + 7
CMP_OPTION =
0xFF
R5
Common
COMPARE(PADTx)
R5
COMPARE(0)
R5 + 1
COMPARE(0)
R5 + 1
COMPARE(1)
R5 + 2
COMPARE(1)
R5 + 2
COMPARE(2)
R5 + 3
COMPARE(2)
R5 + 3
CMP_OPTION =
0xFF
COMPARE(3)
R5 + 4
COMPARE(3)
R5 + 4
COMPARE(0)
R5 + 1
COMPARE(0)
R5 + 1
COMPARE
(PADT0)
R5 + 5
COMPARE(1)
R5 + 2
COMPARE(1)
R5 + 2
COMPARE
(PADT1)
R5 + 6
COMPARE(2)
R5 + 3
COMPARE(2)
R5 + 3
COMPARE
(PADT2)
R5 + 7
COMPARE(3)
R5 + 4
COMPARE(3)
R5 + 4
COMPARE
(PADT3)
R5 + 8
COMPARE(4)
R5 + 5
COMPARE(4)
R5 + 5
COMPARE
(PADT4)
R5 + 9
COMPARE(5)
R5 + 6
COMPARE(5)
R5 + 6
COMPARE(6)
R5 + 7
COMPARE(6)
R5 + 7
COMPARE
(PADT0)
R5 + 8
COMPARE
(PADT1)
R5 + 9
COMPARE
(PADT2)
R5 + 10
COMPARE
(PADT3)
R5 + 11
COMPARE
(PADT4)
R5 + 12
COMPARE
(PADT5)
R5 + 13
COMPARE
(PADT6)
R5 + 14
For LED
COMPARE
(PADT7)
R5 + 15
For Touch Sense
R5
Common
COMPARE(PADTx)
R5
Figure 24-5 Input Parameters Examples 2 (LED & Touch-Sense enabled)
User’s Manual
ROM Library, V1.4
24-25
V1.1, 2010-09
XC83x
ROM Library
24.2.2
FINDTOUCHEDPAD Function (Touch-Sense)
The Touch-sense concept is based on a pad being a capacitor between the pad and
ground. A finger approaching this pad will alter the capacitance. To measure this
change, the arrangement is such that together with a resistor and the I/O pad we have
an RC oscillator. The oscillations are counted in an 8-bit counter over a pre-determined
period, essentially forming a frequency counter. This frequency counting (LTS_TSVAL)
happens for each pad turn. The user can determine the number of samples to
accumulate to form a total frequency counter (TOTAL_TSCTRL/H).
The function FINDTOUCHEDPAD, needed for successfully detecting if a pad has been
touched, consists the following features:
•
•
•
Find Average
Find LowTrip (Trip point)
Find which pad(s) is/are touched, if any. Generate status flag(s).
Figure 24-6 gives an overview of this function while Figure 24-7 shows the respective
SFR settings used for this function.
LPF Gain
2 Divisor n
Average0
Average1
Average2
Average3
Average4
Average5
Average6
Average7
Total_TSCTR x 2 n
LowTrip
subtraction
Y = X – Subtraction m
compare
+
PadFlag0
PadFlag1
PadFlag2
PadFlag3
PadFlag4
PadFlag5
PadFlag6
PadFlag7
increment PADT
i =0
ITF_EN
accumulate
AcCnt
Σ
LTS_TSVAL
i =1
low pass filter
Y’ = K/T*Y + X – 1/T *Y
K = T = 2 Divisor n
LTS _TSVAL
Figure 24-6 FINDTOUCHEDPAD Function Overview
User’s Manual
ROM Library, V1.4
24-26
V1.1, 2010-09
User’s Manual
ROM Library, V1.4
TSINx
24-27
IO pad
OD
TSCTRVAL
8bit counter
TSCTRR
pad control
EPULL
Oscillation pulse counter
TSCTRSAT
TSCTROVF
sensor
pad
(optional)
pull-up
external
COLA
pad select
PADTSW
interrupt
control
time frame
auto scan
TFF
ITF_EN
i=1
ΣLTS_TSVAL
AcCnt
accumulate
i=0
increment PADT
oscillator loop
TSOEXT
active-extend
PADT
subtraction
Divisor n
K= T = 2
LowTrip
n
Total_TSCTR x 2
Y = X– Subtraction m
lowpass filter
Average7
Average6
Average5
Average4
Average3
Average2
Average1
Average0
2
Divisor n
LPF Gain
Y’ = K/T*Y + X – 1/T*Y
pad osc enable
+
compare
-
PadFlag7
PadFlag6
PadFlag5
PadFlag4
PadFlag3
PadFlag2
PadFlag1
PadFlag0
XC83x
ROM Library
Figure 24-7 FINDTOUCHEDPAD Function - SFR Settings
V1.1, 2010-09
XC83x
ROM Library
24.2.2.1 Inputs of FINDTOUCHEDPAD Function
This function calculates a running average for each pad turn to eliminate any spurious
peaks and troughs in the pad frequencies and to create a stable value from which the
trip points can be calculated. The average is derived from the total values from number
of samples (input, AccumulatorCounter) and included low pass filter gain (input, divisor
n). It then takes the stored average and calculates the LowTrip (Trip point) by subtracting
an offset value (input, subtraction m) from the average. This LowTrip value will be the
determining factor if the key has been touched. Status Flags (output, PadResult,
PadFlag and PadError) will be the indication key factors of what is/are detected in the
function. Calculating Average and LowTrip values are skipped when at least one of the
pad flags is set (PadFlag Status!= 0x00).
Common or different Trip point for each pad turn can be chosen and is determined by
the Subtraction Option at IRAM address 0x32. If Subtraction Option is 0x00, common
subtraction m value is initialized at IRAM address 0x34. If different subtraction m values
are selected, Subtraction Option is programmed as the start IRAM address of these
subtraction m values. Common or different Oscillation window period (LTS_COMPARE)
can be determined by the user as well, refer to Section 24.2.1.
The details of the subroutine are listed in Table 24-17. The parameters for the function
are shown also in Section 24.2.2.2. Implementation details is shown in
Section 24.2.2.4.
Table 24-17 Specifications of Find Touched Pad Subroutine
Subroutine
FINDTOUCHEDPAD
Address
DFCCH
Input
Input Parameters at IRAM address or SFR input setting
LTS_GLOBCTL0.TS_EN = 11)
Enable Touch-sense function control and its respective settings
LTS_TSCTL.PADTSW = 0
User needs to disable the hardware control to use this function.2)
IRAM address 0x30
User’s Manual
ROM Library, V1.4
AccumulatorCounter
The number of samples to be accumulated to calculate the
average value. Values supported are 1 to 255
24-28
V1.1, 2010-09
XC83x
ROM Library
Table 24-17 Specifications of Find Touched Pad Subroutine (cont’d)
IRAM address 0x31
ShortCount
The value to be compared with a counter value (named
PadDownCounter (PDC)) to indicate a valid range to set the
Result flag. PDC < ShortCount indicates valid range. PDC is
initialized to be 0xFF at start of a detected pad touch, and is
decremented once at each period.
IRAM address 0x32
Subtraction Option or Subtraction m Address3)
The option to choose between common subtraction value or
different respective subtraction values for all touch pads. If
option is 0x00, it means common subtraction is chosen for all
touch pads. The common subtraction m value is at Iram address
0x34. If not 0x00, it means different subtraction values are
chosen for respective touch pads. In this case, the IRAM start
address for the subtraction m is given here.
IRAM address 0x33
Divisor n
Low pass filter gain (2n) for calculating the average value where
n is 1, 2, 3, 4, 5, 6, 7, 8 for low pass filter gain of 2, 4, 8... 256
IRAM address 0x34
Subtraction m value:
The offset value used to minus from Average to get the LowTrip
(Trip point) value.
Common subtraction m value4)
or
• Subtraction m Address5): Subtraction m value of PADT0
• Subtraction m Address+1: Subtraction m value of PADT1
• Subtraction m Address+2: Subtraction m value of PADT2
• Subtraction m Address+z: Subtraction m value of PADTz
where z is number of pad turn(s) enabled
or
user-defined IRAM
address in 0x32
IRAM address 0x2D
PadError Status
If bit is 1, function will be exited for that Touch-sense Pad Turn.
No analysis will be done. The user should clear this status when
PadFlag bit is 0 for future analysis.
IRAM address 0x2E
PadResult Status
If bit is 1, function will be exited for that Touch-sense Pad Turn.
No analysis will be done. The user should clear this status when
PadFlag bit is 0 for future analysis.
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ROM Library, V1.4
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V1.1, 2010-09
XC83x
ROM Library
Table 24-17 Specifications of Find Touched Pad Subroutine (cont’d)
Output
Output Parameters at IRAM address:
IRAM address 0x2D
PadError Status
Bit 0 indicates the error status of PADT0
Bit 1 indicates the error status of PADT1
..
Bit 7 indicates the error status of PADT7
The byte/bit(s) indicate(s) that the pad(s) is/are touched for too
long. The byte/bit(s) is/are not cleared by function, and must be
cleared by the user. Access this status only when PadFlag status
is 0.
IRAM address 0x2E
PadResult Status
Bit 0 indicates the result status of PADT0
Bit 1 indicates the result status of PADT1
..
Bit 7 indicates the result flag of PADT7
The byte/bit(s) indicate(s) that the pad(s) is/are touched within
valid range. The byte/bit(s) is/are not cleared by function, and
must be cleared by the user. Access this status only when
PadFlag status is 0.
IRAM address 0x2F
PadFlag Status
Bit 0 indicates the flag status of PADT0
Bit 1 indicates the flag status of PADT1
..
Bit 7 indicates the flag status of PADT7
When the byte/bit(s) is/are 1, it indicate(s) that the pad(s) is/are
identify as being touched and analysis is in progress. When
analysis is completed, the byte/bit(s) will be clear by the function.
The byte/bit(s) will be set and cleared by function, the user must
not tamper with this. The user can read the respective PadError
and PadResult bit status when respective PadFlag bit status is 0.
Stack size required 2
Resource
used/destroyed
A, R0, R1, R3, R4, R5, R6, R7
IRAM address 0x2D - 0x2F (3 byte)
XRAM address 0xF0EC - 0xF0FF (max 20 bytes)6)
1) To enable Touch-sense control, as well as number of Touch-Sense pad turns, and the interrupt flag(s) (Time
Frame/Time Slice)
2) The function will control the pad turn number and configure it in LTS_TSCTL.PADT SFR field.
3) The user can programmed this value as 0x34 (for example). And at IRAM address 0x34, the subtraction m
value for PADT0, at 0x35, subtraction m value for PADT1, at 0x36, the subtraction m value for PADT2...etc
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ROM Library, V1.4
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V1.1, 2010-09
XC83x
ROM Library
4) To use common subtraction m value for all touch pads, program subtraction option as 0x00 in iram address
0x32.
5) Subtraction m address is defined in iram address 0x32
6) The function stores parameters that are used to calculate respective Average values, find LowTrip and
determine pad touch status. The user must not modify the data in these locations to keep the touch-sensing
algorithm useful. Refer to Section 24.2.2.3for details.
Notes:
•
•
•
•
•
This function uses fixed IRAM address 0x2D to 0x34, and XRAM address 0xF0EC 0xF0FF. These addresses are not to be destroyed by other user-application. In the
event of error detection, the user may clear these addresses.
The number of Touch-sense Pad Turns enabled must be sequential, e.g. PADT0,
PADT1 etc. for the software round robin of the function to work properly. The user
cannot enable 3 pad turns and defined them as PADT0, PADT4 and PADT6 for
example, it has to be PADT0, PADT1 and PADT2.
Pad turn number will remain for (AccumulatorCounter+11)) time, and the function will
increment the pad turn when TSCTR_Counter2) is 0x00 and will repeat back to
PADT0 once the highest enabled pad turn number is set. For example, if
AccumulatorCounter is defined as 0x04, and 2 Touch-sense Pad Turns are enabled,
the sequences for pad turns will be PADT1, PADT1, PADT1, PADT1, PADT1,
PADT0, PADT0, PADT0, PADT0, PADT0, PADT1..etc. The cycle continues.
This function is normally called in a Time Frame interrupt. But the user can also call
this function in a Time Slice interrupt.
A check whether LTS_GLOBCTL1.FNCOL=0x07 is implemented in this function,
therefore the user can safely call this function in Time Slice interrupt, before
SET_LDLINE_CMP function, without extra code check in between. The function will
check if this Time Slice is for Touch-sense before executing the rest of the function.
If LTS_GLOBCTL1.FNCOL is not 0x07, function will exit. See Figure 24-13.
24.2.2.2 Outputs of FINDTOUCHEDPAD Function
This function detects a pad touch and determines the status of the pad touch. The
outputs are PadFlag, PadResult and PadError status.
The function checks if there is a touch (the current counter value is below the Trip point)
and sets corresponding flag in PadFlag status. When PadFlag is first set, a software
implemented Pad Down Counter (PDC) will be initialized to 0xFF, and it will be
decremented once every period3) till pad touch is removed/lifted or till PDC has been
1) Extra one count is for calculation of Average value.
2) TSCTR_Counter is a parameter in XRAM that holds the user-defined input AccumulatorCounter and will
decrement every time FINDTOUCHEDPAD function is entered when LTS_GLOBCTL1.FNCOL = 0x07 (for
Touch-sense)
3) All Enabled Pads Accumulated Count Period (AEPACP). See Equation (24.23)
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ROM Library, V1.4
24-31
V1.1, 2010-09
XC83x
ROM Library
decremented to 0x00. When PadFlag Status is set, it means the particular pad is being
assessed. During this time, the PadResult and PadError should be ignored. Once
assessment is completed, corresponding flag in PadFlag status will be cleared and the
outcome will be reflected in PadResult and PadError status.
There are 2 scenarios of a Touch-sense pad:
•
•
Pad is touched (PadFlag=1)
Pad is not touched (PadFlag=0)
There are 3 results of a pad being touched:
•
•
•
Valid pad touch (PadResult=1),
Invalid pad touch (short touch - ignore),
Long pad touch (PadError=1)
Once the touch is removed (the counter value is above the Trip point), the PDC is
checked and compared with a pre-determined threshold value, ShortCount (input). If
above this threshold, the PadFlag is simply cleared and no further action takes place.
This is regarded as a invalid key press.
If the PDC is below the threshold but >0, the PadFlag Status is cleared and the
corresponding bit of PadResult Status is set. This means that the pad touch is being
recognized. But once the PDC reaches 0, the PadFlag Status is cleared and the
corresponding bit in a variable called PadError Status is set. This means that there is a
detection of a long pad touch.
Because all these happen over a series of Time Slices, the user-application needs to
check that PadFlag is 0 before reading any PadError or PadResult status. A non-zero
PadFlag variable indicates that pads are still being processed.
PadFlag(F)
Pad Flag Status (IRAM address 0x2F)
7
6
5
Reset Value: 00H
4
3
2
1
0
PadTurn7 PadTurn6 PadTurn5 PadTurn4 PadTurn3 PadTurn2 PadTurn1 PadTurn0
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rw
User’s Manual
ROM Library, V1.4
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24-32
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V1.1, 2010-09
XC83x
ROM Library
Field
Bits
Type
Description
PadTurn0
0
rw
Pad Turn 0 of PadFlag
0B
Pad not touched
Pad touched
1B
PadTurn1
1
rw
Pad Turn 1 of PadFlag
Pad not touched
0B
Pad touched
1B
PadTurn2
2
rw
Pad Turn 2 of PadFlag
0B
Pad not touched
1B
Pad touched
PadTurn3
3
rw
Pad Turn 3 of PadFlag
0B
Pad not touched
Pad touched
1B
PadTurn4
4
rw
Pad Turn 4 of PadFlag
Pad not touched
0B
1B
Pad touched
PadTurn5
5
rw
Pad Turn 5 of PadFlag
0B
Pad not touched
Pad touched
1B
PadTurn6
6
rw
Pad Turn 6 of PadFlag
0B
Pad not touched
Pad touched
1B
PadTurn7
7
rw
Pad Turn 7 of PadFlag
Pad not touched
0B
1B
Pad touched
PadResult(R)
PadResult Status (IRAM address 0x2E)
7
6
5
Reset Value: 00H
4
3
2
1
0
PadTurn7 PadTurn6 PadTurn5 PadTurn4 PadTurn3 PadTurn2 PadTurn1 PadTurn0
rw
rw
rw
rw
rw
rw
Field
Bits
Type
Description
PadTurn0
0
rw
Pad Turn 0 of PadResult
Pad not valid
0B
1B
Pad valid
User’s Manual
ROM Library, V1.4
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ROM Library
Field
Bits
Type
Description
PadTurn1
1
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Pad Turn 1 of PadResult
0B
Pad not valid
Pad valid
1B
PadTurn2
2
rw
Pad Turn 2 of PadResult
Pad not valid
0B
Pad valid
1B
PadTurn3
3
rw
Pad Turn 3 of PadResult
0B
Pad not valid
1B
Pad valid
PadTurn4
4
rw
Pad Turn 4 of PadResult
0B
Pad not valid
Pad valid
1B
PadTurn5
5
rw
Pad Turn 5 of PadResult
Pad not valid
0B
1B
Pad valid
PadTurn6
6
rw
Pad Turn 6 of PadResult
0B
Pad not valid
Pad valid
1B
PadTurn7
7
rw
Pad Turn 7 of PadResult
0B
Pad not valid
Pad valid
1B
PadError(E)
PadError Status (IRAM address 0x2D)
7
6
5
Reset Value: 00H
4
3
2
1
0
PadTurn7 PadTurn6 PadTurn5 PadTurn4 PadTurn3 PadTurn2 PadTurn1 PadTurn0
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Field
Bits
Type
Description
PadTurn0
0
rw
Pad Turn 0 of PadError
0B
Pad is not error
Pad error (long press)
1B
PadTurn1
1
rw
Pad Turn 1 of PadError
Pad is not error
0B
1B
Pad error (long press)
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ROM Library, V1.4
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ROM Library
Field
Bits
Type
Description
PadTurn2
2
rw
Pad Turn 2 of PadError
Pad is not error
0B
Pad error (long press)
1B
PadTurn3
3
rw
Pad Turn 3 of PadError
Pad is not error
0B
Pad error (long press)
1B
PadTurn4
4
rw
Pad Turn 4 of PadError
0B
Pad is not error
1B
Pad error (long press)
PadTurn5
5
rw
Pad Turn 5 of PadError
0B
Pad is not error
Pad error (long press)
1B
PadTurn6
6
rw
Pad Turn 6 of PadError
Pad is not error
0B
1B
Pad error (long press)
PadTurn7
7
rw
Pad Turn 7 of PadError
0B
Pad is not error
Pad error (long press)
1B
24.2.2.3 XRAM Parameters of FINDTOUCHEDPAD Function
The FINDTOUCHEDPAD function calculates average for each pad turn and determines
whether a pad touch is valid, invalid or long touch (via output status). It stores parameters
to keep track of how long the pad is touched (PDC), accumulation of LTS_TSVAL and
the respective calculated AverageL/H for all pad turns. These parameters are used and
updated by the function, thus the user must not modify them to keep the Touch-sense
algorithm useful. The respective parameters, addresses and descriptions are listed in
Table 24-18.
Table 24-18 Parameters Stored in XRAM
Parameter
Address Description
PadDownCounter
(PDC)
0xF0FF
User’s Manual
ROM Library, V1.4
PDC1) is used to keep track of how long the pad is
touched. PDC is initialized to be 0xFF at start of a
detected pad touch, and is decremented once at each
period2). When pad touch is removed, PDC is
compared with input value, ShortCount, and/or 0x00
to decide if pad touch is valid, invalid or long touch.
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Table 24-18 Parameters Stored in XRAM (cont’d)
TOTAL_TSCTR
(High byte)
0xF0FE
TOTAL_TSCTR
(Low byte)
0xF0FD
TSCTR_Counter
0xF0FC
Average0 (High byte) 0xF0FB
TOTAL_TSCTRL/H3) is the accumulated Touchsense counter value (LTS_TSVAL) by input value,
AccumulatorCounter, times. This value will be used to
calculate Average value and to compare with LowTrip
value.4)
TSCTR_Counter5) keeps track on the accumulation
of the LTS_TSVAL, based on input value,
AccumulatorCounter.
Average value6) for pad turn 0 (PADT0)
Average0 (Low byte) 0xF0FA
Average1 (High byte) 0xF0F9
Average value6) for pad turn 1 (PADT1)
Average1 (Low byte) 0xF0F8
Average2 (High byte) 0xF0F7
Average value6) for pad turn 2 (PADT2)
Average2 (Low byte) 0xF0F6
Average3 (High byte) 0xF0F5
Average value6) for pad turn 3 (PADT3)
Average3 (Low byte) 0xF0F4
Average4 (High byte) 0xF0F3
Average value6) for pad turn 4 (PADT4)
Average4 (Low byte) 0xF0F2
Average5 (High byte) 0xF0F1
Average value6) for pad turn 5 (PADT5)
Average5 (Low byte) 0xF0F0
Average6 (High byte) 0xF0EF
Average value6) for pad turn 6 (PADT6)
Average6 (Low byte) 0xF0EE
Average7 (High byte) 0xF0ED
Average value6) for pad turn 7 (PADT7)
Average7 (Low byte) 0xF0EC
1) PDC could be modified in order to adjust the detection period to result in a PadError or PadResult Status.
2) Period refers to the All Enabled Pads Accumulated Count Period. See Equation (24.23).
3) When TSCTR_Counter is not 0x00, it means accumulation has not completed and the TOTAL_TSCTRL/H
value reflected is not total Touch-sense counter value yet.
4) Refer to Section 24.2.2.4 for implementation details.
5) When TSCTR_Counter is 0x00, the TOTAL_TSCTRL/H value reflected is the value to be compared with the
LowTrip value to determine whether a pad touch being lifted/removed is detected. At the next Time Slice or
Time Frame interrupt when PadFlag is 0, this value will be used to calculate corresponding Average value.
6) Average value is updated all the time, except when PadFlag is not 0x00 (pad touch is detected and being
assessed). Refer to Section 24.2.2.4 for implementation details on Average value calculation. The number of
XRAM addresses used, to store Average value for various pad turns, depends on the number of pad turns
enabled. Maximum is 16 addresses for 8 Average values. When not enabled, the respective addresses are
not used.
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ROM Library
24.2.2.4 Implementation Details of Function
The important formulas used in the function are how the Total_TSCTRL/H obtained, how
Average is calculated, how LowTrip (Trip point) is derived and finally how a comparison
is made to determine if a pad is touched or not touched. SFR LTS_TSVAL value is used
for this calculation.
Total value of all samples (TOTAL_TSCTRL/H) is accumulation of SFR LTS_TSVAL by
input, AccumulatorCounter, times, as shown in Equation (24.14).
(24.14)
AccumulatorCounter
∑
TOTAL_TSCTRL/H(x) =
LTS_TSVAL(i)
i=1
where i is the user-defined input AccumulatorCounter (number of samples required),
supporting value 1 to 255.
The Average is calculated as shown in Equation (24.15).
(24.15)
AVERAGEL/H(x-1)
AVERAGEL/H(x) = AVERAGEL/H(x-1) + TOTAL_TSCTRL/H(x) – -------------------------------------------------n
2
where n is the user-defined input Divisor n, supporting value 1 to 8.
The LowTrip (Trip point) value is calculated by subtracting the user-defined input
Subtraction m (offset) from the Average value, as shown in Equation (24.16).
(24.16)
LOWTRIPL/H(x) = AVERAGEL/H(x) – SUBTRACTION m
With the LowTrip value calculated from the Average value, the comparison is done with
the current accumulated LTS_TSVAL values in TOTAL_TSCTRL/H * 2n where n is the
user-defined input Divisor n.
A pad touch is identified when current accumulated LTS_TSVAL is less than LowTrip
value, as shown in Equation (24.17).
(24.17)
n
TOTAL_TSCTRL/H(x) × 2 < LOWTRIPL/H(x)
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A pad not touched or a pad touch being removed/lifted is identified when the current
accumulated LTS_TSVAL is more than LowTrip value, as shown in Equation (24.18).
(24.18)
n
TOTAL_TSCTRL/H(x) × 2 ≥ LOWTRIPL/H(x)
When pad touch is identified, a counter (PDC) is initialized to 0xFF and will start
decrementing till the pad touch is being removed/lifted. At this instant, the PDC is
compared with ShortCount (input) to determine whether the pad touch is a valid or invalid
touch.
Internal states
Because of the time multiplexed nature of the Touch-sense functionality, the function can
be in a number of states when entered and the states can be modified inside this function
and outside by the user application. There are 5 states in total: Idle State, Pad Touched
State, Pad Released State, Error State and Result State. Figure 24-8 shows the state
diagram of the various states and how transition is done from one state to the other.
IDLE
F
0
Total _TSCTRL /H * 2
>=
LowTrip L/H
n
R E
0 0
n
Total_TSCTRL /H * 2
<
LowTrip L/H
ERROR
error flag
cleared by
user
F
0
PDC = 0
R E
0 1
PAD
touched
F R E
1 0 0
Total_TSCTRL /H * 2
>=
LowTrip L/H
RESULT
result flag
cleared by user
F
0
PDC < SC
R E
1 0
PAD
released
F R E
1 1 0
n
PDC >= SC
Figure 24-8 State diagram
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ROM Library
Actions on entering a state:
IDLE:
On Enter: Check if Total_TSCTRL/H * 2n < LowTripL/H point for this pad turn
On Exit: If yes, set the corresponding PadFlag bit, start a counter (Pad Down Counter).
Counter preset value is 0xFF.
Pad Touched:
On Enter: Decrement PDC, check if PDC == 0, check if Total_TSCTRL/H * 2n <
LowTripL/H point for this pad turn
On Exit: Depending on the results of the checks, set the corresponding PadError bit and
clear PadFlag bit or set the PadResult bit
Pad Released:
On Enter: Check if PDC >= ShortCount
On Exit: Clear all flags if >= ShortCount, clear PadFlag bit if PDC < ShortCount
Pad Result:
On Enter: Check if PadResult bit is cleared by the user, if not, exit.
On Exit: IDLE
Pad Error:
On Enter: Check if PadError bit is cleared by the user, if not, exit.
On Exit: IDLE
Pad Down Counter - PDC
When function detects an initial pad touch, it will initialize the PDC value to 0xFF.
Function will decrement PDC value every period1) till pad touch is removed/lifted2). In
case of dual pads, PDC will only be decrement once during both pads’ analysis time
(able to detect that PDC is already decremented before). Figure 24-9 shows how the
Pad Down Counter PDC works, this is a count-down software counter. Period1) is its
clock.
1) All Enabled Pads Accumulated Count Period (AEPACP). See Equation (24.23).
2) Or till PDC has been decremented to 0x00.
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ROM Library
ShortCount
Threshold
Invalid Pad Touch
(Too short)
Valid Pad Touch
Long Pad Touch
AEPACP
...
FFH FEH ...
00H
Counter preset value (0xFF)
Figure 24-9 Pad Down Counter - PDC
Average[0]
Subtraction m (Offset)
T ota l_ T S CT R L/H
Trip point (LowTrip)
Valid Pad Touch
Long Pad Touch
Invalid Pad Touch
(Too short)
PadFlag[0]
PadResult[0]
PadError[0]
Cleared by
the application
All Enabled Pads Accumulated Count Period (AEPACP)
PDC >=
ShortCount
PDC <
ShortCount
PDC <
0x00
Figure 24-10 Timing Diagram
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ROM Library
Figure 24-10 shows the timing diagram and the interaction between PadFlag,
PadResult, PadError and PDC for Pad turn 0. The Trip point (LowTrip) can be fixed or
as in this illustration, hysteresis can be added whenever a padflag is set (by changing
the user-input subtraction m)
The PDC gets pre-loaded with its time-out value on the first PadFlag being set. In any
subsequent pad turn, this counter decrements until either it reached 0 or until all PadFlag
bits are cleared where it is then set to 0. If during a pad turn, the last remaining set
PadFlag gets cleared the PDC gets set to 0 on exit of the function. This can happen
either when a pad is touched too briefly (short count) or when the last pad is released
before PDC times out.
A corner case can arise when the user does not clear the PadError or PadResult before
another pad is touched. In such a situation it is possible that more than two bits in the
PadResult can show up if for example the first valid result was a combination pad being
touched and the next one touched was a single pad whose pad was not part of the
previous combination pad.
PDC is decremented once every 1 period (All Enabled Pads Accumulated Count Period),
even if dual PadFlag bits maybe set.
Time Slice, Time Frame and Period Definition
There is a Time Slice, Time Frame and Periods naming convention. There is hardwarecontrolled scheme period and software-controlled ROM Library scheme period (Single
Pad Accumulated Count Period and All Enabled Pads Accumulated Count Period). The
timing definitions, when Touch-sense is enabled, are shown in the equations below. The
relationship of the periods are illustrated in Figure 24-11.
A Time Slice Duration (TSD) is calculated as shown in Equation (24.19).
(24.19)
Prescaler × 256Time Slice Duration = -----------------------------------f CLK
where
prescaler
is
the
LEDTS-Counter
Clock
Pre-Scale
Factor
(LTS_GLOBCL0.CLK_PS) and the input clock fCLK will be either 8 MHz or 24 MHz,
depending on the USER_ID setting.
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A Time Frame Duration (TFD) is defined as shown in Equation (24.20).
(24.20)
Time Frame Duration = (Number of Time Slice(s)) × TSD
A Period (Hardware-controlled scheme) is defined as shown in Equation (24.21).
(24.21)
Period (Hardware-Controlled Scheme) = (Number of Touch-sense input(s) TSIN[x]) × TFD
For software-controlled ROM Library Scheme, the Single Pad Accumulated Count
Period (SPACP) is defined as shown in Equation (24.22).
(24.22)
Period (SPAC) = ( AccumulatorCounter + 1 ) × TFD
where AccumulatorCounter is the user-defined input for FINDTOUCHEDPAD function.
For software-controlled ROM Library Scheme, the All Enabled Pads Accumulated Count
Period (AEPACP) is defined as shown in Equation (24.23).
(24.23)
Period (AEPAC) = Period (SPAC) × (Number of Touch-sense input(s) TSIN[x])
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PDC is decremented every AEPACP while pad is being touched. When pad touch is
removed/lifted, PDC is checked. Valid pad touch occurs when PDC < ShortCount. Long
pad touch occurs when PDC has decremented to 0x00. The minimum and maximum
valid pad detection period are defined as shown in Equation (24.24) and
Equation (24.25) respectively.
(24.24)
Minimum Valid Pad Detection Period (VPDP) = ( 0xFF – ShortCount + 1 ) × AEPACP
(24.25)
Maximum Valid Pad Detection Period (VPDP) = 0xFF × AEPACP
The user is able to reduce the maximum valid pad detection period (to get faster output
PadError=1) by introducing an ErrorCount, as shown in Equation (24.26).
(24.26)
Maximum Valid Pad Detection Period (VPDP) = ( 0xFF – ErrorCount + 1 ) × AEPACP
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For example, 7 LEDs and 3 Touch Sense Pad Turns are enabled
1 Time-Slice
PADT0
6 5
4
3
2
1
0 TS 6
PADT1
5
4
3
2
1
0 TS 6
PADT0
PADT2
5
4
3
2
1
0 TS 6
5
4
3
2
1
0 TS 6
1 Time-Frame
1Period (hardware-controlled scheme)
For example, 7 LEDs and 3 Touch Sense Pad Turns are enabled, AccumulatorCounter = 0x04
1 Time-Slice
PADT0
6 ...… 0 TS 6
1 TimeFrame
PADT0
PADT0
....… 0 TS 6 …… 0 TS 6
…...
PADT0
PADT1
PADT1
PADT1
..… 0 TS 6 ….… 0 TS 6 ….... 0 TS 6 ….… 0 TS 6
….. 0 TS 6
1Period
(software-controlled ROM library scheme)
(Single Pad Accumulated Count Period)
PADT1
PADT0
…...
PADT0
…...
…...
…...
…...
…...
…...
PADT2
…...
…...
…...
…...
…...
PADT0
…...
…...
…...
…...
…...
…...
…...
1Period
(Single Pad Accumulated
Count Period
1Period
(software-controlled ROM library scheme)
(All Enabled Pads Accumulated Count Period)
PDC decrements once each time in 1 period (All Enabled PADTx Accumulated Count Period) where a pad is touched,
in the case of a combination pad (2 pads touched), the PDC decrements once also in 1 Period (All Enabled PADTx Accumulated Count Period)
Figure 24-11 Period Relationship for Software-Controlled ROM Library Scheme
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ROM Library
24.2.3
Use of the functions in Interrupts
With correct inputs prepared for the functions, the functions can be called from Time
Slice interrupt or Time Frame interrupt, depending on whether LED or/and Touch-sense
is enabled. Figure 24-12 and Figure 24-13 illustrate how the user can use and call the
functions in respective situations.
* function in ROM
When only LED is enabled.
When only Time Slice interrupt is enabled
Time Slice Interrupt
(TimeSliceFlag)
LED Column Data for
display,
COMPARE value for
brightness
SET_LDLINE_CMP ()*
RETI
When only TS is enabled.
When only Time Frame/Slice interrupt is enabled
Time Frame/Slice Interrupt
(TimeFrame/SliceFlag)
Calculate Average,
LowTrip, which pad
touched
FINDTOUCHEDPAD()*
Set COMPARE value for
respective pad’s oscillation
window
SET_LDLINE_CMP ()*
RETI
When only TS are enabled.
When Time Slice & Time Frame interrupts are enabled
Set COMPARE value for
respective pad’s oscillation
window
Time Slice Interrupt
(TimeSliceFlag)
SET_LDLINE_CMP ()*
RETI
^^Time Frame Interrupt has higher priority(default)
Time Frame Interrupt
(TimeFrameFlag)
Calculate Average,
LowTrip, which pad
touched
FINDTOUCHEDPAD ()*
RETI
Figure 24-12 Calling of Functions in Interrupt Routine (i)
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ROM Library
* function in ROM
When LED and TS are enabled.
When Time Slice and Time Frame interrupts are enabled
Time Slice Interrupt
(TimeSliceFlag)
LED Column Data for
display, COMPARE
value for brightness or
oscillation window
SET_LDLINE_CMP ()*
** Called every time slice
regardless of touch sense
or LED column slice
RETI
Time Frame Interrupt
(TimeFrameFlag)
Calculate Average,
LowTrip, which pad
touched
FINDTOUCHEDPAD ()*
^^ Called every time Frame
esp for touch sense
RETI
When LED and TS are enabled.
When only Time Slice interrupt is enabled
Time Slice Interrupt
(TimeSliceFlag )
Calculate Average,
LowTrip, which pad
touched
LED Column Data for
display, COMPARE
value for brightness or
oscillation window
FINDTOUCHEDPAD ()*
^^ If FNCOL is not 0x07,
routine will be exited
SET_LDLINE_CMP ()*
RETI
Figure 24-13 Calling of Functions in Interrupt Routine (ii)
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ROM Library
24.3
EEPROM Emulation ROM Library
The XC83x provide EEPROM emulation functionality via the ROM library. The EEPROM
is emulated using the on-chip flash memory. The ROM library provide a framework to
access the emulated EEPROM.
The ROM library used the following application note as a reference, AP0805710
XC866/XC886/XC888 EEPROM EMULATION.
24.3.1
Feature
The EEPROM emulation ROM library has the following feature
•
•
•
Provide functions to initialize, fix, read and write to emulated EEPROM
Support EEPROM emulation size of 31, 62, 93 or 124 bytes
Up to 1.6 millions endurance cycles for a data retention time of 2 years
24.3.2
System requirement
The ROM library has several requirement
•
•
•
•
Use 512 bytes of flash memory from address AE00H to AFFFH for EEPROM
emulation1)
Written on KEIL C51 toolchain (small memory model, big endian, register calling
convention).
Only support polling based flash operation2)
No support for detection of aborted programming operation
24.3.3
Concept
EEPROM emulation is implemented using 512 bytes of flash that is divided into 2 logical
sectors. At any one time only one of the logical sectors is the “active sectors” i.e. the
sector containing the latest dataset. The user application needs to initialise the emulated
EEPROM before it can be used. This can be done by calling the initialisation function
and specifying the desired emulation scheme. The initialisation function will update the
information in “EEPROMInfo data structure” on Page 24-49 that is used by the ROM
library functions.
The ROM library supports 4 emulation scheme i.e. Mode 0, Mode 1, Mode 2 & Mode 3.
Basically each mode represent the size of the emulated EEPROM.
The user application will access the emulated EEPROM using logical address. The
number of valid logical address is dependent on the size of the emulated EEPROM.
Each logical address represent 32 bytes of data where 31 bytes are user data and one
1) For 8K device EEPROM is emulated from address 1E00H to 1FFFH. For 4K device, EEPROM is emulated
using address 0E00H to 0FFFH
2) Boot ROM flash user-routines (non-background) are used and all interrupts including NMI must be disabled.
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status byte. This represent the required size for each flash write operation i.e. flash word
line (WL) size.
The logical address provides a convenient abstraction so that user application don’t
need to deal with the actual physical flash address that is used for emulation.
The status byte is used by the ROM library to manage the EEPROM emulation. It is
written at the end of each flash wordline. The user application can safely ignore this
status byte.
Table 24-19 EEPROM emulation scheme
Emulation Scheme
Emulated EEPROM size (byte)
Valid logical address
Mode_0
31 data + 1 status
WL_0
Mode_1
62 data + 2 status
WL_0 & WL_1
Mode_2
93 data + 3 status
WL_0, WL_1 & WL_2
Mode_3
124 data + 4 status
WL_0, WL_1, WL_2 & WL_3
Table 24-20 Relationship between logical address and data bytes
Logical address
Data bytes
WL_0
0 to 30
WL_1
31 to 61
WL_2
62 to 92
WL_3
93 to 124
Additionally the initialisation function can perform some basic error detection. It can
detect if an abort occur during a flash erase operation or emulated EEPROM is used for
first time. The initialisation function assumes that flash area used for EEPROM emulation
is already erased when its used for the first time.
The user application will access the emulated EEPROM using logical address via the
read and write function. Each read operation will read out 31 user data bytes and 1 status
byte. The 32 bytes of data will be stored in IRAM location provided by the calling function.
Similarly each write operation can only program 31 bytes and 1 status byte. The data to
be written should be stored in IRAM location provided by the calling function. The status
byte value would be automatically be updated by the write function.
Once the “active sector” is completely filled with data, subsequent write operation will be
in the next logical sector. The next sector is set as the "active sector" and the previous
"active sector" is reclaimed. The reclaim operation involves, programming all valid data
from the previous "active sector" to the current "active sector" before erasing the
previous "active sector".
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To update less than 31 data bytes in the emulated EEPROM, user application needs to
perform a read to the logical address where the data resides. Once the read data are
stored in the IRAM, user application will then need to update the relevant data in IRAM
with the desired data. This is then followed by a call to write function to program the data
into the emulated EEPROM.
24.3.4
API description
The EEPROM emulation operation is controlled via one data structure and 4 functions.
Additionally some definition is provided for ease of use.
24.3.4.1 Constant definition
Several constant definition was added to give meaningful name and promote code
readability
EEPROM Emulation scheme
•
•
•
•
#define MODE_0 32
#define MODE_1 64
#define MODE_2 96
#define MODE_3 128
Logical Address
•
•
•
•
#define WL_0 0
#define WL_1 1
#define WL_2 2
#define WL_3 3
24.3.4.2 EEPROMInfo data structure
The EEPROM emulation API use a data structure called EEPROMInfo to manage the
EEPROM emulation operation.
typedef struct EEPROMInfo{
unsigned int ActiveSector;
unsigned int WriteAddress;
unsigned char DataSize;
}idata EEPROMInfo;
EEPROMinfo is a structure containing 3 variables, ActiveSector, WriteAddress and
DataSize. The structure must be declared by the user application and must reside in
indirect IRAM address.
ActiveSector store the current "active sector" address. It is used by ReadEEPROM() to
find the current emulated dataset. WriteAddress store the start address to write new data
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set when the user application calls WriteEEPROM(). Both variable is updated by call to
InitEEPROM() and WriteEEPROM(). DataSize store the EEPROM emulation dataset
size
EEPROMInfo should not be modified directly by the user. It only should be modified by
functions provided by EEPROM emulation API.
24.3.4.3 Functions
The EEPROM emulation API provide 4 functions
•
•
•
•
InitEEPROM
FixEEPROM
WriteEEPROM
ReadEEPROM
These functions need to be used when accessing the emulated EEPROM.
InitEEPROM
Table 24-21 InitEEPROM
Function name
InitEEPROM
Function prototype unsigned char InitEEPROM(unsigned char mode,
EEPROMInfo *config)
Input
mode - Emulation scheme i.e. size of emulated EEPROM. Valid
value is 32, 64, 96 and 128
config - Pointer to EEPROMInfo data structure
Return
status - Status of emulated EEPROM. Input to FiXEEPROM()
0x0 - Status of emulated EEPROM is OK
0x1 - Sector 8 & 9 needs to be erased
0x2 - Sector 6 & 7 needs to be erased
0x3 - Sector 6 to 9 needs to be erased
Max stack size
4 bytes
InitEEPROM() will initialize the EEPROMInfo data structure based on the selected
emulation mode. It should be called at least once before using the other API functions.
InitEEPROM() assume that flash area used for EEPROM emulation is in erased
condition when InitEEPROM() is called for the first time.
It will update the EEPROM configuration to indicate the current "active sector" and the
flash address that is to be written to on subsequent call to WriteEEPROM().
User’s Manual
ROM Library, V1.4
24-50
V1.1, 2010-09
XC83x
ROM Library
The “active sector” is selected based on the sector containing a valid status byte. If both
logical sector contains valid status byte, the one containing the least amount of valid
status byte is selected as the active sector. Additionally InitEEPROM() will return an error
status requesting the sector with the most valid status byte to be erased. However
there’s a scenario where this might not be desired e.g. if there was a sudden power off
during a WriteEEPROM() reclaim operation.
For example a 124 bytes configured EEPROM is powered off suddenly during the
WriteEEPROM() reclaim operation. Thus not all the 124 bytes of valid information is
copied to the new sector.
Once the “active sector” has been determined, the flash address to be written is
determined as the first flash WL without a valid status byte in the “active sector”.
InitEEPROM() will also check for situation where erase operation has been unexpectedly
aborted and return a status byte indicating sectors that needs to be re-initialised.
FixEEPROM
Table 24-22 FixEEPROM
Function name
FixEEPROM
Function prototype void FixEEPROM(unsigned char sector_status,
unsigned char idata *buffer)
Input
sector_status - status returned by InitEEPROM()
buffer - Pointer to 32 bytes buffer in IRAM location
Return
None
Max stack size
4 bytes + 12 bytes (Boot ROM User Routines)
FixEEPROM() will take the status byte returned by InitEEPROM() and fix the invalid
sectors. It will erase the flash sectors and write a status byte to indicate that the sector
has been erased.
A pointer to a buffer of 32 bytes in IRAM is needed to enable flash write operation. For
save operation ensure that flags in NMISR SFR are cleared before calling this function.
User’s Manual
ROM Library, V1.4
24-51
V1.1, 2010-09
XC83x
ROM Library
WriteEEPROM
Table 24-23 WriteEEPROM
Function name
WriteEEPROM
Function prototype void WriteEEPROM(unsigned char address, char
idata * src, EEPROMInfo *config)
Input
address - Logical address of emulated EEPROM to write to
src - Pointer to 32 bytes of data in IRAM that is to be written
config - Pointer to EEPROMInfo data structures
Return
None
Max. stack size
6 bytes + 12 bytes (Boot ROM User Routines)
WriteEEPROM() will perform the write operation based on EEPROM configuration. It will
program to the valid flash address and update the EEPROM configuration. Each write
operation is 32 bytes (31 data bytes + 1 status byte).
Additionally it will "reclaim" the previous "active sector" when its filled with data. For save
operation ensure that all NMISR SFR flags are cleared before calling this function.
ReadEEPROM
Table 24-24 ReadEEPROM
Function name
ReadEEPROM
Function prototype unsigned char ReadEEPROM(unsigned char address,
char idata * dst, EEPROMInfo *config)
Input
address - Logical address of emulated EEPROM to read from
dst - Pointer to 32 bytes IRAM buffer to store read data
config - Pointer to EEPROMInfo data structure
Output
status - Read operation result
0x00 - Read operation successful
0xFF - Read operation fail
Max stack size
User’s Manual
ROM Library, V1.4
2 bytes
24-52
V1.1, 2010-09
XC83x
ROM Library
ReadEEPROM() will search the current "active sector" for the most current data based
on the given "address". It will always return 32 bytes of data i.e. 31 data byte + 1 status
bytes.
The "address" takes the form of a number from 0 to 3. For dataset size of 32bytes, only
address 0 is valid. For dataset size of 128, address 0 to 3 is valid. Address 2, will return
byte 64 to byte 95 where byte 95 is the status bytes.
Function will return an error code if the address can't be found.
24.3.4.4 Example of API usage
Here’s an example in ‘C’ that use the EEPROM emulation API. The example shows how
to initialise the flash area for use and some error handling mechanism.
#include "EEPROM.h"
void main(void)
{
/*EEPROM emulation required data structure*/
char idata buffer[32];
EEPROMInfo config;
unsigned char eeprom_status;
/*Initialised and check emulated EEPROM integrity*/
eeprom_status = InitEEPROM(MODE_3, &config);
if(0 != eeprom_status){
if( 0x0 == config.ActiveSector){
/*Erase abort detected or first time using EEPROM*/
/*Initialise invalid sectors*/
FixEEPROM(eeprom_status, buffer);
}else{
/*Programming or erasing aborted suddenly during reclaiming
operation */
/*Depending on user application, additional action can be taken*/
/*Initialise invalid sectors. Data would be erased*/
FixEEPROM(eeprom_status, buffer);
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ROM Library, V1.4
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V1.1, 2010-09
XC83x
ROM Library
}
/*Check that EEPROM sectors are in valid condition*/
eeprom_status = InitEEPROM(MODE_3, &config);
if (0 != eeprom_status){
/*Fatal failure in EEPROM*/
while(1);
}
}
/*User application code*/
/*Example of reading and writing to emulated EEPROM*/
/*Get current data*/
ReadEEPROM(WL_1, &buffer, &config);
/*Update data to store and write to EEPROM*/
buffer[20] += 1;
/*Write back updated data*/
WriteEEPROM(WL_1, &buffer, &config);
while(1); /*Wait for power off*/
}
User’s Manual
ROM Library, V1.4
24-54
V1.1, 2010-09
XC83x
Keyword Index
Keyword Index
A
ADC
Accumulated Application Read View
22-65
Alias Feature 22-54
Boundary Flag 22-53
Channel Scan Request Source Handling 22-19
Channel Scan Source 22-18
Clocking Scheme 22-13
Conversion Timing 22-61
Data Reduction and Filtering 22-80
Digital Low Pass Filter Mode 22-82
Standard Data Reduction Mode
22-81
Differential Like Measurement 22-46
Digital Low Pass Filtered Application
Read View 22-66
Error Definitions 22-12
Differential non linearity error (DNL)
22-12
Gain Error 22-12
Integral non linearity error (INL)
22-12
Offset Error 22-12
Total unadjusted error (TUE) 22-12
Interrupt Request Handling 22-83
Channel Events 22-83
Out of Range Comparator Events
22-83
Request Source Events 22-83
Result Events 22-83
Limit Checking 22-52
Out of Range Comparator (ORC)
22-57
Out of range comparator (ORC) 22-9
Queued Request Source Handling
22-25
Queued Source 22-18
Reference Selection 22-45
User’s Manual
Registers
CHCTRx (x = 0 - 2) 22-48
CHCTRx (x = 3 - 5) 22-49
CHCTRx (x = 6 - 7) 22-49
CHINCR 22-89
CHINFR 22-87
CHINSR 22-88
CNF 22-59
CRCR1 22-23
CRMR1 22-21
CRPR1 22-24
ENORC 22-58
ETRCR 22-37
EVINCR 22-86
EVINFR 22-84
EVINSR 22-85
GLOBCTR 22-14
GLOBSTR 22-15
INPCR0 22-51
LCBR0 22-54
LCBR1 22-54
LORE 22-60
PRAR 22-41
Q0R0 22-34
QBUR0 22-36
QINR0 22-33
QMR0 22-29
QSR0 22-31
RCRx (x = 0 - 3) 22-77
RESRxH (x = 0 - 3) 22-72
RESRxL (x = 0 - 3) 22-69, 22-72,
22-75
VFCR 22-79
Request Source Arbitration 22-38
Standard Application Read View 22-65
Alternate user BSL mode 5-5
B
Bitaddressable 3-10
BMI 5-1
Boot and Startup 5-1
L-1
V1.1, 2010-09
XC83x
Keyword Index
Boot ROM 3-1
Boot ROM operating mode 5-4
Alternate user BSL mode 5-5
Boot-Loader Mode 5-4
OCDS mode 5-4
User mode (diagnostic) 5-4
User mode (productive) 5-4
Boot-loader 4-8, 4-13, 5-4
Brownout reset 7-7
Buffer mechanism 4-4
C
Capture/Compare Unit 6
Register map 21-131
CCU6
Block Diagram 21-3
Hall Sensor Mode 21-90
Interrupt Handling 21-110
Multi-Channel Mode 21-87
Registers
CC63RH 21-83
CC63RL 21-83
CC63SRH 21-84
CC63SRL 21-84
CC6xRH 21-46
CC6xRL 21-46
CC6xSRH 21-47
CC6xSRL 21-47
CMPMODIFH 21-54
CMPMODIFL 21-53
CMPSTATL 21-51, 21-52
IENL 21-120, 21-121
INPH 21-125
INPL 21-124
ISL 21-112, 21-113
ISRL 21-118
ISSL 21-116
MCMCTR 21-104
MCMOUTH 21-109
MCMOUTL 21-107
MCMOUTSH 21-106
MCMOUTSL 21-106
MODCTRH 21-99
User’s Manual
MODCTRL 21-98
Offset addresses 21-5
Overview 21-4
PISEL0H 21-128
PISEL0L 21-127
PISEL2 21-129
PSLR 21-103
T12DTCH 21-49
T12DTCL 21-49
T12H 21-43
T12L 21-43
T12MSELH 21-55
T12MSELL 21-55
T12PRH 21-44
T12PRL 21-44
T13H 21-79
T13L 21-79
T13PRH 21-81
T13PRL 21-81
TCTR0H 21-59
TCTR0L 21-57
TCTR2H 21-63
TCTR2L 21-61
TCTR4H 21-65
TCTR4L 21-64
TRPCTRH 21-101
TRPCTRL 21-100
T12 21-17
Capture Modes 21-37
Compare Mode 21-25
Counting Scheme 21-21
Dead-Time Generation 21-32
Hysteresis-like Control Mode 21-31
Output Modulation and Level Selection 21-35
Shadow Register Transfer 21-41
T13 21-67
Compare Mode 21-74
Counting Scheme 21-70
Shadow Register Transfer 21-77
Synchronization to T12 21-72
Trap Handling 21-85
Chip identification number 1-12
L-2
V1.1, 2010-09
XC83x
Keyword Index
Circular stack memory 4-4
CORDIC Coprocessor 13-1
Accuracy 13-10
Arctangent LUTs 13-13
Data Format 13-9
Domains of Convergence 13-8
Equations 13-6
Interrupt 13-13
Linear LUT 13-14
Operating Modes 13-5
Operation 13-4
Overflow Considerations 13-9
Performance 13-12
Registers 13-15
Result Data 13-5
Correction algorithm 4-11
Count Clock 15-10
Counter 14-1
CPU 2-1
Functional Blocks 2-1
Instruction Table 2-10
Instruction Timing 2-8
Registers 2-3
ACC 2-3
B Register 2-3
Data Pointer 2-3
PCON 2-6
PSW 2-3
Stack Pointer 2-3
D
Data memory 3-2
Debug System 10-1
Functional Overview 10-5
Breakpoints 10-5
Debug Suspend Control 10-7
Monitor Program 10-6
Monitor Running 10-7
Return to User Program 10-7
Single Step 10-8
Document
Acronyms 1-14
Terminology 1-14
User’s Manual
Textual conventions 1-13
Dynamic error detection 4-11
E
EEPROM emulation 4-4
Embedded voltage regulator 7-1
Low power voltage regulator 7-2
Main voltage regulator 7-2
Threshold voltage levels 7-2
Error Correction Code 4-11
External data memory 3-3
F
Flash 4-1
Endurance 4-4
Erase mode 4-10
Memory address mapping 4-2
Non-volatile 4-1
Operating modes 4-10
Power-down mode 4-10
Program mode 4-10
Ready-to-read mode 4-10
Sector 4-3
Flash program memory 3-1
G
Gate disturb 4-8
GPIO 11-1
H
Hamming code 4-11
High-impedance 11-3
I
Idle mode 7-12, 7-18
IEN0 14-13
IIC 18-1–18-22
Baud rate generation 18-5
Bus arbitration 18-6
Clock synchronization 18-6
Master receive 18-10
Master transmit 18-7
Operating modes 18-7
L-3
V1.1, 2010-09
XC83x
Keyword Index
Register description 18-15
Register map 18-15
Slave receive 18-13
Slave transmit 18-12
Software reset 18-7
Status code 18-4
In-Application Programming 4-13, 4-14
Aborting background Flash erase 4-17
Background Flash erase 4-16
Background Flash program 4-15
Flash read mode status 4-18
Non-background Flash erase 4-16
Non-background Flash program 4-15
In-System Programming 4-13
Inter-IC Bus 18-1
Internal data memory 3-3
Internal RAM 3-1
Interrupt 9-1
Flags 9-33
Handling 9-12
Priority 9-31
Registers 9-16
Structure 9-10
Type 1 9-11
Type 2 9-11
Interrupt Response Time 9-13
Baud rate detection 17-19
Baud rate range selection 17-17
Break field 17-15
Break/synch field detection 17-17
Header transmission 17-16
LIN frame 17-14
LIN protocol 17-14
Synch byte 17-15
M
MDU 12-1–12-14
Division 12-4
Division with single right shift 12-6
Error detection 12-6
Interrupt generation 12-7
Multiplication with single left shift 12-5
Normalize 12-5
Register description 12-8
Register map 12-8
Shift 12-5
Memory organization 3-1
Special Function Registers 3-4
Address extension by mapping 3-4
Mapped 3-4
Standard 3-4
Address extension by paging 3-7
Local address extension
L
LED and Touch-Sense Controller 20-1
LED Controller 20-1
LEDTSCU 20-1
FNCOL Interpretation 20-16
Function 20-5
Function Enable & Control 20-15
Interrupt 20-19
LED Driving 20-8
Pin Control 20-18
Pin Current Capability 20-10
Registers 20-20
Time-Multiplexed Function 20-14
Timing Calculations 20-16
Touch-Sensing 20-11
LIN 17-14–??
User’s Manual
3-7
Save and restore 3-8
Memory protection 3-4
Minimum erase width 4-3
Minimum program width 4-8
Multifold replications 4-4
Multiplication/Division Unit 12-1
O
OCDS 10-1
Breakpoint 10-9
External Break 10-11
Hardware 10-9
On Instruction Address
L-4
V1.1, 2010-09
XC83x
Keyword Index
10-9
On
IRAM
Address
10-10
Software 10-11
Breakpoint Reaction 10-12
NMI 10-13
NMI Priority 10-15
OD 15-13
P
P0 register description 11-24
P1 register description 11-32
P2 register description 11-41
P3 register description 11-46
Parallel ports 11-1
General bidirectional port structure
11-3
High current bidirectional port structure
11-6
Input mode 11-3
Input port structure 11-7
Kernel registers 11-10
Alternate input functions 11-13
Alternate output functions 11-13
Input control register 11-17
Open drain control register 11-12
Overcurrent detect register 11-15
Overcurrent protection enable register 11-16
Port data in register 11-11
Port data out register 11-11
Pull-Up/Pull-Down device register
11-12
Px_ALTSELn 11-14
Px_OD 11-12
Px_PUDEN 11-13
Px_PUDSEL 11-13
Register addresses 11-8
Slew register 11-16
Normal mode 11-2
Open drain mode 11-2
Overcurrent condition 11-5
User’s Manual
P0 11-18
P1 11-28
P2 11-37
Peripheral clock management 7-23
Personal computer host 4-13
Power-down mode 7-12
Power-down wake-up reset 7-7
Power-on reset 7-2, 7-6
Prewarning period 8-4
Program memory 3-2
R
Read access time 4-1
Real-Time Clock
Mode 0 16-3
Mode 2 16-7
Register Overview 3-13
Reset
Module behavior 7-8
RS-232 4-13
RTC 16-1
Basic Timer Operation 16-3
Mode 1 16-5
Mode 3 16-7
Oscillator 16-2
Registers Description 16-9
RTC registers 16-10
S
Schmitt trigger 11-4
Sectorization 4-3
Soft reset 7-7
Special Function Register area 3-1
SSC 19-1–19-27
Baudrate generation 19-15
Continous tra