ISL6540 IGNS W DES E N R O ART DF MENDE LACEMENT P M O C E D REP N OT R MENDE A Data Sheet RECOM ISL6540 ® July 23, 2008 Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability The ISL6540 is a single-phase voltage-mode PWM controller with input voltage feedforward compensation to maintain a constant loop gain for optimal transient response, especially for applications with a wide input voltage range. Its integrated high speed synchronous rectified MOSFET drivers and other sophisticated features provide complete control and protection for a DC/DC converter with minimum external components, resulting in minimum cost and less engineering design efforts. The output voltage of the converter can be precisely regulated with an internal reference voltage of 0.591V, and has a system tolerance of ±0.85% over commercial temperature and line load variations. An external voltage can be used in place of the internal reference for voltage tracking/DDR applications. The ISL6540 has an internal linear regulator or external linear regulator drive options for applications with only a single supply rail. The internal oscillator is adjustable from 250kHz to 2MHz. The integrated voltage margining, programmable pre-biased soft-start, differential remote sensing amplifier, and programmable input voltage POR features enhance the ISL6540 value. FN9214.1 Features • VIN and Power Rail Operation from +3.3V to +20V • Fast Transient Response - 0 to 100% Duty Cycle - 15MHz Bandwidth Error Amplifier with 6V/μs Slew Rate - Voltage-Mode PWM Leading and Trailing-edge Modulation Control - Input Voltage Feedforward Compensation • 2.9V to 5.6V High Speed 2A/4A MOSFET Gate Drivers - Tri-state for Power Stage Shutdown • Internal Linear Regulator (LR) - 5.6V Bias from VIN • External LR Drive for Optimal Thermal Performance • Voltage Margining with Independently Adjustable Upper and Lower Settings for System Stress Testing & Over Clocking • Reference Voltage I/O for DDR/Tracking Applications • Precise 0.591V Internal Reference with Buffered Output - ±0.85%/±1.25% Over Commercial/Industrial Range • Source and Sink Overcurrent Protections - Low- and High-Side MOSFET rDS(ON) Sensing • Overvoltage and Undervoltage Protections • Small Converter Size - QFN package • Oscillator Programmable from 250kHz to 2MHz • Differential Remote Voltage Sensing with Unity Gain • Programmable Soft-start with Pre-Biased Load Capability • Power Good Indication with Programmable Delay Pinout • EN Input with Voltage Monitoring Capability ISL6540 (28 LD 5x5 QFN) TOP VIEW VMON GND FB COMP FS LSOC HSOC • Pb-Free Plus Anneal Available (RoHS Compliant) 28 27 26 25 24 23 22 Applications • Power Supply for some Microprocessors and GPUs • Wide and Narrow Input Voltage Range Buck Regulators VSEN+ 1 21 BOOT VSEN- 2 20 UGATE REFOUT 3 19 PHASE REFIN 4 18 PGND SS 5 17 LGATE OFS+ 6 16 PVCC OFS- 7 15 LINDRV GND BOTTOM SIDE PAD • Point of Load Applications • Low-Voltage and High Current Distributed Power Supplies Ordering Information PART NUMBER* (Note) 8 9 10 11 12 13 14 VCC MARCTRL PG_DLY PG EN VFF VIN ISL6540CRZ 1 PART MARKING TEMP. PACKAGE PKG. RANGE (°C) (Pb-Free) DWG. # ISL6540CRZ 0 to 70 28 Ld QFN L28.5x5 ISL6540CRZA ISL6540CRZ 0 to 70 28 Ld QFN L28.5x5 -40 to 85 28 Ld QFN L28.5x5 ISL6540IRZA ISL6540IRZ *Add “-T” suffix for tape and reel. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 2 VSEN- VSEN+ COMP FB SS OFS- OFS+ MAR_CTRL REFOUT REFIN G=1 UNITY GAIN DIFF AMP 800mV VCC VMON OTA PG_DLY PGOOD COMP VOLTAGE MARGINING PG 100μA OV/UV COMP EA REFERENCE VREF = 0.591 V POWER-ON RESET (POR) SOURCE OCP VFF VCC SINKING OCP SOFT-START AND FAULT LOGIC LSOC EN FS G = -1 OSCILLATOR PWM COMP EXTERNAL SERIES LINEAR DRIVER LIN_DRV GATE CONTROL LOGIC SOURCE OCP INTERNAL SERIES LINEAR VIN 100μA GND GND PGND LGATE PVCC PHASE UGATE BOOT HSOC ISL6540 Block Diagram FN9214.1 July 23, 2008 ISL6540 Typical Application I (Internal Linear Regulator with Remote Sense) +3.3V to +20V LIN RCC DBOOT CHFIN CF2 CF1 RBOOT VCC VIN CBIN PVCC Internal 5.6V Bias Linear Regulator BOOT VFF HSOC RHSOC CF3 CBOOT CHSOC UGATE Q1 LOUT EN VCC VOUT PHASE REFIN CHFOUT REFOUT LGATE PG CPG_DLY RFS Q2 PGND PG_DLY LSOC ISL6540 RLSOC 10Ω CLSOC FS 10Ω COMP C2 C1 MARCTRL C3 ZFB R3 R2 R1 FB ROFS+ ZIN VMON OFS+ RMARG ROFS- CBOUT RFB VSEN+ OFS- VSENSE+ CSEN ROS SS VSENLINDRV CSS 3 GND VSENSE- GND FN9214.1 July 23, 2008 ISL6540 Typical Application II (External Linear Regulator without Remote Sense) +3.3V to +20V LIN DBOOT CHFIN CF2 CLC RLC RDRV RCC CF1 VCC CBIN RBOOT PVCC BOOT LINDRV HSOC RHSOC VIN CBOOT CF3 CHSOC VFF UGATE Q1 LOUT REFOUT VCC VOUT PHASE REFIN EN PG CPG_DLY RFS PG_DLY CHFOUT Q2 LGATE PGND LSOC ISL6540 FS COMP RLSOC CLSOC ZFB C2 C3 C1 MARCTRL ROFS+ R3 R2 ZIN R1 FB OFS+ ROS VMON RMARG ROFS- CBOUT VCC OFSVSEN+ Rvmon1 SS VSENGND CSS 4 GND RvmonOS FN9214.1 July 23, 2008 ISL6540 Typical Application III (Dual Data Rate I or II) VDDQ 1.8V or 2.5V LIN DBOOT 5V CHFIN RCC CBIN CF2 CF1 VIN REN1 VCC PVCC VFF BOOT EN HSOC CBOOT CF4 REN2 RHSOC CHSOC VTT UGATE Q1 LOUT 1.25V (DDR I) 0.9V (DDR II) 1K 15nF 1K REFIN PHASE REFOUT LGATE CHFOUT DIMM PG CPG_DLY PG_DLY RFS Q2 PGND LSOC ISL6540 FS COMP RLSOC CLSOC ZFB C2 C3 C1 MARCTRL ROFS+ R3 R2 R1 FB OFS+ CBOUT ZIN VMON RMARG ROFS- RFB VSEN+ OFSVSEN- CSEN SS LINDRV GND CSS 5 GND FN9214.1 July 23, 2008 ISL6540 Absolute Maximum Ratings Thermal Information Input Voltage, VIN, VFF . . . . . . . . . . . . . . . . . . . . . . -0.3V to +22.0V Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +36V Phase Voltage, VPHASE . . . . . . . . . . VBOOT - 6V to VBOOT + 0.3V Boot to Phase Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . .6V Other Input or Output Voltages . . . . . . . . . . . . . -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2 Thermal Resistance (Notes 1, 2) θJA (°C/W) θJC (°C/W) QFN Package . . . . . . . . . . . . . . . . . . 32 5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C Recommended Operating Conditions Input Voltage, VIN, VFF . . . . . . . . . . . . . . . . . . . . 3.3V to 20V ±10% Driver Bias Voltage, PVCC . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.6V Signal Bias Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . 2.9V to 5.6V Boot to Phase Voltage (Overcharged), VBOOT - VPHASE . . . . . .<6V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . .-40°C to 85°C Junction Temperature Range. . . . . . . . . . . . . . . . . . .-40°C to 125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. 2. θJC, "case temperature" location is at the center of the package underside exposed pad. See Tech Brief TB379 for details. 3. Test conditions identified as “GBD” are guaranteed by design simulation. Electrical Specifications SYMBOL Recommended Operating Conditions, Unless Otherwise Noted PARAMETER TEST CONDITIONS MIN TYP MAX UNITS INPUT SUPPLY CURRENTS Nominal VCC Supply Current VIN = VCC = PVCC = 5V, Fs = 600kHz, UGATE and LGATE Open - 8 - mA Nominal PVCC Supply Current VIN = VCC = PVCC = 5V; Fs = 600kHz, UGATE and LGATE Open - 5 - mA Nominal Vin Supply Current VIN = VCC = PVCC = 5V; Fs = 600kHz, UGATE and LGATE Open - 1 - mA Shutdown VCC Supply Current EN = 0V, VCC = PVCC = VIN = 5V - 7 - mA IVCC_S Shutdown PVCC Supply Current EN = 0V, VCC = PVCC = VIN = 5V - 1 - mA IVIN_S Shutdown VIN Supply Current EN = 0V, VCC = PVCC = VIN = 5V - 1 - mA IVCC IPVCC IVIN IPVCC_S POWER-ON RESET PORVCC_R Rising VCC Threshold - - 2.90 V PORVCC_F Falling VCC Threshold 2.58 - - V PORVCC_H VCC Hysterisis 184 202 217 mV PORPVCC_R Rising PVCC Threshold - - 2.90 V PORPVCC_F Falling PVCC Threshold 2.58 - - V PORPVCC_H PVCC Hysterisis 187 204 223 mV PORVFF_R Rising VFF Threshold - - 1.54 V PORVFF_F Falling VFF Threshold 1.35 - - V PORVFF_H VFF Hysterisis 124 135 146 mV 0.480 0.496 0.512 V ENABLE VEN_REF Input Reference Voltage IEN_HYS Hysteresis Source Current 7 10 15 μA Maximum Input Voltage - VCC+0.3 - V VEN 6 FN9214.1 July 23, 2008 ISL6540 Electrical Specifications SYMBOL Recommended Operating Conditions, Unless Otherwise Noted (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS OSCILLATOR OSCRANGE Nominal Frequency Range GBD 250 - 2000 kHz ΔOSCCOM Total Variation FS = 250kHz, 600 kHz, VFF = 3.3V to 20V -17 - +17 % FS = 250kHz, 600 kHz, VFF = 3.3V to 20V -22 - +22 % - 0.16*VFF - VP-P ΔOSCIND ΔVOSC VOSC_MIN Ramp Amplitude - 1.0 - V Minimum Usable VFF Voltage VCC = 5V - 3.3 - V DMAX Maximum Duty Cycle Leading and Trailing-edge Modulation - 100 - % DMIN Minimum Duty Cycle Leading and Trailing-edge Modulation - 0 - % 0.07 - VCC-1.8V V -1.2 0 1.8 mV - 19 - mA 0.01 - VCC-1.8V V - 9 mV VFF Ramp Bottom PWM REFERENCE TRACKING VREFIN Input Voltage Range External Reference Offset REFIN = 0.6V IREFOUT Maximum Drive Current CL = 1μF, VCC = 5V, REFOUT = 1.25V VREFOUT Output Voltage Range CL = 1μF VREFOUT_OS Maximum Output Voltage Offset CL = 1μF REFOUT = 1.25V -6 CREFOUT_MIN Minimum Load Capacitance REFOUT = 1.25V - 1.0 - μF - VCC - V TA = 0°C to 70°C 0.586 0.591 0.595 V TA = -40°C to 85°C 0.584 0.591 0.596 V TA = 0°C to 70°C -0.85 - 0.70 % TA = -40°C to 85°C -1.20 - 0.85 % VREFIN_OS VREFIN_DIS Input Disable Voltage REFERENCE VREF_COM Reference Voltage VREF_IND VSYS_COM System Accuracy VSYS_IND ERROR AMPLIFIER UGBW SR DC Gain RL = 10K, CL = 100p, at COMP Pin - 88 - dB Unity Gain-Bandwidth RL = 10K, CL = 100p, at COMP Pin - 15 - MHz Slew Rate RL = 10K, CL = 100p, at COMP Pin - 6 - V/μs Standard Instrumentation Amplifier - 0 - dB - 20 - MHz - 10 - V/μs -3 0 3 mV DIFFERENTIAL AMPLIFIER UG UGBW SR DC Gain Unity Gain Bandwidth Slew Rate COMP = 10pF Offset IVSEN- VVSEN_DIS μA Negative Input Source Current - 6 Input Common Mode Range Max - VCC-1.8 - V Input Common Mode Range Min - -0.2 - V VSEN- Disable Voltage - VCC - V OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA) DC Gain CSS = 0.1μF, at SS Pin - 88 - dB Drive Capability CSS = 0.1μF, at SS Pin 28 38 50 μA 7 FN9214.1 July 23, 2008 ISL6540 Electrical Specifications SYMBOL Recommended Operating Conditions, Unless Otherwise Noted (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS GATE DRIVERS RUGATE Ugate Source Resistance 500mA Source Current, PVCC = 5.0V - 1.0 - Ω IUGATE Ugate Source Saturation Current VUGATE-PHASE = 2.5V, PVCC = 5.0V - 2.0 - A RUGATE Ugate Sink Resistance 500mA Sink Current, PVCC = 5.0V - 1.0 - Ω IUGATE Ugate Sink Saturation Current VUGATE-PHASE = 2.5V, PVCC = 5.0V - 2.0 - A RLGATE Lgate Source Resistance 500mA Source Current, PVCC = 5.0V - 1.0 - Ω ILGATE Lgate Source Saturation Current VLGATE = 2.5V, PVCC = 5.0V - 2.0 - A RLGATE Lgate Sink Resistance 500mA Sink Current, PVCC = 5.0V - 0.4 - Ω ILGATE Lgate Sink Saturation Current VLGATE = 2.5V, PVCC = 5.0V - 4.0 - A - 200 - mA INTERNAL LINEAR REGULATOR IVIN Maximum Current RLIN Saturated Equivalent Impedance VIN = 3.3V PVCC Linear Regulator Voltage VIN = 22V, Load = 0 to 100mA - 2 3.25 Ω 5.42 5.6 5.72 V 0.25 - 0.9 mA LSOC = 0V to Vcc - 1.0V, TA = 0°C to 70°C 79 98 118 μA LSOC = 0V to Vcc - 1.0V, TA =-40°C to 85°C 76 98 122 μA EXTERNAL LINEAR REGULATOR LIN_DRV Maximum Sinking Drive Current OVERCURRENT PROTECTION (OCP) ILSOC ILSOC_OFSET IHSOC IHSOC Low Side OCP (LSOC) Current Source LSOC Maximum Offset Error Vcc = 2.9V and 5.6V TSAMPLE < 10μs - ±2 - mV High Side OCP (HSOC) Current Source HSOC = 0.8V to 22V TA = 0°C to 70°C 92 100 112 μA HSOC = 0.8V to 22V TA =-40°C to 85°C 92 100 115 HSOC = 0.3V to 0.8V 86 - 115 μA - ±2 - mV IHSOC_LOW IHSOC_OFSET HSOC Maximum Offset Error VCC = 2.9V and 5.5V TSAMPLE < 10μs MARGINING CONTROL VMARG Minimum Margining Voltage of Internal Reference RMARG = 10kΩ, ROFS- = 6.01kΩ, MAR_CRTL = 0V -185 -197 -208 mV VMARG Maximum Margining Voltage of Internal Reference RMARG = 10kΩ, ROFS+ = 6.01kΩ, MAR_CRTL = VCC 185 197 208 mV NMARG Margining Transfer Ratio NMARG = (VOFS--VOFS+) / VMARG 4.9 5 5.1 MAR_CTRL Positive Margining Threshold - 1.5 - V MAR_CTRL Negative Margining Threshold - 0.8 - V MAR_CTRL Tri-state Input Level - 1.325 - V VSS Disable Mode POWER GOOD MONITOR VUVR Undervoltage Rising Trip Point -7% -9% -11% VUVF Undervoltage Falling Trip Point -13% -15% -17% VSS VOVR Overvoltage Rising Trip Point 13% 15% 17% VSS VOVF Overvoltage Falling Trip Point 7% 9% 11% VSS - 5 - ms 27 30 33 μA TPG_DLY PGOOD Delay CPG_DLY = 0.1μF IPG_DLY PGOOD Delay Source Current VPG_DLY PGOOD Delay Threshold Voltage 1.44 1.48 1.56 V IPG_LOW PGOOD Low Output Voltage IPGOOD = 5mA - - 0.200 V IPG_MAX Maximum Sinking Current VPGOOD = 0.8V 10 - - mA VPG_MAX Maximum Open Drain Voltage VCC = 3.3V - 6 - V 8 FN9214.1 July 23, 2008 ISL6540 Functional Pin Description OFS- (Pin 7) VSEN+ (Pin 1) This pin sets the negative margining offset voltage. Resistors should be connected to GND (ROFS- ) and OFS+ (RMARG) from this pin. With MAR_CTRL logic low, the internal 0.591V reference is developed at the OFS- pin across resistor ROFS-. The voltage on OFS- is driven from OFS+ through RMARG. The resulting voltage differential between OFS+ and OFS- is divided by 5 and imposed on the system reference. The maximum designed offset of -1V between OFS+ and OFS- pins translates to a -200mV offset of the system reference. This pin provides differential remote sense for the ISL6540. It is the positive input of a standard instrumentation amplifier topology with unity gain, and should connect to the positive rail of the load/processor. The voltage at this pin should be set equal to the internal system reference voltage (0.591V typical.) VSEN- (Pin 2) This pin provides differential remote sense for the regulator. It is the negative input of the instrumentation amplifier, and should connect to the negative rail of the load/processor. Typically 50μA is sourced from this pin. The output of the remote sense buffer is disabled (High Impedance) by pulling VSEN- to VCC. REFOUT (Pin 3) This pin connects to the unmargined system reference through an internal buffer. It has a 19mA drive capability with an output common mode range of GND to VCC. The REFOUT buffer requires at least 1μF of capacitive loading to be stable. This pin should not be left floating. REFIN (Pin 4) When the external reference pin (REFIN) is NOT within ~800 mV of VCC, the REFIN pin is used as the system reference instead of the internal 0.591V reference. The recommended REFIN input voltage range is ~60mV to VCC - 1.8V. SS (Pin 5) This pin provides softstart functionality for the ISL6540. A capacitor connected to ground along with the internal 38mA Operational Transconductance Amplifier (OTA), sets the soft-start interval of the converter. This pin is directly connected to the non-inverting input of the Error Amplifier. To prevent noise injection into the error amplifier the SS capacitor should be located within 150 mils of the SS and GND pins. OFS+ (Pin 6) This pin sets the positive margining offset voltage. Resistors should be connected to GND (ROFS+ ) and OFS-( RMARG) from this pin. With MAR_CTRL logic low, the internal 0.591V reference is developed at the OFS+ pin across resistor ROFS+. The voltage on OFS+ is driven from OFS- through RMARG. The resulting voltage differential between OFS+ and OFS- is divided by 5 and imposed on the system reference. The maximum designed offset of 1V between OFS+ and OFS- pins translates to a 200mV offset. 9 VCC (Pin 8, Analog Circuit Bias) This pin provides power for the ISL6540 analog circuitry. The pin should be connected to a 2.9V to 5.6V bias through an RC filter from PVCC to prevent noise injection into the analog circuitry. This pin can be powered off the internal or external linear regulator options. MARCTRL (Pin 9) The MARCTRL pin controls margining function, a logic high enables positive margining, a logic low sets negative margining, a high impedance disables margining. PG_DLY (Pin 10) Provides the ability to delay the output of the PGOOD assertion by connecting a capacitor from this pin to GND. A 0.1μF capacitor produces approximately a 5ms delay. PGOOD (Pin 11) Provides an open drain Power Good signal when the output is within 9% of nominal output regulation point with 6% hysteresis (15%/9%), and after soft-start is complete. PGOOD monitors the VMON pin. EN (Pin 12) This pin is compared with an internal 0.49V reference and enables the soft-start cycle. This pin also can be used for voltage monitoring. A 10μA current source to GND is active while the part is disabled, and is inactive when the part is enabled. This provides functionality for programmable hysteresis when the EN pin is used for voltage monitoring. VFF (Pin 13) The voltage at this pin is used for input voltage feed forward compensation and sets the internal oscillator ramp peak to peak amplitude at 0.16 * VFF. An external RC filter may be required at this pin in noisy input environments. The minimum recommended VFF voltage is 2.97V. VIN (Pin 14, Internal Linear Regulator Input) This pin should be tied directly to the input rail when using the internal or external linear regulator options. It provides power to the External/Internal Linear drive circuitry. When used with an external 3.3V to 5V supply, this pin should be tied directly to PVCC. FN9214.1 July 23, 2008 ISL6540 LIN_DRV (Pin 15, External Linear Regulator Drive) HSOC (Pin 22) This pin allows the use of an external pass element to power the IC for input voltages above 5.0V. It should be connected to GND when using an external 5V supply or the internal linear regulator. When using the external linear regulator option, this pin should be connected to the gate of a PMOS pass element, a pull up resistor must be connected between the PMOS device’s gate and source for proper operation. The high side sourcing current limit is set by connecting this pin with a resistor and capacitor to the drain of the high side MOSEFT. A 100μA current source develops a voltage across the resistor which is then compared with the voltage developed across the high side MOSFET. An initial ~120ns blanking period is used to eliminate sampling error due to the switching noise before the current is measured. PVCC (Pin 16, Driver Bias Voltage) LSOC (Pin 23) This pin is the output of the internal series linear regulator. It also provides the bias for both low side and high side MOSFET drivers. The maximum voltage differential between PVCC and PGND is 6V. Its recommended operational voltage range is 2.9V to 5.6V. At minimum a 10μF capacitor is required for decoupeing PVCC to PGND. For proper operation the PVCC capacitor must be within 150mils of the PVCC and the PGND pins and must be connected to these pins with dedicated traces. The low side source and sinking current limit is set by placing a resistor (RLSOC ) and capacitor between this pin and PGND. A 100μA current source develops a voltage across RLSOC which is then compared with the voltage developed across the low side MOSFET when on. The sinking current limit is set at 1x of the nominal sourcing limit in ISL6540. An initial ~120ns blanking period is used to eliminate the sampling error due to switching noise before the current is measured. LGATE (Pin 17) FS (Pin 24) This pin provides the drive for the low side MOSFET and should be connected to its gate. This pin provides oscillator switching frequency adjustment by placing a resistor (RFS) from this pin to GND. PGND (Pin 18, Power Ground) COMP (Pin 25) This pin connects to the low side MOSFET's source and provides the ground return path for the lower MOSFET driver and internal power circuitries. In addition, PGND is the return path for the low side MOSFET’s rDS(ON) current sensing circuit. This pin is the error amplifier output. It should be connected to the FB pin through the desired compensation network. PHASE (Pin 19) This pin connects to the source of the high side MOSFET and the drain of the low side MOSFET. This pin represents the return path for the high side gate driver. During normal switching, this pin is used for high side and low side current sensing. UGATE (Pin 20) This pin provides the drive for the high side MOSFET and should be connected to its gate. BOOT (Pin 21) This pin provides the bootstrap bias for the high side driver. The absolute maximum voltage differential between BOOT and PHASE is 6.0V (including the voltage added due to the overcharging of the bootstrap capacitor); its operational voltage range is 2.5V to 5.6V with respect to PHASE. It is recomended that a 2.2Ω resistor be placed in series with the bootstrap diode to prevent over chargeing of the BOOT capacitor during normal operation. FB (Pin 26) This pin is the inverting input of the error amplifier and has a maximum usable voltage of VCC-1.8V. When using the internal differential remote sense functionality, this pin should be connected to VMON by a standard feedback network. In the event the remote sense buffer is disabled, the VMON pin should be connected to VOUT by a resistor divider along with FB’s compensation network. GND (Pin 27, Analog Ground) Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin should not be left floating. VMON (Pin 28) This pin is the output of the differential remote sense instrumentation amplifier. It is connected internally to the OV/UV/POOD comparators. The VMON pin should be connected to the FB pin by a standard feedback network. In the event of the remote sense buffer is disabled, the VMON pin should be connected to VOUT by a resistor divider along with FB’s compensation network. An RC filter should be used if VMON is to be connected directly to FB instead of to VOUT through a separate resistor divider network. GND (Bottom Side Pad, Analog Ground) Signal ground for the IC. All voltage levels are measured with respect to this pin. This pin should not be left floating. 10 FN9214.1 July 23, 2008 ISL6540 Functional Description Soft-start Initialization The POR function activates the internal 38μA OTA which begins charging the external capacitor (CSS) on the SS pin to a target voltage of VCC. The ISL6540’s soft-start logic continues to charge the SS pin until the voltage on COMP exceeds the bottom of the oscillator ramp, at which point, the driver outputs are enabled, with the low side MOSFET first being held low for 200ns to provide for charging of the bootstrap capacitor. Once the driver outputs are enabled, the OTA’s target voltage is then changed to the margined (if margining is being used) reference voltage (VREF_MARG), and the SS pin is ramped up or down accordingly. This method reduces startup surge currents due to a pre-charged output by inhibiting regulator switching until the control loop enters its linear region. By ramping the positive input of the error amplifier to VCC and then to VREF_MARG, it is even possible to mitigate surge currents from outputs that are pre-charged above the set output voltage. As the SS pin connects directly to the non-inverting input of the Error Amplifier, noise on this pin should be kept to a minimum through careful routing and part placement. To prevent noise injection into the error amplifier the SS capacitor should be located within 150mils of the SS and GND pins. Soft-start is declared done when the drivers have been enabled and the SS pin is within ±3mV of VREF_MARG. The ISL6540 automatically initializes upon receipt of power without requiring any special sequencing of the input supplies. The Power-On Reset (POR) function continually monitors the input supply voltages (PVCC,VFF, VCC) and the voltage at the EN pin. Assuming the EN pin is pulled to above ~0.49V, the POR function initiates soft-start operation after all input supplies exceed their POR thresholds. HIGH = ABOVE POR; LOW = BELOW POR VCC POR VFF POR AND SOFT-START PVCC POR EN POR FIGURE 1. SOFT-START INITIALIZATION LOGIC With all input supplies above their POR thresholds, driving the EN pin above 0.49 V initiates a soft-start cycle. In addition to normal TTL logic, the enable pin can be used as a voltage monitor with programmable hysteresis through the use of the internal 10μA sink current and an external resistor divider. This feature is especially designed for applications that have input rails greater than a 3.3V and require a specific input rail POR and Hysteresis levels for better undervoltage protection. Consider for a 12V application choosing RUP = 100kΩ and RDOWN = 5.76kΩ there by setting the rising threshold (VEN_RTH) to 10V and the falling threshold (VEN_FTH) to 9V, for 1V of hysteresis (VEN_HYS). Care should be taken to prevent the voltage at the EN pin from exceeding VCC when using the programmable UVLO functionality. Power Good The power good comparator references the voltage on the soft-start pin to prevent accidental tripping during margining. The trip points are shown on Figure 3. Additionally, power good will not be asserted until after the completion of the softstart cycle. A 0.1μF capacitor at the PG_DLY pin will add an additional ~5ms delay to the assertion of power good. PG_DLY does not delay the deassertion of power good. VMON +15% VIN RUP RDOWN +9% VREF VREF_MARG Sys_Enable -9% IEN_HYS=10μA V EN_HYS R UP = -------------------------I EN_HYS -15% GOOD GOOD UV R UP • V EN_REF R DOWN = --------------------------------------------------------V EN_FTH – V EN_REF V EN_FTH = V EN_RTH – V EN_HYS OV UV FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW 1.5V T PG_DLY = C PG_DLY ⋅ --------------30μA FIGURE 2. ENABLE POR CIRCUIT Under and Overvoltage Protection The Undervoltage (UV) and Overvoltage (OV) protection circuitry compares the voltage on the VMON pin with the 11 FN9214.1 July 23, 2008 ISL6540 reference that tracks with the margining circuitry to prevent accidental tripping. UV and OV functionality is not enabled until the end of soft-start. An OV event is detected asynchronously and causes the high side MOSFET to turn off, the low side MOSFET to turn on (effectively a 0% duty cycle), and PGOOD to pull low. The regulator stays in this state and overrides sourcing and sinking OCP protections until the OV event is cleared. An UV event is detected asynchronously and results in the PGOOD pulling low. Overcurrent Protection The ISL6540 monitors both the high side MOSFET and low side MOSFET for overcurrent events. Dual sensing allows the ISL6540 to detect overcurrent faults at the very low and very high duty cycles that can result from the ISL6540’s wide input range. The OCP function is enabled with the drivers at startup and detects the peak current during each sensing period. A resistor and a capacitor between the LSOC pin and GND set the low side source and sinking current limits. A 100μA current source develops a voltage across the resistor which is then compared with the voltage developed across the low side MOSFET at conduction mode. The measurement comparator uses offset correcting circuitry to provide precise current measurements with roughly ±2mV of offset error. An ~120ns blanking period, implemented on the upper and lower MOSFET current sensing circuitries, is used to reduce the current sampling error due to the leading-edge switching noise. An additional 120ns low pass filter is used to further reduce measurement error due to noise. In sourcing current applications, the LSOC voltage is inverted and compared with the voltage across the MOSFET while on. When this voltage exceeds the LSOC set voltage, a sourcing OCP fault is triggered. A 1000pF or greater filter capacitor should be used in parallel with RLSOC to prevent on chip parasitics from impacting the accuracy of the OCP measurement. Simple Low Side OCP Equation I OC_SOURCE • r DS ( ON )LowSide R LSOC = --------------------------------------------------------------------------------------100μA Detailed Low Side OCP Equations ΔI ⎛I + -----⎞ • r ⎝ OC_SOURCE 2 ⎠ DS ( ON ),L ------------------------------------------------------------------------------------R LSOC = I LSOC • N L V IN - V OUT V OUT ΔI = -------------------------------- • ---------------FS L V IN I LSOC • N L • R LSOC ΔI I OC_SINK = -------------------------------------------------------- – ----2 r DS ( ON ),L N L = Number of low side MOSFETs The ISL6540’s sinking current limit is set to the same voltage as its sourcing limit. In sinking applications, when the voltage across the MOSFET is greater than the voltage developed 12 across the resistor (RLSOC) a sinking OCP event is triggered. To avoid non-synchronous operation at light load, the peak to peak output inductor ripple current should not be greater than twice of the sinking current limit. The high side sourcing current limit is set by connecting the HSOC pin with a resistor (RHSOC) and a capacitor to the drain of the high side MOSEFT. A 100μA current source develops a voltage across the resistor which is then compared with the voltage developed across the high side MOSFET while on. When the voltage drop across the MOSFET exceeds the voltage drop across the resistor, a sourcing OCP event occurs. A 1000pF or greater filter capacitor should be used in parallel with RHSOC to prevent on chip parasitics from impacting the accuracy of the OCP measurement and to smooth the voltage across RHSOC in the presence of switching noise on the input bus. Sourcing OCP faults cause the regulator to disable (Ugate and Lgate drives pulled low, PGOOD pulled low, soft-start capacitor discharged) itself for a fixed period of time after which a normal soft-start sequence is initiated. The period of time the regulator waits before attempting a soft-start sequence is set by three charge and discharge cycles of the soft-start capacitor. Simple High Side OCP Equation I OC_SOURCE • r DS ( ON )HighSide R HSOC = ----------------------------------------------------------------------------------------100μA Detailed High Side OCP Equation ΔI ⎛I + -----⎞ • r ⎝ OC_SOURCE 2 ⎠ DS ( ON ),U R HSOC = --------------------------------------------------------------------------------------I HSOC • N U N U = Number of high side MOSFETs Sinking OCP faults cause the low side MOSFET drive to be disabled, effectively operating the ISL6540 in a nonsynchronous manner. The fault is maintained for three clock cycles at which point it is cleared and normal operation is restored. OVP fault implementation overrides sourcing and sinking OCP events, immediately turning on the low side MOSFET and turning off the high side MOSFET. The OC trip point varies mainly due to the MOSFETs rDS(ON) variations and system noise. To avoid overcurrent tripping in the normal operating load range, find the RHSOC and/or RLSOC resistor from the previous detailed equations with: 1. Maximum rDS(ON) at the highest junction temperature; 2. Minimum ILSOC and/or IHSOC from specification table; 3. Determine the overcurrent trip point greater than the maximum output continuous current at maximum inductor ripple current. FN9214.1 July 23, 2008 ISL6540 Frequency Programming By tying a resistor to GND from FS pin, the switching frequency can be set between 250kHz and 2MHz. Oscillator/VFF The Oscillator is a triangle waveform, providing for leading and falling edge modulation. The bottom of the oscillator waveform is set at 1.0V. The ramp's peak to peak amplitude is determined from the voltage on the VFF (Voltage Feed Forward) pin by the equation: DVosc = 0.16*VFF. An internal RC filter of 233kΩ and 2pF (341kHz) provides filtering of the VFF voltage. An external RC filter may be required to augment this filter in the event that it is insufficient to prevent noise injection or control loop interactions. Voltages below 2.9V on the VFF pin may result in undesirable operation due to extremely small peak to peak oscillator waveforms. The oscillator waveform should not exceed VCC -1.0V. For high VFF voltages the internal/external 5.6 V linear regulator should be used. 5.6V on VCC provides sufficient headroom for 100% duty cycle operation when using the maximum VFF voltage of 22V. In the event of sustained 100% duty cycle operation, defined as 32 clock cycles where no LG pulse is detected, LG will be pulsed on to refresh the design’s Bootstrap capacitor. RESISTANCE (kΩ) 100 range between 3.3V to 20V ±10%. The internal linear regulator is to provide power for both the internal MOSFET drivers through the PVCC pin and the analog circuitry through the VCC pin. The VCC pin should be connected to the PVCC pin with an RC filter to prevent high frequency driver switching noise from entering the analog circuitry. When VIN drops below 5.6V, the pass element will saturate; PVCC will track VIN, minus the dropout of the linear regulator: PVCC = VIN-2xIVIN. When used with an external 5V supply, the VIN pin should be tied directly to PVCC. External Series Linear Regulator The LIN_DRV pin provides sinking drive capability for an external pass element linear regulator controller. The external linear options are especially useful when the internal linear dropout is too large for a given application. When using the external linear regulator option, the LIN_DRV pin should be connected to the gate of a PMOS device, and a resistor should be connected between its gate and source. A resistor and a capacitor should be connected from gate to source to compensate the control loop. A PNP device can be used instead of a PMOS device in which case the LIN_DRV pin should be connected to the base of the PNP pass element. The maximum sinking capability of the LIN_DRV pin is 0.5mA, and should not be exceeded if using an external resistor for a PMOS device. The designer should take care in designing a stable system when using external pass elements. The VCC pin should be connected to the PVCC pin with an RC filter to prevent high frequency driver switching noise from entering the analog circuitry. High Speed MOSFET Gate Driver 10 1 100 1000 10000 FREQUENCY (kHz) FIGURE 4. RFS RESISTANCE vs. FREQUENCY 10 Fs [ Hz ] ≈ 1.178 ×10 • RT [ Ω ] – 0.973 (R T TO GND) Internal Series Linear Regulator The VIN pin is connected to PVCC with a 2Ω internal series linear regulator, which is internally compensated. The external Series Linear regulator option should be used for applications requiring pass elements of less than 2Ω. When using the internal regulator, the LIN_DRV pin should be connected directly to GND. The PVCC and VIN pins should have a bypasses capacitor (at least 10μF on PVCC is required) connected to PGND. For proper operation the PVCC capacitor must be within 150mils of the PVCC and the PGND pins, and be connected to these pins with dedicated traces. The internal series linear regulator’s input (VIN) can 13 The integrated driver has similar drive capability and features to Intersil's ISL6605 stand alone gate driver. The PWM tri-state feature helps prevent a negative transient on the output voltage when the output is being shut down. This eliminates the Schottky diode that is used in some systems for protecting the microprocessor from reversed-outputvoltage damage. See the ISL6605 datasheet for specification parameters that are not defined in the current ISL6540 electrical specifications table. A 1-2Ω resistor is recommended to be in series with the bootstrap diode when using VCCs above 5.0V to prevent the bootstrap capacitor from overcharging due to the negative swing of the trailing edge of the phase node. Margining Control When the MAR_CTRL is pulled high or low, the positive or negative margining functionality is respectively enabled. When MAR_CTRL is left floating, the function is disabled. Upon UP margining, an internal buffer drives the OFS- pin from VCC to maintain OFS+ at 0.591V. The resistor divider, RMARG and ROFS+, causes the voltage at OFS- to be increased. Similarly, upon DOWN margining, an internal buffer drives the OFS+ pin from VCC to maintain OFS- at 0.591V. The resistor divider, RMARG and ROFS-, causes the FN9214.1 July 23, 2008 ISL6540 voltage at OFS+ to be increased. In both modes the voltage difference between OFS+ and OFS- is then sensed with an instrumentation amplifier and is converted to the desired margining voltage by a 5:1 ratio. The maximum designed margining range of the ISL6540 is ±200mV, this sets the MINIMUM value of ROFS+ or ROFS- at approximately 5.9K for an RMARG of 10K for a MAXIMUM of 1V across RMARG. The OFS pins are completely independent and can be set to different margining levels. The maximum usable reference voltage for the ISL6540 is VCC-1.8V, and should not be exceeded when using the margining functionality, i.e, VREF_MARG < VCC - 1.8V. V REF R MARG V MARG_UP = --------------- • --------------------5 R OFS+ ISL6540 STATE MACHINE REFIN 800mV REFOUT MARGINING BLOCK VREF_MARG OTA FIGURE 5. SIMPLIFIED REFERENCE BUFFER V REF R MARG V MARG_DOWN = --------------- • --------------------5 R OFS- An alternative calculation provides for a desired percentage change in the output voltage when using the internal 0.591V reference: R MARG V pct_DOWN = 20 • --------------------R OFS- R MARG V PCT_UP = 20 • --------------------R OFS+ VCC REFERENCE VREF=0.591V When not used in a design OFS+, OFS-, and MARCTRL should be left floating. To prevent damage to the part, OFS+ and OFS- should not be tied to VCC or PVCC. Reference Output Buffer The internal buffer’s output tracks the unmargined system reference. It has a 19mA drive capability, with maximum and minimum output voltage capabilities of VCC and GND respectively. Its capacitive loading can range from 1μF to above 17.6μF, which is designed for 1 to 8 DIMM systems in DDR (Dual Data Rate) applications. 1μF of capacitance should always be present on REFOUT. It is not designed to drive a resistive load and any such load added to the system should be kept above 300kΩ total impedance. Reference Input The REFIN pin allows the user to bypass the internal 0.591V reference with an external reference. Asynchronously if REFIN is NOT within ~800mV of VCC, the external reference pin is used as the control reference instead of the internal 0.591V reference. The minimum usable REFIN voltage is ~60mV while the maximum is VCC - 1.8V VMARG (if present). The limitation is set by the error amplifier's maximum common mode input range of VCC 1.8V for the industrial temperature ranges. 14 Internal Reference and System Accuracy The internal reference is trimmed to 0.591V. The total DC system accuracy of the system is within 0.85% over commercial temperature range, and 1.25% over industrial temperature range. System accuracy includes error amplifier offset, OTA error, and bandgap error. Differential remote sense offset error is not included. As a result, if the differential remote sense is used, then an extra 3mV of offset error enters the system. The use of REFIN may add up to 1.8mV of additional offset error. Differential Remote Sense Buffer The differential remote sense buffer is essentially an instrumentation amplifier with unity gain. The offset is trimmed to 3mV for high system accuracy. As with any instrumentation amplifier typically 6μA are sourced from the VSEN- pin. The output of the remote sense buffer is connected directly to the internal OV/UV comparator. As a result, a resistor divider should be placed on the input of the buffer for proper regulation, as shown in Figure 6. The VMON pin should be connected to the FB pin by a standard feed-back network. A small capacitor, CSEN in Figure 6, can be added to filter out noise, typically CSEN is chosen so the corresponding time constant does not reduce the overall phase margin of the design, typically this is 2x to 10x switching frequency of the regulator. As some applications will not use the differential remote sense, the output of the remote sense buffer can be disabled (high impedance) by pulling VSEN- within 800mV of VCC. As the VMON pin is connected internally to the OV/UV/PGOOD comparator, an external resistor divider must then be connected to VMON to provide correct voltage information for the OV/UV comparator. An RC filter should be used if VMON is to be connected directly to FB instead of to VOUT through a separate resistor divider network. This filter prevents noise injection from disturbing the OV/UV/PGOOD comparators on VMON. VMON may also be connected to the SS pin, which completely bypasses the OV/UV/PGOOD functionality. FN9214.1 July 23, 2008 ISL6540 VSENSE(REMOTE) VOUT (LOCAL) 10Ω GND (LOCAL) 10Ω VSENSE+ (REMOTE) RFB ROS CSEN VSEN+ VSEN- VCC ZIN ZFB VMON OV/UV COMP 800mV COMP FB ERROR AMP GAIN=1 VSS FIGURE 6. SIMPLIFIED UNITY GAIN DIFFERENITAL SENSING IMPLEMENTATION Layout Considerations As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible using ground plane construction or single point grounding. VIN ISL6540 Q1 LO PHASE LGATE Q2 CIN Proper grounding of the IC is important for correct operation in noisy environments. The PGND pin should be connected to board ground at the source of the low side MOSFET with a wide short trace. The GND pin should be connected to a large copper fill under the IC which is subsequently connected to board ground at a quite location on the board, typically found at an input or output bulk (electrolytic) capacitor. BOOT VOUT CO +VIN D1 Q1 CBOOT LOAD UGATE part of ground or power plane in a printed circuit board. The components shown in Figure 8 should be located as close together as possible. Please note that the capacitors CIN and CO each represent numerous physical capacitors. Locate the ISL6540 within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6540 must be sized to handle up to 4A peak current. SS ISL6540 LO VOUT PHASE +5V PGND Q2 LOAD Application Guidelines CO PVCC RETURN CPVCC CSS GND PGND FIGURE 7. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS Figure 7 shows the critical power components of the converter. To minimize the voltage overshoot/undershoot the interconnecting wires indicated by heavy lines should be 15 FIGURE 8. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES FN9214.1 July 23, 2008 ISL6540 Figure 8 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the SS pin and locate the capacitor, CSS close to the SS pin (as described earlier) as the internal current source is only 38μA. Provide local decoupling between PVCC and PGND pins as described earlier. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. C2 COMP R2 C3 R3 C1 FB E/A + R1 VREF Compensating the Converter VMON The ISL6540 single-phase converter is a voltage-mode controller. This section highlights the design considerations for a voltage-mode controller requiring external compensation. To address a broad range of applications, a type-3 feedback network is recommended (see Figure 9). - RFB VSEN- CSEN ROS + VSEN+ VOUT OSCILLATOR VIN C2 R2 C1 PWM CIRCUIT VOSC COMP UGATE FB C3 R3 HALF-BRIDGE DRIVE R1 L DCR PHASE VMON LGATE FIGURE 9. COMPENSATION CONFIGURATION FOR ISL6540 WHEN USING DIFFERENTIAL REMOTE SENSE Figure 10 highlights the voltage-mode control loop for a synchronous-rectified buck converter, when using an internal differential remote sense amplifier. The output voltage (VOUT) is regulated to the reference voltage, VREF, level. The error amplifier output (COMP pin voltage) is compared with the oscillator (OSC) triangle wave to provide a pulsewidth modulated wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (L and C). The output filter capacitor bank’s equivalent series resistance is represented by the series resistor ESR. The modulator transfer function is the small-signal transfer function of VOUT /VCOMP. This function is dominated by a DC gain, given by dMAXVIN /VOSC, and shaped by the output filter, with a double pole break frequency at FLC and a zero at FCE . For the purpose of this analysis C and ESR represent the total output capacitance and its equivalent series resistance. 1 F LC = --------------------------2π ⋅ L ⋅ C C ISL6540 1 F CE = --------------------------------2π ⋅ C ⋅ ESR 16 ISL6540 ESR EXTERNAL CIRCUIT FIGURE 10. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN The compensation network consists of the error amplifier (internal to the ISL6540) and the external R1-R3, C1-C3 components. The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase margin (better than 45°). Phase margin is the difference between the closed loop phase at F0dB and 180°. The equations that follow relate the compensation network’s poles, zeros and gain to the components (R1 , R2 , R3 , C1 , C2 , and C3) in Figures 9 and 10. Use the following guidelines for locating the poles and zeros of the compensation network: 1. Select a value for R1 (1kΩ to 10kΩ, typically). Calculate value for R2 for desired converter bandwidth (F0). If setting the output voltage to be equal to the reference set voltage as shown in Figure 22, the design procedure can be followed as presented. However, when setting the output voltage via a resistor divider placed at the input of the differential amplifier (as shown in Figure 10), in order to compensate for the attenuation introduced by the resistor divider, the below obtained R2 value needs be multiplied by a factor of (ROS+RFB)/ROS. The remainder of the calculations remain unchanged, as long as the compensated R2 value is used. FN9214.1 July 23, 2008 ISL6540 frequency response of the modulator (GMOD), feedback compensation (GFB) and closed-loop response (GCL): V OSC ⋅ R 1 ⋅ F 0 R 2 = --------------------------------------------d MAX ⋅ V IN ⋅ F LC A small capacitor, CSEN in Figure 10, can be added to filter out noise, typically CSEN is chosen so the corresponding time constant does not reduce the overall phase margin of the design, typically this is 2x to 10x switching frequency of the regulator. As the ISL6540 supports 100% duty cycle, dMAX equals 1. The ISL6540 also uses feedforward compensation, as such VOSC is equal to 0.16 multiplied by the voltage at the VFF pin. When tieing VFF to VIN the above equation simplifies to: 0.16 ⋅ R 1 ⋅ F 0 R 2 = ---------------------------------F LC 2. Calculate C1 such that FZ1 is placed at a fraction of the FLC, at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to desired number). The higher the quality factor of the output filter and/or the higher the ratio FCE/FLC, the lower the FZ1 frequency (to maximize phase boost at FLC). d MAX ⋅ V IN 1 + s ( f ) ⋅ ESR ⋅ C G MOD ( f ) = ------------------------------ ⋅ ----------------------------------------------------------------------------------------------------------2 V OSC 1 + s ( f ) ⋅ ( ESR + DCR ) ⋅ C + s ( f ) ⋅ L ⋅ C 1 + s ( f ) ⋅ R2 ⋅ C1 G FB ( f ) = ---------------------------------------------------- ⋅ s ( f ) ⋅ R1 ⋅ ( C1 + C2 ) 1 + s ( f ) ⋅ ( R1 + R3 ) ⋅ C3 -----------------------------------------------------------------------------------------------------------------------⎛ C1 ⋅ C2 ⎞ ⎞ ⎛ ( 1 + s ( f ) ⋅ R 3 ⋅ C 3 ) ⋅ ⎜ 1 + s ( f ) ⋅ R 2 ⋅ ⎜ ---------------------⎟ ⎟ ⎝ C 1 + C 2⎠ ⎠ ⎝ G CL ( f ) = G MOD ( f ) ⋅ G FB ( f ) where, s ( f ) = 2π ⋅ f ⋅ j As before when tieing VFF to VIN terms in the above equations can be simplified as follows: 1 ⋅ V IN d MAX ⋅ V IN ----------------------------- = -------------------------- = 6.25 V OSC 0.16 ⋅ V IN COMPENSATION BREAK FREQUENCY EQUATIONS 3. Calculate C2 such that FP1 is placed at FCE. C1 C 2 = -------------------------------------------------------2π ⋅ R 2 ⋅ C 1 ⋅ F CE – 1 4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3 such that FP2 is placed below FSW (typically, 0.5 to 1.0 times FSW). FSW represents the regulator’s switching frequency. Change the numerical factor to reflect desired placement of this pole. Placement of FP2 lower in frequency helps reduce the gain of the compensation network at high frequency, in turn reducing the HF ripple component at the COMP pin and minimizing resultant duty cycle jitter. R1 R 3 = ---------------------F SW ------------ – 1 F LC 1 C 3 = ------------------------------------------------2π ⋅ R 3 ⋅ 0.7 ⋅ F SW It is recommended that a mathematical model is used to plot the loop response. Check the loop gain against the error amplifier’s open-loop gain. Verify phase margin results and adjust as necessary. The following equations describe the 1 F Z1 = ------------------------------2π ⋅ R 2 ⋅ C 1 1 F P1 = --------------------------------------------C1 ⋅ C2 2π ⋅ R 2 ⋅ --------------------C1 + C2 1 F Z2 = ------------------------------------------------2π ⋅ ( R 1 + R 3 ) ⋅ C 3 1 F P2 = ------------------------------2π ⋅ R 3 ⋅ C 3 Figure 11 shows an asymptotic plot of the DC/DC converter’s gain vs. frequency. The actual modulator gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown. Using the above guidelines should yield a compensation gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 against the capabilities of the error amplifier. The closed loop gain, GCL, is constructed on the log-log graph of Figure 11 by adding the modulator gain, GMOD (in dB), to the feedback compensation gain, GFB (in dB). This is equivalent to multiplying the modulator transfer function and the compensation transfer function and then plotting the resulting gain. FZ1 FZ2 FP1 FP2 GAIN 1 C 1 = ----------------------------------------------2π ⋅ R 2 ⋅ 0.5 ⋅ F LC R2 20 log ⎛ --------⎞ ⎝ R1⎠ MODULATOR GAIN COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP E/A GAIN d MAX ⋅ V IN 20 log --------------------------------V OSC 0 GFB LOG GCL GMOD LOG FLC FCE F0 FREQUENCY FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN 17 FN9214.1 July 23, 2008 ISL6540 A stable control loop has a gain crossing with close to a -20dB/decade slope and a phase margin greater than 45°. Include worst case component variations when determining phase margin. The mathematical model presented makes a number of approximations and is generally not accurate at frequencies approaching or exceeding half the switching frequency. When designing compensation networks, select target crossover frequencies in the range of 10% to 30% of the switching frequency, FSW. Component Selection Guidelines Output Capacitor Selection An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. For example, Intel recommends that the high frequency decoupling for the Pentium Pro be composed of at least forty (40) 1.0μF ceramic capacitors in the 1206 surface-mount package. Follow on specifications have only increased the number and quality of required ceramic decoupling capacitors. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. 18 Output Inductor Selection The output inductor is selected to meet the output voltage ripple requirements and minimize the converter’s response time to the load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: V IN - V OUT V OUT ΔI = -------------------------------- • ---------------FS x L V IN ΔVOUT= ΔI x ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6540 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O × I TRAN t RISE = -------------------------------V IN – V OUT L O × I TRAN t FALL = ------------------------------V OUT where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. With a lower input source such as 1.8V or 3.3V, the worst case response time can be either at the application or removal of load and dependent upon the output voltage setting. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum FN9214.1 July 23, 2008 ISL6540 0.60 MOSFET Selection/Considerations 0.50 The ISL6540 requires 2 N-Channel power MOSFETs. These should be selected based upon rDS(ON), gate supply requirements, and thermal management requirements. 0.5Io KICM 0.40 0.30 0.25Io 0.20 ΔI=0Io 0.10 0.00 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 DUTY CYCLE (D) FIGURE 12. INPUT-CAPACITOR CURRENT MULTIPLIER FOR SINGLE-PHASE BUCK CONVERTER input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately below. I IN, RMS = VO D = ---------VIN I2 2 ( D – D2 ) + Δ -------- D IO 12 OR I IN, RMS = K ICM • I O In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). The upper MOSFET exhibits turn-on and turn-off switching losses as well as the reverse recover loss, while the synchronous rectifier exhibits body-diode conduction losses during the leading and trailing edge dead times. DS ( ON ),L ΔI 2⎞ • r-------------------------- • ( 1 – D ) + P DEAD P LOWER = ⎛ I O 2 + ------⎝ N 12 ⎠ L ΔI ΔI ⎞ • V ⎛ ------⎞ P DEAD = ⎛ I O + ----DT • t DT + ⎝ I O – 12⎠ • V DL • t DL • F S ⎝ 12⎠ DS ( ON ),U ΔI 2-⎞ • r--------------------------- • D + P SW + P Qrr P UPPER = ⎛ I O 2 + ------⎝ N 12 ⎠ U ΔI ΔI ⎞ • t P SW = ⎛ I O + ----+ ⎛ I – ------⎞ • t • VIN • F S ⎝ 12⎠ OFF ⎝ O 12⎠ ON P Qrr = Q rr • VIN • F S For a through hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MVGX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. where D is the duty cycle = VO / VIN; Qrr is the reverse recover charge; tDLand tDT are leading and trailing edge dead time, and tON & tOFF are the switching intervals. These equations do not include the gate-charge losses that are proportional to the total gate charge and the switching frequency and partially dissipated by the internal gate resistance of the MOSFETs. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. ISL6540 DC/DC Converter Application Circuit Detailed information on the application circuit, including a complete Bill-of-Materials and circuit board description, can be found in application note AN1204. See Intersil’s home page on the web: http://www.intersil.com. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN9214.1 July 23, 2008 ISL6540 Package Outline Drawing L28.5x5 28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/07 4X 3.0 5.00 24X 0.50 A B 6 PIN 1 INDEX AREA 6 PIN #1 INDEX AREA 28 22 1 5.00 21 3 .10 ± 0 . 15 15 (4X) 7 0.15 8 14 TOP VIEW 0.10 M C A B - 0.07 4 28X 0.25 + 0.05 28X 0.55 ± 0.10 BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0.1 C BASE PLANE SEATING PLANE 0.08 C ( 4. 65 TYP ) ( 24X 0 . 50) ( SIDE VIEW 3. 10) (28X 0 . 25 ) C 0 . 2 REF 5 0 . 00 MIN. 0 . 05 MAX. ( 28X 0 . 75) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 20 FN9214.1 July 23, 2008