ISL8012
Features
The ISL8012 is a high efficiency, monolithic, synchronous
step-down DC/DC converter that can deliver up to 2A
continuous output current from a 2.7V to 5.5V input
supply. It uses a current control architecture to deliver
very low duty cycle operation at high frequency with fast
transient response and excellent loop stability.
• High Efficiency Synchronous Buck Regulator with up
to 95% Efficiency
The ISL8012 integrates a pair of low ON-resistance
P-Channel and N-Channel internal MOSFETs to maximize
efficiency and minimize external component count. The
100% duty-cycle operation allows less than 240mV
dropout voltage at 2A output current. High 1MHz pulse
width modulation (PWM) switching frequency allows the
use of small external components.
• 2A Guaranteed Output Current
The ISL8012 can be configured for discontinuous or
forced continuous operation at light load. Forced
continuous operation reduces noise and RF interference
while discontinuous mode provides high efficiency by
reducing switching losses at light loads.
Fault protection is provided by internal current limiting
during short circuit and overcurrent conditions, an output
overvoltage comparator and over-temperature monitor
circuit. A power-good output voltage monitor indicates
when the output is in regulation.
The ISL8012 offers a 1ms Power-good (PG) timer at
power-up. When shutdown, ISL8012 discharges the
output capacitor. Other features include internal
soft-start, internal compensation, overcurrent protection,
and thermal shutdown.
The ISL8012 is offered in a space saving 3mmx3mm
10 Ld DFN package lead free package with exposed pad
lead frames for low thermal. The complete converter
occupies less than 0.35in2 area.
• Power-Good (PG) Output with a 1ms Delay
• 2.7V to 5.5V Supply Voltage
• 3% Output Accuracy Over-Temperature/Load/Line
• Start-up with Pre-Biased Output
• Internal Soft-Start - 1ms
• Soft-Stop Output Discharge During Disabled
• 40µA Quiescent Supply Current in PFM Mode
• Selectable Forced PWM Mode and PFM Mode
• Less than 1µA Logic Controlled Shutdown Current
• 100% Maximum Duty Cycle
• Internal Current Mode Compensation
• Peak Current Limiting and Hiccup Mode Short Circuit
Protection
• Over-Temperature Protection
• Small 10 Ld 3mmx3mm DFN
• Pb-Free (RoHS Compliant)
Applications*(see page 15)
• DC/DC POL Modules
• µC/µP, FPGA and DSP Power
• Plug-in DC/DC Modules for Routers and Switchers
• Portable Instruments
• Test and Measurement Systems
• Li-ion Battery Powered Devices
• Small Form Factor (SFP) Modules
• Bar Code Readers
Related Literature*(see page 15)
• See AN1360 for “ISL8012EVAL1Z: 2A Synchronous
Buck Regulator with Integrated MOSFETs”
FN6616.1
March 17, 2010
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL8012
2A Low Quiescent Current 1MHz High Efficiency
Synchronous Buck Regulator
ISL8012
Pin Configuration
ISL8012
(10 LD DFN)
TOP VIEW
VIN 1
10 LX
VCC 2
EN 3
9 PGND
PD
8 SGND
PG 4
7 VFB
MODE 5
6 RSI
Pin Descriptions
SYMBOL
PIN NUMBER
VIN
1
Input supply voltage. Connect a 10µF ceramic capacitor to power ground.
VCC
2
Input supply for the logic. Connect to VIN.
EN
3
Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge
output capacitor when driven to low. Do not leave this pin floating.
PG
4
1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the
output voltage. This output can be reset by a low RSI signal. 1ms starts when RSI goes to high.
MODE
5
Mode Selection pin. Connect to logic high or input voltage VIN for PFM mode; connect to logic low
or ground for forced PWM mode. Do not leave this pin floating.
RSI
6
This input resets the 1ms timer. When the output voltage is within the PGOOD window, an internal
timer is started and generates a PG signal 1ms later when RSI is low. A high RSI resets PG and RSI
high to low transition restarts the internal counter if the output voltage is within the window,
otherwise the counter is reset by the output voltage condition.
VFB
7
Buck regulator output feedback. Connect to the output through a resistor divider for adjustable
output voltage (ISL8012-ADJ). For preset output voltage, connect this pin to the output.
SGND
8
System ground for the control logic. All voltage levels are measured with respect to this pin.
PGND
9
Ground connect for the IC and thermal relief for the package. The exposed pad must be connected
to PGND and soldered to the PCB.
LX
10
Switching node connection. Connect to one terminal of inductor.
Exposed Pad
PD
The exposed pad must be connected to the PGND and SGND pin for proper electrical performance.
The exposed pad must also be connected to as much as possible for optimal thermal performance.
2
DESCRIPTION
March 17, 2010
FN6616.1
ISL8012
Typical Application
OUTPUT
L
INPUT 2.7V TO 5.5V
1.8V/2A
LX
VIN
C2
2x10µF
C1
2x10µF
PGND
R2
124k
C3*
220pF
ISL8012
SGND
EN
R3
100k
R1
100k
PG
VFB
MODE
RSI
*C3 is optional
FIGURE 1. TYPICAL APPLICATION DIAGRAM
Block Diagram
MODE
390k
SHUTDOWN
BANDGAP
0.8V
+
COMP
EAMP
+
EN
SHUTDOWN
27pF
SOFT-START
VIN
OSCILLATOR
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
DRIVER
LX
+
GND
VFB
SLOPE
COMP
+
CSA
0.864V
+
+
OCP
1V
+
0.736V
+
SKIP
PG
1ms
DELAY
RSI
0.2V
0.25V
ZERO-CROSS
SENSING
SCP
+
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM
3
March 17, 2010
FN6616.1
ISL8012
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
ISL8012IRZ
PART
MARKING
012Z
TEMP. RANGE
(°C)
-40 to +85
PACKAGE
(Pb-Free)
10 Ld 3x3 DFN
PKG.
DWG. #
L10.3x3C
NOTES:
1. Add “-T” or suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both
SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL8012. For more information on MSL please see
techbrief TB363.
4
March 17, 2010
FN6616.1
ISL8012
Absolute Maximum Ratings (Reference to GND)
Thermal Information
VIN, VCC. . .
EN, RSI, PG .
LX . . . . . . .
VFB . . . . . .
Thermal Resistance (Typical)
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
. . . . . . . . . . . . . . . . -0.3V to 6V
. . . . . . . . . . . -0.3V to VIN+0.3V
-1.5V (100ns)/-0.3V (DC) to 6.5V
. . . . . . . . . . . . . . -0.3V to 2.7V
Recommended Operating Conditions
VIN Supply Voltage Range . .
Load Current Range . . . . . .
Ambient Temperature Range
ESD Rating
Human Body Model . . . . .
Machine Model . . . . . . . .
θJA (°C/W) θJC (°C/W)
10 Ld 3x3 DFN (Notes 4, 5) . . . .
49
5.5
Junction Temperature Range . . . . . . . . . . -55°C to +125°C
Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
. . . . . . . . . . . . . . 2.7V to 5.5V
. . . . . . . . . . . . . . . . . 0A to 2A
. . . . . . . . . . . . -40°C to +85°C
. . . . . . . . . . . . . . . . . . . . 5kV
. . . . . . . . . . . . . . . . . . . 300V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating
conditions and the typical specifications are measured at the following conditions: TA = -40°C
to +85°C, VIN = 3.6V, EN = VCC, unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 7) TYP (Note 7) UNITS
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising
Falling
Quiescent Supply Current
IVIN
2.5
2.2
Shut Down Supply Current
ISD
40
MODE = VIN, no load at the output and
no switches switching; design info only
15
VIN = 5.5V, EN = low
V
60
µA
2.4
MODE = VIN, no load at the output
MODE = SGND, no load at the output
2.7
V
µA
6
8
mA
0.1
2
µA
0.8
0.816
V
OUTPUT REGULATION
VFB Regulation Voltage
VVFB
TA = 0°C to +85°C
VFB Bias Current
IVFB
VFB = 0.75V
0.784
0.1
-3
µA
Output Voltage Accuracy
VIN = VO + 0.5V to 5.5V, IO = 0A to 2A
(Note 6)
3
%
Line Regulation
VIN = VO + 0.5V to 5.5V (minimal
2.7V), IOUT = 400mA
0.2
%/V
Adjustable version, design info only
20
µA/V
COMPENSATION
Error Amplifier Trans-Conductance
LX
P-Channel MOSFET ON-Resistance
N-Channel MOSFET ON-Resistance
P-Channel MOSFET Peak Current Limit
LX Maximum Duty Cycle
IPK
VIN = 5.5V, IO = 200mA
0.12
0.22
Ω
VIN = 2.7V, IO = 200mA
0.21
0.27
Ω
VIN = 5.5V, IO = 200mA
0.11
0.22
Ω
VIN = 2.7V, IO = 200mA
0.13
0.27
Ω
3.00
3.50
A
2.65
100
5
%
March 17, 2010
FN6616.1
ISL8012
Electrical Specifications
Unless otherwise noted, all parameter limits are established over the recommended operating
conditions and the typical specifications are measured at the following conditions: TA = -40°C
to +85°C, VIN = 3.6V, EN = VCC, unless otherwise noted. Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C.
PARAMETER
SYMBOL
PWM Switching Frequency
fS
TEST CONDITIONS
TA = 0°C to +85°C
MIN
MAX
(Note 7) TYP (Note 7) UNITS
1
1.16
MHz
LX Minimum On-Time
MODE = low (forced PWM mode)
0.840
80
100
ns
Soft-Start-Up Time
VIN = 3.6V
1.1
ms
PG
Output Low Voltage
Sinking 1mA, VFB = 0.7V
0.3
Delay Time
1
PG Pin Leakage Current
PG = VIN = 3.6V
Minimum Supply Voltage for Valid PG
Signal
0.01
V
ms
0.1
1.2
µA
V
Internal PGOOD Low Rising Threshold
Percentage of nominal regulation
voltage
89
92
95
%
Internal PGOOD Low Falling Threshold
Percentage of nominal regulation
voltage
85
88
91
%
Internal PGOOD High Rising Threshold
Percentage of nominal regulation
voltage
107
110
113
%
Internal PGOOD High Falling Threshold
Percentage of nominal regulation
voltage
104
107
110
%
Internal PGOOD Delay Time
30
µs
EN, MODE, RSI
Logic Input Low
0.4
Logic Input High
1.4
Logic Input Leakage Current
Pulled up to 5.5V
V
V
0.1
1
µA
NOTES:
6. Limits established by characterization and are not production tested.
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
6
March 17, 2010
FN6616.1
ISL8012
(Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, MODE = 0V, L = 2.2µH,
C1 = 2x10µF, C2 = 2x10µF, IOUT = 0A to 2A).
100
100
90
90
80
80
1.5VOUT
70
EFFICIENCY (%)
EFFICIENCY (%)
Typical Operating Performance
1.2VOUT
60
50
40
30
20
0.00
2.5VOUT
0.50
1.5VOUT
60
50
40
0.75
1.00
1.25
1.50
1.75
20
0.1
2.00
0.2
0.3
100
100
90
90
80
80
1.2VOUT
1.8VOUT
2.5VOUT
60
50
40
30
3.3VOUT
20
0.00
0.25
0.50
70
1.5VOUT
60
0.75
1.00
1.25
1.50
1.75
0.8
1.8VOUT
2.5VOUT
3.3VOUT
1.2VOUT
40
20
0.1
2.00
0.2
0.3
0.4
0.5
0.6
OUTPUT LOAD (A)
0.7
0.8
FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PFM)
1.000
160
0.875
3.3VIN PWM
POWER DISSIPATION (mW)
POWER DISSIPATION (W)
0.7
30
FIGURE 5. EFFICIENCY vs LOAD (1MHz 5VIN PWM)
0.750
0.625
0.500
0.375
5VIN PFM
5VIN PWM
3.3VIN PFM
0.125
0
0.00
0.6
50
OUTPUT LOAD (A)
0.250
0.5
FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3VIN PFM)
EFFICIENCY (%)
EFFICIENCY (%)
FIGURE 3. EFFICIENCY vs LOAD (1MHz 3.3VIN PWM)
70
0.4
OUTPUT LOAD (A)
OUTPUT LOAD (A)
1.5VOUT
2.5VOUT
1.8VOUT
1.2VOUT
30
1.8VOUT
0.25
70
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
OUTPUT LOAD (A)
FIGURE 7. POWER DISSIPATION vs LOAD (1MHz,
VOUT = 1.8V)
7
140
120
100
80
PWM MODE
60
40
20
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN (V)
FIGURE 8. POWER DISSIPATION WITH NO LOAD vs
VIN (PWM VOUT = 1.8V)
March 17, 2010
FN6616.1
ISL8012
0.50
1.24
0.45
1.23
0.40
0.35
0.30
0.25
PFM
0.20
0.15
0.10
2.0
2.5
3.0
3.5
4.0
VIN (V)
4.5
5.0
5.5
1.22
1.19
1.18
OUTPUT VOLTAGE (V)
1.82
1.52
1.51
1.50
1.49
3.3VIN PFM
1.48
1.47
0.00
0.25
5VIN PFM
0.50
0.75
5VIN PFM
0.25
0.50
1.00
1.25
1.50
1.75
1.79
1.78 3.3VIN PFM
1.77
5VIN PFM
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
OUTPUT LOAD (A)
FIGURE 12. VOUT REGULATION vs LOAD (1MHz,
VOUT = 1.8V)
3.36
2.57
3.35
5VIN PWM
2.55
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.00
5VIN PWM
1.80
1.75
0.00
2.00
2.59
2.53
2.51
2.49
2.43
0.00
1.75
1.76
FIGURE 11. VOUT REGULATION vs LOAD (1MHz,
VOUT = 1.5V)
2.45
1.50
3.3VIN PWM
1.81
OUTPUT LOAD (A)
2.47
0.75
1.00
1.25
OUTPUT LOAD (A)
FIGURE 10. VOUT REGULATION vs LOAD (1MHz,
VOUT = 1.2V)
1.83
3.3VIN PWM
3.3VIN PFM
1.17
1.54
5VIN PWM
3.3VIN PWM
1.20
1.55
1.53
5VIN PWM
1.21
1.16
0.00
6.0
FIGURE 9. POWER DISSIPATION WITH NO LOAD vs
VIN (PFM VOUT = 1.8V)
OUTPUT VOLTAGE (V)
(Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, MODE = 0V, L = 2.2µH,
C1 = 2x10µF, C2 = 2x10µF, IOUT = 0A to 2A). (Continued)
OUTPUT VOLTAGE (V)
POWER DISSIPATION (mW)
Typical Operating Performance
3.3VIN PWM
5VIN PFM
3.3VIN PFM
0.25
0.50
0.75
1.00
1.25
1.50
1.75
FIGURE 13. VOUT REGULATION vs LOAD (1MHz,
VOUT = 2.5V)
8
2.00
4.5VIN PWM
3.34
5VIN PWM
3.33
3.32
3.31
3.30
3.29
OUTPUT LOAD (A)
5VIN PFM
3.28
0.00
4.5VIN PFM
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
OUTPUT LOAD (A)
FIGURE 14. VOUT REGULATION vs LOAD (1MHz,
VOUT = 3.3V)
March 17, 2010
FN6616.1
ISL8012
Typical Operating Performance
(Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, MODE = 0V, L = 2.2µH,
C1 = 2x10µF, C2 = 2x10µF, IOUT = 0A to 2A). (Continued)
LX 2V/DIV
LX 2V/DIV
VOUT RIPPLE
20mV/DIV
VOUT RIPPLE
20mV/DIV
IL 0.5A/DIV
IL 0.5A/DIV
FIGURE 15. STEADY STATE OPERATION AT NO LOAD
(PWM), (1µs/DIV)
FIGURE 16. STEADY STATE OPERATION AT NO LOAD
(PFM), (1µs/DIV)
LX 2V/DIV
LX 2V/DIV
VOUT RIPPLE
50mV/DIV
IL 0.5A/DIV
VOUT RIPPLE
20mV/DIV
FIGURE 17. STEADY STATE OPERATION WITH FULL
LOAD, (5µs/DIV)
IL 0.5A/DIV
FIGURE 18. MODE TRANSITION CCM TO DCM,
(5µs/DIV)
VOUT RIPPLE
50mV/DIV
LX 2V/DIV
VOUT RIPPLE
50mV/DIV
IL 1A/DIV
IL 0.5A/DIV
FIGURE 19. MODE TRANSITION DCM TO CCM,
(50µs/DIV)
9
FIGURE 20. LOAD TRANSIENT (PWM), (50µs/DIV)
March 17, 2010
FN6616.1
ISL8012
Typical Operating Performance
(Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, MODE = 0V, L = 2.2µH,
C1 = 2x10µF, C2 = 2x10µF, IOUT = 0A to 2A). (Continued)
LX 2V/DIV
EN 5V/DIV
VOUT
0.5V/DIV
VOUT RIPPLE
50mV/DIV
IL 0.5A/DIV
IL 1A/DIV
PG 5V/DIV
FIGURE 21. LOAD TRANSIENT (PFM), (500µs/DIV)
FIGURE 22. SOFT-START WITH NO LOAD (PWM),
(500µs/DIV)
EN 2V/DIV
EN 2V/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
IL 0.5A/DIV
IL 0.5A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 23. SOFT-START AT NO LOAD (PFM),
(500µs/DIV)
EN 2V/DIV
FIGURE 24. SOFT-START WITH PRE-BIASED 1V,
(500µs/DIV)
EN 5V/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
IL 1A/DIV
IL 1A/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 25. SOFT-START AT FULL LOAD, (2ms/DIV)
10
FIGURE 26. SOFT-DISCHARGE SHUTDOWN,
(2ms/DIV)
March 17, 2010
FN6616.1
ISL8012
Typical Operating Performance
(Unless otherwise noted, operating conditions are: TA = +25°C,
VVIN = 2.5V to 5.5V, EN = VIN, MODE = 0V, L = 2.2µH,
C1 = 2x10µF, C2 = 2x10µF, IOUT = 0A to 2A). (Continued)
RSI 2V/DIV
RSI 2V/DIV
VOUT RIPPLE
20mV/DIV
VOUT RIPPLE
20mV/DIV
PG 2V/DIV
PG 2V/DIV
FIGURE 27. RSI RESET, (200µs/DIV)
FIGURE 28. RSI RESET (ZOOM OUT), (200µs/DIV)
IL 2A/DIV
IL 2A/DIV
VOUT
0.5V/DIV
VOUT
1V/DIV
LX 2V/DIV
PHASE 2V/DIV
PG 5V/DIV
PG 5V/DIV
FIGURE 29. OUTPUT SHORT CIRCUIT, (500µs/DIV)
FIGURE 30. OUTPUT SHORT CIRCUIT RECOVERY,
(500µs/DIV)
OUTPUT CURRENT LIMIT (A)
3.2
5.5VIN
3.1
3.0
2.9
2.8
2.7
3.3VIN
2.6
2.5
2.4
-50
-25
0
25
50
75
100
TEMPERATURE (°C)
FIGURE 31. OUTPUT CURRENT LIMIT vs TEMPERATURE
11
March 17, 2010
FN6616.1
ISL8012
Theory of Operation
The ISL8012 is a step-down switching regulator
optimized for battery-powered handheld applications.
The regulator operates at 1MHz fixed switching
frequency under heavy load conditions to allow smaller
external inductors and capacitors to be used for minimal
printed-circuit board (PCB) area. At light load, the
regulator reduces the switching frequency (unless forced
to the fixed frequency) to minimize the switching loss
and to maximize the battery life. The quiescent current
when the output is not loaded is typically only 40µA. The
supply current is typically only 0.1µA when the regulator
is shut down.
network. The maximum EAMP voltage output is
precisely clamped to 1.47V.
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
PWM Control Scheme
Pulling the MODE pin LOW (<0.4V) forces the converter
into PWM mode, regardless of output current. The
ISL8012 employs the current-mode pulse-width
modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting. Figure 2
shows the block diagram. The current loop consists of the
oscillator, the PWM comparator, current sensing circuit
and the slope compensation for the current loop stability.
The gain for the current sensing circuit is typically
285mV/A. The control reference for the current loops
comes from the error amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the MOSFET
starts to ramp-up. When the sum of the current amplifier
CSA and the slope compensation (675mV/µs) reaches
the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn
off the P-MOSFET and turn on the N-Channel MOSFET.
The N-MOSFET stays on until the end of the PWM cycle.
Figure 32 shows the typical operating waveforms during
the PWM operation. The dotted lines illustrate the sum of
the slope compensation ramp and the current-sense
amplifier’s CSA output.
The output voltage is regulated by controlling the VEAMP
voltage to the current loop. The bandgap circuit outputs
a 0.8V reference voltage to the voltage loop. The
feedback signal comes from the VFB pin. The soft-start
block only affects the operation during the start-up and
will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage
error signal to a current output. The voltage loop is
internally compensated with the 27pF and 390kΩ RC
FIGURE 32. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the MODE pin HIGH (>1.4V) forces the converter
into PFM mode. The ISL8012 enters a pulse-skipping
mode at light load to minimize the switching loss by
reducing the switching frequency. Figure 33 illustrates
the skip-mode operation. A zero-cross sensing circuit
shown in Figure 2 monitors the N-MOSFET current for
zero crossing. When 8 consecutive cycles of the inductor
current crossing zero are detected, the regulator enters
the skip mode. During the 8 detecting cycles, the current
in the inductor is allowed to become negative. The
counter is reset to zero when the current in any cycle
does not cross zero.
Once the skip mode is entered, the pulse modulation
starts being controlled by the SKIP comparator shown in
Figure 2. Each pulse cycle is still synchronized by the
PWM clock. The P-MOSFET is turned on at the clock's
rising edge and turned off when the output is higher than
1.5% of the nominal regulation or when its current
reaches the peak Skip current limit value. Then the
inductor current is discharging to zero Ampere and stays
at zero. The internal clock is disabled. The output voltage
reduces gradually due to the load current discharging the
output capacitor. When the output voltage drops to the
nominal voltage, the P-MOSFET will be turned on again
at the rising edge of the internal clock as it repeats the
previous operations.
The regulator resumes normal PWM mode operation
when the output voltage drops 1.5% below the nominal
voltage.
CLOCK
8 CYCLES
SKIP CURRENT LIMIT
LOAD CURRENT
IL
0
NOMINAL +1.5%
VOUT
NOMINAL
FIGURE 33. SKIP MODE OPERATION WAVEFORMS
12
March 17, 2010
FN6616.1
ISL8012
Mode Control
UVLO
The ISL8012 has a MODE pin that controls the operation
mode. When the MODE pin is driven to low or shorted to
ground, the regulator operates in a forced PWM mode.
The forced PWM mode remains the fixed PWM frequency
at light load instead of entering the skip mode.
When the input voltage is below the undervoltage
lock-out (UVLO) threshold, the regulator is disabled.
Overcurrent Protection
The overcurrent protection is realized by monitoring the
CSA output with the OCP comparator, as shown in
Figure 2. The current sensing circuit has a gain of
285mV/A, from the P-MOSFET current to the CSA
output. When the CSA output reaches 1V, which is
equivalent to 2.9A for the switch current (0.15V offset),
the OCP comparator is tripped to turn off the P-MOSFET
immediately. The overcurrent function protects the
switching converter from a shorted output by
monitoring the current flowing through the upper
MOSFET.
Upon detection of overcurrent condition, the upper
MOSFET will be immediately turned off and will not be
turned on again until the next switching cycle.
Short-Circuit Protection
The short-circuit protection SCP comparator monitors the
VFB pin voltage for output short-circuit protection. When
the VFB is lower than 0.2V, the SCP comparator forces
the PWM oscillator frequency to drop to minimum value
to reduce the power dissipation. This comparator is
effective during start-up or an output short-circuit event.
RSI/PG Function
When powering up, the open-collector Power-Good
output holds low for about 1ms after VO reaches the
preset voltage. When the active-HI reset signal RSI is
issued, PG goes to low immediately and holds for the
same period of time after RSI comes back to LOW. The
output voltage is unaffected. Please refer to the timing
diagram in Figure 34. When the function is not used,
connect RSI to ground and leave the pull-up resistor R4
open at the PG pin.
The PG output also serves as a 1ms delayed Power-Good
signal when the pull-up resistor R1 is installed. The RSI
pin needs to be directly (or indirectly through a resistor)
connected to Ground for PG to be actively monitoring the
output voltage.
Soft Start-Up
The soft-start-up reduces the in-rush current during the
start-up. The soft-start block outputs a ramp reference to
the input of the error amplifier. This voltage ramp limits
the inductor current as well as the output voltage speed
so that the output voltage rises in a controlled fashion.
When VFB is less than 0.2V at the beginning of the softstart, the switching frequency is reduced to 1/3 of the
nominal value so that the output can start up smoothly
at light load condition. During soft-start, the IC operates
in the SKIP mode to support pre-biased output condition.
Enable
The enable (EN) input allows the user to control the
turning on or off the regulator for purposes such as
power-up sequencing. When the regulator is enabled,
there is typically a 600µs delay for waking up the
bandgap reference and then the soft-start-up begins.
Discharge Mode (Soft-Stop)
When a transition to shutdown mode occurs or the VIN
UVLO is set, the outputs discharge to GND through an
internal 100Ω switch.
Power MOSFETs
The power MOSFETs are optimized for best efficiency.
The ON-resistance for the P-MOSFET is typically 120mΩ
and the ON-resistance for the N-MOSFET is typically
110mΩ.
100% Duty Cycle
The ISL8012 features 100% duty cycle operation to
maximize the battery life. When the battery voltage
drops to a level that the ISL8012 can no longer maintain
the regulation at the output, the regulator completely
turns on the P-MOSFET. The maximum dropout voltage
under the 100% duty-cycle operation is the product of
the load current and the ON-resistance of the P-MOSFET.
Thermal Shut-Down
The ISL8012 has built-in thermal protection. When the
internal temperature reaches +140°C, the regulator is
completely shut down. As the temperature drops to
+115°C, the ISL8012 resumes operation by stepping
through the soft-start.
Applications Information
VO
Output Inductor and Capacitor Selection
MIN
25ns
RSI
1ms
1ms
PG
FIGURE 34. RSI AND PG TIMING DIAGRAM
13
To consider steady state and transient operations,
ISL8012 typically uses a 2.2µH output inductor. The
higher or lower inductor value can be used to optimize
the total converter system performance. For example, for
higher output voltage 3.3V application, in order to
decrease the inductor current ripple and output voltage
ripple, the output inductor value can be increased. It is
recommended to set the ripple inductor current
March 17, 2010
FN6616.1
ISL8012
approximately 30% of the maximum output current for
optimized performance. The inductor ripple current can
be expressed as shown in Equation 1:
VO ⎞
⎛
V O • ⎜ 1 – ---------⎟
V
⎝
IN⎠
ΔI = --------------------------------------L • fS
(EQ. 1)
The inductor’s saturation current rating needs to be at
least larger than the peak current. The ISL8012 protects
the typical peak current 6A. The saturation current needs
be over 7A for maximum output current application.
ISL8012 uses an internal compensation network and the
output capacitor value is dependent on the output
voltage. The ceramic capacitor is recommended to be
X5R or X7R. The recommended X5R or X7R minimum
output capacitor values are shown in Table 1.
TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT
VOUT
(V)
COUT
(µF)
L
(µH)
0.8
2x10
1.5~3.3
1.2
2x10
1.5~3.3
1.5
2x10
1.8~3.3
1.8
2x10
2.2~3.3
2.5
2x10
2.2~4.7
3.3
2x10
2.2~4.7
3.6
2x10
2.2~4.7
In Table 1, the minimum output capacitor value is given
for the different output voltage to make sure that the
whole converter system is stable.
Output Voltage Selection
The output voltage of the regulator can be programmed
via an external resistor divider that is used to scale the
output voltage relative to the internal reference voltage
and feed it back to the inverting input of the error
amplifier. Refer to Figure 1.
The output voltage programming resistor, R3, will depend
on the value chosen for the feedback resistor and the
desired output voltage of the regulator. The value for the
feedback resistor is typically between 10kΩ and 100kΩ,
as shown in Equation 2.
R 2 × 0.8V
R 3 = ---------------------------------V OUT – 0.8V
(EQ. 2)
If the output voltage desired is 0.8V, then R3 is left
unpopulated and R2 is shorted. For better performance,
add 220pF in parallel with R2 (124kΩ).
Input Capacitor Selection
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide
filtering function to prevent the switching current from
flowing back to the battery rail. Two 10µF X5R or X7R
ceramic capacitors are a good starting point for the input
capacitor selection.
Layout Recommendation
The layout is a very important converter design step to
make sure the designed converter works well. For the
ISL8012 buck converter, the power loop is composed of
the output inductor L, the output capacitor COUT, LX pin
and SGND pin. It is necessary to make the power loop as
small as possible.
The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to
the thermal epad is preferable. In addition, a solid
ground plane on the second layer is helpful for EMI
performance. Then connect the epad to the ground plane
with at lease 5 vias for best thermal performance.
For additional products, see www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
March 17, 2010
FN6616.1
ISL8012
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
web to make sure you have the latest Rev.
DATE
REVISION
CHANGE
2010-03-17
FN6616.1
Added “Related Literature” to page 1 per new data sheet standards.
Moved “Pin Configuration” to page 2 and converted “Pin Descriptions” on page 2 to tabular format,
per new data sheet standards.
Added inverter symbol on the RSI pin in the “Block Diagram” on page 3.
Added ESD ratings to “Absolute Maximum Ratings (Reference to GND)” on page 5 per new data sheet
standards.
Added “Revision History” on page 15 and “Products” on page 15 per new data sheet standards.
2009-10-29
On page 2: Redrew chamfered corner on Pinout to look like POD on page 15
On page 7 to page 11 in common conditions of “Typical Performance Curves”: Changed "L = 1.5µH
to 2.2µH" to "L = 2.2µH”
“Input Capacitor Selection” on page 14: changed "Two 22µF X5R or X7R ceramic capacitors are a
good starting point.." to "Two 10µF X5R or X7R ceramic capacitors are a good starting point.."
2009-10-27
On page 16: Updated POD to latest revision (changes from Rev 0 to Rev 1 were to add land pattern
and move dimensions from table onto drawing)
“Typical Application” on page 3: Changed value of C1 & C2 from 22µF to 2x10µF.
n page 7 to page 11 in common conditions of “Typical Performance Curves”: Changed "L = 1.5µH" to
"L = 1.5µH to 2.2uH"
On page 14 in Table 1: Changed value of all COUT caps from 22µF to 2x10µF.
“Input Capacitor Selection” on page 14: changed "One 22µF X5R or X7R ceramic capacitor is a good
starting point.." to "Two 22µF X5R or X7R ceramic capacitors are a good starting point.."
Throughout: Converted to new format. Added new required content as follows:
On page 4: Added MSL Note 3 to “Ordering Information”
On page 5: In the “Electrical Specifications”: Adding standard over temp note to common conditions
("Boldface limits apply...) Moved Note 7 "Parameters with MIN and/or MAX limits are 100% tested at
+25°C, unless otherwise specified. Temperature limits established by characterization and are not
production tested" from common conditions to MIN MAX columns as part of new standard
“Thermal Information” on page 5: Updated Theta JC Note 5 from "ThetaJC, “case temperature”
location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379."
to "For ThetaJC, the “case temp” location is the center of the exposed metal pad on the package
underside." per ASYD record and new standards
2009-07-15
On page 2 in Pinout: Deleted the circle and chamfered the corner of thermal pad (to match POD). Redrew pins 1, 5, 6, 10 to look the same as the other pins
Updated Pb-free Note 2 in “Ordering Information” on page 4 based on lead finish, per packaging.
On page 5: In the “Electrical Specifications”: Removed Note "Parts are 100% tested at +25°C.
Temperature limits established by characterization and are not production tested." from MIN MAX
columns and replaced with new verbiage in common conditions "Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested."
2008-03-11
FN6616.0
Initial release.
Products
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Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones,
handheld products, and notebooks. Intersil's product families address power management and analog signal
processing functions. Go to www.intersil.com/products for a complete list of Intersil product families.
*For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device
information page on intersil.com: ISL8012
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
FITs are available from our website at http://rel.intersil.com/reports/search.php
15
March 17, 2010
FN6616.1
ISL8012
Package Outline Drawing
L10.3x3C
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 2, 09/09
3.00
6
PIN #1 INDEX AREA
A
B
10
6
PIN 1
INDEX AREA
1
2.38
3.00
0.50
2
10 x 0.25
6
(4X)
0.10 C B
1.64
TOP VIEW
10x 0.40
BOTTOM VIEW
5
(4X)
PACKAGE
OUTLINE
0.10 M C B
SEE DETAIL "X"
(10 x 0.60)
(10x 0.25)
0.90
MAX
0.10 C
BASE PLANE
2.38
0.20
C
SEATING PLANE
0.08 C
SIDE VIEW
(8x 0.50)
1.64
TYPICAL RECOMMENDED LAND PATTERN
C
0.20 REF
5
0.05
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension b applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
7. COMPLAINT TO JEDEC MO-229-WEED-3 except for E-PAD
dimensions.
16
March 17, 2010
FN6616.1