ISL9105 ® Data Sheet February 13, 2007 FN6415.1 600mA Low Quiescent Current 1.6MHz High Efficiency Synchronous Buck Regulator Features ISL9105 is a 600mA, 1.6MHz step-down regulator that is ideal for powering low-voltage microprocessors in handheld devices such as PDAs and cellular phones. It is optimized for generating low output voltages down to 0.8V. The supply voltage range is from 2.7V to 5.5V allowing the use of a single Li+ cell, three NiMH cells or a regulated 5V input. It has a guaranteed minimum output current of 600mA. 1.6MHz pulse-width modulation (PWM) switching frequency allows using small external components. It has flexible operation mode selection of forced PWM mode and low IQ mode with typical 25μA quiescent current for highest light load efficiency to maximize battery life. • Selectable Forced PWM Mode and SKIP Mode • High Efficiency Synchronous Buck Regulator with up to 95% Efficiency • 25μA Quiescent Supply Current in SKIP Mode • 2.7V to 5.5V Supply Voltage • 216ms POR Timer • 3% Output Accuracy Over Temperature/Line/Load • 600mA Guaranteed Output Current • Less Than 1μA Logic Controlled Shutdown Current • 100% Maximum Duty Cycle for Lowest Dropout The ISL9105 includes a pair of low on-resistance P-Channel and N-Channel internal MOSFETs to maximize efficiency and minimize external component count. 100% duty-cycle operation allows less than 200mV dropout voltage at 600mA output current. • Discharge Output Capacitor when Shutdown The ISL9105 offers a typical 216ms Power-On-Reset (POR) timer at power-up. The timer output can be reset by RSI. When shutdown, ISL9105 discharges the output capacitor. Other features include internal digital soft-start, enable for power sequence, overcurrent protection, and thermal shutdown. • Over-Temperature Protection The ISL9105 is offered in a 2mmx3mm 8 Ld DFN package with 1mm maximum height. The complete converter occupies less than 1cm2 area. Applications • Internal Loop Compensation • Internal Digital Soft-Start • Peak Current Limit Protection, Short Circuit Protection • Enable • Small 8 Ld 2x3mm DFN • Pb-Free Plus Anneal Available (RoHS Compliant) • Single Li-Ion Battery-Powered Equipment • DSP Core Power Ordering Information(to be updated) PART NUMBER (NOTE) ISL9105IRZ-T TEMP. RANGE PART (°C) MARKING 05Z PACKAGE (Pb-free) • PDAs and Palmtops PKG. DWG. # Pinout ISL9105 (8 LD DFN) TOP VIEW -40 to +85 8 Ld 2x3 DFN L8.2x3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 VIN 1 8 PHASE EN 2 7 GND POR 3 6 FB MODE 4 5 RSI CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL9105 Absolute Maximum Ratings (Reference to GND) Thermal Information Supply Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.5V EN, RSI, MODE, POR . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V PHASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.5V to 6.5V FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) 2x3 DFN Package . . . . . . . . . . . . . . 75 6 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to 600mA Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specification are measured at the following conditions: TA = +25°C, VIN = 3.6V, EN = VIN, RSI = MODE = 0V, L = 3.3μH, C1 = 10μF, C2 = 10μF, IOUT = 0A (see the Typical Application Circuit). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Rising - 2.5 2.7 V Falling 2.2 2.4 - V MODE = VIN, no load at the output - 25 50 μA MODE = GND, no load at the output - 5 8 mA VIN = 5.5V, EN = low - 0.1 2 μA TA = 0°C to +85°C 0.784 0.8 0.816 V TA = -40°C to +85°C 0.78 0.8 0.82 V FB = 0.75V - 0.1 - μA Output Voltage Accuracy VIN = VO + 0.5V to 5.5V, IO = 0mA to 600mA -3 - 3 % Line Regulation VIN = VO + 0.5V to 5.5V (minimal 2.7V) - 0.2 - %/V 600 - - mA Design info only - 20 - μA/V P-Channel MOSFET On Resistance VIN = 3.6V, IO = 200mA - 0.16 0.22 Ω N-Channel MOSFET On Resistance VIN = 3.6V, IO = 200mA - 0.14 0.22 Ω 0.75 1.0 1.3 A - 100 - % 1.2 1.6 1.8 MHz - - 140 ns - 1.1 - ms - - 0.3 V 150 216 275 ms - 0.01 0.1 μA SUPPLY VIN Under Voltage Lockout Threshold Quiescent Supply Current VUVLO IVIN Shutdown Supply Current ISD OUTPUT REGULATION FB Regulation Voltage VFB FB Bias Current IFB Maximum Output Current COMPENSATION Error Amplifier Trans-Conductance PHASE P-Channel MOSFET Peak Current Limit IPK PHASE Maximum Duty Cycle PWM Switching Frequency fS PHASE Minimum On Time MODE = low (forced PWM mode) Soft-Start-Up Time POR Output Low Voltage Sinking 1mA, FB = 0.7V Delay Time POR Pin Leakage Current POR = VIN = 3.6V 2 FN6415.1 February 13, 2007 ISL9105 Electrical Specifications Unless otherwise noted, all parameter limits are guaranteed over the recommended operating conditions and the typical specification are measured at the following conditions: TA = +25°C, VIN = 3.6V, EN = VIN, RSI = MODE = 0V, L = 3.3μH, C1 = 10μF, C2 = 10μF, IOUT = 0A (see the Typical Application Circuit). (Continued) PARAMETER SYMBOL TEST CONDITIONS Minimum Supply Voltage for Valid POR Signal MIN TYP MAX UNITS 1.2 - - V Internal PGOOD Low Rising Threshold Percentage of nominal regulation voltage 89.5 92 94.5 % Internal PGOOD Low Falling Threshold Percentage of nominal regulation voltage 85 88 91 % Internal PGOOD High Rising Threshold Percentage of nominal regulation voltage 105.5 108 110.5 % Internal PGOOD High Falling Threshold Percentage of nominal regulation voltage 102 105 108 % - 64 - μs Logic Input Low - - 0.4 V Logic Input High 1.4 - - V Internal PGOOD Delay Time EN, MODE, RSI - 0.1 1 μA Thermal Shutdown - 150 - °C Thermal Shutdown Hysteresis - 25 - °C Logic Input Leakage Current Pulled up to 5.5V Pin Descriptions PHASE VIN Switching node connection. Connect to one terminal of inductor. Input supply voltage. Connect a 10μF ceramic capacitor to power ground. GND System ground. EN Regulator enable pin. Enable the output when driven to high. Shutdown the chip and discharge output capacitor when driven to low. Do not leave this pin floating. FB POR RSI 216ms timer output. At power-up or EN HI, this output is a 216ms delayed Power-Good signal for the output voltage. This output can be reset by a low RSI signal. 216ms starts when RSI goes to high. This input resets the 216ms timer. When the output voltage is within the PGOOD window, an internal timer is started and generates a POR signal 216ms later when RSI is low. A high RSI resets POR and RSI high to low transition restarts the internal counter if the output voltage is within the window, otherwise the counter is reset by the output voltage condition. MODE Mode Selection pin. Connect to logic high or input voltage VIN for low IQ mode; connect to logic low or ground for forced PWM mode. Do not leave this pin floating. 3 Buck regulator output feedback. Connect to the output through a voltage divider resistor. Exposed Pad The exposed pad must be connected to the GND pin for proper electrical performance. The exposed pad must also be connected to as much as possible for optimal thermal performance. FN6415.1 February 13, 2007 ISL9105 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 3.6V, EN = VIN, RSI = MODE = 0V, L = 3.3µH, C1 = 10µF, C2 = 10µF, IOUT = 0A) 100 100 VO = 2.5V 90 EFFICIENCY (%) EFFICIENCY (%) 90 80 VO = 1.6V 70 VO = 0.8V 60 VIN = 2.7V 80 VIN = 3.6V 70 60 VIN = 5.5V 50 1 10 100 LOAD CURRENT (mA) 50 1000 FIGURE 1. EFFICIENCY vs LOAD CURRENT (VIN = 3.6V) 1 10 100 LOAD CURRENT (mA) 1000 FIGURE 2. EFFICIENCY vs LOAD CURRENT (VO = 1.6V) 1.640 1.635 1.630 1.630 1.625 VOUT (V) 1.635 1.625 1.620 I_LOAD = 300mA I_LOAD = 600mA 1.615 1.620 VIN = 3.6V VIN = 2.7V VIN = 5.5V 1.615 1.610 1.610 2.7 1.605 3.7 4.7 0 100 200 300 400 OUTPUT CURRENT (mA) VIN (V) FIGURE 3. LINE REGULATION 500 600 FIGURE 4. LOAD REGULATION 40 5.5 5.0 INPUT CURRENT (mA) 35 INPUT CURRENT (μA) VOUT (V) I_LOAD = 0A 30 25 20 15 10 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 5 0 2.73 0.5 0.20 3.74 VIN (V) 0.20 FIGURE 5. I_Q vs VIN (PFM) 4 4.70 0 2.7 3.2 3.7 VIN (V) 4.2 4.7 FIGURE 6. I_Q vs VIN (PWM) FN6415.1 February 13, 2007 ISL9105 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 3.6V, EN = VIN, RSI = MODE = 0V, L = 3.3µH, C1 = 10µF, C2 = 10µF, IOUT = 0A) (Continued) EN EN VPHASE VPHASE VOUT VOUT IL IL FIGURE 7. SOFT-START (PFM, VIN = 3.6V, VOUT = 1.6V, IO = 10mA) VOUT(AC COUPLED) FIGURE 8. SOFT-START (PWM, VIN = 3.6V, VOUT = 1.6V, IO = 1mA) VOUT(AC COUPLED) VPHASE VPHASE IL IL 400mA 600mA IOUT IOUT 200mA 5mA FIGURE 9. LOAD TRANSIENT (PWM, VIN = 3.6V, VOUT = 1.6V) FIGURE 10. LOAD TRANSIENT (PWM, VIN = 3.6V, VOUT = 1.6V) VPHASE VPHASE VOUT VOUT IL IOUT 600mA IL 600mA 10mA 10mA FIGURE 11. LOAD TRANSIENT (PFM, VIN = 3.6V, VOUT = 1.6V) 5 IOUT FIGURE 12. LOAD TRANSIENT (PFM, VIN = 3.6V, VOUT = 1.6V) FN6415.1 February 13, 2007 ISL9105 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 3.6V, EN = VIN, RSI = MODE = 0V, L = 3.3µH, C1 = 10µF, C2 = 10µF, IOUT = 0A) (Continued) VOUT (AC COUPLED) VPHASE IL 50mA IOUT 10mA FIGURE 13. (PFM, VIN = 3.6V, VOUT = 1.6V) Typical Applications ISL9105 INPUT 2.7V TO 5.5V VIN OUTPUT 1.6V/600mA L PHASE C2 C1 10µF EN R2 100k C3 GND R1 100k R3 100k VIN POR FB MODE RSI FIGURE 14. TYPICAL APPLICATION DIAGRAM PARTS DESCRIPTION MANUFACTURERS PART NUMBER SPECIFICATIONS SIZE L Output inductor Sumida CDRH4D14/HP-4R7 4.7μH/1.40A/115mΩ 4.6x4.6x1.5mm Sumida CDRH2D14NP-3R3 3.3μH/1.20A/100mΩ 3.2x3.2x1.55mm Coilcraft LPS3015-472MLB 4.7μH/1.10A/200mΩ 3.3x3.3x1.4mm C1 Input capacitor Murata GRM21BR60J106KE19L 10μF/6.3V 2.0x1.25x1.25mm (0805) C2 Output capacitor Murata GRM21BR60J475KA11L 4.7μF/6.3V, 10μF/6.3V 2.0x1.25x1.25mm (0805) Panasonic ECJ-1VC2A100D 10pF/100V 0603 100kΩ 1.6x0.8x0.45mm (0603) C3 R1 Pull-up resistor Various 6 FN6415.1 February 13, 2007 ISL9105 Block Diagram MODE Soft SOFT START SHUTDOWN SHUTDOWN BANDGAP 0.8V + EN VIN OSCILLATOR + COMP EAMP PWM/PFM LOGIC CONTROLLER PROTECTION DRIVER PHASE + GND FB Slope SLOPE COMP + CSA1 REF4 + + OCP REF1 + SKIP REF2 + REF3 POR POR DELAY ZERO CROSS SENSING RSI REF5 SCP + Theory of Operation The ISL9105 is a step-down switching regulator optimized for battery-powered handheld applications. The regulator operates at 1.6MHz fixed switching frequency under heavy load condition to allow small external inductor and capacitors to be used for minimal printed-circuit board (PCB) area. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The quiescent current when the output is not loaded is typically only 25μA. The supply current is typically only 0.1μA when the regulator is shut down. PWM Control Scheme The ISL9105 employs the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 15 shows the block diagram. The current loop consists of the oscillator, the PWM comparator COMP, current sensing circuit, and the slope compensation for the current loop stability. The current sensing circuit consists of the 7 resistance of the P-Channel MOSFET when it is turned on and the Current Sense Amplifier (CSA). The control reference for the current loops comes from the Error Amplifier (EAMP) of the voltage loop. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the P-Channel MOSFET starts ramping up. When the sum of the CSA output and the compensation slope reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-Channel MOSFET and to turn on the N-Channel MOSFET. The NChannel MOSFET remains on till the end of the PWM cycle. Figure 15 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the compensation ramp and the CSA output. FN6415.1 February 13, 2007 ISL9105 The output voltage is regulated by controlling the reference voltage to the current loop. The bandgap circuit outputs a 0.8V reference voltage to the voltage control loop. The feedback signal comes from the FB pin. The soft-start block only affects the operation during the start-up and will be discussed separately in the “Soft-Start-Up” on page 9. The error amplifier is a transconductance amplifier, which converts the voltage error signal to a current output. The voltage loop is internally compensated by a RC network. The maximum EAMP voltage output is precisely clamped to the bandgap voltage (1.172V). edge of the clock and turned off when its current reaches 20% of the peak current limit. As the average inductor current in each cycle is higher than the average current of the load, the output voltage rises cycle over cycle. When the output voltage reaches 1.5% above the nominal voltage, the P-Channel MOSFET is turned off immediately and the inductor current is fully discharged to zero and remains zero. The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-Channel MOSFET will be turned on again, repeating the previous operations. VEAMP The regulator resumes PWM mode operation when the output voltage drops 1.5% below the nominal voltage. VCSA1 Enable The enable (EN) input allows user to control the turn-on and turn-off of the regulator for purposes such as power-up sequencing. When the regulator is enabled, there is a typically a 600µs delay for waking up the internal reference circuit, then the soft start-up begins. When the regulator is disabled, the P-MOSFET is turned off immediately and the output capacitor is discharged. DUTY CYCLE IL VOUT POR Signal FIGURE 15. PWM OPERATION WAVEFORMS SKIP Mode The ISL9105 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the effective switching frequency. Figure 16 illustrates the skip-mode operation. A zero-cross sensing circuit (as shown in Figure 15) monitors the N-Channel MOSFET current for zero crossing. When the N-Channel MOSFET current is detected crossing zero for 8 consecutive cycles, the regulator enters the skip mode. During the 8 consecutive cycles, the inductor current is allowed to be negative. The internal counter is reset to zero when the sensed N-Channel MOSFET current does not cross zero in any cycle within the 8 consecutive cycles. Once ISL9105 enters SKIP mode, the pulse modulation starts being controlled by the SKIP comparator shown in Figure 15. Each pulse cycle is still synchronized by the PWM clock. The P-Channel MOSFET is turned on at the rising The ISL9105 offers a Power-On Reset (POR) signal. When the output voltage is not within a power-good window, the POR pin outputs an open-drain low signal (Figure 15), which can be used to reset the microprocessor. When the output voltage is within a power-good window, a power-good signal is issued to turn off the open-drain POR pin. The rising edge of the POR output is delayed by 216ms(typical) from the time the power-good signal is issued. Mode Selection MODE pin is provided on ISL9105 to select the operation mode. When it is driven to logic low or shorted to ground, the regulator operates in the forced PWM mode. The forced PWM mode remains the fixed PWM frequency (typically 1.6MHz) at all load conditions. When the MODE pin is driven to logic high or connected to input voltage VIN, the regulator operates in either SKIP mode or fixed PWM mode depending upon the load condition. CLOCK 8 CYCLES CURRENT LIMIT IL LOAD CURRENT 0 NOMINAL + 1.5% VOUT NOMINAL FIGURE 16. SKIP MODE OPERATION WAVEFORMS 8 FN6415.1 February 13, 2007 ISL9105 RSI Signal Thermal Shut Down The RSI signal is an input signal, which can reset the POR signal. As shown in Figure 15, the power-good signal is gated by the RSI signal. When the RSI is high, the POR signal will remain low, regardless of the power-good signal. The ISL9105 provides built-in thermal protection. When the internal temperature reaches +150°C, the regulator is completely shutdown. As the temperature drops to +125°C, the ISL9105 resumes operation by stepping through a soft-start-up. Overcurrent Protection The overcurrent protection can protect ISL9105 itself as well as other external components when over load condition happens. It is realized by monitoring the CSA output with the OCP comparator, as shown in Figure 15. The current sensing circuit has a gain of 0.4V/A. When the CSA output reaches 0.4V, (which means the current at P-Channel MOSFET reaches 1A) the OCP comparator is triggered to turn off the P-Channel MOSFET immediately. Short-Circuit Protection ISL9105 has a Short-Circuit Protection (SCP) comparator monitors the FB pin voltage for output short-circuit protection. When the FB is lower than 0.2V, the SCP comparator forces the PWM oscillator frequency to drop to 1/3 of the normal operation value. This comparator is effective during start-up or an output short-circuit event. UVLO When the input voltage is below the Under-Voltage Lock Out (UVLO) threshold, the regulator is disabled. Soft-Start-Up The soft-start-up eliminates the in-rush current during the start-up. The soft-start block outputs a ramp reference to both the voltage loop and the current loop. The two ramps limit the inductor current rising speed as well as the output voltage speed so that the output voltage rises in a controlled fashion. At the very beginning of the start-up, the output voltage is less than 0.2V; hence the PWM operating frequency is 1/3 of the normal frequency. Power MOSFETs The two power MOSFETs are optimized to achieve better efficiency. The on resistance for the P-Channel MOSFET is typically 160mΩ and the on resistance for the N-Channel MOSFET is typically 140mΩ. 100% Duty Cycle Operation The ISL9105 features 100% duty cycle operation to maximize the battery life. When the input voltage drops to a level that the ISL9105 can no longer maintain the switching regulation at the output, the P-Channel MOSFET is completely turned on. The maximum drop out voltage under the 100% duty-cycle operation is the product of the load current and the on resistance of the P-Channel MOSFET. Minimum input voltage VIN under this condition is the sum of output voltage and the voltage drop cross the output inductor and P-Channel MOSFET. 9 Applications Information Output Inductor and Capacitor Selection To achieve better steady state and transient operation, ISL9105 typically uses a 4.7µH output inductor. Higher or lower inductor value can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. The peak-to-peak inductor current ripple can be expressed in Equation 1: V OUT⎞ ⎛ V OUT • ⎜ 1 – ----------------⎟ V IN ⎠ ⎝ ΔI = ----------------------------------------------------L • fS (EQ. 1) In Equation 1, the inductance should consider the value with worst case tolerances; and for switching frequency fS, the minimum fS from the Electrical Specifications Table on page 2 can be used. To select the inductor, its saturation current rating should be at least higher than the sum of the maximum output current and (ΔI)/2 from Equation 1. ISL9105 uses internal compensation network and the output capacitor value is dependant on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. Input Capacitor Selection The main functions for the input capacitor is to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. A 10μF/6.3V ceramic capacitor (X5R or X7R) is a good starting point for the input capacitor selection. Output Voltage Setting Resistor Selection The voltage divider resistors, R2 and R3, shown in Figure 14 set the output voltage. The output voltage can be calculated by Equation 2: R 2⎞ ⎛ V O = 0.8 • ⎜ 1 + -------⎟ R 3⎠ ⎝ (EQ. 2) where the 0.8V is the reference voltage. The voltage divider, which consists of R2 and R3, increases the quiescent current by VO/(R2+R3), so larger resistance is desirable. On the other hand, the FB pin has leakage current that will cause error in the output voltage setting. The leakage current is typically 0.1μA. To minimize the accuracy impact on the output voltage, select the R3 no larger than 200kΩ. FN6415.1 February 13, 2007 ISL9105 PCB Layout Recommendation The PCB layout is a very important converter design step to make sure the designed converter works well. For ISL9105, the power loop is composed of the output inductor L, the output capacitor COUT, the PHASE pin and the GND pin. It is necessary to make the power loop as small as possible and the connecting traces among them should be direct, short and wide. The switching node of the converter, the PHASE pin, and the traces connected to the node are very noisy, so keep the voltage feedback trace away from these noisy traces. The input capacitor should be placed to VIN pin as close as possible. And the ground of input and output capacitors should be connected as close as possible. The heat of the IC is mainly dissipated through the thermal pad. Maximizing the copper area connected to the thermal pad is preferable. In addition, a solid ground plane is helpful for better EMI performance. 10 FN6415.1 February 13, 2007 ISL9105 Dual Flat No-Lead Plastic Package (DFN) L8.2x3 8 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS 2X SYMBOL 0.15 C A A D 2X 0.15 C B MIN 0.80 0.90 1.00 - - - 0.05 - 0.32 5,8 1.75 7,8 1.90 7,8 0.20 REF 0.20 D D2 INDEX AREA B 0.10 A SIDE VIEW C SEATING PLANE - 1.65 - 3.00 BSC 1.65 e // 0.25 2.00 BSC 1.50 E E2 TOP VIEW NOTES A b E MAX A1 A3 6 NOMINAL 1.80 - 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 C 0.08 C N 8 Nd 4 A3 2 3 Rev. 0 6/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. D2 (DATUM B) 7 8 2. N is the number of terminals. 3. Nd refers to the number of terminals on D. D2/2 1 6 INDEX AREA 4. All dimensions are in millimeters. Angles are in degrees. 2 NX k (DATUM A) 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. E2 E2/2 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. NX L 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. N N-1 NX b e 8 5. Dimension b applies to the metallized terminal and is measured between 0.25mm and 0.30mm from the terminal tip. 5 0.10 (Nd-1)Xe REF. M C A B BOTTOM VIEW CL (A1) NX (b) L 5 SECTION "C-C" C C TERMINAL TIP e FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6415.1 February 13, 2007