HS-82C55ARH TM Data Sheet August 2000 File Number 3191.2 Radiation Hardened CMOS Programmable Peripheral Interface Features The Intersil HS-82C55ARH is a high performance, radiation hardened CMOS version of the industry standard 8255A and is manufactured using a hardened field, self-aligned silicon gate CMOS process. It is a general purpose programmable I/O device which may be used with many different microprocessors. There are 24 I/O pins which are organized into two 8-bit and two 4-bit ports. Each port may be programmed to function as either an input or an output. Additionally, one of the 8-bit ports may be programmed for bidirectional operation, and the two 4-bit ports can be programmed to provide handshaking capabilities. The high performance, radiation hardness, and industry standard configuration of the HS-82C55ARH make it compatible with the HS-80C86RH radiation hardened microprocessor. • QML Qualified per MIL-PRF-38535 Requirements Static CMOS circuit design insures low operating power. Bus hold circuitry eliminates the need for pull-up resistors. The Intersil hardened field CMOS process results in performance equal to or greater than existing radiation resistant products at a fraction of the power. • Direct Bit Set/Reset Capability Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed here must be used when ordering. • 2.0mA Drive Capability on All I/O Port Outputs Detailed Electrical Specifications for these devices are contained in SMD 5962-95819. A “hot-link” is provided on our homepage for downloading. www.intersil.com/spacedefense/space.asp Ordering Information ORDERING NUMBER INTERNAL MKT. NUMBER TEMP. RANGE (oC) • Electrically Screened to SMD # 5962-95819 • Radiation Hardened - Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max) - Transient Upset . . . . . . . . . . . . . . . . . . . . <108 rad(Si)/s - Latch Up Free EPI-CMOS • Low Power Consumption - IDDSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20µA • Pin Compatible with NMOS 8255A and the Intersil 82C55A • High Speed, No “Wait State” Operation with 5MHz HS-80C86RH • 24 Programmable I/O Pins • Bus-Hold Circuitry on All I/O Ports Eliminates Pull-Up Resistors • Enhanced Control Word Read Capability • Hardened Field, Self-Aligned, Junction Isolated CMOS Process • Single 5V Supply • Military Temperature Range . . . . . . . . . . . -55oC to 125oC Pinout CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T40 TOP VIEW PA3 1 40 PA4 PA2 2 39 PA5 PA1 3 38 PA6 PA0 4 37 PA7 5962R9581901QQC HS1-82C55ARH-8 -55 to 125 RD 5 36 WR 5962R9581901VQC HS1-82C55ARH-Q -55 to 125 CS 6 35 RESET GND 7 34 D0 A1 8 33 D1 1 A0 9 32 D2 PC7 10 31 D3 PC6 11 30 D4 PC5 12 29 D5 PC4 13 28 D6 PC0 14 27 D7 PC1 15 26 VDD PC2 16 25 PB7 PC3 17 24 PB6 PB0 18 23 PB5 PB1 19 22 PB4 PB2 20 21 PB3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 HS-82C55ARH Pin Descriptions SYMBOL PIN NUMBERS TYPE DESCRIPTION PA0-7 1-4, 37-40 I/O Port A: General purpose I/O Port. Data direction and mode is determined by the contents of the Control Word. PB0-7 18-25 I/O Port B: General purpose I/O port. See Port A. PC0-3 14-17 I/O Port C (Lower): Combination I/O port and control port associated with Port B. See Port A. PC4-7 10-13 I/O Port C (Upper): Combination I/O Port and control port associated with Port A. See Port A. D0-7 27-34 I/O Bidirectional Data Bus: Three-State data bus enabled as an input when CS and WR are low and as an output when CS and RD are low. VDD 26 I VDD: The +5V power supply pin. A 0.1µF capacitor between pins 26 and 7 is recommended for decoupling. GND 7 I Ground. CS 6 I Chip Select: A “low” on this input pin enables the communication between the HS-82C55ARH and the CPU. RD 5 I Read: A “low” on this input pin enables the HS-82C55ARH to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to “read from” the HS-82C55ARH. WR 36 I Write: A “low” on this input pin enables the CPU to write data or control words into the HS-82C55ARH. A0 and A1 8, 9 I Port Select 0 and Port Select 1: These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word registers. They are normally connected to the Least Significant Bits of the address bus (A0 and A1). Reset 35 I Reset: A “high” on this input clears the control register and all ports (A, B, C) are set to the input mode. “Bus hold” devices internal to the HS-82C55ARH will hold the I/O port inputs to a logic “1” state with a maximum hold current of 400µA. 2 HS-82C55ARH Functional Diagram +5V POWER SUPPLIES GND GROUP A CONTROL BIDIRECTIONAL DATA BUS GROUP A PORT A (8) I/O PA7 - PA0 GROUP A PORT C UPPER (4) I/O PC7 - PC4 GROUP B PORT C LOWER (4) I/O PC3 - PC0 GROUP B PORT B (8) I/O PB7 - PB0 DATA BUS BUFFER D7 - D0 8-BIT INTERNAL DATA BUS RD WR A1 A0 RESET READ/WRITE CONTROL LOGIC GROUP B CONTROL CS AC Test Circuit AC Testing Input, Output Waveforms V1 INPUT R1 2.8V TEST POINT FROM OUTPUT UNDER TEST 1.5V 1.5V 0.4V C1 (NOTE) R2 NOTE: AC Testing: All parameters tested as per test circuits. Input rise and fall times are driven at 1V/ns. NOTE: Includes stray and jig capacitance. TEST CONDITIONS DEFINITION TABLE V1 R1 R2 C1 1.7V 523Ω Open 150pF 3 HS-82C55ARH Waveforms TWLWH TRLRH WR RD TDVWH TPVRL TRHPX TWHDX D7 - D0 INPUT TAVRL TAVWL TRHAX TWHAX CS, A1, A0 CS, A1, A0 OUTPUT D7 - D0 TRLDV TRHDZ TWHPV FIGURE 1. MODE 0 (BASIC INPUT) FIGURE 2. MODE 0 (BASIC OUTPUT) TWHOL TSLSH WR STB TKLOH OBF IBF TRLNL TSLIH TRHIL INTR INTR TWLNL TSHNH ACK RD TKLKH TKHNH TSHPX INPUT FROM PERIPHERAL OUTPUT TPVSH TWHPV FIGURE 3. MODE 1 (STROBED INPUT) FIGURE 4. MODE 1 (STROBED OUTPUT) DATA FROM CPU TO HS-82C55ARH A0 - A1, CS WR TAVWL TKLOH OBF TWHAX DATA BUS TWHOL INTR TDVWH TKLKH TWHDX WR ACK TWLWH TSLSH STB FIGURE 6. WRITE TIMING IBF TSLIH TKLPV TKHPX A0 - A1, CS TPVSH PERIPHERAL BUS RD DATA FROM PERIPHERAL TO HS-82C55ARH TAVRL TSHPX TRHAX TRLRH TRHIL RD DATA FROM HS-82C55ARH TO PERIPHERAL TRHDX DATA FROM HS-82C55ARH TO CPU FIGURE 5. MODE 2 (BIDIRECTIONAL) NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. 4 TAVRL DATA BUS HIGH IMPEDANCE VALID FIGURE 7. READ TIMING HIGH IMPEDANCE HS-82C55ARH Burn-In Circuits PROGRAMMABLE PERIPHERAL INTERFACE PROGRAMMABLE PERIPHERAL INTERFACE VDD 1 40 1 40 2 39 2 39 3 38 3 38 4 37 4 37 5 36 F0 F0 5 36 6 35 6 35 7 34 7 34 8 33 F2 8 33 F4 9 32 F1 9 32 F6 10 31 F5 10 31 F5 11 30 F0 11 30 12 29 12 29 13 28 13 28 14 27 14 27 15 26 16 25 15 26 16 17 24 25 17 18 23 24 18 23 19 20 22 19 22 21 20 21 F0 F4 STATIC CONFIGURATION NOTES: F7 F3 VDD DYNAMIC CONFIGURATION NOTES: 1. VDD = 6.0V ±0.5% 4. VDD = 6.0V ±5% for Burn-In 2. IDD <500µA 5. VDD = 5.0V ±5% for Life Test 3. TA Min = 125oC 6. All resistors are 10kΩ ±5% 7. -0.3V ≤ VIL ≤ 0.8V 8. VDD - 1.0V ≤ VIH ≤ VDD 9. IDD < 5mA 10. F0 = 10kHz, 50% Duty cycle 11. F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2 . . . F7 = F6/2 12. TA Min = 125oC 5 HS-82C55ARH Irradiation Circuit CMOS PROGRAMMABLE PERIPHERAL INTERFACE +5.5V +5V GND POWER SUPPLIES GROUP A CONTROL GROUP A PORT A (8) I/O PA7PA0 GROUP A PORT C UPPER (4) I/O PC7PC4 GROUP B PORT C LOWER (4) I/O PC3PC0 GROUP B PORT B (8) I/O PB7PB0 1 40 2 39 3 38 4 37 5 36 6 35 7 34 8 33 9 32 10 31 11 30 12 29 13 28 14 27 15 26 16 25 17 24 Read/Write and Control Logic 18 23 19 22 20 21 The function of this block is to manage all of the internal and external transfer of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. BIDIRECTIONAL DATA BUS DATA BUS BUFFER D7D0 +5.5V 8-BIT INTERNAL DATA BUS RD WR A1 A0 RESET READ/ WRITE CONTROL LOGIC GROUP B CONTROL CS FIGURE 8. BLOCK DIAGRAM DATA BUS BUFFER, READ/WRITE, GROUP A AND B CONTROL LOGIC FUNCTIONS Group A and Group B Controls NOTE: 13. VDD = 5.5V Functional Description The HS-82C55ARH is a programmable peripheral interface designed to allow microcomputer systems to control and interface with all types of peripheral devices. It has the ability to generate and respond to all asynchronous handshaking signals necessary to transfer data to and from peripheral devices, and it can also interrupt the processor when a peripheral needs servicing. These capabilities allow the HS-82C55ARH to be used in an unlimited number of applications including EXTERNAL SYSTEM CONTROL, ASYNCHRONOUS DATA TRANSFER, and SYSTEMS MONITORING. Data Bus Buffer This three-state bidirectional 8-bit buffer is used to interface the HS-82C55ARH to the system data bus (see Figure 8). Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. 6 The functional configuration of each port is programmed by the systems software. In essence, the CPU writes a control word to the HS-82C55ARH. The control word contains information such as “mode”, “bit set”, “bit reset”, etc., that initializes the functional configuration of the HS-82C55ARH. Each of the Control blocks (Group A and Group B) accepts “commands” from the Read/Write Control Logic, receives “control words” from the internal data bus and issues the proper commands to its associated ports. Control Group - Port A and Port C upper (C7 - C4). Control Group - Port B and Port C lower (C3 - C0). Ports A, B, C The HS-82C55ARH contains three 8-bit ports (A, B and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or “personality” to further enhance the power and flexibility of the HS-82C55ARH. Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both “pull-up” and “pull-down” bus hold devices are present on Port A. See Figure 9A. Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. See Figure 9B. HS-82C55ARH Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and can be used for the control signal outputs and status signal inputs in conjunction with Ports A and B. See Figure 9B. ADDRESS BUS CONTROL BUS DATA BUS RD CONTROL MASTER RESET RD, WR D7 - D0 A0 - A1 CS B C A MODE 0 EXTERNAL PORT A PIN INTERNAL DATA IN 8 I/O INTERNAL DATA OUT 4 I/O 4 I/O 8 I/O PB7 - PB0 PC3 - PC0 PC7 - PC4 PA7 - PA0 WR SIGNAL MODE 1 B C A FIGURE 9A. 8 I/O VDD MASTER RESET 8 I/O PB7 - PB0 CONTROL CONTROL PA7 - PA0 OR I/O OR I/O P B MODE 2 C A 8 I/O EXTERNAL PORT B, C PIN INTERNAL DATA IN 8 I/O PB7 - PB0 BIDIRECTIONAL PA7 - PA0 CONTROL INTERNAL DATA OUT FIGURE 10. BASIC MODE DEFINITIONS AND BUS INTERFACE WR SIGNAL TABLE 1. FIGURE 9B. FIGURE 9. I/O PORT CONFIGURATION Operational Description Control Word The data direction and mode of Ports A, B and C are determined by the contents of the Control Word. See Figure 11. The Control Word can be both written and read as shown in Table 1 and 2. During write operations, the function of the Control Word being written is determined by data bit D7. If D7 is low, the data on D0 - D3 will set or reset one of the bits of Port C. See Figure 12. During read Operations, the Control Word will always be in the format illustrated in Figure 11 with Bit D7 high to indicate Control Word Mode Information. INPUT OPERATION (READ) A1 A0 RD WR CS 0 0 0 1 0 Port A - Data Bus 0 1 0 1 0 Port B - Data Bus 1 0 0 1 0 Port C - Data Bus 1 1 0 1 0 Control Word - Data Bus TABLE 2. OUTPUT OPERATION (WRITE) A1 A0 RD WR CS 0 0 1 0 0 Data Bus - Port A 0 1 1 0 0 Data Bus - Port B 1 0 1 0 0 Data Bus - Port C 1 1 1 0 0 Data Bus - Control Word TABLE 3. 7 A1 A0 RD WR CS X X X X 1 DISABLE FUNCTION Data Bus - 3-State HS-82C55ARH TABLE 3. A1 A0 RD WR CS X X 1 1 0 DISABLE FUNCTION Data Bus - 3-State CONTROL WORD GROUP B D7 D6 D5 D4 D3 D2 D1 D0 PORT C (LOWER) 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT MODE SELECTION 0 = MODE 0 1 = MODE 1 Mode 0 to monitor simple switch closings or display computational results, Group A could be programmed in Mode 1 to monitor a keyboard or tape recorder on an interrupt-driven basis. The mode definitions and possible mode combinations may seem confusing at first but after a cursory review of the complete device operation a simple, logical I/O approach will surface. The design of the HS-82C55ARH has taken into account things such as efficient PC board layout, control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic. Such design represents the maximum use of the available pins. GROUP A PORT C (UPPER) 1 = INPUT 0 = OUTPUT PORT A 1 = INPUT 0 = OUTPUT MODE SELECTION 00 = MODE 0 01 = MODE 1 1X = MODE 2 CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 BIT SET/RESET X X 1 = SET 0 = RESET X DON’T CARE BIT SELECT 0 0 0 0 MODE SET FLAG 1 = ACTIVE 1 1 0 0 2 0 1 0 3 1 1 0 4 0 0 1 5 1 0 1 6 0 1 1 7 1 B0 1 B1 1 B2 BIT SET/RESET FLAG 0 = ACTIVE FIGURE 11. MODE SET CONTROL WORD FORMAT FIGURE 12. BIT SET/RESET CONTROL WORD FORMAT Mode Selection There are three basic modes of operation that can be selected by the system software: Mode 0 - Basic Input/Output Mode 1 - Strobed Input/Output Mode 2 - Bidirectional Bus When the RESET input goes “high”, all ports will be set to the input mode with all 24 port lines held at the logic “one” level by internal bus hold devices. After reset, the HS-82C55ARH can remain in the input mode with no additional initialization required. This eliminates the need for pull-up or pull-down resistors in all CMOS designs. During the execution of the system program, any of the other modes may be selected using a single output instruction. This allows a single HS-82C55ARH to service a variety of peripheral devices with a simple software maintenance routine. Single Bit/Set/Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction. See Figure 12. This feature reduces software requirements in control-based applications. Interrupt Control Functions When the HS-82C55ARH is programmed to operate in Mode 1 or Mode 2, control signals are provided that can be used as interrupt request inputs to the CPU. The interrupt request signals, generated from Port C, can be inhibited or enable by setting or resetting the associated INTE flip-flop, using the Bit Set/Reset function of Port C. This function allows the programmer to enable or disable a CPU interrupt by a specific I/O device without affecting any other device in the interrupt structure. INTE Flip-Flop Definition: The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions. All of the output registers, including the status register, will be reset whenever the mode is changed. Modes may be combined so that their functional definition can be “tailored” to almost any I/O structure. For instance: Group B can be programmed in 8 (BIT-SET) - INTE is SET - Interrupt enable. (BIT-RESET) - INTE is RESET - Interrupt disable. NOTE: All mask flip-flops are automatically reset during mode selection and device Reset. HS-82C55ARH Operating Modes Mode 0 Basic Functional Definitions: Mode 0 (Basic Input/Output) • Two 8-bit ports and two 4-bit ports This functional configuration provides simple input and output operations for each of the three ports. No handshaking it required, data is simply written to or read from a specific port. • Any port can be input or output • Outputs are latched • Inputs are not latched • 16 different Input/Output configurations possible TRLRH RD TRHPX TPVRL INPUT TAVRL TRHAX CS, A1, A0 D7 - D0 TRLDV TRHDX FIGURE 13. MODE 0 (BASIC INPUT) TWLWH WR TWHDX TDVWH D7 - D0 TAVWL TWHAX CS, A1, A0 OUTPUT TWHPV FIGURE 14. MODE 0 (BASIC OUTPUT) 9 HS-82C55ARH Mode 0 Port Definition A B GROUP A GROUP B D4 D3 D1 D0 PORT A PORT C (UPPER) NO. PORT B PORT C (LOWER) 0 0 0 0 Output Output 0 Output Output 0 0 0 1 Output Output 1 Output Input 0 0 1 0 Output Output 2 Input Output 0 0 1 1 Output Output 3 Input Input 0 1 0 0 Output Input 4 Output Output 0 1 0 1 Output Input 5 Output Input 0 1 1 0 Output Input 6 Input Output 0 1 1 1 Output Input 7 Input Input 1 0 0 0 Input Output 8 Output Output 1 0 0 1 Input Output 9 Output Input 1 0 1 0 Input Output 10 Input Output 1 0 1 1 Input Output 11 Input Input 1 1 0 0 Input Input 12 Output Output 1 1 0 1 Input Input 13 Output Input 1 1 1 0 Input Input 14 Input Output 1 1 1 1 Input Input 15 Input Input Mode 0 Configurations CONTROL WORD #0 CONTROL WORD #1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 8 A 4 C D7 - D0 B 8 PA7 - PA0 4 8 A 4 PC7 - PC4 C D7 - D0 PC3 - PC0 PB7 - PB0 B CONTROL WORD #2 0 0 0 0 0 1 8 PC7 - PC4 PC3 - PC0 PB7 - PB0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 0 0 0 1 1 8 A C B 10 8 PA7 - PA0 4 D7 - D0 4 CONTROL WORD #3 D7 D6 D5 D4 D3 D2 D1 D0 1 PA7 - PA0 4 8 A 4 PC7 - PC4 D7 - D0 C PC3 - PC0 PB7 - PB0 PA7 - PA0 B 4 8 PC7 - PC4 PC3 - PC0 PB7 - PB0 HS-82C55ARH Mode 0 Configurations (Continued) CONTROL WORD #4 CONTROL WORD #5 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 8 A 4 C D7 - D0 B 8 PA7 - PA0 4 8 A 4 PC7 - PC4 C D7 - D0 PC3 - PC0 PB7 - PB0 B CONTROL WORD #6 0 0 0 1 0 1 1 0 0 0 1 0 1 C B 8 PA7 - PA0 4 4 8 A C D7 - D0 PC3 - PC0 PB7 - PB0 B 1 0 0 0 1 0 0 1 0 0 0 C B 4 8 A C D7 - D0 PC3 - PC0 PB7 - PB0 B 0 0 1 8 PC3 - PC0 PB7 - PB0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 1 0 0 1 1 8 A C B 11 8 PA7 - PA0 4 D7 - D0 4 PC7 - PC4 CONTROL WORD #11 D7 D6 D5 D4 D3 D2 D1 D0 1 PA7 - PA0 4 PC7 - PC4 CONTROL WORD #10 0 PB7 - PB0 8 PA7 - PA0 4 0 PC3 - PC0 1 8 A 1 8 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 - D0 4 PC7 - PC4 CONTROL WORD #9 D7 D6 D5 D4 D3 D2 D1 D0 0 PA7 - PA0 4 PC7 - PC4 CONTROL WORD #8 0 PB7 - PB0 1 8 A 1 8 PC3 - PC0 D7 D6 D5 D4 D3 D2 D1 D0 0 D7 - D0 4 PC7 - PC4 CONTROL WORD #7 D7 D6 D5 D4 D3 D2 D1 D0 1 PA7 - PA0 4 8 A 4 PC7 - PC4 D7 - D0 C PC3 - PC0 PB7 - PB0 PA7 - PA0 B 4 8 PC7 - PC4 PC3 - PC0 PB7 - PB0 HS-82C55ARH Mode 0 Configurations (Continued) CONTROL WORD #12 CONTROL WORD #13 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 8 A 4 C D7 - D0 B 8 PA7 - PA0 4 8 A PC7 - PC4 C D7 - D0 PB7 - PB0 0 1 1 0 1 8 B CONTROL WORD #14 0 4 PC3 - PC0 PC3 - PC0 PB7 - PB0 D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 0 1 1 0 1 1 8 A C B 8 PA7 - PA0 4 D7 - D0 PC7 - PC4 CONTROL WORD #15 D7 D6 D5 D4 D3 D2 D1 D0 1 PA7 - PA0 4 4 8 A PA7 - PA0 4 PC7 - PC4 C D7 - D0 4 PC3 - PC0 PB7 - PB0 Operating Modes 8 B PC7 - PC4 PC3 - PC0 PB7 - PB0 INTR (Interrupt Request) Mode 1 (Strobed Input/Output) This functional configuration provides a means for transferring I/O data to or from a specified port in conjunction with strobes or “handshaking” signals. In Mode 1, Port A and Port B use the lines on Port C to generate or accept these “handshaking” signals. Mode 1 Basic Functional Definitions: • Two Groups (Group A and Group B) • Each group contains one 8-bit port and one 4-bit control/data port. A “high” on this output can be used to interrupt the CPU when an input device is requesting service. INTR is set by the rising edge of STB and reset by the falling edge of RD. This procedure allows an input device to request service from the CPU by simply strobing its data into the port. INTE A Controlled by Bit Set/Reset of PC4. INTE B Controlled by Bit Set/Reset of PC2. MODE 1 (PORT A) CONTROL WORD MODE 1 (PORT B) CONTROL WORD • The 8-bit data port can be either input or output. Both inputs and outputs are latched. D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 • The 4-bit port is used for control and status of the 8-bit port. PC6, 7 1 = INPUT 0 = OUTPUT 1 Input Control Signal Definition 0 1 1 1/0 1 PA7 - PA0 STB (Strobe Input) INTE A A “low” on this input loads data into the input latch. INTE B STB A IBF A PC5 IBF (Input Buffer Full F/F) A “high” on this output indicates that the data has been loaded into the input latch; in essence, an acknowledgment. IBF is set by STB input being low and is reset by the rising edge of the RD input. PB7 - PB0 8 PC4 1 RD PC1 8 STB B IBF B RD INTR A PC3 2 PC6, 7 I/O FIGURE 15. MODE 1 INPUT 12 PC2 1 PC0 INTR B HS-82C55ARH INTE A TSLSH Controlled by Bit Set/Reset of PC6. STB INTE B IBF TRLNL Controlled by Bit Set/Reset of PC2. TSLIH TRHIL INTR TWHOL TSHNH WR RD TKHOL OBF TSHPX INPUT FROM PERIPHERAL TPVSH INTR TWLNL FIGURE 16. MODE 1 (STROBED INPUT) ACK TKLKH Output Control Signal Definition TKHNH OUTPUT OBF (Output Buffer Full F/F) The OBF output will go “low” to indicate that the CPU has written data out to the specified port. This does not mean valid data is sent out of the port at this time since OBF can go true before data is available. Data is guaranteed valid at the rising edge of OBF. See Note 1. The OBF F/F will be set by the rising edge of the WR input and reset by ACK input being low. ACK (Acknowledge Input) A “low” on this input informs the HS-82C55ARH that the data from Port A or Port B is ready to be accepted. In essence, a response from the peripheral device indicating that it is ready to accept data. See Note 14. INTR (Interrupt Request) A “high” on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU. INTR is set by the rising edge of ACK and reset by the falling edge of WR. MODE 1 (PORT A) MODE 1 (PORT B) CONTROL WORD CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1/0 1 1 TWHPV FIGURE 18. MODE 1 (STROBED OUTPUT) NOTE: 14. To strobe data into the peripheral device, the user must operate the strobe line in a hand shaking mode. The user needs to send OBF to the peripheral device, generate an ACK from the peripheral device and then latch data into the peripheral device on the rising edge of OBF. Combinations of Mode 1: Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed I/O applications. PORT A (STROBED INPUT) PORT B (STROBED OUTPUT) CONTROL WORD CONTROL WORD D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 1 1/0 1 RD 0 OBF A ACK A PC7 INTE A PB7 - PB0 PC6 PC1 INTE B WR PC2 PC0 0 1 0 1/0 1 PA7 - PA0 8 WR PA7 - PA0 8 INTR B WR PC7 OBF A PC5 IBF A PC6 ACK A INTR A PC3 PB7 - PB0 I/O 8 RD PB7 - PB0 8 PC1 OBF B PC2 STB B PC2 ACK B PC1 IBF B PC0 INTR B PC0 INTR B FIGURE 19. COMBINATIONS OF MODE 1 13 I/O PC4, 5 I/O FIGURE 17. MODE 1 OUTPUT INTR A 2 2 PC4, 5 8 STB A PC6, 7 OBF B ACK B 1 PC4 2 WR INTR A PC3 1 PC4, 5 1 = INPUT 0 = OUTPUT PC3 8 0 PC6, 7 1 = INPUT 0 = OUTPUT PC4, 5 1 = INPUT 0 = OUTPUT PA7 - PA0 PORT A (STROBED OUTPUT) PORT B (STROBED INPUT) HS-82C55ARH Operating Modes CONTROL WORD MODE 2 (Strobed Bidirectional Bus I/O) The functional configuration provides a means for communicating with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving data (bidirectional bus I/O). “Handshaking” signals are provided to maintain proper bus flow discipline similar to MODE 1. Interrupt generation and enable/disable functions are also available. D7 D6 D5 D4 D3 D2 D1 D0 1 0 1/0 1/0 1/0 PC2 - PC0 1 = INPUT 0 = OUTPUT PORT B 1 = INPUT 0 = OUTPUT GROUP B MODE 0 = MODE 0 1 = MODE 1 Mode 2 Basic Functional Definitions: FIGURE 20. MODE CONTROL WORD • Used in Group A only. • One 8-bit, bidirectional bus port (Port A) and a 5-bit control port (Port C). PC3 • Both inputs and outputs are latched. • The 5-bit control port (Port C) is used for control and status for the 8-bit, bidirectional bus port (Port A). 8 PA7- PA0 PC7 OBF A INTE 1 PC6 ACK A INTE 2 PC7 STB A PC6 IBF A Bidirectional Bus I/O Control Signal Definition INTR (INTERRUPT REQUEST) A high on this output can be used to interrupt the CPU for both input or output operations. INTR will be set either by the rising edge of ACK (INTE1 = 1) or the rising edge of STB (INTE2 = 1). INTR will be reset by the falling edge of WR (if previously set by the rising edge or ACK), the falling edge of RD (if previously set by the rising edge of STB), or the falling edge of WR when immediately following a low RD pulse or the falling edge of RD when immediately following a low WR pulse (if previously set by the rising edges of both ACK and STB). INTR A WR RD 3 PC2- PC0 I/O FIGURE 21. MODE 2 (BIDIRECTIONAL) DATA FROM CPU TO HS-82C55ARH Output Operations WR OBF (OUTPUT BUFFER FULL) The OBF output will go “low” to indicate that the CPU has written data out to Port A. TKHOL OBF TWHOL INTR TKLKH ACK (ACKNOWLEDGE) A “low” on this input enables the three-state output buffer of Port A to send out the data. Otherwise, the output buffer will be in the high impedance state. ACK INTE 1 (THE INTE FLIP-FLOP ASSOCIATED WITH OBF) IBF TSLSH STB TSLIH Controlled by Bit Set/Reset of PC6. TKHPX TKLPV Input Operations TPVSH PERIPHERAL BUS STB (STROBE INPUT) TSHPX A “low” on this input loads data into the input latch. IBF (INPUT BUFFER FULL F/F) A “high” on this output indicates that data has been loaded into the input latch. INTE 2 (THE INTE FLIP-FLOP ASSOCIATED WITH IBF) Controlled by Bit Set/Reset of PC4. 14 RD DATA FROM PERIPHERAL TO HS-82C55ARH DATA FROM HS-82C55ARH TO PERIPHERAL TRHIL DATA FROM HS-82C55ARH TO CPU NOTE: Any sequence where WR occurs before ACK and STB occurs before RD is permissible. FIGURE 22. MODE 2 (BIDIRECTIONAL) HS-82C55ARH MODE DEFINITION SUMMARY MODE 0 MODE 1 MODE 2 IN OUT IN OUT PA0 AP1 PA2 PA3 PA4 PA5 PA6 PA7 In In In In In In In In Out Out Out Out Out Out Out Out In In In In In In In In Out Out Out Out Out Out Out Out PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 In In In In In In In In Out Out Out Out Out Out Out Out In In In In In In In In Out Out Out Out Out Out Out Out - PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 In In In In In In In In Out Out Out Out Out Out Out Out INTR B IBF B STB B INTR A STB A IBF A I/O I/O INTR B OBF B ACK B INTR A I/O I/O ACK A OBF A I/O I/O I/O INTR A STB A IBF A ACK A OBF A Special Mode Combination Considerations There are several combinations of modes possible. For any combination, some or all of Port C lines are used for control or status. The remaining bits are either inputs or outputs as defined by a “Set Mode” command. During a read of Port C, the state of all the Port C lines, except the ACK and STB lines, will be placed on the data bus. In place of the ACK and STB line states, flag status will appear on the data bus in the PC2, PC4, and PC6 bit positions as illustrated by Figure 25. Through a “Write Port C” command, only the Port C pins programmed as outputs in a Mode 0 group can be written. No other pins can be affected by a “Write Port C” command, nor can the interrupt enable flags be accessed. To write to any Port C output programmed as an output in a Mode 1 group or to change an interrupt enable flag, the “Set/Reset Port C Bit” command must be used. With a “Set/Reset Port C Bit” command, any Port C line programmed as an output (including IBF and OBF) can be written, or an interrupt enable flag can be either set or reset. Port C lines programmed as inputs, including ACK and STB lines, associated with Port C fare not affected by a “Set/ Reset Port C Bit” command. Writing to the corresponding Port C bit positions of the ACK and STB lines with the “Set/ Reset Port C Bit” command will affect the Group A and Group B interrupt enable flags, as illustrated in Figure 25. 15 GROUP A ONLY Mode 0 or Mode 1 Only INPUT CONFIGURATION D4 D3 D2 D7 D6 D5 I/O I/O IBFA INTEA INTRA INTEB GROUP A D7 OBFA INTEA I/O D0 INTRB GROUP B OUTPUT CONFIGURATION D5 D4 D3 D2 D6 D1 IBFB I/O INTRA D1 D0 INTEB OBFB INTRB GROUP A GROUP B FIGURE 23. MODE 1 STATUS WORD FORMAT D7 D6 D5 D4 D3 D2 D1 D0 OBFA INTE1 IBFA INTE2 INTRA X X X GROUP A GROUP B NOTE: (Defined by Mode 0 or Mode 1 Selection) FIGURE 24. MODE 2 STATUS WORD FORMAT HS-82C55ARH Current Drive Capability Any output on Port A, B or C can sink or source 2.5mA. This feature allows the 82C55A to directly drive Darlington type drivers and high-voltage displays that require such sink or source current. Reading Port C Status (Figures 23 and 24) In Mode 0, Port C transfers data to or from the peripheral device. When the 82C55A is programmed to function in Modes 1 or 2, Port C generates or accepts “hand shaking” signals with the peripheral device. Reading the contents of Port C allows the programmer to test or verify the “status” of each peripheral device and change the program flow accordingly. 16 There is no special instruction to read the status information from Port C. A normal read operation of Port C is executed to perform this function. INTERRUPT ENABLE FLAG POSITION ALTERNATE PORT C PIN SIGNAL (MODE) INTE B PC2 ACKB (Output Mode 1) or STBB (Input Mode 1) INTE A2 PC4 STBA (Input Mode 1 or Mode 2) INTE A1 PC6 ACKA (Output Mode 1 or Mode 2) FIGURE 25. INTERRUPT ENABLE FLAGS IN MODES 1 AND 2 HS-82C55ARH Die Characteristics DIE DIMENSIONS: Top Metallization: 3420µm x 4350µm x 485µm ±25µm Type: Al/Si Thickness: 11kÅ ±2kÅ INTERFACE MATERIALS: ADDITIONAL INFORMATION: Glassivation: Type: SiO2 Thickness: 8kÅ ±1kÅ Worst Case Current Density: 7.7 x 104 A/cm2 Metallization Mask Layout (6) CS (7) VSS (8) A1 (9) A0 (10) PC7 (11) PC6 (12) PC5 (13) PC4 (14) PC0 (15) PC1 HS-82C55ARH PB3 (21) (40) PA4 PB4 (22) (39) PA5 PB5 (23) (38) PA6 PB6 (24) (37) PA7 PB7 (25) (36) WR RESET (35) (1) PA3 D0 (34) PB2 (20) D1 (33) (2) PA2 D2 (32) PB1 (19) D3 (31) (3) PA1 D4 (30) PB0 (18) D5 (29) (4) PA0 D6 (28) PC3 (17) D7 (27) (5) RD VDD (26) PC2 (16) All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 17 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil Ltd. 8F-2, 96, Sec. 1, Chien-kuo North, Taipei, Taiwan 104 Republic of China TEL: 886-2-2515-8508 FAX: 886-2-2515-8369