DATASHEET

REVISIONS
LTR
DESCRIPTION
DATE (YR-MO-DA)
APPROVED
A
Changes to conditions in table I. Addition of test condition 2 in figure 4.
Editorial changes throughout.
96-11-13
Thomas M. Hess
B
Update boilerplate to MIL-PRF-38535 requirements and update the radiation
hardness assurance boilerplate paragraphs. - LTG
08-01-23
Thomas M. Hess
REV
SHEET
REV
B
B
B
B
B
B
B
B
SHEET
15
16
17
18
19
20
21
22
REV STATUS
REV
B
B
B
B
B
B
B
B
B
B
B
B
B
B
OF SHEETS
SHEET
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PMIC N/A
PREPARED BY
Thomas M. Hess
STANDARD
MICROCIRCUIT
DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
CHECKED BY
Thomas M. Hess
APPROVED BY
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
Monica L. Poelking
DRAWING APPROVAL DATE
MICROCIRCUIT, DIGITAL, RADIATION
HARDENED, CMOS, PROGRAMMABLE
PERIPHERAL INTERFACE, MONOLITHIC
SILICON
95-12-28
AMSC N/A
REVISION LEVEL
B
SIZE
CAGE CODE
A
67268
SHEET
DSCC FORM 2233
APR 97
1 OF
5962-95819
22
5962-E148-08
1. SCOPE
1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)
and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or
Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN.
1.2 PIN. The PIN is as shown in the following example:
5962
R
95819
Federal
stock class
designator
\
RHA
designator
(see 1.2.1)
01
V
Q
C
Device
type
(see 1.2.2)
Device
class
designator
(see 1.2.3)
Case
outline
(see 1.2.4)
Lead
finish
(see 1.2.5)
/
\/
Drawing number
1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are
marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A
specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.
1.2.2 Device type(s). The device type(s) identify the circuit function as follows:
Device type
Generic number
01
Circuit function
82C55ARH
Radiation hardened, CMOS, programmable
peripheral interface
1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as
follows:
Device class
Device requirements documentation
M
Vendor self-certification to the requirements for MIL-STD-883 compliant, nonJAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A
Q or V
Certification and qualification to MIL-PRF-38535
1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
Q
Descriptive designator
CDIP2-T40
Terminals
Package style
40
Dual-in-line
1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535,
appendix A for device class M.
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REVISION LEVEL
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SHEET
2
1.3 Absolute maximum ratings. 1/
Supply voltage (VDD) ..................................................................................................
Input or output voltage range .....................................................................................
Storage temperature range (TSTG)..............................................................................
Junction temperature (TJ)...........................................................................................
Thermal resistance, junction-to-case (θJC)
Case X....................................................................................................................
Thermal resistance, junction-to-ambient (θJA)
Case X....................................................................................................................
Maximum package power dissipation at TA = +125°C (PD) 2/
Case X....................................................................................................................
Maximum lead temperature (soldering, 10 seconds)..................................................
+7.0 V dc
VSS -0.3 V dc to VDD +0.3 V dc
-65°C to +150°C
+175°C
+6°C/W
+40°C/W
1.25 W
+300°C
1.4 Recommended operating conditions.
Operating supply voltage range (VDD) ........................................................................
Operating temperature range (TA)..............................................................................
Input low voltage range (VIL) ......................................................................................
Input high voltage range (VIH).....................................................................................
4.5 V dc to +5.5 V dc
-55°C to +125°C
0 V dc to +0.8 V dc
VDD -1.5 V dc to VDD
1.5 Radiation features.
Maximum total dose available (Dose rate = 50 – 300 rads(Si)/sec) ...........................
Transient upset ..........................................................................................................
Single event upset (SEU) ...........................................................................................
Single event latchup (SEL).........................................................................................
> 100K Rads(Si)
> 108 Rads(Si)/sec 3/
50 MeV/(mg/cm2) 3/
50 MeV/(mg/cm2) 3/
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 MIL-STD-1835 -
Test Method Standard Microcircuits.
Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 MIL-HDBK-780 -
List of Standard Microcircuit Drawings.
Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
________
1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the
maximum levels may degrade performance and affect reliability.
2/ If device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is based on θJA)
at a rate of 25.0 mW/°C .
3/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the
purchase order or contract.
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REVISION LEVEL
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2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein.
Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation or contract.
AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM)
ASTM F1192- Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation
of Semiconductor Devices.
(Copies of this document is available online at http://www.astm.org/ or from ASTM International, P. O. Box C700,
100 Barr Harbor Drive, West Conshohocken, PA 19428-2959).
2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of
this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with
MIL-PRF-38535 and as specified herein or as modified in the device manufacturer's Quality Management (QM) plan. The
modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for
device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified
herein.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in
MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.
3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.
3.2.3 Block diagram. The block diagram shall be as specified on figure 2.
3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 3.
3.2.5 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4.
3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the
electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full
ambient operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical
tests for each subgroup are defined in table IA.
3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be
marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer
has the option of not marking the "5962-" on the device. For RHA product using this option, the RHA designator shall still be
marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be
in accordance with MIL-PRF-38535, appendix A.
3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a "QML" or "Q" as required in
MIL-PRF-38535. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, appendix A.
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3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535
listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of
compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103
(see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this
drawing shall affirm that the manufacturer's product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and
herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.
3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for
device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing.
3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product
(see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing.
3.9 Verification and review for device class M. For device class M, DSCC, DSCC's agent, and the acquiring activity retain the
option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made
available onshore at the option of the reviewer.
3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in
microcircuit group number 105 (see MIL-PRF-38535, appendix A).
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TABLE IA. Electrical performance characteristics.
Test
Symbol
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
TTL output high voltage
VOH1
VDD = 4.5 V, IO = -2.5 mA
VIN = 0 V, 4.5 V
1, 2, 3
All
3.0
V
CMOS output high voltage
VOH2
VDD = 4.5 V, IO = -100 μA
VIN = 0 V, 4.5 V
1, 2, 3
All
VDD-0.4
V
Output low voltage
VOL
VDD = 4.5 V, IO = 2.5 mA
VIN = 0 V, 4.5 V
1, 2, 3
All
Input leakage current
IIL,
IIH
VDD = 5.5 V
VIN = 0 V, 4.5 V
1, 2, 3
All
Output leakage current
IOZL,
IOZH
VDD = 5.5 V
VIN = 0 V, 4.5 V
1, 2, 3
Input current bus hold high
IBHH
VDD = 4.5 V or 5.5 V 2/
VIN = 3.0 V, Ports A, B, C
Input current bus hold low
IBHL
Standby power supply
current
0.4
V
-1.0
1.0
μA
All
-10
10
μA
1, 2, 3
All
-800
-60
μA
VDD = 4.5 V or 5.5 V 3/
VIN = 1.0 V, Port A
1, 2, 3
All
60
800
μA
IDDSB
VDD = 5.5 V, IO = 0 mA
VIN = GND or VDD
1, 2, 3
All
20
μA
Darlington drive voltage
VDAR
1, 2, 3
All
Input capacitance
CIN
4
All
10
pF
I/O capacitance
CI/O
VDD = 4.5 V, IO = -2.0 mA
VIN = GND or VDD
VDD = Open, f = 1 MHz
All measurements referenced
to device ground
See 4.4.1c
VDD = Open, f = 1 MHz
All measurements referenced
to device ground
See 4.4.1c
4
All
20
pF
Functional tests
VDD = 4.5 V or 5.5 V
VIN = GND or VDD, f = 1 MHz
See 4.4.1b
7, 8
All
Noise immunity functional
test
VDD = 5.5 V, VIN = GND or
VDD = 1.5 V and
VDD = 4.5 V
VIN = 0.8 V or VDD
See 4.4.1b 4/
7, 8
All
3.9
V
See footnotes at end of table.
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TABLE IA. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
READ
Address stable before RD
tAVRL
Address stable after RD
tRHAX
RD pulse width
tRLRH
Data valid from RD
tRLDV
VDD = 4.5 V, 5.5 V
See figure 4
Test Condition 1
9, 10, 11
All
0
ns
9, 10, 11
All
0
ns
9, 10, 11
All
250
ns
9, 10, 11
All
200
ns
9, 10, 11
All
10
ns
Data float after RD
tRHDX
VDD = 4.5 V, 5.5 V
See figure 4
Test Condition 2
Time between RDs and/or
WRs
tRWHRWL
VDD = 4.5 V, 5.5 V
See figure 4
Test Condition 1
9, 10, 11
All
300
ns
Address stable before WR
tAVWL
VDD = 4.5 V, 5.5 V
See figure 4
Test Condition 1
9, 10, 11
All
0
ns
Address stable after WR
tWHAX
VDD = 4.5 V, 5.5 V
See figure 4, Ports A and B
Test Condition 1
9, 10, 11
All
20
ns
VDD = 4.5 V, 5.5 V
See figure 4, Port C
Test Condition 1
9, 10, 11
All
100
ns
WRITE
WR pulse width
tWLWH
VDD = 4.5 V, 5.5 V
See figure 4
Test Condition 1
9, 10, 11
All
100
ns
Data valid to WR high
tDVWH
VDD = 4.5 V, 5.5 V
See figure 4
Test Condition 1
9, 10, 11
All
100
ns
Data valid after WR high
tWHDX
VDD = 4.5 V, 5.5 V
See figure 4, Ports A and B
Test Condition 1
9, 10, 11
All
30
ns
VDD = 4.5 V, 5.5 V
See figure 4, Port C
Test Condition 1
9, 10, 11
All
100
ns
See footnotes at end of table.
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TABLE IA. Electrical performance characteristics – Continued.
Test
Symbol
Conditions 1/
-55°C ≤ TA ≤ +125°C
unless otherwise specified
Group A
subgroups
Device
type
Limits
Min
Unit
Max
OTHER TIMINGS
WR = 1 to output
tWHPV
Peripheral data before RD
tPVRL
Peripheral data after RD
VDD = 4.5 V, 5.5 V
See figure 4
Test Condition 1
9, 10, 11
All
350
ns
9, 10, 11
All
0
ns
tRHPX
9, 10, 11
All
0
ns
ACK pulse width
tKLKH
9, 10, 11
All
200
ns
STB pulse width
tSLSH
9, 10, 11
All
100
ns
Peripheral data before
tPVSH
9, 10, 11
All
20
ns
tSHPX
9, 10, 11
All
50
ns
STB high
Peripheral data after
STB high
ACK = 0 to output
tKLPV
9, 10, 11
All
175
ns
9, 10, 11
All
9, 10, 11
All
150
ns
ACK = 1 to output float
tKHPZ
VDD = 4.5 V, 5.5 V
See figure 4
Test Condition 2
WR = 1 to OBF = 0
tWHOL
VDD = 4.5 V, 5.5 V
See figure 4
Test Condition 1
ACK = 0 to OBF =1
tKLOH
9, 10, 11
All
150
ns
STB = 0 to IBF = 1
tSLIH
9, 10, 11
All
150
ns
RD = 1 to IBF = 0
tRHIL
9, 10, 11
All
150
ns
RD = 0 to INTR = 1
tRLNL
9, 10, 11
All
200
ns
STB = 1 to INTR = 1
tSHNH
9, 10, 11
All
150
ns
ACK = to INTR =1
tKHNH
9, 10, 11
All
150
ns
WR = 0 to INTR = 0
tWLNL
9, 10, 11
All
200
ns
RESET pulse width 5/
tRSHRSL
9, 10, 11
All
9, 10, 11
All
75
ns
9, 10, 11
All
250
ns
Data float after RD 6/
tRHDX
ACK = 1 to output float 6/
tKHPZ
VDD = 4.5 V, 5.5 V
See figure 4
Test Condition 2
10
ns
500
ns
1/
RHA devices supplied to this drawing have been characterized through all levels M, D, P, L and R of irradiation.
However, this device is only tested at the 'R' level. Pre and Post irradiation values are identical unless otherwise
specified in table IA. When performing post irradiation electrical measurements for any RHA level, TA = +25°C.
2/
IBHH should be measured after raising VIN and then lowering to 3.0 V.
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TABLE IA. Electrical performance characteristics – Continued.
3/ IBHL should be measured after lowering VIN to VSS and then raising to 0.8 V.
4/ For VIH(VDD = 5.5 V)and VIL (VDD = 4.5 V) each of the following groups is tested separately with all other inputs
using VIH = 2.5 V, VIL = 0.4: PA, PB, PC control pins (pins 5, 6, 8, 9, 35, 36).
5/ Period of initial RESET pulse after power-on must be least 50 μs. Subsequent RESET pulses may be 500 ns minimum.
6/ These parameters, are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design changes which would affect these characteristics.
TABLE IB. SEP test limits. 1/ 2/
Device
type
TA =
Temperature
±10°C
Bias for
latch-up test
VDD = 5.5 V
no latch-up
LET = 3/ 4/
VDD = 4.5 V
Effective LET
no upsets
[MeV/(mg/cm2)]
01
1/
2/
3/
4/
+25°C
≥ 50
For SEP test conditions, see 4.4.4.3 herein.
Technology characterization and model verification supplemented by in-line data may be used
in lieu of end-of-line testing. Test plan must be approved by TRB and qualifying activity.
Worst case temperature is TA ≥ +125°C.
Tested to an LET of ≥ 50 MeV/(mg/cm2), with no latch-up (SEL).
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Device type
01
Case outline
Q
Terminal
number
Terminal
symbol
Terminal
number
Terminal
symbol
1
PA3
21
PB3
2
PA2
22
PB4
3
PA1
23
PB5
4
PA0
24
PB6
5
RD
25
PB7
6
CS
26
VDD
7
GND
27
D7
8
A1
28
D6
9
A0
29
D5
10
PC7
30
D4
11
PC6
31
D3
12
PC5
32
D2
13
PC4
33
D1
14
PC0
34
D0
15
PC1
35
RESET
16
PC2
36
WR
17
PC3
37
PA7
18
PB0
38
PA6
19
PB1
39
PA5
20
PB2
40
PA4
FIGURE 1. Terminal connections.
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FIGURE 2. Block diagram.
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Pin
Symbol
Pin
Symbol
1
VDD
21
VDD
2
VDD
22
VDD
3
VDD
23
VDD
4
VDD
24
VDD
5
VDD
25
VDD
6
VDD
26
VDD
7
GND
27
VDD
8
VDD
28
VDD
9
VDD
29
VDD
10
VDD
30
VDD
11
VDD
31
VDD
12
VDD
32
VDD
13
VDD
33
VDD
14
VDD
34
VDD
15
VDD
35
VDD
16
VDD
36
VDD
17
VDD
37
VDD
18
VDD
38
VDD
19
VDD
39
VDD
20
VDD
40
VDD
NOTE: VDD = 5.5 V
FIGURE 3. Radiation exposure circuit.
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NOTE:
1. Any sequence where WR occurs before ACK and STB occurs before RD is permissible.
FIGURE 4. Switching waveforms and test circuit.
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FIGURE 4. Switching waveforms and test circuit - Continued.
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NOTE:
1. To strobe data into the peripheral device the user must operate the strobe line in a hand shaking mode. The users needs to
send OBF to the peripheral device, generate an ACK from the peripheral device and then latch data into the peripheral device
on the rising edge of OBF.
FIGURE 4. Switching waveforms and test circuit - Continued.
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FIGURE 4. Switching waveforms and test circuit - Continued.
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SHEET
16
NOTE: Input rise and fall times are driven at 1 V/ns.
Test Conditions
V1
R1
R2
C1
1
1.7 v
523Ω
Open
150 pF
2
VDD
2000Ω
1690Ω
50 pF
FIGURE 4. Switching waveforms and test circuit - Continued.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95819
A
REVISION LEVEL
B
SHEET
17
4. VERIFICATION
4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with
MIL-PRF-38535 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan
shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in
accordance with MIL-PRF-38535, appendix A.
4.2 Screening. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted
on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in
accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection.
4.2.1 Additional criteria for device class M.
a.
Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition A, B, C or D. The test circuit shall be maintained by the manufacturer under document revision
level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015.
(2) TA = +125°C, minimum.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
4.2.2 Additional criteria for device classes Q and V.
a.
The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the
device manufacturer's QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under
document revision level control of the device manufacturer's Technology Review Board (TRB) in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1015 of MIL-STD-883.
b.
Interim and final electrical test parameters shall be as specified in table IIA herein.
c.
Additional screening for device class V beyond the requirements of device class Q shall be as specified in
MIL-PRF-38535, appendix B.
4.3 Qualification inspection for device classes Q and V. Qualification inspection for device classes Q and V shall be in
accordance with MIL-PRF-38535. Inspections to be performed shall be those specified in MIL-PRF-38535 and herein for groups
A, B, C, D, and E inspections (see 4.4.1 through 4.4.4).
4.4 Conformance inspection. Technology conformance inspection for classes Q and V shall be in accordance with
MIL-PRF-38535 including groups A, B, C, D, and E inspections and as specified herein. Quality conformance inspection for
device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed
for device class M shall be those specified in method 5005 of MIL-STD-883 and herein for groups A, B, C, D, and E inspections
(see 4.4.1 through 4.4.4).
4.4.1 Group A inspection.
a.
Tests shall be as specified in table IIA herein.
b.
For device class M, subgroups 7 and 8 tests shall be sufficient to verify the functionality of the device. For device
classes Q and V, subgroups 7 and 8 shall include verifying the functionality of the device.
c.
Subgroup 4 (CIN and CI/O measurements) shall be measured only for the initial test and after process or design changes
which may affect capacitance. A minimum sample size of 5 devices with zero rejects shall be required.
4.4.2 Group C inspection. The group C inspection end-point electrical parameters shall be as specified in table IIA herein.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95819
A
REVISION LEVEL
B
SHEET
18
TABLE IIA. Electrical test requirements.
Test requirements
Interim electrical
parameters (see 4.2)
Final electrical
parameters (see 4.2)
Group A test
requirements (see 4.4)
Group C end-point electrical
parameters (see 4.4)
Group D end-point electrical
parameters (see 4.4)
Group E end-point electrical
parameters (see 4.4)
Subgroups
(in accordance with
MIL-PRF-38535, table III)
Subgroups
(in accordance with
MIL-STD-883,
method 5005, table I)
Device
class M
1, 7, 9
Device
class Q
1, 7, 9
Device
class V
1, 7, 9
1/ 1, 2, 3, 7, 8, 9, 10,
11
1/ 1, 2, 3, 7,
8, 9, 10, 11
2/ 3/ 1, 2, 3,
7, 8, 9, 10, 11
1, 2, 3, 4, 7, 8, 9, 10,
11
1, 2, 3, 4, 7, 8,
9, 10, 11
1, 2, 3, 4, 7,
8, 9, 10, 11
1, 2, 3, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9,
10, 11
3/ 1, 2, 3, 7,
8, 9, 10, 11
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1, 7, 9
1/ PDA applies to subgroup 1.
2/ PDA applies to subgroups 1, 7 and deltas.
3/ Delta limits as specified in table IIB herein shall be required when specified and the delta values shall be
completed with reference to the zero hour electrical parameters.
TABLE IIB. Burn-in and operating life test, delta parameters (+25°C).
Symbol
Delta limits
Standby power supply current
ICCSB
±10 μA
Input leakage current
IIH, IIL
±200 nA
Low level output voltage
VOL
±80 mV
CMOS High level output voltage
VOH
±150 mV
Output leakage current
IOZL, IOZH
±2 μA
TTL output high voltage
VOH1
±600 mV
Parameter 1/
1/ These parameters shall be recorded before and after the required burn-in
and life test to determine delta limits.
4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STD-883:
a.
Test condition A, B, C or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
b.
TA = +125°C, minimum.
c.
Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95819
A
REVISION LEVEL
B
SHEET
19
4.4.2.2 Additional criteria for device classes Q and V. The steady-state life test duration, test condition and test temperature,
or approved alternatives shall be as specified in the device manufacturer's QM plan in accordance with MIL-PRF-38535. The
test circuit shall be maintained under document revision level control by the device manufacturer's TRB in accordance with
MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the
inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of
MIL-STD-883.
4.4.3 Group D inspection. The group D inspection end-point electrical parameters shall be as specified in table IIA herein.
4.4.4 Group E inspection. Group E inspection is required only for parts intended to be marked as radiation hardness assured
(see 3.5 herein).
a.
End-point electrical parameters shall be as specified in table IIA herein.
b.
For device classes Q and V, the devices or test vehicle shall be subjected to radiation hardness assured tests as
specified in MIL-PRF-38535 for the RHA level being tested. For device class M, the devices shall be subjected to
radiation hardness assured tests as specified in MIL-PRF-38535, appendix A for the RHA level being tested. All device
classes must meet the postirradiation end-point electrical parameter limits as defined in table IA at TA = +25°C ±5°C,
after exposure, to the subgroups specified in table IIA herein.
4.4.4.1 Total dose irradiation testing. Total dose irradiation testing shall be performed in accordance with MIL-STD-883
method 1019, condition A and as specified herein.
4.4.4.1.1 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level
greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall
be the pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and
after any design or process changes which may affect the RHA response of the device.
4.4.4.2 Dose rate upset testing. When required by the customer, dose rate upset testing shall be performed in accordance
with method 1021 of MIL-STD-883 and herein.
a. Transient dose rate upset testing shall be performed at initial qualification and after any design or process changes
which may effect the RHA performance of the devices. Test 10 devices with 0 defects unless otherwise specified.
b. Transient dose rate upset testing for class Q and V devices shall be performed as specified by a TRB approved
radiation hardness assurance plan and MIL-PRF-38535. Device parameters that influence upset immunity shall be
monitored at the wafer level in accordance with the wafer level hardness assurance plan and MIL-PRF-38535.
4.4.4.3 Single event phenomena (SEP). When specified in the purchase order or contract, SEP testing shall be performed on
class V devices. SEP testing shall be performed on the Standard Evaluation Circuit (SEC) or alternate SEP test vehicle as
approved by the qualifying activity at initial qualification and after any design or process changes which may affect the upset or
latchup characteristics. Test 4 devices with zero failures. ASTM F1192 may be used as a guideline when performing SEP
testing. The recommended test conditions for SEP are as follows:
a. The ion beam angle of incidence shall be between normal to the die surface and 60° to the normal, inclusive
(i.e. 0° ≤ angle ≤ 60°). No shadowing of the ion beam due to fixturing or package related effects is allowed.
b. The fluence shall be ≥ 100 errors or ≥ 107 ions/cm2.
c. The flux shall be between 102 and 105 ions/cm2/s. The cross-section shall be verified to be flux independent by
measuring the cross-section at two flux rates which differ by at least an order of magnitude.
d. The particle range shall be ≥ 20 microns in silicon.
e. The upset test temperature shall be +25°C. The latchup test temperature shall be at the maximum rated operating
temperature ±10°C.
f. Bias conditions shall be VDD = 4.5 V dc for the upset measurements and VDD = 5.5 V dc for the latchup measurements.
g. For SEP test limits, see table IB herein.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95819
A
REVISION LEVEL
B
SHEET
20
4.5 Methods of inspection. Methods of inspection shall be specified as follows:
4.5.1 Voltage and current. Unless otherwise specified, all voltages given are referenced to the microcircuit GND terminal.
Currents given are conventional current and positive when flowing into the referenced terminal.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535 for device classes
Q and V or MIL-PRF-38535, appendix A for device class M.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.1.1 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing.
6.1.2 Substitutability. Device class Q devices will replace device class M devices.
6.2 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.3 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic
devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544.
6.4 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.5 Abbreviations, symbols, and definitions. The abbreviations, symbols, and definitions used herein are defined in
MIL-PRF-38535 and MIL-HDBK-1331 and as follows:
Pin symbol
Type
PA0-7
I/O
Port A: General purpose I/O port. Data direction and mode is determined by the
contents of the control word.
PB0-7
I/O
Port B: General purpose I/O port. See port A.
PC0-3
I/O
Port C(Lower): Combination I/O port and control port associated with port B. See port A.
PC4-7
I/O
Port C (Upper): Combination I/O port and control port associated with Port A.
See port A.
D0-7
I/O
Bidirectional data bus: Three-state data bus enabled as an input when CS and WR are
low and as an output when CS and RD are low.
VDD
P
VDD: The +5 V power supply pin. A 0.1 μF capacitor between pins 26 and 7 is
recommended for decoupling.
GND
Description
Ground.
CS
I
Chip select: A "low" on this input pin enables the communication between the device and
the CPU.
RD
I
Read: A "low" on this input pin enables the device to send the data or status information
to the CPU on the data bus. In essence, it allows the CPU to "read from" the device.
WR
I
Write: A "low" on this input pin enables the CPU to write data or control words into the
device.
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
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A
REVISION LEVEL
B
SHEET
21
6.5 Abbreviations, symbols, and definitions – Continued.
Pin symbol
Type
A0 and A1
I
Port select 0 and Port select 1: These input signals, in conjunction with the RD and WR
inputs, control the selection of one of the three ports or the control word registers. They
are normally connected to the least significant bits of the address bus (A0 and A1).
RESET
I
Reset: A "high" on this input clears the control register and all ports (A,B,C) are set to
the input mode. "Bus hold" devices internal to the device will hold the I/O port inputs to a
logic "1" state with a maximum hold current of 400 μA.
Description
6.6 Sources of supply.
6.6.1 Sources of supply for device classes Q and V. Sources of supply for device classes Q and V are listed in QML-38535.
The vendors listed in QML-38535 have submitted a certificate of compliance (see 3.6 herein) to DSCC-VA and have agreed to
this drawing.
6.6.2 Approved sources of supply for device class M. Approved sources of supply for class M are listed in MIL-HDBK-103.
The vendors listed in MIL-HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been
submitted to and accepted by DSCC-VA.
6.7 Additional information. When specified in the purchase order or contract, a copy of the following additional data shall be
supplied.
a. RHA upset levels.
b. Test conditions (SEP).
c. Number of upsets (SEP).
d. Number of transients (SEP).
e. Occurrence of latchup (SEP).
STANDARD
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
DSCC FORM 2234
APR 97
SIZE
5962-95819
A
REVISION LEVEL
B
SHEET
22
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 08-01-23
Approved sources of supply for SMD 5962-95819 are listed below for immediate acquisition information only and shall
be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised
to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate
of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
5962R9581901QQC
5962R9581901VQC
Vendor
CAGE
number
34371
34371
Vendor
similar
PIN 2/
HS1-82C55ARH-8
HS1-82C55ARH-Q
1/ The lead finish shown for each PIN representing
a hermetic package is the most readily available
from the manufacturer listed for that part. If the
desired lead finish is not listed, contact the vendor
to determine its availability.
2/ Caution. Do not use this number for item
acquisition. Items acquired to this number may not
satisfy the performance requirements of this drawing.
Vendor CAGE
number
34371
Vendor name
and address
Intersil Corporation
1650 Robert J. Conlan Blvd
Palm Bay, FL 32905
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.