DG611, DG612, DG613 Vishay Siliconix High-Speed, Low-Glitch D/CMOS Analog Switches DESCRIPTION FEATURES The DG611, DG612, DG613 feature high-speed lowcapacitance lateral DMOS switches. Charge injection has been minimized to optimize performance in fast sample-andhold applications. • • • • • • Each switch conducts equally well in both directions when on and blocks up to 16 Vp-p when off. Capacitances have been minimized to ensure fast switching and low-glitch energy. To achieve such fast and clean switching performance, the DG611, DG612, DG613 are built on the Vishay Siliconix proprietary D/CMOS process. This process combines n-channel DMOS switching FETs with low-power CMOS control logic and drivers. An epitaxial layer prevents latchup. The DG611 and DG612 differ only in that they respond to opposite logic levels. The versatile DG613 has two normally open and two normally closed switches. It can be given various configurations, including four SPST, two SPDT, one DPDT. Fast switching - tON: 12 ns Low charge injection: ± 2 pC Wide bandwidth: 500 MHz 5 V CMOS logic compatible Low RDS(on): 18 Low quiescent power : 1.2 nW • Single supply operation BENEFITS • • • • • • Improved data throughput Minimal switching transients Improved system performance Easily interfaced Low insertion loss Minimal power consumption APPLICATIONS • • • • • • • • For additional information see Applications Note AN207. Fast sample-and-holds Synchronous demodulators Pixel-rate video switching Disk/tape drives DAC deglitching Switched capacitor filters GaAs FET drivers Satellite receivers FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG611 DG611 IN1 1 16 IN2 D1 2 15 D2 S1 3 14 S2 V- 4 Dual-In-Line 13 and SOIC V+ GND 5 12 VL S4 6 11 S3 D4 7 10 D3 IN4 8 9 IN3 Top View D1 IN1 NC IN2 D2 Key 3 2 1 20 19 S1 4 18 S2 V- 5 17 V+ NC 6 16 NC 15 VL GND S4 LCC Top View 7 8 14 9 10 11 12 13 S3 Four SPST Switches per Package TRUTH TABLE Logic 0 1 DG611 ON OFF DG612 OFF ON Logic “0” 1 V Logic “1” 4 V D4 IN4 NC IN3 D3 * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 70057 S11-0154-Rev. I, 31-Jan-11 www.vishay.com 1 DG611, DG612, DG613 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG613 IN1 1 D1 2 S1 3 V- 4 GND 5 DG613 16 IN2 15 D2 14 S2 12 VL S4 6 11 S3 D4 7 10 D3 9 IN3 IN4 Key Dual-In-Line 13 V+ and SOIC Top View 8 D1 IN1 NC 3 2 1 IN2 D2 20 19 S1 4 18 S2 V- 5 17 V+ NC 6 16 NC GND S4 LCC Top View 7 15 8 14 9 10 11 12 13 VL S3 Four SPST Switches per Package TRUTH TABLE Logic SW1, SW4 0 OFF SW2, SW3 ON 1 ON OFF Logic “0” 1 V Logic “1” 4 V D4 IN4 NC IN3 D3 ORDERING INFORMATION Temp. Range Package Part Number DG611, DG612 16-Pin Plastic DIP - 40 °C to 85 °C 16-Pin Narrow SOIC DG611DJ DG611DJ-E3 DG612DJ DG612DJ-E3 DG611DY DG611DY-E3 DG611DY-T1 DG611DY-T1-E3 DG612DY DG612DY-E3 DG612DY-T1 DG612DY-T1-E3 DG613 16-Pin Plastic DIP DG613DJ DG613DJ-E3 16-Pin Narrow SOIC DG613DY DG613DY-E3 DG613DY-T1 DG613DY-T1-E3 - 40 °C to 85 °C www.vishay.com 2 Document Number: 70057 S11-0154-Rev. I, 31-Jan-11 DG611, DG612, DG613 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Parameter Limit V+ to V- - 0.3 to 21 V+ to GND - 0.3 to 21 V- to GND - 19 to 0.3 - 1 to (V+) + 1 or 20 mA, whichever occurs first (V-) - 1 to (V+) + 1 or 20 mA, whichever occurs first (V-) - 0.3 to (V+) + 16 or 20 mA, whichever occurs first ± 30 VL to GND VIN a VS, VDa Continuous Current (Any Terminal) Current, S or D (Pulsed at 1 µs, 10 % Duty Cycle) Storage Temperature Power Dissipation (Package) b ± 100 CerDIP - 65 to 150 Plastic - 65 to 125 16-Pin Plastic DIPc 470 16-Pin Narrow SOICd 600 16-Pin CerDIPe 900 20-Pin LCCe 900 Unit V mA °C mW Notes: a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC board. c. Derate 6 mW/°C above 75 °C. d. Derate 7.6 mW/°C above 75 °C. e. Derate 12 mW/°C above 75 °C. RECOMMENDED OPERATING RANGE Parameter Limit V+ 5 to 21 V- - 10 to 0 VL 4 to V+ VIN 0 to VL VANALOG Document Number: 70057 S11-0154-Rev. I, 31-Jan-11 Unit V V- to (V+) - 5 www.vishay.com 3 DG611, DG612, DG613 Vishay Siliconix SPECIFICATIONSa Parameter Analog Switch Analog Signal Rangee Switch On-Resistance Resistance Match Bet Ch. Symbol Test Conditions Unless Otherwise Specified V+ = 15 V, V- = - 3 V VL = 5 V, VIN = 4 V, 1 Vf VANALOG V- = - 5 V, V+ = 12 V RDS(on) RDS(on) IS = - 1 mA, VD = 0 V Source Off Leakage IS(off) VS = 0 V, VD = 10 V Drain Off Leakage Current ID(off) VS = 10 V, VD = 0 V Switch On Leakage Current ID(on) VS = V D = 0 V A Suffix D Suffix - 55 °C to 125 °C - 40 °C to 85 °C Temp.b Full Room Full Room Room Hot Room Hot Room Hot Digital Control Input Voltage High VIH Full Input Voltage Low VIL Input Current IIN Input Capacitance CIN Full Room Hot Room Typ.c Min.d Max.d Min.d Max.d Unit -5 7 45 60 -5 7 45 60 V 0.25 20 0.25 20 0.4 40 - 0.25 - 20 - 0.25 - 20 - 0.4 - 40 18 2 ± 0.001 ± 0.001 ± 0.001 - 0.25 - 20 - 0.25 - 20 - 0.4 - 40 4 0.005 -1 - 20 0.25 20 0.25 20 0.4 40 4 1 1 20 -1 - 20 1 1 20 5 CS(off) VS = 0 V Room 3 Off State Output Capacitance CD(off) VD = 0 V Room 2 On State Input Capacitance CS(on) VS = V D = 0 V Room 10 RL = 50 RL = 300 CL = 3 pF VS = ± 2 V, See test circuit, figure 2 Room 500 Room 12 25 25 Room 8 20 20 Room Full Room Full Room 19 35 50 25 35 35 50 25 35 Room 3 4 4 Room 74 Room 87 Room Full Room Full Room Full Room Full 0.005 Bandwidth BW tON Turn-Off Timee tOFF Turn-On Time tON Turn-Off Time tOFF Charge Injectione Ch. Injection Changee,g RL = 300 CL = 75 pF VS = ± 2 V, See test circuit, figure 2 Q CL = 1 nF, VS = 0 V Q CL = 1 nF, |VS| 3 V RIN = 50 RL = 50 f = 5 MHz RIN = 10 , RL = 50 f = 5 MHz Off Isolatione OIRR Crosstalke XTALK nA V µA pF Dynamic Characteristics Off State Input Capacitance Turn-On Timee pF MHz 16 4 ns pC dB Power Supplies Positive Supply Current I+ Negative Supply Current I- Logic Supply Current IL VIN = 0 V or 5 V Ground Current www.vishay.com 4 IGND - 0.005 1 5 -1 -5 0.005 - 0.005 1 5 -1 -5 1 5 -1 -5 1 5 µA -1 -5 Document Number: 70057 S11-0154-Rev. I, 31-Jan-11 DG611, DG612, DG613 Vishay Siliconix SPECIFICATIONS FOR UNIPOLAR SUPPLIESa Symbol Test Conditions Unless Otherwise Specified V+ = 15 V, V- = - 3 V VL = 5 V, VIN = 4 V, 1 Vf Temp.b A Suffix D Suffix - 55 °C to 125 °C - 40 °C to 85 °C Ty.pc Min.d Max.d Min.d 7 0 Max.d Parameter Analog Switch Analog Signal Rangee VANALOG 7 V Switch On-Resistance RDS(on) IS = - 1 mA, VD = 1 V Room 25 60 60 tON RL = 300 CL = 3 pF VS = 2 V, See test circuit, figure 2 Room 15 30 30 Room 10 25 25 Dynamic Characteristics Turn-On Timee Turn-Off Time e tOFF Full 0 Unit ns Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 °C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. Guaranteed by design, not subject to production test. f. VIN = input voltage to perform proper function. g. Q = |Q at VS = 3 V - Q at VS = - 3 V|. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 3 IS = - 1 mA 350 2 V+ = 12 V V- = - 5 V 300 I S , I D - Leakage Current (pA) R DS(on) - Drain-Source On-Resistance () 400 V+ = 5 V V- = - 5 V 250 V+ = 15 V V- = - 3 V 200 150 100 V+ = 15 V V- = - 3 V 1 IS(off), ID(off) 0 -1 -2 ID(on) 50 0 -5 -4 -2 0 2 4 6 VD - Drain Voltage (V) 8 10 RDS(on) vs. VD and Power Supply Voltages Document Number: 70057 S11-0154-Rev. I, 31-Jan-11 12 -3 -4 -2 0 2 4 6 8 VD or V S - Drain or Source Voltage (V) 10 Leakage Current vs. Analog Voltage www.vishay.com 5 DG611, DG612, DG613 Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 6 24 20 tON 18 4 16 Time (ns) V TH - Logic Input Voltage (V) 22 V+ = 15 V V- = - 3 V 5 3 2 14 tOFF 12 10 8 V+ = 15 V V- = - 3 V RL = 300 CL = 10 pF 6 1 4 2 0 0 0 5 10 - 55 15 - 15 5 25 45 65 85 105 Temperature (°C) Input Switching Threshold vs. VL Switching Times vs. Temperature 400 125 20 V+ = 15 V V- = - 3 V V+ = 15 V V- = - 3 V IS = - 1 mA 350 300 10 Qd 250 Charge (pC) R DS(on) - Drain-Source On-Resistance () - 35 VL - Logic Supply Voltage (V) 200 150 0 Qs 25 °C 100 - 10 125 °C 50 - 55 °C - 20 0 -4 -2 0 2 4 6 VD - Drain Voltage (V) 8 10 12 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 VANALOG - Analog Voltage (V) RDS(on) vs. VD and Temperature Charge Injection vs. Analog Voltage 0 10 nA RL = 50 -4 Insertion Loss (dB) I S(off) , I D(off) - Leakage (A) 1 nA 100 pA ID(on) 10 pA IS(off), ID(off) 1 pA -8 - 12 - 3 dB Point - 16 - 20 - 24 0.1 pA - 55 - 25 0 25 50 75 Temperature (°C) 100 Leakage Currents vs. Temperature www.vishay.com 6 125 1 10 100 1000 f - Frequency (MHz) - 3 dB Bandwidth/Insertion Loss vs. Frequency Document Number: 70057 S11-0154-Rev. I, 31-Jan-11 DG611, DG612, DG613 Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) - 120 6 V+ = 15 V V- = - 3 V V+ = 15 V V- = - 3 V VL = 5 V CX = 0, 5 V 5 4 Supply Current (mA) - 100 Crosstalk (dB) - 80 - 60 Off Isolation 3 I+ 2 1 IL 0 -1 I- -2 - 40 -3 -4 -5 - 20 1 10 1K 100 100K 100K 1M 10M f - Frequency (Hz) f - Frequency (MHz) Crosstalk and Off Isolation vs. Frequency Supply Currents vs. Switching Frequency SCHEMATIC DIAGRAM (Typical Channel) V+ VL S Input Logic INX Level Translator Driver D DMOS Switch V- Figure 1. TEST CIRCUITS +5V + 15 V VL V+ D Logic Input ±2V S tr < 10 ns tf < 10 ns 5V VO 50 % 0V VS = ± 2 V 90 % IN GND V- RL 300 CL Switch Output 20 % 0V tON tOFF VCL (includes fixture and stray capacitance) VO = V S RL RL + rDS(on) Figure 2. Switching Time Document Number: 70057 S11-0154-Rev. I, 31-Jan-11 www.vishay.com 7 DG611, DG612, DG613 Vishay Siliconix TEST CIRCUITS +5V C VL S1 VS +5V Rg = 50 + 15 V + 15 V C V+ D1 50 IN1 1 V, 4 V Rg V+ D VL S IN Vg NC VO 1 V, 4 V CL 1 nF 5V GND S2 VO D2 RL IN2 GND V- C VVS XTA LK Isolation = 20 log -3V VO C = RF bypass -3V Figure 4. Crosstalk Figure 3. Charge Injection APPLICATIONS High-Speed Sample-and-Hold Pixel-Rate Switch In a fast sample-and-hold application, the analog switch characteristics are critical. A fast switch reduces aperture uncertainty. A low charge injection eliminates offset (step) errors. A low leakage reduces droop errors. The CLC111, a fast input buffer, helps to shorten acquisition and settling times. A low leakage, low dielectric absorption hold capacitor must be used. Polycarbonate, polystyrene and polypropylene are good choices. The JFET output buffer reduces droop due to its low input bias current. (see figure 5.) Windows, picture-in-picture, title overlays are economically generated using a high-speed analog switch such as the DG613. For this application the two video sources must be sync locked. The glitch-less analog switch eliminates halos. (see figure 6.) GaAs FET Drivers Figure 7 illustrates a high-speed GaAs FET driver. To turn the GaAs FET on 0 V are applied to its gate via S1, whereas to turn it off, - 8 V are applied via S2. This high-speed, low-power driver is especially suited for applications that require a large number of RF switches, such as phased array radars. +5V Input Buffer + 12 V Output Buffer Analog Input CLC111 S D + LF356 - 75 5 V Control ± 5 V Output to A/D IN 1/ 4 CHOLD 650 pF Polystyrene DG611 -5V Figure 5. High-Speed Sample-and-Hold www.vishay.com 8 Document Number: 70057 S11-0154-Rev. I, 31-Jan-11 DG611, DG612, DG613 Vishay Siliconix APPLICATIONS +5V + 12 V Output Buffer Background D + Composite Output 75 CLC410 - 75 1/ CLC114 2 250 Titles 250 75 5 V Control 1/ 2 DG613 -5V Figure 6. A Pixel-Rate Switch Creates Title Overlays +5V S1 VL V+ D1 RF IN GaAs RF OUT IN1 1/ 2 DG613 S2 5V D2 IN2 GND V- -8V Figure 7. A High-Speed GaAs FET Driver that Saves Power Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?70057. Document Number: 70057 S11-0154-Rev. I, 31-Jan-11 www.vishay.com 9 Package Information Vishay Siliconix SOIC (NARROW): 16ĆLEAD JEDEC Part Number: MS-012 MILLIMETERS 16 15 14 13 12 11 10 Dim A A1 B C D E e H L Ĭ 9 E 1 2 3 4 5 6 7 8 INCHES Min Max Min Max 1.35 1.75 0.053 0.069 0.10 0.20 0.004 0.008 0.38 0.51 0.015 0.020 0.18 0.23 0.007 0.009 9.80 10.00 0.385 0.393 3.80 4.00 0.149 0.157 1.27 BSC 0.050 BSC 5.80 6.20 0.228 0.244 0.50 0.93 0.020 0.037 0_ 8_ 0_ 8_ ECN: S-03946—Rev. F, 09-Jul-01 DWG: 5300 H D C All Leads e Document Number: 71194 02-Jul-01 B A1 L Ĭ 0.101 mm 0.004 IN www.vishay.com 1 Package Information Vishay Siliconix PDIP: 16ĆLEAD 16 15 14 13 12 11 10 9 E E1 1 2 3 4 5 6 7 8 D S Q1 A A1 L 15° MAX C B1 e1 Dim A A1 B B1 C D E E1 e1 eA L Q1 S B eA MILLIMETERS Min Max INCHES Min Max 3.81 5.08 0.150 0.200 0.38 1.27 0.015 0.050 0.38 0.51 0.015 0.020 0.89 1.65 0.035 0.065 0.20 0.30 0.008 0.012 18.93 21.33 0.745 0.840 7.62 8.26 0.300 0.325 5.59 7.11 0.220 0.280 2.29 2.79 0.090 0.110 7.37 7.87 0.290 0.310 2.79 3.81 0.110 0.150 1.27 2.03 0.050 0.080 0.38 1.52 .015 0.060 ECN: S-03946—Rev. D, 09-Jul-01 DWG: 5482 Document Number: 71261 06-Jul-01 www.vishay.com 1 Package Information Vishay Siliconix CERDIP: 16ĆLEAD 16 15 14 13 12 11 10 9 E1 E 1 2 3 4 5 6 7 8 D S Q1 A A1 L1 L e1 C B B1 MILLIMETERS Dim A A1 B B1 C D E E1 e1 eA L L1 Q1 S ∝ eA INCHES Min Max Min Max 4.06 5.08 0.160 0.200 0.51 1.14 0.020 0.045 0.38 0.51 0.015 0.020 1.14 1.65 0.045 0.065 0.20 0.30 0.008 0.012 19.05 19.56 0.750 0.770 7.62 8.26 0.300 0.325 6.60 7.62 0.260 0.300 2.54 BSC ∝ 0.100 BSC 7.62 BSC 0.300 BSC 3.18 3.81 0.125 0.150 3.81 5.08 0.150 0.200 1.27 2.16 0.050 0.085 0.38 1.14 0.015 0.045 0° 15° 0° 15° ECN: S-03946—Rev. G, 09-Jul-01 DWG: 5403 Document Number: 71282 03-Jul-01 www.vishay.com 1 Packaging Information Vishay Siliconix 20ĆLEAD LCC A1 D L1 A Dim 28 e 1 2 E A A1 B D E e L L1 MILLIMETERS Min Max INCHES Min Max 1.37 2.24 0.054 0.088 1.63 2.54 0.064 0.100 0.56 0.71 0.022 0.028 8.69 9.09 0.342 0.358 8.69 9.09 0.442 0.358 1.27 BSC 0.050 BSC 1.14 1.40 0.045 0.055 1.96 2.36 0.077 0.093 ECN: S-03946—Rev. B, 09-Jul-01 DWG: 5321 L Document Number: 71290 02-Jul-01 B www.vishay.com 1 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SO-16 RECOMMENDED MINIMUM PADS FOR SO-16 0.372 (9.449) 0.152 0.022 0.050 0.028 (0.559) (1.270) (0.711) (3.861) 0.246 (6.248) 0.047 (1.194) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index APPLICATION NOTE Return to Index www.vishay.com 24 Document Number: 72608 Revision: 21-Jan-08 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU. Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21 conform to JEDEC JS709A standards. Revision: 02-Oct-12 1 Document Number: 91000