INTERSIL JANSR2N7398

JANSR2N7398
Formerly FSL430R4
2A, 500V, 2.50 Ohm, Rad Hard,
N-Channel Power MOSFET
June 1998
Features
Description
• 2A, 500V, rDS(ON) = 2.50Ω
The Discrete Products Operation of Intersil Corporation has
developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event
Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to
provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary
for military applications have not been sacrificed.
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm2 with
VDS up to 80% of Rated Breakdown and
VGS of 10V Off-Bias
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BVDSS
- Typically Survives 2E12 if Current Limited to IDM
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation
tolerant. The MOSFET is well suited for applications
exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and
drivers for high-power bipolar switching transistors requiring
high speed and low gate drive power. This type can be
operated directly from integrated circuits.
• Photo Current
- 8.0nA Per-RAD(Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
- for 3E12 Neutrons/cm2
- Usable to 3E13 Neutrons/cm2
Also available at other radiation and screening levels. See us
on the web, Intersil’s home page: http://www.intersil.com.
Contact your local Intersil Sales Office for additional
information.
Ordering Information
PART NUMBER
JANSR2N7398
PACKAGE
TO-205AF
BRAND
Symbol
JANSR2N7398
Die Family TA17639.
MIL-PRF-19500/631.
Package
TO-205AF
D
G
S
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
2-46
File Number
4372.1
JANSR2N7398
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS
Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Continuous Drain Current
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS
Maximum Power Dissipation
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure). . . . . . . . . . . . . . . . . . . . . . IAS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS
Pulsed Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JANSR2N7398
500
500
UNITS
V
V
2
1
6
±20
A
A
A
V
25
10
0.20
6
2
6
-55 to 150
300
W
W
W/oC
A
A
A
oC
oC
1.0
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
500
-
-
V
TC = -55oC
-
-
5.0
V
TC = 25oC
1.5
-
4.0
V
TC = 125oC
0.5
-
-
V
TC = 25oC
-
-
25
µA
TC = 125oC
-
-
250
µA
TC = 25oC
-
-
100
nA
TC = 125oC
-
-
200
nA
-
-
5.25
V
TC = 25oC
-
1.80
2.50
Ω
TC = 125oC
-
-
4.80
Ω
-
-
80
ns
-
-
100
ns
td(OFF)
-
-
150
ns
tf
-
-
140
ns
-
-
52
nC
Drain to Source Breakdown Voltage
BVDSS
ID = 1mA, VGS = 0V
Gate Threshold Voltage
VGS(TH)
VGS = VDS,
ID = 1mA
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On-State Voltage
Drain to Source On Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge (Not on Slash Sheet)
IDSS
IGSS
VDS(ON)
rDS(ON)12
td(ON)
tr
VDS = 400V,
VGS = 0V
VGS = ±20V
VGS = 12V, ID = 2A
ID = 1A,
VGS = 12V
VDD = 250V, ID = 2A,
RL = 125Ω, VGS = 12V,
RGS = 7.5Ω
Qg(TOT)
VGS = 0V to
20V
VDD = 250V,
ID = 2A
Gate Charge at 12V
Qg(12)
VGS = 0V to
12V
-
28
35
nC
Threshold Gate Charge (Not on Slash Sheet)
Qg(TH)
VGS = 0V to 2V
-
-
2.1
nC
Gate Charge Source
Qgs
-
4.7
6.7
nC
Gate Charge Drain
Qgd
-
13
16
nC
Thermal Resistance Junction to Case
RθJC
-
-
5.0
oC/W
Thermal Resistance Junction to Ambient
RθJA
-
-
175
oC/W
2-47
JANSR2N7398
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Forward Voltage
VSD
Reverse Recovery Time
TEST CONDITIONS
MIN
ISD = 2A
trr
PARAMETER
MAX
UNITS
0.6
-
1.8
V
-
-
390
ns
ISD = 2A, dISD/dt = 100A/µs
Electrical Specifications up to 100K RAD
TYP
TC = 25oC, Unless Otherwise Specified
MIN
MAX
UNITS
Drain to Source Breakdown Volts
(Note 3)
SYMBOL
BVDSS
VGS = 0, ID = 1mA
TEST CONDITIONS
500
-
V
Gate to Source Threshold Volts
(Note 3)
VGS(TH)
VGS = VDS, ID = 1mA
1.5
4.0
V
Gate to Body Leakage
(Notes 2, 3)
IGSS
VGS = ±20V, VDS = 0V
-
100
nA
Zero Gate Leakage
(Note 3)
IDSS
VGS = 0, VDS = 400V
-
25
µA
Drain to Source On-State Volts
(Notes 1, 3)
VDS(ON)
VGS = 12V, ID = 2A
-
5.25
V
Drain to Source On Resistance
(Notes 1, 3)
rDS(ON)12
VGS = 12V, ID = 1A
-
2.50
Ω
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS .
Single Event Effects (SEB, SEGR) (Note 4)
ENVIRONMENT (NOTE 5)
TEST
Single Event Effects Safe Operating
Area
SYMBOL
ION
SPECIES
TYPICAL LET
(MeV/mg/cm)
TYPICAL
RANGE (µ)
APPLIED
VGS BIAS
(V)
SEESOA
Ni
26
43
-15
(NOTE 6)
MAXIMUM
VDS BIAS
(V)
500
Ni
26
43
-20
450
Br
37
36
-5
500
Br
37
36
-10
400
Br
37
36
-15
100
NOTES:
4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm2 (typical), T = 25oC.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
Typical Performance Curves
Unless Otherwise Specified
LET = 26MeV/mg/cm2, RANGE = 43µ
LET = 37MeV/mg/cm2, RANGE = 36µ
600
1E-3
LIMITING INDUCTANCE (HENRY)
FLUENCE = 1E5 IONS/cm2 (TYPICAL)
500
VDS (V)
400
300
200
100
TEMP = 25oC
0
0
-5
-10
-15
-20
-25
VGS (V)
1E-4
ILM = 10A
30A
1E-5
100A
300A
1E-6
1E-7
10
30
100
300
DRAIN SUPPLY (V)
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
2-48
FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO IAS
1000
JANSR2N7398
Typical Performance Curves
Unless Otherwise Specified
2.5
(Continued)
30
TC = 25oC
10
ID , DRAIN CURRENT (A)
ID , DRAIN (A)
2.0
1.5
1.0
0.5
0
-50
0
50
100
100µs
1
1ms
10ms
0.1
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
100ms
0.01
150
10
100
VDS , DRAIN TO SOURCE VOLTAGE (V)
1
TC , CASE TEMPERATURE (oC)
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
1000
FIGURE 4. FORWARD BIAS SAFE OPERATING CURVE
2.5
PULSE DURATION = 250ms,VGS = 12V, ID = 1A
NORMALIZED rDS(ON)
2.0
QG
12V
QGS
QGD
1.5
1.0
0.5
VG
0.0
-80
FIGURE 5. BASIC GATE CHARGE WAVEFORM
NORMALIZED THERMAL RESPONSE (ZθJC)
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
CHARGE
FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE
10
1
0.5
0.1
0.2
0.1
0.05
0.02
0.01
SINGLE PULSE
PDM
0.01
0.001
10-5
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
10-4
10-3
10-2
10-1
t, RECTANGULAR PULSE DURATION (s)
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
2-49
t1
100
t2
101
JANSR2N7398
Typical Performance Curves
Unless Otherwise Specified
(Continued)
IAS , AVALANCHE CURRENT (A)
10
5
STARTING TJ = 25oC
STARTING TJ = 150oC
IF R = 0
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD)
IF R ≠ 0
tAV = (L/R) ln [(IAS*R) /
(1.3 RATED BVDSS - VDD) + 1]
1
0.001
0.01
0.1
10
1
tAV , TIME IN AVALANCHE (ms)
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN IAS IS REACHED
VDS
L
BVDSS
+
CURRENT I
TRANSFORMER AS
tP
-
VARY tP TO OBTAIN
REQUIRED PEAK IAS
VDD
50V-150V
DUT
tP
VDD
+
50Ω
VGS ≤ 20V
0V
VDS
IAS
50Ω
tAV
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
tON
VDD
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
VDS
VGS = 12V
10%
DUT
10%
0V
90%
RGS
50%
VGS
50%
PULSE WIDTH
10%
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT
FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
2-50
JANSR2N7398
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANS) TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MAX
UNITS
Gate to Source Leakage Current
IGSS
VGS = ±20V
±20 (Note 7)
nA
Zero Gate Voltage Drain Current
IDSS
VDS = 80% Rated Value
Drain to Source On Resistance
rDS(ON)
TC = 25oC at Rated ID
Gate Threshold Voltage
VGS(TH)
ID = 1.0mA
±25 (Note 7)
µA
±20% (Note 8)
Ω
±20% (Note 8)
V
NOTES:
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
Screening Information
TEST
JANS
Gate Stress
VGS = 30V, t = 250µs
Pind
Required
Pre Burn-In Tests (Note 9)
MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)
Steady State Gate
Bias (Gate Stress)
MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
Interim Electrical Tests (Note 9)
All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse
Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 240 hours
PDA
5%
Final Electrical Tests (Note 9)
MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
Safe Operating Area
Unclamped Inductive Switching
SYMBOL
SOA
TEST CONDITIONS
VDS = 200V, t = 10ms
MAX
UNITS
0.56
A
IAS
VGS(PEAK) = 15V, L = 0.1mH
6
A
Thermal Response
∆VSD
tH = 10ms; VH = 25V; IH = 2A
125
mV
Thermal Impedance
∆VSD
tH = 500ms; VH = 25V; IH = 1A
250
mV
2-51
JANSR2N7398
Rad Hard Data Packages - Intersil Power Transistors
1. JANS Rad Hard - Standard Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning Attributes Data Sheet
Hi-Rel Lot Traveler
HTRB - Hi Temp Gate Stress Post Reverse
Bias Data and Delta Data
HTRB - Hi Temp Drain Stress Post Reverse
Bias Delta Data
F. Group A
- Attributes Data Sheet
G. Group B
- Attributes Data Sheet
H. Group C
- Attributes Data Sheet
I. Group D
- Attributes Data Sheet
2. JANS Rad Hard - Optional Data Package
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- Hi-Rel Lot Traveler
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups A2, A3, A4, A5 and A7 Data
G. Group B
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups B1, B3, B4, B5 and B6 Data
H. Group C
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Subgroups C1, C2, C3 and C6 Data
I. Group D
- Attributes Data Sheet
- Hi-Rel Lot Traveler
- Pre and Post Radiation Data
2-52
JANSR2N7398
TO-205AF
3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE
INCHES
ØD
ØD1
SYMBOL
P
A
h
SEATING
PLANE
L
Øb
e
e1
2
e2
1
90o
3
45o
j
k
MIN
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.160
0.180
4.07
4.57
-
Øb
0.016
0.021
0.41
0.53
2, 3
ØD
0.350
0.370
8.89
9.39
-
ØD1
0.315
0.335
8.01
8.50
-
e
0.095
0.105
2.42
2.66
4
e1
0.190
0.210
4.83
5.33
4
e2
0.095
0.105
2.42
2.66
4
h
0.010
0.020
0.26
0.50
-
j
0.028
0.034
0.72
0.86
-
k
0.029
0.045
0.74
1.14
-
L
0.500
0.560
12.70
14.22
3
P
0.075
-
1.91
-
5
NOTES:
1. These dimensions are within allowable dimensions of Rev. E of
JEDEC TO-205AF outline dated 11-82.
2. Lead dimension (without solder).
3. Solder coating may vary along lead length, add typically 0.002
inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.100 inches (2.54mm) from bottom
of seating plane.
5. This zone controlled for automatic handling. The variation in
actual diameter within this zone shall not exceed 0.010 inches
(0.254mm).
6. Lead no. 3 butt welded to stem base.
7. Controlling dimension: Inch.
8. Revision 3 dated 6-94.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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FAX: (407) 724-7240
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2-53
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