HI1179 ® October 25, 2005 R oH and e e r Pb-F S Co m t plian 8-Bit, 35 MSPS, Video A/D Converter Features Description • Resolution 8-Bit . . . . . . . . . . . . . . . . . . . ±0.5 LSB (DNL) The HI1179 is an 8-bit CMOS analog-to-digital converter for video use that features a sync clamp function. The adoption of a 2-step parallel method realizes low power consumption and a maximum conversion speed of 35 MSPS, allowing up to 8x over sampling of NTSC and PAL signals. • ENOB at fIN = 1MHz . . . . . . . . . . . . . . . . . . . . . . 7.6 Bits • Maximum Sampling Frequency . . . . . . . . . . . 35 MSPS • Low Power Consumption 80mW (at 35 MSPS Typ) (Reference Current Excluded) The HI1179 is available in the Industrial temperature range and is supplied in 32 lead Plastic Metric Quad Flatpack (MQFP) package. For lower sampling rates, refer to the HI1176 data sheet. • Built-In Input Clamp Function (DC Restore) • No Sample/Hold Required • Internal Voltage Reference • Input CMOS Compatible Ordering Information • Three-State TTL Compatible Output • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V PART NUMBER • Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . 8pF • Reference Impedance (Typ) . . . . . . . . . . . . . . . . . 330Ω • Direct Replacement for Sony CXD1179 TEMP. RANGE (oC) HI1179JCQ -40 to 85 HI1179-EV 25 PACKAGE PKG. NO. 32 Ld MQFP Q32.7x7-S Evaluation Board Applications Pinout • Desktop Video VRBS VREF 3 22 AVSS D3 4 21 VIN D4 5 20 AVDD D5 6 19 AVDD D6 7 18 VRT (MSB) D7 8 17 9 10 11 12 13 14 15 16 VRB VRTS AVDD CLP AVSS D2 TEST 23 TEST 2 CLK D1 DVDD 32 31 30 29 28 27 26 25 24 NC 1 DVDD (LSB) D0 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.Copyright Intersil Americas Inc. 1997, 1999, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. 1 CCP DVSS • Low Cost High Speed Data Acquisition Systems CLE NC • Image Scanners OE • Video Digitizing DVSS HI1179 (MQFP) TOP VIEW • Multimedia FN3666.4 HI1179 Functional Block Diagram DVSS 28 25 VRBS OE 30 REFERENCE SUPPLY DVSS 31 D0 (LSB) 1 D1 2 D2 3 D3 4 D4 5 D5 6 D6 7 D7 (MSB) 8 24 VRB 23 AVSS LOWER DATA LATCHES UPPER DATA LATCHES LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATORS (4-BIT) 22 AVSS 21 VIN LOWER ENCODER (4-BIT) LOWER SAMPLING COMPARATORS (4-BIT) UPPER ENCODER (4-BIT) UPPER SAMPLING COMPARATORS (4-BIT) 20 AVDD 19 AVDD 18 VRT 17 VRTS 16 AVDD DVDD 10 DVDD 11 CLOCK GENERATOR CLK 12 NC - 9 + NC 32 15 CLP 14 TEST LOGIC 29 27 26 CLE CCP VREF 2 13 TEST HI1179 Typical Application Schematic +5V (DIGITAL) 74ACO4 CLOCK IN 0.1µF +5V (ANALOG) 0.01µF HA5020 VIDEO IN 75Ω + - 0.1µF 10pF 1kΩ 1kΩ 0.01µF 16 15 14 13 12 11 10 9 8 17 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 1 24 25 26 27 28 29 30 31 32 D0 GND (ANALOG) GND (DIGITAL) +5V (DIGITAL) NON-CLAMP APPLICATION (INTERNAL REFERENCE USED) 3 HI1179 Absolute Maximum Ratings Thermal Information Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Reference Voltage, VRT , VRB . . . . . . . . . . . . . . . . . . . . VDD to VSS Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Digital Output Voltage, VOH , VOL . . . . . . . . . . . . . . . . . VDD to VSS Thermal Resistance (Typical, Note 1) θJAoC/W MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range, TSTG . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) Recommended Operating Conditions (Note 2) Analog Input Voltage, VIN . . . . . . . . .VRB to VRT (1.8VP-P to AVDD) Clock Pulse Width tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14ns (Min) tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14ns (Min) Supply Voltage AVDD , AVSS, DVDD , DVSS . . . . . . . . . . . . . . . +4.75V to +5.25V |DGND-AGND| . . . . . . . . . . . . . . . . . . . . . . . . . . . .0mV to 100mV Reference Input Voltage VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V and Above VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V and Below Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications fC = 35 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 2) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PERFORMANCE Maximum Conversion Speed, fC VIN = 0.5V to 2.5V, fIN = 1kHz Ramp 35 40 - MSPS Minimum Conversion Speed, fC VIN = 0.5V to 2.5V, fIN = 1kHz Ramp - - 0.5 MSPS Integral Non-Linearity, INL fC = 35 MSPS, VIN = 0.5V to 2.5V -1.0 ±0.5 +1.3 LSB Differential Non-Linearity, DNL fC = 35 MSPS, VIN = 0.5V to 2.5V -0.5 ±0.3 +0.5 LSB fIN = 1MHz - 7.6 - Bits fIN = 5MHz - 7.3 - Bits NTSC 40 IRE Mod Ramp, fC = 14.3 MSPS - 1.0 - % Differential Phase Error, DP - 0.5 - Degree Aperture Jitter, tAJ - 30 - ps EOT -60 -40 -20 mV EOB +55 +75 +95 mV - 2 - ns -1dB - 25 - MHz -3dB - 60 - MHz VIN = 1.5V + 0.07VRMS - 8 - pF Reference Pin Current, IREF 4.5 6.1 8.7 mA Reference Resistance (VRT to VRB), RREF 230 330 440 Ω DYNAMIC CHARACTERISTICS ENOB Differential Gain Error, DG Offset Voltage Sampling Delay, tSD ANALOG INPUTS Analog Input Bandwidth, BW Analog Input Capacitance, CIN REFERENCE INPUT 4 HI1179 Electrical Specifications fC = 35 MSPS, VDD = +5V, VRB = 0.5V, VRT = 2.5V, TA = 25oC (Note 2) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.52 0.56 0.60 V 1.96 2.10 2.24 V 2.13 2.33 2.53 V VIH 3.5 - - V VIL - - 0.5 V VIH = VDD - - 5 µA VIL = 0V - - 5 µA VOH = VDD -0.5V -1.1 -2.5 - mA VOL = 0.4V 3.7 6.5 - mA VOH = VDD - - 16 µA VOL = 0V - - 16 µA INTERNAL VOLTAGE REFERENCES Self Bias VRB Short VRB to VRBS , Short VRT to VRTS VRT - VRB VRT - VRB Short VRT to VRTS , Short VRB to AVSS DIGITAL INPUTS Digital Input Voltage Digital Input Current IIH VDD = Max IIL DIGITAL OUTPUTS Digital Output Current IOH OE = VSS , VDD = Min IOL Digital Output Leakage Current IOZH OE = VDD, VDD = Max IOZL TIMING CHARACTERISTICS Output Data Delay, tD Load is One TTL Gate and 10pF Load 7 13 18 ns Output Enable/Disable Delay tPZH, tPZL RL = 1K, CL = 15pF, OE = 5V → 0V 5 8 14 ns tPHZ, tPLZ RL = 1K, CL = 15pF, OE = 0V → 5V 4 6.5 11 ns - 16 22 mA VREF = 0.5V -20 0 +20 mV VREF = 2.5V -30 -10 +10 mV - 25 - ns POWER SUPPLY CHARACTERISTIC Supply Current, IDD fC = 35 MSPS, NTSC Ramp Wave Input CLAMP CHARACTERISTICS Clamp Offset Voltage, EOC VIN = DC, PWS = 3µs Clamp Pulse Delay, tCPD NOTE: 2. Electrical specifications guaranteed only under the stated operating conditions. 5 HI1179 Timing Diagrams tPW1 tPW0 CLOCK ANALOG INPUT N DATA OUTPUT : POINT FOR ANALOG SIGNAL SAMPLING N+1 N-3 N-2 N-2 N+3 N-1 N+4 N N+1 tD = 13ns FIGURE 1. VI (1) VI (2) VI (3) VI (4) ANALOG INPUT EXTERNAL CLOCK UPPER COMPARATOR BLOCK S (1) S (1) DIGITAL OUTPUT S (3) C (3) MD (2) RV (1) H (1) H (0) C (0) C (1) LD (-2) MD (3) RV (3) S (3) H (3) H (2) C (2) LD (0) OUT (-1) FIGURE 2. 6 C (4) C (3) LD (1) S (2) OUT (-2) S (4) RV (2) LD (-1) LOWER DATA A LOWER DATA B C (2) MD (1) RV (0) LOWER REFERENCE VOLTAGE LOWER COMPARATOR BLOCK B S (2) MD (0) UPPER DATA LOWER COMPARATOR BLOCK A C (1) S (4) H (4) LD (2) OUT (0) OUT (1) HI1179 Timing Diagrams (Continued) 4V 7V (tPZL , tPLZ) 1.4V OE 1.4V 0V OPEN (tPZH , tPHZ) S1 tPLZ tPZL R1 500Ω TEST POINT FROM OUTPUT UNDER TEST 3.5V DATA OUTPUT WAVEFORM 1 VOL 0.3V tPZH R2 500Ω CL 15pF tPHZ 0.3V VOH DATA OUTPUT WAVEFORM 2 FIGURE 3A. THREE-STATE LOAD CIRCUIT Typical Performance Curves 0V FIGURE 3B. THREE-STATE OUTPUT ENABLE/DISABLE TIMES fC = 35 MSPS, TA = 25oC, Unless Otherwise Specified 8.0 -30 fC = 35 MSPS fC = 35 MSPS 7.5 -40 HARMONICS (dBc) ENOB 1.4V 7.0 6.5 SECOND HARMONIC -50 THIRD HARMONIC -60 6.0 -70 1 5 7.5 10 15 1 5 7.5 fIN (MHz) fIN (MHz) FIGURE 4. ENOB vs INPUT FREQUENCY 10 15 FIGURE 5. HARMONICS vs INPUT FREQUENCY 8.5 -30 fC = 35 MSPS 8.0 -35 fIN = 1MHz 7.5 -40 THD (dBc) ENOB fIN = 5MHz 7.0 fIN = 10MHz fIN = 10MHz -45 fIN = 5MHz 6.5 -50 6.0 -55 fIN = 1MHz 5.5 -60 20 27 35 0 40 25 50 TEMPERATURE (oC) CLOCK FREQUENCY (MHz) FIGURE 6. ENOB vs CLOCK FREQUENCY FIGURE 7. THD vs TEMPERATURE 7 75 HI1179 Typical Performance Curves fC = 35 MSPS, TA = 25oC, Unless Otherwise Specified (Continued) 60 9 fC = 35 MSPS fC = 35 MSPS fIN = 1MHz 55 fIN = 1MHz 50 SFDR (dBc) ENOB 8 fIN = 5MHz 7 fIN = 10MHz fIN = 5MHz 45 fIN = 10MHz 40 6 35 30 5 0 25 50 75 0 25 TEMPERATURE (oC) FIGURE 8. ENOB vs TEMPERATURE 75 FIGURE 9. SFDR vs TEMPERATURE 0 150 POWER DISSIPATION (mW) OUTPUT LEVEL (dB) 50 TEMPERATURE (oC) -1 -2 TA = 75oC VDD = 5V 100 VDD = 4V 50 -3 0 0.1 1 10 100 0 fIN (MHz) 5 10 15 20 25 FIGURE 10. OUTPUT LEVEL vs INPUT FREQUENCY SYMBOL 1-8 D0 to D7 35 40 FIGURE 11. POWER DISSIPATION vs CLOCK FREQUENCY Pin Descriptions PIN NUMBER 30 CLOCK FREQUENCY (MHz) EQUIVALENT CIRCUIT DESCRIPTION D0 (LSB) to D7 (MSB) output. D1 8 HI1179 Pin Descriptions (Continued) PIN NUMBER SYMBOL 9 NC EQUIVALENT CIRCUIT DESCRIPTION This pin must be left open. Used for test purposes only. DVDD 9 DVSS 10 DVDD 12 CLK Digital +5V. Clock Input. DVDD 12 DVSS 11, 13, 14 TEST Pin 11 must be connected to DVDD . Pin 13, and Pin 14 must be connected to DVDD or DVSS . Used for test purposes only. DVDD 11 13 14 DVSS 15 CLP Clamp Pulse Input. The input signal voltage is clamped to VREF while the clamp pulse is low. DVDD 15 DVSS 16, 19, 20 AVDD 17 VRTS Analog +5V. When shorted with VRT , generates approximately +2.6V. AVDD 17 18 VRT 24 VRB Reference Voltage (Top). AVDD 18 24 AVSS 9 Reference Voltage (Bottom). HI1179 Pin Descriptions (Continued) PIN NUMBER SYMBOL 21 VIN EQUIVALENT CIRCUIT DESCRIPTION Analog Input. AVDD 21 AVSS 22, 23 AVSS 25 VRBS Analog Ground. AVSS When shorted with VRB , generates approximately +0.5V. 25 26 VREF Clamp Reference Voltage Input. AVDD 26 AVSS 27 CCP Integrates the voltage for clamp control. CCP and VIN voltage changes are in phase. AVDD 27 AVSS 28, 31 DVSS 29 CLE Digital ground. When CLE is low, clamp function is activated. When CLE is high, clamp function is OFF and only the usual A/D converter function is active. By connecting CLE pin to DVDD via a several hundred Ω resistance, the clamp pulse can be tested. DVDD 29 DVSS 30 OE CLAMP PULSE DVDD 30 DVSS 10 When OE is low, data is valid. When OE is high, D0 to D7 pins are high impedance. HI1179 A/D OUTPUT CODE TABLE DIGITAL OUTPUT CODE INPUT SIGNAL VOLTAGE STEP MSB VRT 255 1 • • • • • • • • VRB LSB 1 1 1 1 1 1 1 • • • • • • 128 1 0 0 0 0 0 0 0 127 0 1 1 1 1 1 1 1 0 0 0 • • • • • • 0 0 0 0 0 0 Detailed Description The HI1179 is a 2-step A/D converter featuring a 4-bit upper comparator group and two lower comparator groups of 4 bits each. The reference voltage can be obtained from the onboard bias generator or be supplied externally. This IC uses an offset canceling type comparator that operates synchronously with an external clock. The operating modes of the part are input sampling/autozero (S), hold (H), and compare (C). Op amps such as the HA-2544, the HA5020 and the HFA1100 family should make excellent input amplifiers depending on the applications requirements. In order to prevent parasitic oscillation, it may be necessary to insert a resistor between the output of the amplifier and the A/D input. The input can be AC or DC coupled. If AC coupled the input will float to about 1/2 (VRT + VRB). The other option is to use the internal clamp, which will be discussed later. When DC coupling the input be sure to disable the clamp function (CLE, pin 29). The operation of the part is illustrated in Figure 2. A reference voltage that is between VRT-VRB is constantly applied to the upper 4-bit comparator group. VI(1) is sampled with the falling edge of the first clock by the upper comparator block. The lower block A also samples VI(1) on the same edge. The upper comparator block finalizes comparison data MD(1) with the rising edge of the first clock. Simultaneously the reference supply generates a reference voltage RV(1) that corresponds to the upper results and applies it to the lower comparator block A. The lower comparator block finalizes comparison data LD(1) with the rising edge of the second clock. MD(1) and LD(1) are combined and output as OUT(1) with the rising edge of the third clock. There is a 2.5 clock cycle delay from the analog input sampling point to the corresponding digital output data. Notice how the lower comparator blocks A and B alternate generating the lower data in order to increase the overall A/D sampling rate. Reference Input The HI1179 has an internal reference with the option to use an external reference if more accuracy is desired. The analog input range of the A/D is set by the voltage between VRT and VRB . The internal reference can be used by shorting VRT to VRTS and VRB to VRBS . The internal bias generator will set VRT to about 2.6V and VRB to about 0.6V. The analog input range of the A/D will now be from 0.6V to 2.6V. The internal reference may be subjected to power supply variations since the internal reference resistor ladder is connected directly to VDD and VSS . Any supply variations can be minimized by good decoupling of VRT and VRB . Power, Grounding, and Decoupling An external reference can be used for increased accuracy, by connecting the reference voltage to VRT and VRB . If an external reference is used, VRT should be keep below 2.8V and (VRT - VRB) should be less than 2.8V and greater than 1.8V. If a VRB below +0.6V is used the linearity of the part may degrade. An ICL8069 reference and a dual op amp, with outputs connect to VRT and VRB , makes a good, low cost external reference. Separate analog and digital grounds to reduce noise effects, connecting them at a single point near the HI1179. Analog and digital power should also be separated for optimum performance. If a single 5V supply is used, isolate the analog and digital power with an inductor or ferrite bead to minimize the digital noise on the analog supply. Bypass both the digital and analog VDD pins to their respective grounds with a ceramic 0.1µF capacitor close to the pin. Bypass VRT and VRB to analog ground with a 0.1µF capacitor when using either internal or external references. Analog Input Clamp Operation The analog input capacitance is small when compared with other flash type A/D converters. However, it is necessary to drive the input with a low impedance source with sufficient bandwidth and drive capability. The HI1179 provides a clamp (DC restore) option that allows the user to clamp a portion of the analog input to a voltage set by the VREF pin before the signal is digitized. The clamp 11 HI1179 function is enabled by tying CLE low. In this case a negative going pulse is sent to the CLP pin. VIN will now be clamped during the low period of the clamp pulse to the voltage on the VREF pin. Figure 15 shows the HI1179 configured for this mode of operation.The clamp pulse is latched by the ADC sampling clock through an external latch. This is not necessary to the operation of the clamp function but in video applications, if this is not done, then a slight beat might be generated as vertical sag according to the relation between the sampling frequency and the clamp frequency. The pulse width of the input clamp pulse will depend on the input signal. For example, a 1µs pulse width will allow the user to clamp the back porch of an NTSC input signal to the reference voltage, VREF . The clamp can be disabled by tying CLE high and then the HI1179 acts like a normal A/D converter, accepting a DC coupled input. The Typical Application Schematic illustrates the operation of HI1179 when the clamp function is not used. Additional information on the HI1179 is available in Application Note 9407, “Using the HI1176/HI1179 Evaluation Board”. Test Circuits +V S2 - S1: ON IF A < B S2: ON IF A > B S1 + -V A<B A>B COMPARATOR VIN DUT HI1179 8 “0” A8 B8 A1 A0 B1 B0 8 BUFFER “1” DVM 000 • • • 00 TO 111 • • • 10 8 CLK (35MHz) CONTROLLER FIGURE 12. INTEGRAL AND DIFFERENTIAL NON-LINEARITY ERROR AND OFFSET VOLTAGE TEST CIRCUIT 2.6V ERROR RATE fC -1kHz SG HPF 0.6V 1 2 NTSC SIGNAL SOURCE 100 IRE 0 -40 SG (CW) 40 IRE MODULATION VIN AMP DUT HI1179 8 TTL 1 8 10-BIT D/A ECL 620 2 CLK VECTOR SCOPE 2.6V BURST -5.2V 620 SYNC COUNTER HI20201 DG DP 0.6V -5.2V TTL fC ECL FIGURE 13. MAXIMUM OPERATIONAL SPEED AND DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT 12 HI1179 Test Circuits (Continued) VDD VRT 2.6V IOL VIN IOH VIN VRB 0.6V VRB 0.6V VDD VRT 2.6V CLK CLK VOL OE GND VOH OE + GND - FIGURE 14A. + - FIGURE 14B. FIGURE 14. DIGITAL OUTPUT CURRENT TEST CIRCUIT Typical Application Circuits + 5V (DIGITAL) 74ACO4 0.1µF CLOCK IN CK CLAMP PULSE IN LATCH Q +5V (ANALOG) 0.01µF HA5020 10µF VIDEO IN + - 75Ω + 0.1µF 10pF 1k 0.01µF 1k 16 15 14 13 12 11 10 9 8 17 D7 18 7 D6 19 6 D5 20 5 D4 21 4 D3 22 3 D2 23 2 D1 24 1 25 26 27 28 29 30 31 32 D0 +5V (ANALOG) 20K VREF 0.01µF GND (ANALOG) GND (DIGITAL) FIGURE 15. INPUT CLAMP APPLICATION (INTERNAL REFERENCE USED) 13 HI1179 Typical Application Circuits (Continued) ICL8069 REFERENCE AMP HA5020 (Single) HA5022 (Dual) HA5024 (Quad) HA5013 (Triple) HFA1105 (Single) HFA1205 (Dual) HFA1405 (Quad) A/D HI1179 (8-Bit) DSP/µP HSP9501 HSP48410 HSP48908 HSP48901 HSP48212 HSP43881 HSP43168 D/A HI1171 (8-Bit) CA3338 (8-Bit) AMP HA5020 (Single) HA2842 (Single) HFA1115 (Single) HFA1212 (Dual) HFA1412 (Quad) HSP9501: Programmable Data Buffer HSP48410: Histogrammer/Accumulating Buffer, 10-Bit Pixel Resolution, 4K x 4K Frame Size HSP48908: 2-D Convolver, 3 x 3 Kernal Convolution, 8-Bit HSP48901: 3 x 3 Image Filter, 30MHz, 8-Bit HSP48212: Video Mixer HSP43881: Digital Filter, 30MHz, 1-D and 2-D FIR Filters HSP43168: Dual FIR Filter, 10-Bit, 33MHz/45MHz CMOS Logic Available in HC, HCT, AC, ACT and FCT. FIGURE 16. 8-BIT VIDEO COMPONENTS Static Performance Definitions Dynamic Performance Definitions Offset, full-scale, and gain all use a measured value of the internal voltage reference to determine the ideal plus and minus full-scale values. The results are all displayed in LSBs. The first code transition should occur at a level 1/2 LSB above the negative full-scale. Offset is defined as the deviation of the actual code transition from this point. Note that this is adjustable to zero. Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the HI1179. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 1024 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. The distortion numbers are quoted in dBc (decibels with respect to carrier) and DO NOT include any correction factors for normalizing to full scale. Full-Scale Error (FSE) Signal-to-Noise Ratio (SNR) The last code transition should occur for a analog input that is 11/2 LSBs below positive full scale. Full-scale error is defined as the deviation of the actual code transition from this point. SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Differential Linearity Error (DNL) Signal-to-Noise + Distortion Ratio (SINAD) DNL is the worst case deviation of a code width from the ideal value of 1 LSB. The converter is guaranteed to have no missing codes. SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Integral Linearity Error (INL) Effective Number Of Bits (ENOB) INL is the worst case deviation of a code center from a best fit straight line calculated from the measured data. The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: Offset Error (VOS) ENOB = (SINAD - 1.76 + VCORR) / 6.02, where: VCORR = 0.5dB. 14 HI1179 Total Harmonic Distortion Timing Definitions This is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal. Sampling Delay (tSD) Sampling delay is the time delay between the external sample command (the falling edge of the clock) and the time at which the signal is actually sampled. This delay is due to internal clock path propagation delays. 2nd and 3rd Harmonic Distortion This is the ratio of the RMS value of the 2nd and 3rd harmonic component respectively to the RMS value of the measured input signal. Aperture Jitter (tAJ) Spurious Free Dynamic Range (SFDR) This is the RMS variation in the sampling delay due to variation of internal clock path delays. SFDR is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. If the harmonics are buried in the noise floor it is the largest peak. Data Latency (tLAT) After the analog sample is taken, the data on the bus is available after 2.5 cycles of the clock. This is due to the architecture of the converter where the data has to ripple through the stages. This delay is specified as the data latency. After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The digital data lags the analog input by 2.5 cycles. Full Power Input Bandwidth Full power bandwidth is the frequency at which the amplitude of the digitally reconstructed output has decreased 3dB below the amplitude of the input sine wave. The input sine wave has a peak-to-peak amplitude equal to the reference voltage. The bandwidth given is measured at the specified sampling frequency. Output Data Delay (tD) Output Data Delay is the delay time from when the data is valid (rising clock edge) to when it shows up at the output bus. This is due to internal delays at the digital output. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 15