T NT DUC PRO LACEME r at E T OL E REP rt Cente tsc O B S E N D ED m/ pp o MM nical Su tersil.co O C n E ech TSheet ww.i August 1996, Rev D NO R Data t o ur S I L or w c a t n R o E c 8-INT 1-88 EL4095 ® Video Gain Control/Fader/Multiplexer Features The EL4095 is a versatile variable-gain building block. At its core is a fader which can variably blend two inputs together and an output amplifier that can drive heavy loads. Each input appears as the input of a current-feedback amplifier and with external resistors can separately provide any gain desired. The output is defined as: • Full function video fader VOUT = A*VINA (0. 5V + VGAIN) + B*VINB (0.5V–VGAIN), • ±5V to ±15V operation where A and B are the fed-back gains of each channel. Additionally, two logic inputs are provided which each override the analog VGAIN control and force 100% gain for one input and 0% for the other. The logic inputs switch in only 25ns and provide high attenuation to the off channel, while generating very small glitches. Signal bandwidth is 60MHz, and gain-control bandwidth 20MHz. The gain control recovers from overdrive in only 70ns. The EL4095 operates from ±5V to ±15V power supplies, and is available in both 14-pin DIP and narrow surface mount packages. Pinout • 0.02%/0.02° differential gain/phase @ 100% gain • 25ns multiplexer included • Output amplifier included • Calibrated linear gain control • 60MHz bandwidth • Low thermal errors Applications • Video faders/wipers • Gain control • Graphics overlay • Video text insertion • Level adjust • Modulation Ordering Information PART NUMBER EL4095 (14-PIN PDIP, SO) TOP VIEW FN7161 TEMP. RANGE PACKAGE PKG. NO. EL4095CN -40°C to +85°C 14-Pin PDIP MDP0031 EL4095CS -40°C to +85°C 14-Pin SO MDP0027 Manufactured under U.S. Patent No. 5,321,371, 5,374,898 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL4095 Absolute Maximum Ratings (TA = 25°C) VS+ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V VS Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . .+33V +VINA,Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VS-) -0.3V +VINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to (VS+) +0.3V IIN Current Into -VINA, -VINB . . . . . . . . . . . . . . . . . . . . . . . . 5mA VGAIN Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGAIN ±5V VGAIN Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS- to VS+ VFORCEInput Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6V IOUT Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35mA TA Operating Temperature Range . . . . . . . . . . . .-40°C to +85°C TJ Operating Junction Temperature. . . . . . . . . . . 0°C to +150°C TST Storage Temperature Range. . . . . . . . . . . . .-65°C to +150°C Internal Power Dissipation . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Open-Loop DC Electrical Specifications VS = ±15V, TA = 25°C, VGAIN ground unless otherwise specified LIMITS PARAMETER DESCRIPTION MIN TYP MAX UNITS 1.5 5 mV VOS Input Offset Voltage IB+ +VIN Input Bias Current 5 10 µA IB- -VIN Input Bias Current 10 50 µA CMRR Common Mode Rejection -CMRR -VIN Input Bias Current Common Mode Rejection PSRR Power Supply Rejection Ratio -IPSR -VIN Input Current Power Supply Rejection Ratio ROL Transimpedance RIN- -VIN Input Resistance VIN +VIN Range VO Output Voltage Swing ISC Output Short-Circuit Current VIH Input High Threshold at Force A or Force B Inputs VIL Input Low Threshold at Force A or Force B Inputs IFORCE, High Input Current of Force A or Force B, VFORCE = 5V IFORCE, Low Input Current of Force A or Force B, VFORCE = 0V Feedthrough, Forced Feedthrough of Deselected Input to Output, Deselected Input at 100% Gain Control 60 75 VGAIN, 100% Minimum Voltage at VGAIN for 100% Gain 0.45 0.5 0.55 V VGAIN, 0% Maximum Voltage at VGAIN for 0% Gain -0.55 -0.5 -0.45 V NL, Gain Gain Control Non-linearity, VIN = ±0.5V 2 4 % RIN, VG Impedance between VGAIN and VGAIN 5.5 6.5 kΩ NL, AV = 1 AV = 0.5 AV = 0.25 Signal Non-linearity, VIN = ±1V, VGAIN = 0.55V Signal Non-linearity, VIN = ±1V, VGAIN = 0V Signal Non-linearity, VIN = ±1V, VGAIN = -0.25V IS Supply Current 2 65 80 0.5 65 1.5 95 0.2 0.2 dB µA/V dB 2 µA/V 0.4 MΩ 80 Ω (V-) + 3.5 (V+) -3.5 V (V-) +2 (V+) -2 V 160 mA 2.0 V 80 125 0.8 V -440 4.5 -50 µA -650 µA dB % % <0.01 0.03 0.07 0.4 17 21 % mA EL4095 Closed-Loop AC Electrical Specifications VS = ±15V, AV = +1, RF = RIN = 1kΩ, RL = 500Ω, CL = 15pF, CIN- = 2pF, TA = 25°C, AV = 100% unless otherwise noted LIMITS PARAMETER DESCRIPTION SR Slew Rate; VOUT from -3V to +3V Measured at -2V and +2V BW Bandwidth dG dθ TS MIN Settling Time to 0.2%; VOUT from -2V to +2V MAX UNITS 330 V/µs -3dB 60 MHz -1dB 30 MHz -0.1dB 6 MHz 0.02 % 0.07 % AV = 25% 0.07 % AV = 100% 0.02 ° AV = 50% 0.05 ° AV = 25% 0.15 ° AV = 100% 100 ns AV = 25% 100 ns Differential Gain; AC Amplitude of 286mVP-P at 3.58MHz AV = 100% on DC Offset of -0.7V, 0V and +0.7V AV = 50% Differential Phase; AC Amplitude of 286mVP-P at 3.58MHz on DC Offset of -0.7V, 0V and +0.7V TYP TFORCE Propagation Delay from VFORCE = 1.4V to 50% Output Signal Enabled or Disabled Amplitude 25 ns BW, Gain -3dB Gain Control Bandwidth, VGAIN Amplitude 0.5 VP-P 20 MHz TREC, Gain Gain Control Recovery from Overload; VGAIN from -0.7V to 0V 70 ns 3 EL4095 Typical Performance Curves Large-Signal Pulse Response Gain = +1 Small-Signal Pulse Response for Various Gains Frequency Response with Different Values of RF - Gain = +1 4 Large-Signal Pulse Response Gain = -1 Frequency Response for Different Gains-AV = +1 Frequency Response with Different Values of RF - Gain = -1 EL4095 Typical Performance Curves (Continued) Frequency Response with Different Values of RF - Gain = -1 Frequency Response with Various Values of Parasitic CIN- Change in Bandwidth and Slewrate with Supply Voltage - Gain = +1 5 Frequency Response with Various Load Capacitances and Resistances Input Noise Voltage and Current vs Frequency Change in Bandwidth and Slewrate with Supply Voltage - Gain = -1 EL4095 Typical Performance Curves (Continued) Change in Bandwidth and Slewrate with Temperature - Gain = +1 DC Nonlinearity vs Input Voltage Gain = +1 Differential Gain and Phase Errors vs Gain Control Setting - Gain = +1 6 Change in Bandwidth and Slewrate with Temperature - Gain = -1 Change in VOS and IB- vs die Temperature Differential Gain and Phase Errors vs Gain Control Setting - Gain = -1 EL4095 Typical Performance Curves (Continued) Differential Phase Error vs DC Offset - Gain = +1 Differential Phase Error vs DC Offset - Gain = +1 Differential Phase Error vs DC Offset - Gain = -1 Differential Phase Error vs DC Offset - Gain = -1 Attenuation over Frequency - Gain = +1 Attenuation over Frequency - Gain = -1 7 EL4095 Typical Performance Curves (Continued) Gain vs VG (1 VDC at VINA) Gain Control Response to a Non-Overloading Step, Constant Sinewave at VINA VGAIN Overload Recovery Response—No AC Input 8 Gain Control Gain vs Frequency VGAIN Overload Recovery Delay Cross-Fade Balance -0V on AIN and BIN; Gain = +1 EL4095 Typical Performance Curves (Continued) Change in V100% and V0% of Gain Control vs Supply Voltage Force Response Supply Current vs Supply Voltage 9 Change in V100% and V0% of Gain Control vs VGAIN Offset Change in V100% and V0% of Gain Control vs Die Temperature Force-Induced Output Transient Package Power Dissipation vs Ambient Temperature EL4095 Test Circuit, AV = +1 Applications Information The EL4095 is a general-purpose two-channel fader whose input channels each act as a current-feedback amplifier (CFA) input. Each input can have its own gain factor as established by external resistors. For instance, the Test Circuit shows two channels each arranged as +1 gain, with the traditional single feedback resistor RF connected from VOUT to the -VIN of each channel. The EL4095 can be connected as an inverting amplifier in the same manner as any CFA. Frequency Response Like other CFAs, there is a recommended feedback resistor, which for this circuit is 1kΩ. The value of RF sets the closedloop -3dB bandwidth, and has only a small range of practical variation. The user should consult the typical performance curves to find the optional value of RF for a given circuit gain. In general, the bandwidth will decrease slightly as closedloop gain is increased; RF can be reduced to make up for bandwidth loss. Too small a value of RF will cause frequency response peaking and ringing during transients. On the other hand, increasing RF will reduce bandwidth but improve stability. 10 EL4095 FIGURE 1. EL4095 IN INVERTING CONNECTION Stray capacitance at each -VIN terminal should absolutely be minimized, especially in a positive-gain mode, or peaking will occur. Similarly, the load capacitance should be minimized. If more than 25pF of load capacitance must be driven, a load resistor from 100Ω to 400Ω can be added in parallel with the output to reduce peaking, but some bandwidth degradation may occur. A “snubber” load can alternatively be used. This is a resistor in series with a capacitor to ground, 150Ω and 100pF being typical values. The advantage of a snubber is that it does not draw DC load current. A small series resistor, low tens of ohms, can also be used to isolate reactive loads. Here are a few idealized examples, based on a gain of +1 for channels A and B and RF = 1kΩ for different gain settings: Gain VINA VINB I (-VINA) I (-VINB) VOUT 100% 1V 0 0 1mA 1V 75% 1V 0 -250µA 750µA 0.75V 50% 1V 0 -500µA 500µA 0.5V 25% 1V 0 -750µA 250µA 0.25V 0% 1V 0 -1mA 0 0V Distortion The signal voltage range of the +VIN terminals is within 3.5V of either supply rail. One must also consider the range of error currents that will be handled by the -VIN terminals. Since the -VIN of a CFA is the output of a buffer which replicates the voltage at +VIN, error currents will flow into the -VIN terminal. When an input channel has 100% gain assigned to it, only a small error current flows into its negative input; when low gain is assigned to the channel the output does not respond to the channel’s signal and large error currents flow. 11 Thus, either -VIN can receive up to 1mA error current for 1V of input signal and 1kΩ feedback resistors. The maximum error current is 3mA for the EL4095, but 2mA is more realistic. The major contributor of distortion is the magnitude of error currents, even more important than loading effects. The performance curves show distortion versus input amplitude for different gains. If maximum bandwidth is not required, distortion can be reduced greatly (and signal voltage range enlarged) by increasing the value of RF and any associated gain-setting resistor. EL4095 100% Accuracies When a channel gain is set to 100%, static and gain errors are similar to those of a simple CFA. The DC output error is expressed by VOUT, Offset = VOS* AV + (IB-)*RF. The input offset voltage scales with fed-back gain, but the bias current into the negative input, IB-, adds an error not dependent on gain. Generally, IB- dominates up to gains of about seven. The fractional gain error is given by EGAIN = (RF + AV*RIN -) RF + AV RIN)/ROL The gain error is about 0.3% for a gain of one, and increases only slowly for increasing gain. RIN- is the input impedance of the input stage buffer, and ROL is the transimpedance of the amplifier, 80kΩ and 350kΩ respectively. Gain Control Inputs The gain control inputs are differential and may be biased at any voltage as long as VGAIN is less than 2.5V below V+ and 3V above V-. The differential input impedance is 5.5kΩ, and a common-mode impedance is more than 500kΩ. With zero differential voltage on the gain inputs, both signal inputs have a 50% gain factor. Nominal calibration sets the 100% gain of VINA input at +0.5V of gain control voltage, and 0% at -0.5V of gain control. VINB’s gain is complementary to that of VINA; +0.5V of gain control sets 0% gain at VINB and -0.5V gain control sets 100% VINB gain. The gain control does not have a completely abrupt transition at the 0% and 100% points. There is about 10mV of “soft” transfer at the gain endpoints. To obtain the most accurate 100% gain factor or best attenuation of 0% gain, it is necessary to overdrive the gain control input by about 30mV. This would set the gain control voltage range as -0.565mV to +0.565V, or 30mV beyond the maximum guaranteed 0% to 100% range. In fact, the gain control internal circuitry is very complex. Here is a representation of the terminals: FIGURE 2. REPRESENTATION OF GAIN CONTROL INPUTS VG AND VG For gain control inputs between ±0.5V (±90µA), the diode bridge is a low impedance and all of the current into VG flows 12 back out through VG. When gain control inputs exceed this amount, the bridge becomes a high impedance as some of the diodes shut off, and the VG impedance rises sharply from the nominal 5.5kΩ to over 500kΩ. This is the condition of gain control overdrive. The actual circuit produces a much sharper overdrive characteristics than does the simple diode bridge of this representation. The gain input has a 20MHz -3dB bandwidth and 17ns risetime for inputs to ±0.45V. When the gain control voltage exceeds the 0% or 100% values, a 70ns overdrive recovery transient will occur when it is brought back to linear range. If quicker gain overdrive response is required, the Force control inputs of the EL4095 can be used. Force Inputs The Force inputs completely override the VGAIN setting and establish maximum attainable 0% and 100% gains for the two input channels. They are activated by a TTL logic low on either of the FORCE pins, and perform the analog switching very quickly and cleanly. FORCEA causes 100% gain on the A channel and 0% on the B channel. FORCEB does the reverse, but there is no defined output state when FORCEA and FORCEB are simultaneously asserted. The Force inputs do not incur recovery time penalties, and make ideal multiplexing controls. A typical use would be text overlay, where the A channel is a video input and the B channel is digitally created text data. The FORCEA input is set low normally to pass the video signal, but released to display overlay data. The gain control can be used to set the intensity of the digital overlay. Other Applications Circuits The EL4095 can also be used as a variable-gain single input amplifier. If a 0% lower gain extreme is required, one channel’s input should simply be grounded. Feedback resistors must be connected to both -VIN terminals; the EL4095 will not give the expected gain range when a channel is left unconnected. This circuit gives +0.5 to +2.0 gain range, and is useful as a signal leveller, where a constant output level is regulated from a range of input amplitudes: EL4095 FIGURE 3. LEVELING CIRCUIT WITH 0.5 ≤ AV ≤ 2 Here the A input channel is configured for a gain of +2 and the B channel for a gain of +1 with its input attenuated by 1/2. The connection is virtuous because the distortions do not increase monotonically with reducing gain as would the simple single-input connection. For video levels, however, these constants can give fairly high differential gain error. The problem occurs for large inputs. Assume that a “twice-size” video input occurs. The Aside stage sees the full amplitude, but the gain would be set to 100% B-input gain to yield an overall gain of 1/2 to produce a standard video output. The -VIN of the A side is a buffer output that reproduces the input signal, and drives RGA and RFA. Into the two resistors 2.1mA of error current flows for a typical 1.4V of input DC offset, creating distortion in a A-side input stage. RGA and RFA could be increased together in value to reduce the error current and distortions, but increasing RFA would lower bandwidth. A solution would be to simply attenuate the input signal magnitude and restore the EL4095 output level to standard level with another amplifier so: 13 EL4095 FIGURE 4. REDUCED-GAIN LEVELER FOR VIDEO INPUTS AND DIFFERENTIAL GAIN AND PHASE PERFORMANCE (SEE TEXT) Although another amplifier is needed to gain the output back to standard level, the reduced error currents bring the differential phase error to less than 0.1 over the entire input range. A useful technique to reduce video distortion is to DCrestore the video level going into the EL4095, and offsetting black level to -0.35V so that the entire video span encompasses ±0.35V rather than the unrestored possible span of ±0.7V (for standard-sized signals). For the preceding leveler circuit, the black level should be set more toward -0.7V to accommodate the largest input, or made to vary 14 with the gain control itself (large gain, small offset; small gain, larger offset). The EL4095 can be wired as a four quadrant multiplier: EL4095 FIGURE 5. EL4095 CONNECTED AS A FOUR-QUADRANT MULTIPLIER The A channel gains the input by +1 and the B channel by -1. Feedthrough suppression of the Y input can be optimized by introducing an offset between channel A and B. This is easily done by injecting an adjustable current into the summing junction (-VIN terminal) of the B input channel. The two input channels can be connected to a common input through two dissimilar filters to create a DC-controlled variable filter. This circuit provides a controlled range of peaking through rolloff characteristics: 15 EL4095 FIGURE 6. VARIABLE PEAKING FILTER The EL4095 is connected as a unity-gain fader, with an LRC peaking network connected to the A-input and an RC rolloff network connected to the B-input. The plot shows the range of peaking controlled by the VGAIN input. This circuit would be useful for flattening the frequency response of a system, or for providing equalization ahead of a lossy transmission line. where AV is the fed-back gain of the EL4095. Here is a plot of input-referred noise vs AV: Noise The electrical noise of the EL4095 has two components: the voltage noise in series with +VIN is 5nV√Hz wideband, and there is a current noise injected into -VIN of 35pA√Hz. The output noise will be V n, out = 2 ( A V × V n, input ) + ( I n, input × R F ) 2 , FIGURE 7. INPUT-REFERRED NOISE VS CLOSED-LOOP GAIN and the input-referred noise is V n, input – referred = 2 ( V n, input ) + ( I n, input × R F ⁄ A V ) 16 2 EL4095 Thus, for a gain of three or more the fader has a noise as good as an op-amp. The only trade-off is that the dynamic range of the input is reduced by the gain due to the nonlinearity caused by gained-up output signals. Power Dissipation Peak die temperature must not exceed 150°C. This allows 75°C internal temperature rise for a 75°C ambient. The EL4095 in the 14-pin PDIP package has a thermal resistance of 65°C/W, and can thus dissipate 1.15W at a 75°C ambient temperature. The device draws 20mA maximum supply current, only 600mW at ±15V supplies, and the circuit has no dissipation problems in this package. The SO-14 surface-mount package has a 105°C/W thermal resistance with the EL4095, and only 714mW can be dissipated at 75°C ambient temperature. The EL4095 thus can be operated with ±15V supplies at 75°C, but additional dissipation caused by heavy loads must be considered. If this is a problem, the supplies should be reduced to ±5V to ±12V levels. The output will survive momentary short-circuits to ground, but the large available current will overheat the die and also potentially destroy the circuit’s metal traces. The EL4095 is reliable within its maximum average output currents and operating temperatures. EL4095 Macromodel This macromodel is offered to allow simulation of general EL4095 behavior. We have included these characteristics: Small-signal frequency response Signal path DC distortions Output loading effects VGAIN I-V characteristics Input impedance VGAIN overdrive recovery delay Off-channel feedthrough 100% gain error Output impedance over frequency FORCE operation -VIN characteristics and sensitivity to parasitic capacitance These will give a good range of results of various operating conditions, but the macromodel does not behave identically as the circuit in these areas: Temperature effects Manufacturing tolerances Signal overload effects Supply voltage effects Signal and VG operating range Slewrate limitations Current-limit Noise Video and high-frequency distortions Power supply interactions Glitch and delay from FORCE inputs 17 EL4095 FIGURE 8. THE EL4095 MACROMODEL SCHEMATIC 18 EL4095 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19