AN11051 Pin FMEA for HEF4000 family Rev. 2 — 15 July 2015 Application note Document information Info Content Keywords FMEA, HEF4000, CMOS, wide operating supply range (3 V to 15 V) Abstract This application note provides a Failure Modes and Effects Analysis (FMEA) for the device pins of the NXP Semiconductors’ HEF4000 family under typical failure situations AN11051 NXP Semiconductors Pin FMEA for HEF4000 family Revision history Rev Date Description v 1.0 20110428 initial version v. 2.0 20150715 Table 4: Added pin VEE Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] AN11051 Application note All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 6 AN11051 NXP Semiconductors Pin FMEA for HEF4000 family 1. Introduction Though the HEF4000 series is one of the oldest CMOS logic families around, it is still frequently used in new designs because of its ease of design-in, wide operating supply range (3 V to 15 V), excellent noise immunity, and low power consumption. All of the standard functions are available, plus more specialized functions such as IEEE bus interfaces and PLL frequency synthesizers. 2. Pin FMEA This application note provides a Failure Modes and Effects Analysis (FMEA) for the device pins of the NXP Semiconductor AUP family under typical failure situations such as a short-circuit to VDD or VSS or to a neighboring pin, or if a pin is left open. Some HEF4000 family devices have special functions, that can have different behaviors. A failure is classified according to its effect on the HEF4000 device and the functionality of the application; see Table 1. Table 1. Classification of failure effects Class Failure effect A damage to device affects application functionality B no damage to device may affect application functionality C no damage to device no affect to application functionality Table 2. Pin Class Remarks Input B normal operating condition, no damage, no leakage, may affect functionality Output C if output defined HIGH, no damage, no leakage, no output level change Output A if output defined LOW, short-circuits and high currents can damage device, output level changes VSS B short-circuits and high currents can damage device, will affect functionality Table 3. AN11051 Application note FMEA matrix for pin short-circuit to VDD FMEA matrix for pin short-circuit to VSS Pin Class Remarks Input B normal operating condition, no damage, no leakage, may affect functionality Output C if output defined LOW, no damage, no leakage, no output level change Output A if output defined HIGH, short-circuits and high currents can damage device, output level changes VDD B no damage to device, will affect functionality All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 6 AN11051 NXP Semiconductors Pin FMEA for HEF4000 family Table 4. FMEA matrix for pin left open Pin Class Remarks Input B undefined operating condition, no damage, increases leakage, may affect functionality Output C normal operating condition, no damage, no leakage VSS; VEE B undefined operating condition, no damage, increases leakage, will affect functionality VDD B undefined operating condition, no damage, increases leakage (only for I/O types), will affect functionality Table 5. FMEA matrix for pin short-circuits between neighboring pins Pin Class Input to input Remarks C if inputs have same voltage levels: no damage, no leakage B if inputs have different voltage levels: leakage increases, will affect functionality A if input and output have different voltage levels, can cause high current and can damage device, will affect functionality C if input and output have same voltage levels, no damage, no leakage Input to VSS - see Table 3 Input to VDD - see Table 2 Output to output C if outputs have same voltage levels, no damage, no leakage A if outputs have different voltage levels, can cause high current and can damage device, will affect functionality Input to output Output to input - same effect as ‘input to output’ condition Output to VSS - see Table 3 Output to VDD - see Table 2 VSS to VDD - not applicable, these pins are not neighbors 3. Abbreviations Table 6. AN11051 Application note Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor FMEA Failure Modes and Effects Analysis PLL Phase-Locked Loop All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 6 AN11051 NXP Semiconductors Pin FMEA for HEF4000 family 4. Legal information 4.1 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 4.2 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. 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NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product AN11051 Application note design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 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In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer’s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 4.3 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 2 — 15 July 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 6 AN11051 NXP Semiconductors Pin FMEA for HEF4000 family 5. Contents 1 2 3 4 4.1 4.2 4.3 5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin FMEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 4 5 5 5 5 6 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 15 July 2015 Document identifier: AN11051