PIC16(L)F1703/7 14/20-Pin 8-Bit Advanced Analog Flash Microcontrollers Core Features eXtreme Low-Power (XLP) Features • C Compiler Optimized RISC Architecture • Only 49 Instructions • Operating Speed: - 0-32 MHz - 125 ns minimum instruction cycle • Interrupt Capability • 16-Level Deep Hardware Stack • Up to Two 8-Bit Timers • One 16-bit Timer • Power-on Reset (POR) • Power-up Timer (PWRT) • Low-Power Brown-out Reset (LPBOR) • Programmable Watchdog Timer (WDT) up to 256s • Programmable Code Protection • Sleep mode: 50 nA @ 1.8V, typical • Watchdog Timer: 500 nA @ 1.8V, typical • Operating Current: - 8 uA @ 32 kHz, 1.8V, typical - 32 uA/MHz @ 1.8V, typical Memory • • • • Two Kwords Flash Program Memory 256 Bytes Data SRAM Memory Direct, Indirect and Relative Addressing modes High-Endurance Flash Data Memory (HEF) - 128 bytes of nonvolatile data storage - 100k erase/write cycles Intelligent Analog Peripherals • Operational Amplifiers: - Two configurable rail-to-rail Op Amps - Selectable internal and external channels - 2 MHz gain bandwidth product • 10-Bit Analog-to-Digital Converter (ADC): - Up to 12 external channels - Conversion available during Sleep - Temperature Indicator • Zero-Cross Detector (ZCD): - Detect when AC signal on pin crosses ground Clocking Structure • 16 MHz Internal Oscillator Block: - ±1% at calibration - Selectable frequency range from 0 to 32 MHz • 31 kHz Low-Power Internal Oscillator Operating Characteristics Programming/Debug Features • Operating Voltage Range: - 1.8V to 3.6V (PIC16LF1703/7) - 2.3V to 5.5V (PIC16F1703/7) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C • In-Circuit Debug Integrated On-Chip • Emulation Header for Advanced Debug: - Provides trace, background debug and up to 32 hardware break points • In-Circuit Serial Programming™ (ICSP™) via Two Pins Digital Peripherals • Capture/Compare/PWM (CCP) module • Serial Communications: - SPI, I2C • Up to 18 I/O Pins and One Input Pin: - Individually programmable weak pull-ups - Slew rate control - Interrupt-on-change with edge-select • Peripheral Pin Select (PPS): - Enables pin mapping of digital I/O 2013-2015 Microchip Technology Inc. DS40001722C-page 1 PIC16(L)F1703/7 Device Data Sheet Index Program Memory Flash (words) Data SRAM (bytes) High-Endurance Flash (bytes) I/O’s(2) 10-bit ADC (ch) 8-bit DAC High-Speed/ Comparators Op Amp Zero Cross Timers (8/16-bit) CCP PWM COG EUSART MSSP (I2C/SPI) CLC PPS Debug(1) XLP PIC16(L)F170x Family Types PIC16(L)F1703 (3) 2048 256 128 12 8 0 0 2 1 2/1 2 0 0 0 1 0 Y I/E Y PIC16(L)F1704 (1) 4096 512 128 12 8 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y PIC16(L)F1705 (2) 8192 1024 128 12 8 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y PIC16(L)F1707 (3) 2048 256 128 18 12 0 0 2 1 2/1 2 0 0 0 1 0 Y I/E Y PIC16(L)F1708 (1) 4096 512 128 18 12 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y PIC16(L)F1709 (2) 8192 1024 128 18 12 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y Note 1: 2: Debugging Methods: (I) – Integrated on Chip; (H) – using Debug Header; E – using Emulation Header. One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS40001715 PIC16(L)F1704/8 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers. 2: DS40001729 PIC16(L)F1705/9 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers. 3: DS40001722 PIC16(L)F1703/7 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers Note: For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. DS40001722C-page 2 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Pin Diagrams FIGURE 1: 14-PIN DIAGRAM FOR PIC16(L)F1703 VDD RA5 RA4 VPP/MCLR/RA3 RC5 RC4 RC3 FIGURE 2: 1 2 3 4 5 6 7 PIC16(L)F1703 PDIP, SOIC, TSSOP 14 13 12 11 10 9 8 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 16-PIN PACKAGE DIAGRAM FOR PIC16(L)F1703 16 VDD 15 NC 14 NC 13 VSS QFN 1 12 RA0/ICSPDAT 2 11 RA1/ICSPCLK 3 PIC16(L)F1703 10 RA2 4 9 RC0 RC4 RC3 RC2 RC1 5 6 7 8 RA5 RA4 RA3/MCLR/VPP RC5 2013-2015 Microchip Technology Inc. DS40001722C-page 3 PIC16(L)F1703/7 FIGURE 3: 20-PIN PACKAGE DIAGRAM FOR PIC16(L)F1707 PDIP, SOIC, SSOP VDD 20 VSS 2 19 RA4 3 18 RA1/ICSPCLK VPP/MCLR/RA3 4 17 RA2 RC5 5 16 RC0 15 RC1 14 RC2 13 RB4 9 12 RB5 10 11 RB6 RC3 RC6 RC7 RB7 6 7 8 PIC16(L)F1707 RA5 RA0/ICSPDAT RC4 FIGURE 4: 1 20-PIN PACKAGE DIAGRAM FOR PIC16(L)F1707 20 19 18 17 16 RA4 RA5 VDD VSS RA0/ICSPDAT QFN 1 15 RA1/ICSPCLK 2 14 RA2 3 PIC16(L)F1707 13 RC0 4 12 RC1 5 11 RC2 RC7 RB7 RB6 RB5 RB4 6 7 8 9 10 VPP/MCLR/RA3 RC5 RC4 RC3 RC6 DS40001722C-page 4 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 ADC Reference Op Amp Zero Cross MSSP Interrupt Pull-up Basic 13 12 AN0 VREF- — — — — — IOC Y ICSPDAT RA1 12 11 AN1 VREF+ — — — — — IOC Y ICSPCLK RA2 11 10 AN2 — — ZCD T0CKI(1) — — INT(1) IOC Y — RA3 4 3 — — — — — — — IOC Y MCLR VPP RA4 3 2 AN3 — — — T1G(1) — — IOC Y CLKOUT RA5 2 1 — — — — T1CKI(1) — — IOC Y CLKIN RC0 10 9 AN4 — — SCK(1) IOC Y — OPA1IN+ — — CCP QFN RA0 Timers PDIP/SOIC/TSSOP 14/16-PIN ALLOCATION TABLE (PIC16(L)F1703) I/O(2) TABLE 1: SCL(3) RC1 9 8 AN5 — OPA1IN- — — — SDI(1) SDA(3) IOC Y — RC2 8 7 AN6 — OPA1OUT — — — — IOC Y — SS(1) RC3 7 6 AN7 — OPA2OUT — — CCP2(1) IOC Y — RC4 6 5 — — OPA2IN- — — — — IOC Y — RC5 5 4 — — OPA2IN+ — — CCP1(1) — IOC Y — VDD 1 16 — — — — — — — — — VDD VSS 14 13 — — — — — — — — — VSS OUT(2) Note 1: 2: 3: (3) — — — — — — — CCP1 SDA — — — — — — — — — — CCP2 SCL(3) SCK — — — — — — — — — — — SDO — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 2013-2015 Microchip Technology Inc. DS40001722C-page 5 PIC16(L)F1703/7 Zero Cross Timers MSSP Interrupt Pull-up Basic 16 AN0 VREF- — — — — — IOC Y ICSPDAT 18 15 AN1 VREF+ — — — — — IOC Y ICSPCLK Y — RA2 17 14 AN2 — — ZCD RA3 4 1 — — — — RA4 3 20 AN3 — — RA5 2 19 — — RB4 13 10 AN10 — RB5 12 9 AN11 — RB6 11 8 — — CCP ADC 19 RA1 Op Amp QFN RA0 Reference PDIP/SOIC/ SSOP 20-PIN ALLOCATION TABLE (PIC16(L)F1707) I/O(2) TABLE 2: (1) T0CKI (1) — — INT IOC — — — IOC Y MCLR VPP — T1G(1) — — IOC Y CLKOUT — — T1CKI — — IOC Y CLKIN OPA1IN- — — — SCK(1) SDA(3) IOC Y — OPA1IN+ — — — — IOC Y — — — — — SDI(1) SCL(3) IOC Y — RB7 10 7 — — — — — — — IOC Y — RC0 16 13 AN4 — — — — — — IOC Y — RC1 15 12 AN5 — — — — — — IOC Y — RC2 14 11 AN6 — OPA1OUT — — — — IOC Y — RC3 7 4 AN7 — OPA2OUT — — CCP2(1) — IOC Y — RC4 6 3 — IOC Y — — — — — — RC5 5 2 — — — — — RC6 8 5 AN8 — OPA2IN- — — RC7 9 6 AN9 — OPA2IN+ — — VDD 1 18 — — — — — VSS 20 17 — — — — — OUT(2) Note 1: 2: 3: — CCP1 (1) — IOC Y — SS(1) IOC Y — — — IOC Y — — — — — VDD — — — — VSS — — — — — — — — CPP1 SDA(3) — — — — — — — — — — CPP2 SCL(3) SCK — — — — — — — — — — — SDO — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. All pin digital outputs default to PORT latch data. Any pin can be selected as a peripheral digital output with the PPS output selection registers. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001722C-page 6 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 15 3.0 Memory Organization ................................................................................................................................................................. 17 4.0 Device Configuration .................................................................................................................................................................. 48 5.0 Resets ........................................................................................................................................................................................ 53 6.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 61 7.0 Interrupts .................................................................................................................................................................................... 72 8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 85 9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 89 10.0 Flash Program Memory Control ................................................................................................................................................. 94 11.0 I/O Ports ................................................................................................................................................................................... 110 12.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 128 13.0 Interrupt-On-Change ................................................................................................................................................................ 135 14.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 141 15.0 Temperature Indicator Module ................................................................................................................................................. 143 16.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 145 17.0 Operational Amplifier (OPA) Modules ...................................................................................................................................... 159 18.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 162 19.0 Timer0 Module ......................................................................................................................................................................... 166 20.0 Timer1 Module with Gate Control............................................................................................................................................. 169 21.0 Timer2 Module ......................................................................................................................................................................... 180 22.0 Capture/Compare/PWM Modules ............................................................................................................................................ 184 23.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 194 24.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 249 25.0 Instruction Set Summary .......................................................................................................................................................... 251 26.0 Electrical Specifications............................................................................................................................................................ 265 27.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 293 28.0 Development Support............................................................................................................................................................... 310 29.0 Packaging Information.............................................................................................................................................................. 314 The Microchip Web Site ..................................................................................................................................................................... 335 Customer Change Notification Service .............................................................................................................................................. 335 Customer Support .............................................................................................................................................................................. 335 Product Identification System ............................................................................................................................................................ 336 2013-2015 Microchip Technology Inc. DS40001722C-page 7 PIC16(L)F1703/7 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected]. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS40001722C-page 8 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 1.0 DEVICE OVERVIEW The PIC16(L)F1703/7 are described within this data sheet. They are available in 14-pin and 20-pin DIP packages and 16-pin and 20-pin QFN packages. Figure 1-1 shows a block diagram of the PIC16(L)F1703/7 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. Peripheral PIC16(L)F1707 DEVICE PERIPHERAL SUMMARY PIC16(L)F1703 TABLE 1-1: Analog-to-Digital Converter (ADC) ● ● Fixed Voltage Reference (FVR) ● ● Zero-Cross Detection (ZCD) ● ● Temperature Indicator ● ● Capture/Compare/PWM (CCP/ECCP) Modules CCP1 ● ● CCP2 ● ● MSSP ● ● Op Amp 1 ● ● Op Amp 2 ● ● Timer0 ● ● Timer1 ● ● Timer2 ● ● Master Synchronous Serial Ports Op Amp Timers 2013-2015 Microchip Technology Inc. DS40001722C-page 9 PIC16(L)F1703/7 FIGURE 1-1: PIC16(L)F1703/7 BLOCK DIAGRAM Program Flash Memory RAM PORTA PORTB(1) CLKOUT Timing Generation HFINTOSC/ LFINTOSC Oscillator CLKIN PORTC CPU Figure 2-1 MCLR ZCD Op Amps Timer0 Temp. Indicator Note 1: 2: DS40001722C-page 10 ADC 10-Bit Timer1 FVR Timer2 MSSP CCPs PIC16(L)F1707 only. See applicable chapters for more information on peripherals. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 1-2: PIC16(L)F1703 PINOUT DESCRIPTION Name Function RA0/AN0/VREF-/ICSPDAT RA0 Input Type AN VREF- AN ICSPDAT ST RA1 Description TTL/ST CMOS General purpose I/O. AN0 RA1/AN1/VREF+/ICSPCLK Output Type — ADC Channel 0 input. — ADC Negative Voltage Reference input. CMOS ICSP™ Data I/O. TTL/ST CMOS General purpose I/O. AN1 AN VREF+ AN — ADC Voltage Reference input. ICSPCLK ST — Serial Programming Clock. RA2/AN2/ZCD/T0CKI(1)/INT(1) RA2 AN2 RA3/MCLR/VPP RA4/AN3/T1G(1)/CLKOUT TTL/ST CMOS General purpose I/O. — ZCD — AN Zero Cross Detection Current Source/Sink. T0CKI TTL/ST — Timer0 clock input. INT TTL/ST — External interrupt. RA3 TTL/ST CMOS General purpose I/O. ADC Channel 2 input. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. TTL/ST CMOS General purpose I/O. AN3 AN T1G TTL/ST CLKOUT — RA5 T1CKI CLKIN RC0/AN4/OPA1IN+/SCK(1)/SCL(3) ADC Channel 1 input. AN RA4 RA5/T1CKI(1)/CLKIN — RC0 — ADC Channel 3 input. — Timer1 gate input. CMOS FOSC/4 output. TTL/ST CMOS General purpose I/O. TTL/ST — Timer1 clock input. TTL/ST — External clock input (EC mode). TTL/ST CMOS General purpose I/O. AN4 AN — ADC Channel 4 input. OPA1IN+ AN — Operational Amplifier 1 non-inverting input. SCK ST — SPI clock. SCL I2C — I2C clock. RC1/AN5/OPA1IN-/SDI(1)/SDA(3) RC1 AN5 TTL/ST CMOS General purpose I/O. AN — ADC Channel 5 input. OPA1IN- AN — Operational Amplifier 1 inverting input. SDI CMOS — SPI data input. SDA I2C — I2C data input. RC2/AN6/OPA1OUT RC2 TTL/ST CMOS General purpose I/O. AN6 AN — ADC Channel 6 input. OPA1OUT — AN Operational Amplifier 1 output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. 2013-2015 Microchip Technology Inc. DS40001722C-page 11 PIC16(L)F1703/7 TABLE 1-2: PIC16(L)F1703 PINOUT DESCRIPTION (CONTINUED) Name Function RC3/AN7/OPA2OUT/CCP2(1)/SS(1) RC3 RC4/OPA2IN- VDD VSS OUT(2) Output Type Description TTL/ST CMOS General purpose I/O. AN7 AN — ADC Channel 7 input. OPA2OUT — AN Operational Amplifier 2 output. CCP2 TTL/ST — Capture/Compare/PWM2. SS TTL/ST — Slave Select input. RC4 OPA2IN- RC5/OPA2IN+/CCP1(1) Input Type RC5 TTL/ST CMOS General purpose I/O. AN — Operational Amplifier 2 inverting input. TTL/ST CMOS General purpose I/O. OPA2IN+ AN — CCP1 TTL/ST — Capture/Compare/PWM1. VDD Power — Positive supply. VSS Power — Ground reference. CCP1 — CMOS Capture/Compare/PWM1 output. CCP2 — CMOS Capture/Compare/PWM2 output. SDA(3) — OD Operational Amplifier 2 non-inverting input. I2C data input/output. SDO — CMOS SPI data output. SCK — CMOS SPI clock output. SCL(3) — OD I2C clock output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001722C-page 12 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 1-3: PIC16(L)F1707 PINOUT DESCRIPTION Name RA0/AN0/VREF-/ICSPDAT RA1/AN1/VREF+/ICSPCLK RA2/AN2/ZCD/ T0CKI(1)/INT(1) Function RA0 AN VREF- AN ICSPDAT ST RA1 RA4/AN3/T1G(1)/CLKOUT RA5/T1CKI/CLKIN — ADC Negative Voltage Reference input. CMOS ICSP™ Data I/O. TTL/ST CMOS General purpose I/O. VREF+ AN — ADC Voltage Reference input. ST — Serial Programming Clock. RA2 AN2 — ADC Channel 1 input. TTL/ST CMOS General purpose I/O. AN — ZCD — AN Zero-Cross Detection Current Source/Sink. T0CKI ST — Timer0 clock input. ST — External interrupt. RA3 ADC Channel 2 input. TTL/ST CMOS General purpose I/O. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RA4 TTL/ST CMOS General purpose I/O. AN3 AN T1G ST CLKOUT — RA5 RB4 — ADC Channel 3 input. — Timer1 gate input. CMOS FOSC/4 output. TTL/ST CMOS General purpose I/O. ST — Timer1 clock input. ST — External clock input (EC mode). TTL/ST CMOS General purpose I/O. AN10 AN — ADC Channel 10 input. OPA1IN- AN — Operational Amplifier 1 inverting input. SCK ST SDA I2C RB5 OPA1IN+ RB7 ADC Channel 0 input. ICSPCLK AN11 RB6/SDI(1)/SCL(3) — AN CLKIN RB5/AN11/OPA1IN+ Description AN1 T1CKI RB4/AN10/OPA1IN-/SCK(1)/ SDA(3) Output Type TTL/ST CMOS General purpose I/O. AN0 INT RA3/MCLR/VPP Input Type CMOS SPI clock. OD I2C data input/output. TTL/ST CMOS General purpose I/O. AN — ADC Channel 11 input. AN — Operational Amplifier 1 non-inverting input. RB6 TTL/ST CMOS General purpose I/O. SDI CMOS — SPI data input. SCL I2C OD I2C clock. RB7 TTL/ST CMOS General purpose I/O. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. 2013-2015 Microchip Technology Inc. DS40001722C-page 13 PIC16(L)F1703/7 TABLE 1-3: PIC16(L)F1707 PINOUT DESCRIPTION (CONTINUED) Name Function RC0/AN4 RC0 RC1/AN5 RC1 RC2/AN6/OPA1OUT RC2 AN4 AN5 RC3/AN7/OPA2OUT/CCP2(1) Input Type Output Type Description TTL/ST CMOS General purpose I/O. AN — ADC Channel 4 input. TTL/ST CMOS General purpose I/O. AN — ADC Channel 5 input. TTL/ST CMOS General purpose I/O. AN6 AN — ADC Channel 6 input. OPA1OUT — AN Operational Amplifier 1 output. RC3 AN7 TTL/ST CMOS General purpose I/O. AN OPA2OUT — CCP2 ST — ADC Channel 7 input. AN Operational Amplifier 2 output. CMOS Capture/Compare/PWM2. RC4 RC4 TTL/ST CMOS General purpose I/O. RC5/CCP1(1) RC5 TTL/ST CMOS General purpose I/O. CCP1 RC6/AN8/OPA2IN-/SS(1) RC6 CMOS Capture/Compare/PWM1. AN8 AN — ADC Channel 8 input. OPA2IN- AN — Operational Amplifier 2 inverting input. ST — Slave Select input. SS RC7/AN9/OPA2IN+ ST TTL/ST CMOS General purpose I/O. RC7 TTL/ST CMOS General purpose I/O. AN9 AN — ADC Channel 9 input. OPA2IN+ AN — Operational Amplifier 2 non-inverting input. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. CCP1 — CMOS Capture/Compare/PWM1 output. CCP2 — CMOS Capture/Compare/PWM2 output. (3) — OUT(2) SDA OD I2C data input/output. SDO — CMOS SPI data output. SCK — CMOS SPI clock output. SCL(3) I2C OD I2C clock output. Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C = Schmitt Trigger input with I2C HV = High Voltage Note 1: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2. 2: All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. 3: These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001722C-page 14 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 2.0 Relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and FIGURE 2-1: • • • • Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Direct Addr 7 5 Indirect Addr 12 12 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer CLKIN CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset MUX ALU 8 W reg Internal Oscillator Block VDD 2013-2015 Microchip Technology Inc. VSS DS40001722C-page 15 PIC16(L)F1703/7 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving” for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled, will cause a software Reset. See Section 3.6 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.7 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 25.0 “Instruction Set Summary” for more details. DS40001722C-page 16 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM implemented for the PIC16(L)F1703/7 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 3-1). 3.2 Note 1: The method to access Flash memory through the PMCON registers is described in Section 10.0 “Flash Program Memory Control”. High-Endurance Flash This device has a 128-byte section of high-endurance Program Flash Memory (PFM) in lieu of data EEPROM. This area is especially well suited for non-volatile data storage that is expected to be updated frequently over the life of the end product. See Section 10.2 “Flash Program Memory Overview” for more information on writing data to PFM. See Section 3.2.1.2 “Indirect Read with FSR” for more information about using the FSR registers to read byte data stored in PFM. The following features are associated with access and control of program memory and data memory: • PCL and PCLATH • Stack • Indirect Addressing 3.1 Program Memory Organization The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes TABLE 3-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) Last Program Memory Address High-Endurance Flash Memory Address Range (1) 2,048 07FFh 0780h-07FFh PIC16(L)F1703/7 Note 1: High-endurance Flash applies to low byte of each address in the range. 2013-2015 Microchip Technology Inc. DS40001722C-page 17 PIC16(L)F1703/7 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1703/7 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.2.1.1 RETLW Instruction Stack Level 0 Stack Level 1 The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. Stack Level 15 EXAMPLE 3-1: Reset Vector 0000h Interrupt Vector 0004h 0005h On-chip Program Memory 3.2.1 Page 0 07FFh 0800h constants BRW RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 3.2.1.2 Rollover to Page 1 7FFFh Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. The high directive will set bit<7> if a label points to a location in program memory. DS40001722C-page 18 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 2013-2015 Microchip Technology Inc. DS40001722C-page 19 PIC16(L)F1703/7 3.3 Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.7 “Indirect Addressing” for more information. Data memory uses a 12-bit address. The upper five bits of the address define the Bank address and the lower seven bits select the registers/RAM in that bank. DS40001722C-page 20 3.3.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Table 3-2. For detailed information, see Table 3-9. TABLE 3-2: CORE REGISTERS Addresses BANKx x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 3.3.1.1 STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. 3.4 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 25.0 “Instruction Set Summary”). Note: The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. Register Definitions: Status REGISTER 3-1: STATUS: STATUS REGISTER U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u — — — TO PD Z DC(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT Time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. 2013-2015 Microchip Technology Inc. DS40001722C-page 21 PIC16(L)F1703/7 3.4.1 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.4.2 FIGURE 3-2: 7-bit Bank Offset 0Bh 0Ch GENERAL PURPOSE RAM Core Registers (12 bytes) Special Function Registers (20 bytes maximum) 1Fh 20h Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.7.2 “Linear Data Memory” for more information. 3.4.3 Memory Region 00h There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 3.4.2.1 BANKED MEMORY PARTITIONING General Purpose RAM (80 bytes maximum) COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh 3.4.4 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Tables 3-3 through 3-8. DS40001722C-page 22 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. TABLE 3-3: PIC16(L)F1703/7 MEMORY MAP (BANKS 0-7) BANK 0 000h BANK 1 080h Core Registers (Table 3-2) 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh PORTA PORTB PORTC — — PIR1 PIR2 PIR3 — TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON — — — 020h Core Registers (Table 3-2) 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh BANK 3 180h Core Registers (Table 3-2) 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh LATA LATB LATC — — — — — — — BORCON FVRCON — — — — ZCD1CON — — — 120h General Purpose Register 80 Bytes General Purpose Register 80 Bytes BANK 4 200h Core Registers (Table 3-2) 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h Core Registers (Table 3-2) ANSELA ANSELB ANSELC — — PMADR PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 — — — — — — — — 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh — 220h 16Fh 1EFh 26Fh 0F0h 170h 1F0h 270h Accesses 70h - 7Fh 0FFh Accesses 70h - 7Fh 17Fh Accesses 70h - 7Fh 1FFh WPUA WPUB WPUC — — SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON1 SSP1CON2 SSP1CON3 — — — — — — — 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h 27Fh 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh — 320h 2FFh SLRCONA SLRCONB SLRCONC — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 36Fh 370h Accesses 70h - 7Fh Unimplemented 3EFh 3F0h Accesses 70h - 7Fh 37Fh INLVLA INLVLB INLVLC — — IOCAP IOCAN IOCAF IOCBP IOCBN IOCBF IOCCP IOCCN IOCCF — — — — — — 3A0h Unimplemented Unimplemented 2F0h BANK 7 380h Core Registers (Table 3-2) ODCONA ODCONB ODCONC — — CCPR1L CCPR1H CCP1CON — — — — CCPR2 CCPR2L CCPR2H CCP2CON — — — — 2EFh Accesses 70h - 7Fh BANK 6 300h Core Registers (Table 3-2) Unimplemented Unimplemented 0EFh Common RAM 70h - 7Fh BANK 5 280h Accesses 70h - 7Fh 3FFh DS40001722C-page 23 PIC16(L)F1703/7 General Purpose Register 80 Bytes 07Fh TRISA TRISB TRISC — — PIE1 PIE2 PIE3 — OPTION_REG PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 ADCON2 0A0h 06Fh 070h BANK 2 100h PIC16(L)F1703/7 MEMORY MAP (BANKS 8-15) BANK 8 400h BANK 9 480h Core Registers (Table 3-2) 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h 4EFh 4F0h Accesses 70h - 7Fh 2013-2015 Microchip Technology Inc. 47Fh — — — — — — — — — — — — — — — — — — — — 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h — — — — — OPA1CON — — — OPA2CON — — — — — — — — — — 56Fh 570h 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h — — — — — — — — — — — — — — — — — — 5EFh 5F0h 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h — — — — — — — — — — — — — — — — — — — — 66Fh 670h 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h — — — — — — — — — — — — — — — — — — — — 6EFh 6F0h 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h Unimplemented 76Fh 770h Accesses 70h - 7Fh 6FFh BANK 15 780h Core Registers (Table 3-2) Unimplemented Accesses 70h - 7Fh 67Fh BANK 14 700h Core Registers (Table 3-2) Unimplemented Accesses 70h - 7Fh 5FFh BANK 13 680h Core Registers (Table 3-2) Unimplemented Accesses 70h - 7Fh 57Fh BANK 12 600h Core Registers (Table 3-2) Unimplemented Accesses 70h - 7Fh 4FFh BANK 11 580h Core Registers (Table 3-2) Unimplemented Unimplemented 46Fh 470h BANK 10 500h Unimplemented 7EFh 7F0h Accesses 70h - 7Fh 77Fh — — — — — — — — — — — — — — — — — — — — Accesses 70h - 7Fh 7FFh PIC16(L)F1703/7 DS40001722C-page 24 TABLE 3-4: 2013-2015 Microchip Technology Inc. TABLE 3-5: PIC16(L)F1703/7 MEMORY MAP (BANKS 16-23) BANK 16 800h BANK 17 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 89Fh 8A0h Unimplemented 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h Unimplemented 8EFh 8F0h Accesses 70h - 7Fh 87Fh Core Registers (Table 3-2) 98Bh 98Ch 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h Core Registers (Table 3-2) A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h Unimplemented 9EFh 9F0h 96Fh 970h Accesses 70h - 7Fh 97Fh — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h Core Registers (Table 3-2) B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h Unimplemented Accesses 70h - 7Fh A7Fh — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) B8Bh B8Ch B8Dh B8Eh B8Fh B90h B91h B92h B93h B94h B95h B96h B97h B98h B99h B9Ah B9Bh B9Ch B9Dh B9Eh B9Fh BA0h Unimplemented Unimplemented Accesses 70h - 7Fh B7Fh — — — — — — — — — — — — — — — — — — — — BEFh BF0h B6Fh B70h Accesses 70h - 7Fh AFFh BANK 23 B80h B00h AEFh AF0h A6Fh A70h BANK 22 Core Registers (Table 3-2) Unimplemented Accesses 70h - 7Fh 9FFh BANK 21 A80h A00h Core Registers (Table 3-2) Unimplemented Accesses 70h - 7Fh 8FFh — — — — — — — — — — — — — — — — — — — — BANK 20 Accesses 70h - 7Fh BFFh DS40001722C-page 25 PIC16(L)F1703/7 86Fh 870h — — — — — — — — — — — — — — — — — — — — BANK 19 980h 900h 880h Core Registers (Table 3-2) BANK 18 PIC16(L)F1703/7 MEMORY MAP (BANKS 24-31) BANK 24 C00h BANK 25 C80h Core Registers (Table 3-2) C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Unimplemented 2013-2015 Microchip Technology Inc. C6Fh C70h — — — — — — — — — — — — — — — — — — — — CEFh CF0h D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h — — — — — — — — — — — — — — — — — — — — D6Fh D70h D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h — — — — — — — — — — — — — — — — — — — — BANK 29 E80h Core Registers (Table 3-2) BANK 30 F00h Core Registers (Table 3-2) BANK 31 F80h Core Registers (Table 3-2) Core Registers (Table 3-2) E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h See Table 3-7 for E18h register mapping E19h details E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h See Table 3-7 for E98h register mapping E99h details E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h See Table 3-7 for F18h register mapping F19h details F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h See Table 3-8 for F98h register mapping F99h details F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h E6Fh E70h EEFh EF0h F6Fh F70h FEFh FF0h Unimplemented DEFh DF0h Accesses 70h - 7Fh D7Fh BANK 28 E00h Core Registers (Table 3-2) Unimplemented Accesses 70h - 7Fh CFFh BANK 27 D80h Core Registers (Table 3-2) Unimplemented Accesses 70h - 7Fh C7Fh BANK 26 D00h Accesses 70h - 7Fh DFFh Accesses 70h - 7Fh E7Fh Accesses 70h - 7Fh EFFh Accesses 70h - 7Fh F7Fh Accesses 70h - 7Fh FFFh PIC16(L)F1703/7 DS40001722C-page 26 TABLE 3-6: PIC16(L)F1703/7 TABLE 3-7: PIC16(L)F1703/7 MEMORY MAP (BANKS 28-31) Bank 28 E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h E21h E22h E23h E24h E25h E26h E27h E28h E29h E2Ah E2Bh E2Ch E2Dh E2Eh E2Fh E30h E31h E32h E33h E34h E35h E36h E37h E38h E39h E3Ah E3Bh E3Ch E3Dh E3Eh E3Fh E40h — — — PPSLOCK INTPPS T0CKIPPS T1CKIPPS T1GPPS CCP1PPS CCP2PPS — — — — — — — — — — SSPCLKPPS SSPDATPPS SSPSSPPS — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Bank 29 E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h EA1h EA2h EA3h EA4h EA5h EA6h EA7h EA8h EA9h EAAh EABh EACh EADh EAEh EAFh EB0h EB1h EB2h EB3h EB4h EB5h EB6h EB7h EB8h EB9h EBAh EBBh EBCh EBDh EBEh EBFh EC0h — E6Fh Legend: Note 1: — — — — RA0PPS RA1PPS RA2PPS — RA4PPS RA5PPS — — — — — — RB4PPS(1) RB5PPS(1) RB6PPS(1) RB7PPS(1) RC0PPS RC1PPS RC2PPS RC3PPS RC4PPS RC5PPS RC6PPS(1) RC7PPS(1) — — — — — — — — — — — — — — — — — — — — — — — — Bank 30 F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F21h F22h F23h F24h F25h F26h F27h F28h F29h F2Ah F2Bh F2Ch F2Dh F2Eh F2Fh F30h F31h F32h F33h F34h F35h F36h F37h F38h F39h F3Ah F3Bh F3Ch F3Dh F3Eh F3Fh F40h — — EEFh — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — F6Fh = Unimplemented data memory locations, read as ‘0’, Only available on PIC16(L)F1707 devices 2013-2015 Microchip Technology Inc. DS40001722C-page 27 PIC16(L)F1703/7 TABLE 3-8: PIC16(L)F1703/7 MEMORY MAP, BANK 31 Bank 31 F8Ch FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: Unimplemented Read as ‘0’ STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — STKPTR TOSL TOSH = Unimplemented data memory locations, read as ‘0’, DS40001722C-page 28 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 3.4.5 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-9 can be addressed from any Bank. TABLE 3-9: Addr Name CORE FUNCTION REGISTERS SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0-31 x00h or INDF0 x80h Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or INDF1 x81h Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or PCL x82h Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 ---1 1000 ---q quuu x03h or STATUS x83h — — — TO PD Z DC C x04h or FSR0L x84h Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h or FSR0H x85h Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h or FSR1L x86h Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h or FSR1H x87h Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 ---0 0000 ---0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 0000 000x 0000 000u x08h or BSR x88h — x09h or WREG x89h — BSR4 BSR3 BSR2 BSR1 BSR0 Working Register x0Ah or PCLATH x8Ah — x0Bh or INTCON x8Bh GIE Legend: — Write Buffer for upper seven bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. 2013-2015 Microchip Technology Inc. DS40001722C-page 29 2013-2015 Microchip Technology Inc. TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx --uu uuuu Bank 0 00Ch PORTA (3) 00Dh PORTB RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ---- 00Eh PORTC RC7(3) RC6(3) RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 00Fh — Unimplemented — — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF — — SSP1IF CCP1IF TMR2IF TMR1IF 00-- 0000 00-- 0000 012h PIR2 — — — — BCL1IF — — CCP2IF ---- 0--0 ---- 0--0 013h PIR3 — — — ZCDIF — — — — ---0 ---- ---0 ---- — — — 014h Unimplemented TMR0 Timer0 Module Register xxxx xxxx uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 018h T1CON 0000 -0-0 uuuu -u-u 019h T1GCON 0000 0x00 uuuu uxuu 01Ah TMR2 Holding Register for the Least Significant Byte of the 16-bit TMR2 Register 0000 0000 0000 0000 01Bh PR2 Holding Register for the Most Significant Byte of the 16-bit TMR2 Register 1111 1111 1111 1111 01Ch T2CON -000 0000 -000 0000 — — 01Dh to 01Fh Legend: DS40001722C-page 30 Note 1: 2: 3: 4: — TMR1CS<1:0> TMR1GE — T1GPOL T1CKPS<1:0> T1GTM T1GSPM T2OUTPS<3:0> — T1SYNC T1GGO/ DONE T1GVAL TMR2ON Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1703 only. PIC16(L)F1707 only. Unimplemented on PIC16LF1703/7. — TMR1ON T1GSS<1:0> T2CKPS<1:0> PIC16(L)F1703/7 015h 2013-2015 Microchip Technology Inc. TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — TRISA5 TRISA4 —(1) Value on POR, BOR Value on all other Resets Bank 1 TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- 08Eh TRISC TRISC7(3) TRISC6(3) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111 — — 08Ch TRISA (3) 08Fh 090h — Unimplemented — Unimplemented — — — SSP1IE CCP1IE TMR2IE TMR1IE 00-- 0000 0000 0000 — — BCL1IE — — CCP2IE ---- 0--0 000- 0000 — ZCDIE — — — — ---0 ---- ---0 ---- PSA PIE1 TMR1GIE ADIE — 092h PIE2 — — 093h PIE3 — — 091h 094h — Unimplemented 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE 096h PCON STKOVF STKUNF — RWDT 097h WDTCON — — — RMCLR RI POR WDTPS<4:0> OSCTUNE — 099h OSCCON SPLLEN 09Ah OSCSTAT — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR 09Bh ADRES — — — — — — — 09Bh ADRESL 09Ch ADRESH 09Dh ADCON0 — 09Eh ADCON1 ADFM 09Fh ADCON2 DS40001722C-page 31 Note 1: 2: 3: 4: — 1111 1111 BOR 00-1 11qq qq-q qquu SWDTEN --01 0110 --01 0110 TUN<5:0> --00 0000 --00 0000 0011 1-00 0011 1-00 HFIOFS -qq0 0q0q qqqq -q0q — — — ADC Result Register Low xxxx xxxx uuuu uuuu ADC Result Register High xxxx xxxx uuuu uuuu -000 0000 -000 0000 0000 -000 0000 -000 0000 ---- 0000 ---- IRCF<3:0> — CHS<4:0> ADCS<2:0> TRIGSEL<3:0> SCS<1:0> GO/DONE — ADNREF — — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1703 only. PIC16(L)F1707 only. Unimplemented on PIC16LF1703/7. ADON ADPREF<1:0> — — PIC16(L)F1703/7 098h Legend: — 1111 1111 PS<2:0> Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA 10Dh LATB(3) 10Eh LATC — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- uuuu ---- LATC7(3) LATC6(3) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu 10Fh — Unimplemented — — 110h — Unimplemented — — 111h — Unimplemented — — 112h — Unimplemented — — 113h — Unimplemented — — 114h — Unimplemented — — 115h — Unimplemented — — 10-- ---q uu-- ---u 0q00 0000 0q00 0000 116h BORCON SBOREN BORFS — — 117h FVRCON FVREN FVRRDY TSEN TSRNG — — CDAFVR<1:0> — BORRDY ADFVR<1:0> 118h — Unimplemented — — 119h — Unimplemented — — 11Ah — Unimplemented — — 11Bh — Unimplemented — — 0-x0 --00 0-x0 --00 11Ch ZCD1CON ZCD1EN — ZCD1OUT ZCD1POL — — ZCD1INTP ZCD1INTN 11Dh — Unimplemented — — 11Eh — Unimplemented — — 11Fh — Unimplemented — — Legend: 2013-2015 Microchip Technology Inc. Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1703 only. PIC16(L)F1707 only. Unimplemented on PIC16LF1703/7. PIC16(L)F1703/7 DS40001722C-page 32 TABLE 3-10: 2013-2015 Microchip Technology Inc. TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 3 18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 -111 ---1 -111 18Dh ANSELB(3) — — ANSB5 ANSB4 — — — — --11 ---- --11 ---- 18Eh ANSELC ANSC7(3) ANSC6(3) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 11-- 1111 11-- 1111 18Fh — — — 190h — Unimplemented Unimplemented 191h PMADRL 192h PMADRH 193h PMDATL 194h PMDATH — — 195h PMCON1 — CFGS 196h PMCON2 197h VREGCON(4) Program Memory Address Register Low Byte —(1) Program Memory Address Register High Byte Program Memory Read Data Register Low Byte Program Memory Read Data Register High Byte — — 0000 0000 1000 0000 1000 0000 xxxx xxxx uuuu uuuu --xx xxxx --uu uuuu LWLO FREE WRERR WREN WR RD -000 x000 -000 q000 0000 0000 0000 0000 — — — — VREGPM Reserved ---- --01 ---- --01 Program Memory Control Register 2 — — 0000 0000 — Unimplemented — — 199h — Unimplemented — — 19Ah — Unimplemented — — 19Bh — Unimplemented — — 19Ch — Unimplemented — — 19Dh — Unimplemented — — 19Eh — Unimplemented — — 19Fh — Unimplemented — — Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1703 only. PIC16(L)F1707 only. Unimplemented on PIC16LF1703/7. DS40001722C-page 33 PIC16(L)F1703/7 198h Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 4 20Ch WPUA 20Dh WPUB(3) 20Eh WPUC — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 --11 1111 WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ---- WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 (3) WPUC7 (3) WPUC6 1111 1111 1111 1111 20Fh — Unimplemented — — 210h — Unimplemented — — xxxx xxxx uuuu uuuu 211h SSP1BUF 212h SSP1ADD ADD<7:0> xxxx xxxx uuuu uuuu 213h SSP1MSK MSK<7:0> xxxx xxxx uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 Synchronous Serial Port Receive Buffer/Transmit Register 214h SSP1STAT SMP CKE D/A P 215h SSP1CON1 WCOL SSPOV SSPEN CKP 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 — — 218h — 21Fh Legend: Note 1: 2: 3: 4: — S R/W UA BF SSPM Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1703 only. PIC16(L)F1707 only. Unimplemented on PIC16LF1703/7. PIC16(L)F1703/7 DS40001722C-page 34 TABLE 3-10: 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 5 28Ch ODCONA 28Dh ODCONB(3) 28Eh ODCONC 28Fh — — — ODA5 ODA4 — ODA2 ODA1 ODA0 --00 -000 --00 -000 ODB7 ODB6 ODB5 ODB4 — — — — 0000 ---- 0000 ---- ODC7(3) ODC6(3) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 0000 0000 0000 — — Unimplemented 290h — 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) 293h CCP1CON 294h — 297h — Unimplemented — — DC1B<1:0> CCP1M<3:0> Unimplemented — — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 — — 298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx uuuu uuuu 299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu 29Ah CCP2CON --00 0000 --00 0000 — — 29Bh — 29Fh Legend: — DC2B<1:0> CCP2M<3:0> Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1703 only. PIC16(L)F1707 only. Unimplemented on PIC16LF1703/7. DS40001722C-page 35 PIC16(L)F1703/7 Note 1: 2: 3: 4: — — Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 6 30Ch SLRCONA 30Dh SLRCONB(3) 30Eh SLRCONC 30Fh — 31Fh — — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 --11 -111 --11 -111 SLRB7 SLRB6 SLRB5 SLRB4 — — — — 1111 ---- 1111 ---- SLRC7(3) SLRC6(3) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 1111 1111 1111 1111 — — --11 1111 --11 1111 Unimplemented Bank 7 38Ch INLVLA (3) — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 38Dh INLVLB INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 1111 ---- 1111 ---- 38Eh INLVLC INLVLC7(3) INLVLC6(3) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111 38Fh — Unimplemented — — 390h — Unimplemented — — 391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000 392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 394h IOCBP(3) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 0000 ---- 0000 ---- 395h IOCBN(3) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 0000 ---- 0000 ---- 396h IOCBF(3) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 0000 ---- 0000 ---- 397h IOCCP IOCCP7(3) IOCCP6(3) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0000 0000 0000 398h IOCCN IOCCN7(3) IOCCN6(3) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000 IOCCF (3) (3) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000 399h 2013-2015 Microchip Technology Inc. 39Ah — 39Fh IOCCF7 IOCCF6 — Unimplemented — — — Unimplemented — — Bank 8 40Ch — 41Fh Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1703 only. PIC16(L)F1707 only. Unimplemented on PIC16LF1703/7. PIC16(L)F1703/7 DS40001722C-page 36 TABLE 3-10: 2013-2015 Microchip Technology Inc. TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — 00-0 --00 00-0 --00 — — 00-0 --00 00-0 --00 Name Bit 7 — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 9 48Ch to 49Fh Bank 10 50Ch — 510h 511h OPA1CON 512h — 514h 515h — OPA2CON 516h — 51Fh OPA1EN OPA1SP — OPA1UG — — OPA1PCH<1:0> Unimplemented OPA2EN OPA2SP — OPA2UG — — OPA2PCH<1:0> — Unimplemented — — — Unimplemented — — Bank 11-27 58Ch/ 59Fh — D8Ch/ D9Fh Legend: DS40001722C-page 37 PIC16(L)F1703/7 Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1703 only. PIC16(L)F1707 only. Unimplemented on PIC16LF1703/7. Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 — Unimplemented Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — Bank 28 E0Ch — E0Eh E0Fh PPSLOCK — — — ---- ---0 ---- ---0 E10h INTPPS — — — INTPPS<4:0> ---0 0010 ---u uuuu E11h T0CKIPPS — — — T0CKIPPS<4:0> ---0 0010 ---u uuuu E12h T1CKIPPS — — — T1CKIPPS<4:0> ---0 0101 ---u uuuu E13h T1GPPS — — — T1GPPS<4:0> ---0 0100 ---u uuuu E14h CCP1PPS — — — CCP1PPS<4:0> ---1 0101 ---u uuuu E15h CCP2PPS — — — CCP2PPS<4:0> ---1 0011 ---u uuuu — — E16h to E1Fh E20h E21h E22h E23h to E6Fh 2013-2015 Microchip Technology Inc. Legend: Note 1: 2: 3: 4: — SSPCLKPPS SSPDATPPS SSPSSPPS — — — — Unimplemented — PPSLOCKED — — — SSPCLKPPS<4:0> ---1 0000(3) ---u uuuu — — — SSPCLKPPS<4:0> ---0 1110(4) ---u uuuu — — — SSPDATPPS<4:0> ---1 0001(3) ---u uuuu (4) — — — SSPDATPPS<4:0> ---0 1100 ---u uuuu — — — SSPSSPPS<4:0> ---1 0011(3) ---u uuuu — — — SSPSSPPS<4:0> ---1 0110(4) ---u uuuu — — Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1703 only. PIC16(L)F1707 only. Unimplemented on PIC16LF1703/7. PIC16(L)F1703/7 DS40001722C-page 38 TABLE 3-10: 2013-2015 Microchip Technology Inc. TABLE 3-10: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 6 Value on POR, BOR Value on all other Resets — — RA0PPS<4:0> ---0 0000 ---u uuuu — RA1PPS<4:0> ---0 0000 ---u uuuu — RA2PPS<4:0> ---0 0000 ---u uuuu — — Name Bit 7 Bit 5 E8Ch — E8Fh — Unimplemented E90h RA0PPS — — — E91h RA1PPS — — E92h RA2PPS — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 29 E93h — E94h Unimplemented — — — RA4PPS<4:0> ---0 0000 ---u uuuu RA5PPS — — — RA5PPS<4:0> ---0 0000 ---u uuuu E96h to E9Fh — — — EA0h RC0PPS — — — RC0PPS<4:0> ---0 0000 ---u uuuu EA1h RC1PPS — — — RC1PPS<4:0> ---0 0000 ---u uuuu EA2h RC2PPS — — — RC2PPS<4:0> ---0 0000 ---u uuuu EA3h RC3PPS — — — RC3PPS<4:0> ---0 0000 ---u uuuu EA4h RC4PPS — — — RC4PPS<4:0> ---0 0000 ---u uuuu EA5h RC5PPS — — — RC5PPS<4:0> ---0 0000 ---u uuuu EA6h — EEFh — Unimplemented — — — Unimplemented — — Unimplemented Bank 30 F0Ch — F6Fh Legend: DS40001722C-page 39 Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1703 only. PIC16(L)F1707 only. Unimplemented on PIC16LF1703/7. PIC16(L)F1703/7 RA4PPS E95h Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 — Unimplemented Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — ---- -xxx ---- -xxx xxxx xxxx uuuu uuuu ---x xxxx ---u uuuu -xxx xxxx uuuu uuuu Bank 31 F8Eh to FE3h FE4h STATUS_ FE5h WREG_ SHAD FE6h BSR_ SHAD — — — — Z — DC Working Register Shadow — — — Bank Select Register Shadow C SHAD FE7h PCLATH_ SHAD FE8h FSR0L_ SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu FE9h FSR0H_ SHAD Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu FEAh FSR1L_ SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu FEBh FSR1H_ SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu FECh — FEDh STKPTR FEEh TOSL FEFh 2013-2015 Microchip Technology Inc. Legend: Note 1: 2: 3: 4: TOSH — Program Counter Latch High Register Shadow Unimplemented — — — Current Stack Pointer Top of Stack Low byte — Top of Stack High byte x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1703 only. PIC16(L)F1707 only. Unimplemented on PIC16LF1703/7. — — ---x xxxx ---x xxxx xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu PIC16(L)F1703/7 DS40001722C-page 40 TABLE 3-10: PIC16(L)F1703/7 3.5 3.5.3 PCL and PCLATH COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). FIGURE 3-3: If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. PC LOADING OF PC IN DIFFERENT SITUATIONS 14 PCH 6 7 14 PCH PCL 0 PCLATH PC 8 ALU Result PCL 0 4 0 11 OPCODE <10:0> PC 14 PCH PCL 0 CALLW 6 PCLATH PC Instruction with PCL as Destination GOTO, CALL 6 PCLATH 0 14 7 0 PCH 8 W PCL 0 BRW PC + W 14 PCH 3.5.4 BRANCHING The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. 15 PC The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. PCL 0 BRA 15 PC + OPCODE <8:0> 3.5.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 3.5.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556). 2013-2015 Microchip Technology Inc. DS40001722C-page 41 PIC16(L)F1703/7 3.6 3.6.1 Stack The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. All devices have a 16-level x 15-bit wide hardware stack (refer to Figure 3-1). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note: Note: Care should be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time, STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR. There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK Reference Figure 3-4 through Figure 3-7 for examples of accessing the stack. ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL DS40001722C-page 42 0x1F 0x0000 STKPTR = 0x1F Stack Reset Enabled (STVREN = 1) 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-6: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL 2013-2015 Microchip Technology Inc. 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x06 DS40001722C-page 43 PIC16(L)F1703/7 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.6.2 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.7 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory DS40001722C-page 44 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x0FFF Reserved 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. 2013-2015 Microchip Technology Inc. DS40001722C-page 45 PIC16(L)F1703/7 3.7.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing 4 BSR 0 6 Indirect Addressing From Opcode 0 7 0 Bank Select Location Select FSRxH 0 0 0 7 FSRxL 0 0 Bank Select 00000 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 Location Select 0x00 0x7F DS40001722C-page 46 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 3.7.2 3.7.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 3-10: 7 FSRnH 0 0 1 LINEAR DATA MEMORY MAP 0 7 FSRnL 0 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 3-11: 7 1 FSRnH PROGRAM FLASH MEMORY MAP 0 Location Select Location Select 0x2000 7 FSRnL 0x8000 0 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Program Flash Memory (low 8 bits) Bank 2 0x16F 0xF20 Bank 30 0x29AF 2013-2015 Microchip Technology Inc. 0xF6F 0xFFFF 0x7FFF DS40001722C-page 47 PIC16(L)F1703/7 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. DS40001722C-page 48 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 U-1 — U-1 R/P-1 — CLKOUTEN R/P-1 U-1 R/P-1 BOREN<1:0> — bit 8 bit 13 R/P-1 CP (1) R/P-1 R/P-1 MCLRE PWRTE R/P-1 R/P-1 R/P-1 WDTE<1:0> R/P-1 — R/P-1 FOSC<1:0> bit 0 bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13-12 Unimplemented: Read as ‘1’ bit 11 CLKOUTEN: Clock Out Enable bit 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 Unimplemented: Read as ‘1’ bit 7 CP: Code Protection bit(1) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUE3 bit bit 5 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled bit 2 Unimplemented: Read as ‘1’ bit 1-0 FOSC<1:0>: Oscillator Selection bits 11 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 10 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 01 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin 00 = INTOSC oscillator: I/O function on CLKIN pin Note 1: The entire Flash program memory will be erased when the code protection is turned off during an erase. When a Bulk Erase Program Memory Command is executed, the entire program Flash memory and configuration memory will be erased. 2013-2015 Microchip Technology Inc. DS40001722C-page 49 PIC16(L)F1703/7 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 LVP (1) R/P-1 DEBUG R/P-1 (2) LPBOR R/P-1 (3) BORV R/P-1 R/P-1 STVREN PLLEN bit 13 bit 8 R/P-1 U-1 U-1 U-1 U-1 R/P-1 ZCDDIS — — — — PPS1WAY R/P-1 bit 7 R/P-1 WRT<1:0> bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(2) 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 LPBOR: Low-Power BOR Enable bit 1 = Low-Power Brown-out Reset is disabled 0 = Low-Power Brown-out Reset is enabled bit 10 BORV: Brown-out Reset Voltage Selection bit(3) 1 = Brown-out Reset voltage (VBOR), low trip point selected 0 = Brown-out Reset voltage (VBOR), high trip point selected bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7 ZCDDIS: ZCD Disable bit 1 = ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON 0 = ZCD always enabled bit 6-3 Unimplemented: Read as ‘1’ bit 2 PPS1WAY: PPSLOCK Bit One-Way Set Enable bit 1 = The PPSLOCK bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented 0 = The PPSLOCK bit can be set and cleared as needed (provided an unlocking sequence is executed) bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 4 kW Flash memory 11 = Write protection off 10 = 000h to 1FFh write protected, 200h to FFFh may be modified by PMCON control 01 = 000h to 7FFh write protected, 800h to FFFh may be modified by PMCON control 00 = 000h to FFFh write protected, no addresses may be modified by PMCON control Note 1: 2: 3: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. See VBOR parameter for specific trip point voltages. DS40001722C-page 50 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.4 “Write Protection” for more information. 4.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected. 4.5 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16(L)F170X Memory Programming Specification” (DS41683). 2013-2015 Microchip Technology Inc. DS40001722C-page 51 PIC16(L)F1703/7 4.6 Device ID and Revision ID The 14-bit device ID word is located at 8006h and the 14-bit revision ID is located at 8005h. These locations are read-only and cannot be erased or modified. See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.7 Register Definitions: Device and Revision REGISTER 4-3: DEVID: DEVICE ID REGISTER R R R R R R DEV<13:8> bit 13 R R bit 8 R R R R R R DEV<7:0> bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 ‘0’ = Bit is cleared DEV<13:0>: Device ID bits Device DEVID<13:0> Values PIC16F1703 11 0000 0100 0011 (3043h) PIC16LF1703 11 0000 0100 0101 (3045h) PIC16F1707 11 0000 0100 0010 (3042h) PIC16LF1707 11 0000 0100 0100 (3044h) REGISTER 4-4: REVID: REVISION ID REGISTER R R R R R R REV<13:8> bit 13 R R bit 8 R R R R R R REV<7:0> bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 ‘0’ = Bit is cleared REV<13:0>: Revision ID bits DS40001722C-page 52 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 5.0 RESETS There are multiple ways to reset this device: • • • • • • • • • A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Rev. 10-000006A 8/14/2013 ICSP™ Programming Mode Exit RESET Instruction Stack Underflow Stack Overlfow MCLRE VPP/MCLR Sleep WDT Time-out Device Reset Power-on Reset VDD BOR Active(1) Brown-out Reset LPBOR Reset Note 1: R LFINTOSC Power-up Timer PWRTE See Table 5-1 for BOR active conditions. 2013-2015 Microchip Technology Inc. DS40001722C-page 53 PIC16(L)F1703/7 5.1 Power-On Reset (POR) 5.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. 5.1.1 • • • • POWER-UP TIMER (PWRT) The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration Words. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). TABLE 5-1: The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are: BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to Table 5-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 5-2 for more information. BOR OPERATING MODES BOREN<1:0> SBOREN Device Mode BOR Mode 11 X X Active Awake Active 10 X Sleep Disabled 1 X Active 0 X Disabled X X Disabled 01 00 Instruction Execution upon: Release of POR or Wake-up from Sleep Waits for BOR ready(1) (BORRDY = 1) Waits for BOR ready (BORRDY = 1) Waits for BOR ready(1) (BORRDY = 1) Begins immediately (BORRDY = x) Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. 5.2.1 BOR IS ALWAYS ON When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 5.2.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. 5.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. DS40001722C-page 54 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 5-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 5.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’. Register Definitions: BOR Control REGISTER 5-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS(1) — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Words 01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect. If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control): 1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Words. 2013-2015 Microchip Technology Inc. DS40001722C-page 55 PIC16(L)F1703/7 5.4 Low-Power Brown-Out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 5-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 5-2. 5.4.1 ENABLING LPBOR The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled. 5.4.1.1 LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON register and to the power control block. 5.5 MCLR 5.6 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section 9.0 “Watchdog Timer (WDT)” for more information. 5.7 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Table 5-4 for default conditions after a RESET instruction has occurred. 5.8 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 3.6.2 “Overflow/Underflow Reset” for more information. 5.9 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 5-2). 5.10 TABLE 5-2: The Power-up Timer is controlled by the PWRTE bit of Configuration Words. MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 5.5.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Note: 5.5.2 A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 11.1 “PORTA Registers” for more information. DS40001722C-page 56 Power-Up Timer The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. 5.11 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator start-up timer runs to completion (if required for oscillator source). MCLR must be released (if enabled). The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for more information. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution after 10 FOSC cycles (see Figure 5-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 5-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2013-2015 Microchip Technology Inc. DS40001722C-page 57 PIC16(L)F1703/7 5.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset conditions of these registers. TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during normal operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 5-4: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 ---1 0uuu uu-- uuuu ---u uuuu uu-- u0uu Condition Interrupt Wake-up from Sleep RESET Instruction Executed PC + 1 (1) 0000h Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. DS40001722C-page 58 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 5.13 Power Control (PCON) Register The PCON register bits are shown in Register 5-2. The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) 5.14 Register Definitions: Power Control REGISTER 5-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 STKOVF STKUNF — R/W/HC-1/q R/W/HC-1/q RWDT R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u RI POR BOR RMCLR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware bit 5 Unimplemented: Read as ‘0’ bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (cleared by hardware) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2013-2015 Microchip Technology Inc. DS40001722C-page 59 PIC16(L)F1703/7 TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 55 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 59 STATUS — — — TO PD Z DC C 21 WDTCON — — SWDTEN 92 WDTPS<4:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. DS40001722C-page 60 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 6.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 6.1 Overview The oscillator module has a limited variety of clock sources and selection features that allow it to be used in applications while maximizing performance and minimizing power consumption. Figure 6-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, or one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: • Selectable system clock source between external or internal sources via software. The oscillator module can be configured in one of the following clock modes. 1. 2. 3. 4. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz) ECM – External Clock Medium Power mode (0.5 MHz to 4 MHz) ECH – External Clock High-Power mode (4 MHz to 32 MHz) INTOSC – Internal oscillator (31 kHz to 32 MHz) Clock Source modes are selected by the FOSC<1:0> bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered. The ECH, ECM, and ECL clock modes rely on an external logic level signal as the device clock source. Each mode is optimized for a different frequency range. The INTOSC internal oscillator block produces low, medium, and high-frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 6-1). A wide selection of device clock frequencies may be derived from these three clock sources. 2013-2015 Microchip Technology Inc. DS40001722C-page 61 PIC16(L)F1703/7 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 6-1: Timer1 Clock Source Option for other modules T1CKI T1OSC 01 CLKIN External Oscillator 0 Sleep 0 1 00 PRIMUX 4 x PLL 1 PLLMUX IRCF<3:0> 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz 500 kHz Source 16 MHz (HFINTOSC) 500 kHz (MFINTOSC) 31 kHz Source INTOSC SCS<1:0> 31 kHz 0000 WDT, PWRT 31 kHz (LFINTOSC) Inputs SCS FOSC<1:0> PLLEN or SPLLEN 0 =00 1 =00 ≠00 ≠00 X DS40001722C-page 62 0 1X 1111 MUX HFPLL Postscaler Internal Oscillator Block FOSC To CPU and Peripherals Outputs IRCF PRIMUX PLLMUX x 1 0 =1110 1 1 ≠1110 1 0 x 0 0 1 x 0 1 X X X X 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 6.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on an external clock signal such as an oscillator module. Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase-Lock Loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 6.3 “Clock Switching” for additional information. 6.2.1 EXTERNAL CLOCK SOURCES There is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. FIGURE 6-2: Clock from Ext. System FOSC/4 or I/O(1) Note 1: EXTERNAL CLOCK (EC) MODE OPERATION CLKIN PIC® MCU CLKOUT Output depends upon CLKOUTEN bit of the Configuration Words. An external clock source can be used as the device system clock by performing one of the following actions: • Program the FOSC<1:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to an external clock source determined by the value of the FOSC bits. See Section 6.3 “Clock Switching”for more information. 6.2.1.1 EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the CLKIN input. CLKOUT is available for general purpose I/O or CLKOUT. Figure 6-2 shows the pin connections for EC mode. EC mode has three power modes to select from through Configuration Words: • ECH – High power, 4-32 MHz • ECM – Medium power, 0.5-4 MHz • ECL – Low power, 0-0.5 MHz 2013-2015 Microchip Technology Inc. DS40001722C-page 63 PIC16(L)F1703/7 6.2.1.2 4x PLL The oscillator module contains a 4x PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4x PLL must fall within specifications. See the PLL Clock Timing Specifications in Table 26-9. The 4x PLL may be enabled for use by one of two methods: 1. 2. Program the PLLEN bit in Configuration Words to a ‘1’. Write the SPLLEN bit in the OSCCON register to a ‘1’. If the PLLEN bit in Configuration Words is programmed to a ‘1’, then the value of SPLLEN is ignored. 6.2.2 INTERNAL CLOCK SOURCES The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<1:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 6.3 “Clock Switching” for more information. In INTOSC mode, CLKIN is available for general purpose I/O. CLKOUT is available for general purpose I/O or CLKOUT. The function of the CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. The internal oscillator block has two independent oscillators and a dedicated Phase-Lock Loop, HFPLL that can produce one of three internal system clock sources. 1. 2. 3. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase-Lock Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. DS40001722C-page 64 6.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 6-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of multiple frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The HFINTOSC is enabled by: • Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and • FOSC<1:0> = 00, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ A fast start-up oscillator allows internal circuits to power up and stabilize before switching to HFINTOSC. The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running. The High-Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. 6.2.2.2 MFINTOSC The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 6-3). The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The MFINTOSC is enabled by: • Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and • FOSC<1:0> = 00, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The Medium-Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 6.2.2.3 Internal Oscillator Frequency Adjustment The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 6-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. 6.2.2.4 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a multiplexer (see Figure 6-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: 6.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The postscaled output of the 16 MHz HFINTOSC, 500 kHz MFINTOSC, and 31 kHz LFINTOSC connect to a multiplexer (see Figure 6-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: - 32 MHz (requires 4x PLL) 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (default after Reset) 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source. • Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and • FOSC<1:0> = 00, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ Peripherals that use the LFINTOSC are: • Power-up Timer (PWRT) • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running. 2013-2015 Microchip Technology Inc. DS40001722C-page 65 PIC16(L)F1703/7 6.2.2.6 32 MHz Internal Oscillator Frequency Selection The Internal Oscillator Block can be used with the 4x PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: • The FOSC bits in Configuration Words must be set to use the INTOSC source as the device system clock (FOSC<1:0> = 00). • The SCS bits in the OSCCON register must be cleared to use the clock determined by FOSC<1:0> in Configuration Words (SCS<1:0> = 00). • The IRCF bits in the OSCCON register must be set to the 8 MHz HFINTOSC set to use (IRCF<3:0> = 1110). • The SPLLEN bit in the OSCCON register must be set to enable the 4x PLL, or the PLLEN bit of the Configuration Words must be programmed to a ‘1’. Note: When using the PLLEN bit of the Configuration Words, the 4x PLL cannot be disabled by software and the SPLLEN option will not be available. The 4x PLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to ‘1x’. The SCS bits must be set to ‘00’ to use the 4x PLL with the internal oscillator. DS40001722C-page 66 6.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 6-3). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. 7. IRCF<3:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete. See Figure 6-3 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 6-1. Start-up delay specifications are located in the oscillator tables of Section 26.0 “Electrical Specifications”. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 6-3: HFINTOSC/ MFINTOSC INTERNAL OSCILLATOR SWITCH TIMING LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Oscillator Delay(1) Start-up Time 2-cycle Sync Running LFINTOSC IRCF <3:0> 0 0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Oscillator Delay(1) Start-up Time 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> =0 0 System Clock Note 1: See Table 6-1, Oscillator Switching Delays, for more information. 2013-2015 Microchip Technology Inc. DS40001722C-page 67 PIC16(L)F1703/7 6.3 Clock Switching The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 6-1. • Default system oscillator determined by FOSC bits in Configuration Words • Timer1 32 kHz crystal oscillator • Internal Oscillator Block (INTOSC) 6.3.1 SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register select the system clock source that is used for the CPU and peripherals. • When the SCS bits of the OSCCON register = 00, the system clock source is determined by the value of the FOSC<1:0> bits in the Configuration Words. • When the SCS bits of the OSCCON register = 01, the system clock source is the secondary oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. TABLE 6-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) Sleep/POR MFINTOSC(1) HFINTOSC(1) 31 kHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz 2 cycles Sleep/POR EC DC – 32 MHz 2 cycles LFINTOSC EC DC – 32 MHz 1 cycle of each Any clock source MFINTOSC(1) HFINTOSC(1) 31.25 kHz-500 kHz 31.25 kHz-16 MHz 2 s (approx.) Any clock source LFINTOSC(1) 31 kHz 1 cycle of each PLL inactive PLL active 16-32 MHz 2 ms (approx.) Note 1: PLL inactive. DS40001722C-page 68 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 6.4 Register Definitions: Oscillator Control REGISTER 6-1: R/W-0/0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 R/W-1/1 SPLLEN R/W-1/1 R/W-1/1 IRCF<3:0> U-0 R/W-0/0 — R/W-0/0 SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Words = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Words = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 1111 = 16 MHz HF 1110 = 8 MHz or 32 MHz HF(2) 1101 = 4 MHz HF 1100 = 2 MHz HF 1011 = 1 MHz HF 1010 = 500 kHz HF(1) 1001 = 250 kHz HF(1) 1000 = 125 kHz HF(1) 0111 = 500 kHz MF (default upon Reset) 0110 = 250 kHz MF 0101 = 125 kHz MF 0100 = 62.5 kHz MF 0011 = 31.25 kHz HF(1) 0010 = 31.25 kHz MF 000x = 31 kHz LF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 =Reserved 00 = Clock determined by FOSC<1:0> in Configuration Words Note 1: 2: Duplicate frequency derived from HFINTOSC. 32 MHz when SPLLEN bit is set. Refer to Section 6.2.2.6 “32 MHz Internal Oscillator Frequency Selection”. 2013-2015 Microchip Technology Inc. DS40001722C-page 69 PIC16(L)F1703/7 REGISTER 6-2: OSCSTAT: OSCILLATOR STATUS REGISTER U-0 R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q — PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 Unimplemented: Read as ‘0’ bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Timer Status bit 1 = Running from the clock defined by the FOSC<1:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<1:0> = 00) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS40001722C-page 70 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 6-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 = Minimum frequency • • • 111111 = 000000 = Oscillator module is running at the factory-calibrated frequency 000001 = • • • 011110 = 011111 = Maximum frequency TABLE 6-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 Register on Page OSCCON SPLLEN OSCSTAT — PLLR OSCTUNE — — PIR2 — — — — BCL1IF — — CCP2IF 82 — — — — BCL1IE — — CCP2IE 79 PIE2 Legend: CONFIG1 CONFIG2 Legend: OSTS — HFIOFR HFIOFL SCS<1:0> MFIOFR LFIOFR 69 HFIOFS 70 TUN<5:0> 71 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. TABLE 6-3: Name IRCF<3:0> Bit 1 Bits SUMMARY OF CONFIGURATION BITS ASSOCIATED WITH CLOCK SOURCES Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 — CLKOUTEN Bit 10/2 13:8 — — — 7:0 CP MCLRE PWRTE 13:8 — — LVP DEBUG LPBOR BORV 7:0 ZCDDIS — — — — PPS1WAY WDTE<1:0> Bit 9/1 BOREN<1:0> Bit 8/0 — FOSC<1:0> — STVREN PLLEN WRT<1:0> Register on Page 49 50 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. 2013-2015 Microchip Technology Inc. DS40001722C-page 71 PIC16(L)F1703/7 7.0 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC TMR0IF TMR0IE Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IE) PIE1<0> Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE Interrupt to CPU PEIE PIRn<7> PIEn<7> DS40001722C-page 72 GIE 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 or PIE2 registers) 7.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 7-2 and Figure 7-3 for more details. The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See “Section 7.5 “Automatic Context Saving”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. 2013-2015 Microchip Technology Inc. DS40001722C-page 73 PIC16(L)F1703/7 FIGURE 7-2: INTERRUPT LATENCY F OSC Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(0004h) Inst(PC) Interrupt GIE PC Execute PC-1 PC 2 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC DS40001722C-page 74 PC+2 NOP NOP 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 FOSC CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h Inst (0004h) Forced NOP 0005h Inst (0005h) Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 26.0 “Electrical Specifications””. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. 2013-2015 Microchip Technology Inc. DS40001722C-page 75 PIC16(L)F1703/7 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 8.0 “Power-Down Mode (Sleep)” for more details. 7.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • • • • • W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved. DS40001722C-page 76 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 7.6 Register Definitions: Interrupt Control REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: Note: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers have been cleared by software. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2013-2015 Microchip Technology Inc. DS40001722C-page 77 PIC16(L)F1703/7 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE — — SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5-4 Unimplemented: Read as ‘0’ bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001722C-page 78 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 7-3: U-0 PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 — U-0 — — U-0 R/W-0/0 U-0 U-0 R/W-0/0 — BCL1IE — — CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 2013-2015 Microchip Technology Inc. DS40001722C-page 79 PIC16(L)F1703/7 REGISTER 7-4: U-0 PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 — — U-0 R/W-0/0 U-0 U-0 U-0 U-0 — ZCDIE — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 ZCDIE: Zero-Cross Detection Interrupt Enable bit 1 = ZCD interrupt enabled 0 = ZCD interrupt disabled bit 3-0 Unimplemented: Read as ‘0’ Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001722C-page 80 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 TMR1GIF ADIF U-0 — U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5-4 Unimplemented: Read as ‘0’ bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2013-2015 Microchip Technology Inc. DS40001722C-page 81 PIC16(L)F1703/7 REGISTER 7-6: U-0 PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 U-0 — — U-0 — U-0 R/W-0/0 U-0 U-0 R/W-0/0 — BCL1IF — — CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2-1 Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001722C-page 82 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 7-7: U-0 PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 — — U-0 R/W-0/0 U-0 U-0 U-0 U-0 — ZCDIF — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 ZCDIF: Zero-Cross Detection Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3-0 Unimplemented: Read as ‘0’ Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2013-2015 Microchip Technology Inc. DS40001722C-page 83 PIC16(L)F1703/7 TABLE 7-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 INTCON Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IF Bit 1 Bit 0 INTF IOCIF Register on Page GIE PEIE TMR0IE INTE IOCIE WPUEN INTEDG TMR0CS TMR0SE PSA PIE1 TMR1GIE ADIE — — SSP1IE CCP1IE TMR2IE TMR1IE 78 PIE2 — — — — BCL1IE — — CCP2IE 79 OPTION_REG PS<2:0> 77 168 PIE3 — — — ZCDIE — — — — 80 PIR1 TMR1GIF ADIF — — SSP1IF CCP1IF TMR2IF TMR1IF 81 PIR2 — — — — BCL1IF — — CCP2IF 82 PIR3 — — — ZCDIF — — — — 83 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts. DS40001722C-page 84 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep The Power-down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. Timer1 and peripherals that operate from Timer1 continue operation in Sleep when the Timer1 clock source selected is: • LFINTOSC • T1CKI • Secondary oscillator ADC is unaffected, if the dedicated FRC oscillator is selected. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). Resets other than WDT are not affected by Sleep mode. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: • • • • • External Reset input on MCLR pin, if enabled BOR Reset, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information) The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 5.12 “Determining the Cause of a Reset”. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include the FVR module. See Section 14.0 “Fixed Voltage Reference (FVR)” for more information on the FVR module. 2013-2015 Microchip Technology Inc. DS40001722C-page 85 PIC16(L)F1703/7 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared FIGURE 8-1: • If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) TOST(3) CLKOUT(2) Interrupt flag Interrupt Latency (4) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Processor in Sleep PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Forced NOP 0004h 0005h Inst(0004h) Inst(0005h) Forced NOP Inst(0004h) External clock. High, Medium, Low mode assumed. CLKOUT is shown here for timing reference. TOST = 1024 TOSC. This delay does not apply to EC and INTOSC Oscillator modes. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. DS40001722C-page 86 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 8.2 Low-Power Sleep Mode The PIC16F1703/7 device contains an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1703/7 allows the user to optimize the operating current in Sleep, depending on the application requirements. A Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. With this bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep. 8.2.1 SLEEP CURRENT VS. WAKE-UP TIME In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. 8.2.2 PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The Low-Power Sleep mode is intended for use only with the following peripherals: • • • • Brown-Out Reset (BOR) Watchdog Timer (WDT) External interrupt pin/Interrupt-on-change pins Timer1 (with external clock source < 100 kHz) Note: The PIC16LF1703/7 does not have a configurable Low-Power Sleep mode. PIC16LF1703/7 is an unregulated device and is always in the lowest power state when in Sleep, with no wake-up time penalty. This device has a lower maximum VDD and I/O voltage than the PIC16F1703/7. See Section 26.0 “Electrical Specifications” for more information. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. 2013-2015 Microchip Technology Inc. DS40001722C-page 87 PIC16(L)F1703/7 8.3 Register Definitions: Voltage Regulator Control VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) REGISTER 8-1: U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 — — — — — — VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up 0 = Normal-Power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as ‘1’. Maintain this bit set. Note 1: 2: PIC16F1703/7 only. See Section 26.0 “Electrical Specifications”. TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Name Bit 7 Bit 6 INTCON Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 77 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 137 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 137 — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 137 IOCBP(1) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 138 IOCBN(1) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 138 IOCAF (1) IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 138 IOCCP IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 139 IOCCN IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 139 IOCCF IOCCF7(1) IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 139 PIE1 TMR1GIE ADIE — — SSP1IE CCP1IE TMR2IE TMR1IE 78 PIE2 — — — — BCL1IE — — CCP2IE 79 PIE3 — — — ZCDIE — — — — 80 PIR1 TMR1GIF ADIF — — SSP1IF CCP1IF TMR2IF TMR1IF 81 PIR2 — — — — BCL1IF — — CCP2IF 82 PIR3 — — — ZCDIF — — — — 83 STATUS — — — TO PD Z DC C 21 VREGCON(2) — — — — — — VREGPM Reserved 88 WDTCON — — SWDTEN 92 Legend: Note 1: 2: WDTPS<4:0> — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode. PIC16(L)F1707 only. PIC16F1703/7 only. DS40001722C-page 88 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 9.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (nominal) • Multiple Reset conditions • Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> = 01 SWDTEN WDTE<1:0> = 11 LFINTOSC 23-bit Programmable Prescaler WDT WDT Time-out WDTE<1:0> = 10 Sleep 2013-2015 Microchip Technology Inc. WDTPS<4:0> DS40001722C-page 89 PIC16(L)F1703/7 9.1 Independent Clock Source 9.4 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Table 26-8 for the LFINTOSC specification. 9.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 9-1. 9.2.1 WDT IS ALWAYS ON WDT protection is active during Sleep. WDT IS OFF IN SLEEP WDT protection is not active during Sleep. WDT CONTROLLED BY SOFTWARE When the WDTE bits of Configuration Words are set to ‘01’, the WDT is controlled by the SWDTEN bit of the WDTCON register. WDT protection is unchanged by Sleep. See Table 9-1 for more details. TABLE 9-1: • • • • • • • Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep Oscillator fail WDT is disabled Oscillator Start-up Timer (OST) is running 9.5 Operation During Sleep When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the WDTE bits of Configuration Words are set to ‘10’, the WDT is on, except in Sleep. 9.2.3 The WDT is cleared when any of the following conditions occur: See Table 9-2 for more information. When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on. 9.2.2 Clearing the WDT When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for more information on the OST. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. See STATUS Register (Register 3-1) for more information. WDT OPERATING MODES WDTE<1:0> SWDTEN Device Mode 11 X X 10 X WDT Mode Active Awake Active 1 01 Sleep X 0 00 9.3 X X Disabled Active Disabled Disabled Time-Out Period The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is two seconds. DS40001722C-page 90 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 9-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep CLRWDT Command Cleared Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Change INTOSC divider (IRCF bits) 2013-2015 Microchip Technology Inc. Unaffected DS40001722C-page 91 PIC16(L)F1703/7 9.6 Register Definitions: Watchdog Control REGISTER 9-1: U-0 WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 — R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 (1) — WDTPS<4:0> R/W-0/0 SWDTEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32) • • • 10011 = Reserved. Results in minimum interval (1:32) 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 bit 0 Note 1: = = = = = = = = = = = = = = = = = = = 1:8388608 (223) (Interval 256s nominal) 1:4194304 (222) (Interval 128s nominal) 1:2097152 (221) (Interval 64s nominal) 1:1048576 (220) (Interval 32s nominal) 1:524288 (219) (Interval 16s nominal) 1:262144 (218) (Interval 8s nominal) 1:131072 (217) (Interval 4s nominal) 1:65536 (Interval 2s nominal) (Reset value) 1:32768 (Interval 1s nominal) 1:16384 (Interval 512 ms nominal) 1:8192 (Interval 256 ms nominal) 1:4096 (Interval 128 ms nominal) 1:2048 (Interval 64 ms nominal) 1:1024 (Interval 32 ms nominal) 1:512 (Interval 16 ms nominal) 1:256 (Interval 8 ms nominal) 1:128 (Interval 4 ms nominal) 1:64 (Interval 2 ms nominal) 1:32 (Interval 1 ms nominal) SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 1x: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 00: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. DS40001722C-page 92 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 9-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 OSCCON SPLLEN STATUS — — WDTCON — — Bit 5 Bit 4 Bit 3 IRCF<3:0> — Bit 2 — TO PD Bit 1 Bit 0 SCS<1:0> Z DC WDTPS<4:0> Register on Page 69 C 21 SWDTEN 92 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer. TABLE 9-4: Name CONFIG1 CONFIG2 Bits SUMMARY OF CONFIGURATION BITS ASSOCIATED WITH WATCHDOG TIMER Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 — CLKOUTEN 13:8 — — — 7:0 CP MCLRE PWRTE 13:8 — — LVP DEBUG 7:0 ZCDDIS — — — WDTE<1:0> Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> — — FOSC<1:0> LPBOR BORV STVREN PLLEN — PPS1WAY WRT<1:0> Register on Page 49 50 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer. 2013-2015 Microchip Technology Inc. DS40001722C-page 93 PIC16(L)F1703/7 10.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are: • • • • • • PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH When accessing the program memory, the PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the PMADRH:PMADRL register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read. The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. The Flash program memory can be protected in two ways; by code protection (CP bit in Configuration Words) and write protection (WRT<1:0> bits in Configuration Words). Code protection (CP = 0)(1), disables access, reading and writing, to the Flash program memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all Flash program memory, Configuration bits and User IDs. Write protection prohibits self-write and erase to a portion or all of the Flash program memory as defined by the bits WRT<1:0>. Write protection does not affect a device programmers ability to read, write or erase the device. Note 1: Code protection of the entire Flash program memory array is enabled by clearing the CP bit of Configuration Words. 10.1 PMADRL and PMADRH Registers The PMADRH:PMADRL register pair can address up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register. DS40001722C-page 94 10.1.1 PMCON1 AND PMCON2 REGISTERS PMCON1 is the control register for Flash program memory accesses. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared by hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. The PMCON2 register is a write-only register. Attempting to read the PMCON2 register will return all ‘0’s. To enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the PMCON2 register. The required unlock sequence prevents inadvertent writes to the program memory write latches and Flash program memory. 10.2 Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum size that can be erased by user software. After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the PMDATH:PMDATL register pair. Note: If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations. See Table 10-1 for Erase Row size and the number of write latches for Flash program memory. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 10-1: Device PIC16(L)F1703 PIC16(L)F1707 10.2.1 FLASH MEMORY ORGANIZATION BY DEVICE Row Erase (words) Write Latches (words) 16 16 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored. The data is available in the very next cycle, in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions. PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user. Note: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a 2-cycle instruction on the next instruction after the RD bit is set. FIGURE 10-1: FLASH PROGRAM MEMORY READ FLOWCHART Start Read Operation Select Program or Configuration Memory (CFGS) Select Word Address (PMADRH:PMADRL) Initiate Read operation (RD = 1) Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced Data read now in PMDATH:PMDATL End Read Operation 2013-2015 Microchip Technology Inc. DS40001722C-page 95 PIC16(L)F1703/7 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PC +3 PC+3 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here PC + 5 INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit PMDATH PMDATL Register EXAMPLE 10-1: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWF PMADRL PROG_ADDR_LO PMADRL PROG_ADDR_HI PMADRH ; Select Bank for PMCON registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF NOP NOP PMCON1,CFGS PMCON1,RD ; ; ; ; Do not select Configuration Space Initiate read Ignored (Figure 10-1) Ignored (Figure 10-1) MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location DS40001722C-page 96 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 10.2.2 FLASH MEMORY UNLOCK SEQUENCE The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: • Row Erase • Load program memory write latches • Write of program memory write latches to program memory • Write of program memory write latches to User IDs The unlock sequence consists of the following steps: FIGURE 10-3: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Start Unlock Sequence Write 055h to PMCON2 Write 0AAh to PMCON2 1. Write 55h to PMCON2 2. Write AAh to PMCON2 3. Set the WR bit in PMCON1 Initiate Write or Erase operation (WR = 1) 4. NOP instruction 5. NOP instruction Once the WR bit is set, the processor will always force two NOP instructions. When an Erase Row or Program Row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. When the operation is loading the program memory write latches, the processor will always force the two NOP instructions and continue uninterrupted with the next instruction. Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced End Unlock Sequence Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. 2013-2015 Microchip Technology Inc. DS40001722C-page 97 PIC16(L)F1703/7 10.2.3 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 10-2. After the “BSF PMCON1,WR” instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions immediately following the WR bit set instruction. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. FIGURE 10-4: FLASH PROGRAM MEMORY ERASE FLOWCHART Start Erase Operation Disable Interrupts (GIE = 0) Select Program or Configuration Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Erase Operation (FREE = 1) Enable Write/Erase Operation (WREN = 1) Unlock Sequence Figure 10-3 (FIGURE x-x) CPU stalls while Erase operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Erase Operation DS40001722C-page 98 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF BCF BSF BSF INTCON,GIE PMADRL ADDRL,W PMADRL ADDRH,W PMADRH PMCON1,CFGS PMCON1,FREE PMCON1,WREN MOVLW MOVWF MOVLW MOVWF BSF NOP NOP 55h PMCON2 0AAh PMCON2 PMCON1,WR BCF BSF PMCON1,WREN INTCON,GIE 2013-2015 Microchip Technology Inc. ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; Not configuration space ; Specify an erase operation ; Enable writes ; ; ; ; ; ; ; ; ; ; Start of required sequence to initiate erase Write 55h Write AAh Set WR bit to begin erase NOP instructions are forced as processor starts row erase of program memory. The processor stalls until the erase process is complete after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts DS40001722C-page 99 PIC16(L)F1703/7 10.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash program memory. Note: Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 10-5 (row writes to program memory with 16 write latches) for more details. The write latches are aligned to the Flash row address boundary defined by the upper 10-bits of PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) with the lower five bits of PMADRL, (PMADRL<4:0>) determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF. The special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. If the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. 1. 2. 3. Set the WREN bit of the PMCON1 register. Clear the CFGS bit of the PMCON1 register. Set the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is ‘1’, the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the PMADRH:PMADRL register pair with the address of the location to be written. 5. Load the PMDATH:PMDATL register pair with the program memory data to be written. 6. Execute the unlock sequence (Section 10.2.2 “Flash Memory Unlock Sequence”). The write latch is now loaded. 7. Increment the PMADRH:PMADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is ‘0’, the write sequence will initiate the write to Flash program memory. 10. Load the PMDATH:PMDATL register pair with the program memory data to be written. 11. Execute the unlock sequence (Section 10.2.2 “Flash Memory Unlock Sequence”). The entire program memory latch content is now written to Flash program memory. Note: The program memory write latches are reset to the blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example 10-3. The initial address is loaded into the PMADRH:PMADRL register pair; the data is loaded using indirect addressing. DS40001722C-page 100 2013-2015 Microchip Technology Inc. 7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 16 WRITE LATCHES 6 0 7 5 4 PMADRH - r9 r8 r7 r6 r5 0 7 PMADRL r4 r3 r2 r1 r0 c4 c3 c2 c1 - 5 - 0 7 PMDATH PMDATL 6 c0 Rev. 10-000004A_A0 0 8 14 Program Memory Write Latches 5 10 14 PMADRL<4:0> Write Latch #0 00h 14 CFGS = 0 2013-2015 Microchip Technology Inc. PMADRH<6:0>: PMADRL<7:5> Row Address Decode 14 14 Write Latch #1 01h 14 Write Latch #30 1Eh 14 Write Latch #31 1Fh 14 14 Row Addr Addr Addr Addr 000h 0000h 0001h 001Eh 001Fh 001h 0020h 0021h 003Eh 003Fh 002h 0040h 0041h 005Eh 005Fh 3FEh 7FC0h 7FC1h 7FDEh 7FDFh 3FFh 7FE0h 7FE1h 7FFEh 7FFFh Flash Program Memory 400h CFGS = 1 8000h - 8003h 8004h – 8005h 8006h 8007h – 8008h 8009h - 801Fh USER ID 0 - 3 reserved DEVICE ID Dev / Rev Configuration Words reserved Configuration Memory PIC16(L)F1703/7 DS40001722C-page 101 FIGURE 10-5: PIC16(L)F1703/7 FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Last word to write ? Yes No Unlock Sequence (Figure10-3 x-x) Figure Select Write Operation (FREE = 0) No delay when writing to Program Memory Latches Load Write Latches Only (LWLO = 1) Increment Address (PMADRH:PMADRL++) Write Latches to Flash (LWLO = 0) Unlock Sequence (Figure10-3 x-x) Figure CPU stalls while Write operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Write Operation DS40001722C-page 102 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 EXAMPLE 10-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BCF BSF BSF INTCON,GIE PMADRH ADDRH,W PMADRH ADDRL,W PMADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H PMCON1,CFGS PMCON1,WREN PMCON1,LWLO ; ; ; ; ; ; ; ; ; ; ; ; ; Disable ints so required sequences will execute properly Bank 3 Load initial address MOVIW MOVWF MOVIW MOVWF FSR0++ PMDATL FSR0++ PMDATH ; Load first data byte into lower ; ; Load second data byte into upper ; MOVF XORLW ANDLW BTFSC GOTO PMADRL,W 0x1F 0x1F STATUS,Z START_WRITE ; Check if lower bits of address are '00000' ; Check if we're on the last of 32 addresses ; ; Exit if last of 32 words, ; MOVLW MOVWF MOVLW MOVWF BSF NOP 55h PMCON2 0AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; PMADRL,F LOOP ; Still loading latches Increment address ; Write next latches PMCON1,LWLO ; No more loading latches - Actually start Flash program ; memory write 55h PMCON2 0AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; Load initial data address Load initial data address Not configuration space Enable writes Only Load Write Latches Required Sequence LOOP NOP INCF GOTO Required Sequence START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF BSF PMCON1,WREN INTCON,GIE 2013-2015 Microchip Technology Inc. Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor loads program memory write latches Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor writes all the program memory write latches simultaneously to program memory. After NOPs, the processor stalls until the self-write process in complete after write processor continues with 3rd instruction Disable writes Enable interrupts DS40001722C-page 103 PIC16(L)F1703/7 10.3 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. FIGURE 10-7: FLASH PROGRAM MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure10-1 x.x) Figure An image of the entire row read must be stored in RAM Modify Image The words to be modified are changed in the RAM image Erase Operation (Figure10-4 x.x) Figure Write Operation use RAM image (Figure10-6 x.x) Figure End Modify Operation DS40001722C-page 104 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 10-2. When read access is initiated on an address outside the parameters listed in Table 10-2, the PMDATH:PMDATL register pair is cleared, reading back ‘0’s. TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1) Address Function Read Access Write Access 8000h-8003h 8005h-8006h 8007h-8008h User IDs Device ID/Revision ID Configuration Words 1 and 2 Yes Yes Yes Yes No No EXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF CLRF PMADRL PROG_ADDR_LO PMADRL PMADRH ; Select correct Bank ; ; Store LSB of address ; Clear MSB of address BSF BCF BSF NOP NOP BSF PMCON1,CFGS INTCON,GIE PMCON1,RD INTCON,GIE ; ; ; ; ; ; Select Configuration Space Disable interrupts Initiate read Executed (See Figure 10-2) Ignored (See Figure 10-2) Restore interrupts MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location 2013-2015 Microchip Technology Inc. DS40001722C-page 105 PIC16(L)F1703/7 10.5 Write Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation (Figure x.x) Figure 10-1 PMDAT = RAM image ? Yes No No Fail Verify Operation Last Word ? Yes End Verify Operation DS40001722C-page 106 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 10.6 Register Definitions: Flash Program Memory Control REGISTER 10-1: R/W-x/u PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDATL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMDATL<7:0>: Read/write value for Least Significant bits of program memory REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDATH<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PMDATH<13:8>: Read/write value for Most Significant bits of program memory REGISTER 10-3: R/W-0/0 PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADRL<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMADRL<7:0>: Specifies the Least Significant bits for program memory address REGISTER 10-4: U-1 PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 —(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADRH<14:8> bit 0 bit 7 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 PMADRH<14:8>: Specifies the Most Significant bits for program memory address Note 1: Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001722C-page 107 PIC16(L)F1703/7 REGISTER 10-5: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1 R/W-0/0 R/W-0/0 R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 —(1) CFGS LWLO(3) FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6 CFGS: Configuration Select bit 1 = Access Configuration, User ID and Device ID Registers 0 = Access Flash program memory bit 5 LWLO: Load Write Latches Only bit(3) 1 = Only the addressed program memory write latch is loaded/updated on the next WR command 0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches will be initiated on the next WR command bit 4 FREE: Program Flash Erase Enable bit 1 = Performs an erase operation on the next WR command (hardware cleared upon completion) 0 = Performs a write operation on the next WR command bit 3 WRERR: Program/Erase Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit). 0 = The program or erase operation completed normally bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash bit 1 WR: Write Control bit 1 = Initiates a program Flash program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash is complete and inactive bit 0 RD: Read Control bit 1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash read Note 1: 2: 3: Unimplemented bit, read as ‘1’. The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1). The LWLO bit is ignored during a program memory erase operation (FREE = 1). DS40001722C-page 108 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 10-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 PMCON2<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Register on Page Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 77 CFGS LWLO FREE WRERR WREN WR RD 108 PMCON1 (1) — PMCON2 PMCON2<7:0> 109 PMADRL PMADR 107 (1) — PMADRH PMADR<14:8> PMDATL — PMDATH Legend: Note 1: CONFIG1 CONFIG2 Legend: — 107 PMDAT<13:8> 107 — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory. Unimplemented, read as ‘1’. TABLE 10-4: Name 107 PMDAT SUMMARY OF CONFIGURATION BITS ASSOCIATED WITH FLASH PROGRAM MEMORY Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 — — — — CLKOUTEN WDTE<1:0> Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> 7:0 CP MCLRE PWRTE — 13:8 — — LVP DEBUG LPBOR BORV 7:0 ZCDDIS — — — — PPS1WAY — FOSC<1:0> STVREN PLLEN WRT<1:0> Register on Page 49 50 — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory. 2013-2015 Microchip Technology Inc. DS40001722C-page 109 PIC16(L)F1703/7 11.0 I/O PORTS FIGURE 11-1: GENERIC I/O PORT OPERATION Each port has six standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) • INLVLx (input level control) • ODCONx registers (open drain) • SLRCONx registers (slew rate Some ports may have one or more of the following additional registers. These registers are: D Write LATx Write PORTx TRISx Q CK VDD Data Register Data Bus I/O pin • ANSELx (analog select) • WPUx (weak pull-up) Read PORTx In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. To digital peripherals To analog peripherals ANSELx VSS PIC16(L)F1703 ● PIC16(L)F1707 ● PORTC Device PORTB PORT AVAILABILITY PER DEVICE PORTA TABLE 11-1: Read LATx ● ● ● The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 11-1. DS40001722C-page 110 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 11.1 11.1.1 PORTA Registers DATA REGISTER PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 11-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input-only and its TRIS bit will always read as ‘1’. Example 11-1 shows how to initialize PORTA. 11.1.5 The INLVLA register (Register 11-8) controls the input voltage threshold for each of the available PORTA input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTA register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 26-4 for more information on threshold levels. Note: Reading the PORTA register (Register 11-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). 11.1.2 DIRECTION CONTROL The TRISA register (Register 11-2) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 11.1.3 OPEN DRAIN CONTROL The ODCONA register (Register 11-6) controls the open-drain feature of the port. Open drain operation is independently selected for each pin. When an ODCONA bit is set, the corresponding port output becomes an open drain driver capable of sinking current only. When an ODCONA bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.1.4 SLEW RATE CONTROL The SLRCONA register (Register 11-7) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONA bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONA bit is cleared, The corresponding port pin drive slews at the maximum rate possible. 2013-2015 Microchip Technology Inc. INPUT THRESHOLD CONTROL 11.1.6 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELA register (Register 11-4) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. EXAMPLE 11-1: ; ; ; ; INITIALIZING PORTA This code example illustrates initializing the PORTA register. The other ports are initialized in the same manner. BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'00111000' TRISA ; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA<5:3> as inputs ;and set RA<2:0> as ;outputs DS40001722C-page 111 PIC16(L)F1703/7 11.1.7 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. Each pin defaults to the PORT latch data after reset. Other functions are selected with the peripheral pin select logic. See Section 12.0 “Peripheral Pin Select (PPS) Module” for more information. Analog input functions, such as ADC inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELA register. Digital output functions may continue to control the pin when it is in Analog mode. DS40001722C-page 112 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 11.2 Register Definitions: PORTA REGISTER 11-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 11-2: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1 — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 3 Unimplemented: Read as ‘1’ bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001722C-page 113 PIC16(L)F1703/7 REGISTER 11-3: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemented: Read as ‘0’ bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 11-4: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — — ANSA4 — ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 ANSA4: Analog Select between Analog or Digital Function on pin RA4 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. bit 3 Unimplemented: Read as ‘0’ bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS40001722C-page 114 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 11-5: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. REGISTER 11-6: ODCONA: PORTA OPEN DRAIN CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — ODA5 ODA4 — ODA2 ODA1 ODA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 ODA<5:4>: PORTA Open Drain Enable bits For RA<5:4> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) bit 3 Unimplemented: Read as ‘0’ bit 2-0 ODA<2:0>: PORTA Open Drain Enable bits For RA<2:0> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) 2013-2015 Microchip Technology Inc. DS40001722C-page 115 PIC16(L)F1703/7 REGISTER 11-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 SLRA<5:4>: PORTA Slew Rate Enable bits For RA<5:4> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate bit 3 Unimplemented: Read as ‘0’ bit 2-0 SLRA<2:0>: PORTA Slew Rate Enable bits For RA<2:0> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 11-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits For RA<5:0> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change DS40001722C-page 116 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 11-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 114 INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 116 LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 114 ODCONA — — ODA5 ODA4 — ODA2 ODA1 ODA0 115 WPUEN INTEDG TMR0CS TMR0SE PSA PORTA OPTION_REG — — RA5 RA4 RA3 SLRCONA — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 116 TRISA — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 113 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 115 WPUA Legend: Note 1: CONFIG1 CONFIG2 Legend: 168 RA1 RA0 113 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Unimplemented, read as ‘1’. TABLE 11-3: Name PS<2:0> RA2 SUMMARY OF CONFIGURATION BITS ASSOCIATED WITH PORTA Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 — — — — CLKOUTEN 7:0 CP MCLRE PWRTE 13:8 — — LVP 7:0 ZCDDIS — — WDTE<1:0> DEBUG — LPBOR — Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> — BORV PPS1WAY — FOSC<1:0> STVREN PLLEN WRT<1:0> Register on Page 49 50 — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. 2013-2015 Microchip Technology Inc. DS40001722C-page 117 PIC16(L)F1703/7 11.3 PORTB Registers (PIC16(L)F1707 only) PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 11-10). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 11-1 shows how to initialize an I/O port. 11.3.4 The INLVLB register (Register 11-16) controls the input voltage threshold for each of the available PORTB input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTB register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 26-4 for more information on threshold levels. Note: Reading the PORTB register (Register 11-9) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATB). 11.3.1 DIRECTION CONTROL The TRISB register (Register 11-10) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 11.3.2 OPEN DRAIN CONTROL The ODCONB register (Register 11-14) controls the open-drain feature of the port. Open drain operation is independently selected for each pin. When an ODCONB bit is set, the corresponding port output becomes an open drain driver capable of sinking current only. When an ODCONB bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.3.3 11.3.5 DS40001722C-page 118 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELB register (Register 11-12) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: SLEW RATE CONTROL The SLRCONB register (Register 11-15) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONB bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONB bit is cleared, The corresponding port pin drive slews at the maximum rate possible. INPUT THRESHOLD CONTROL 11.3.6 The ANSELB bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. PORTB FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after reset. Other functions are selected with the peripheral pin select logic. See Section 12.0 “Peripheral Pin Select (PPS) Module” for more information. Analog input functions, such as ADC and Op Amp inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELB register. Digital output functions may continue to control the pin when it is in Analog mode. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 11.4 Register Definitions: PORTB REGISTER 11-9: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 RB7 RB6 RB5 RB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 RB<7:4>: PORTB General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 3-0 Unimplemented: Read as ‘0’ Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 11-10: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 TRISB7 TRISB6 TRISB5 TRISB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 TRISB<7:4>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output bit 3-0 Unimplemented: Read as ‘0’ REGISTER 11-11: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 LATB7 LATB6 LATB5 LATB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 LATB<7:4>: PORTB Output Latch Value bits(1) bit 3-0 Unimplemented: Read as ‘0’ Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. 2013-2015 Microchip Technology Inc. DS40001722C-page 119 PIC16(L)F1703/7 REGISTER 11-12: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 — — ANSB5 ANSB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 3-0 Unimplemented: Read as ‘0’ Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. REGISTER 11-13: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 WPUB7 WPUB6 WPUB5 WPUB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: 2: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. DS40001722C-page 120 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 11-14: ODCONB: PORTB OPEN DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 ODB7 ODB6 ODB5 ODB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 ODB<7:4>: PORTB Open Drain Enable bits For RB<7:4> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) bit 3-0 Unimplemented: Read as ‘0’ REGISTER 11-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 SLRB7 SLRB6 SLRB5 SLRB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 SLRB<7:4>: PORTB Slew Rate Enable bits For RB<7:4> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate bit 3-0 Unimplemented: Read as ‘0’ REGISTER 11-16: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 INLVLB<7:4>: PORTB Input Level Select bits For RB<7:4> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change bit 3-0 Unimplemented: Read as ‘0’ 2013-2015 Microchip Technology Inc. DS40001722C-page 121 PIC16(L)F1703/7 TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSB5 ANSB4 — — — — 120 INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 121 LATB LATB7 LATB6 LATB5 LATB4 — — — — 119 ODCONB ODB7 ODB6 ODB5 ODB4 — — — — 121 RB7 RB6 RB5 RB4 — — — — 119 SLRB7 SLRB6 SLRB5 SLRB4 — — — — 121 Name ANSELB INLVLB PORTB SLRCONB TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 121 WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 120 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. DS40001722C-page 122 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 11.5 11.5.1 PORTC Registers DATA REGISTER PORTC is a 6-bit wide bidirectional port in the PIC16(L)F1703 device and 8-bit wide bidirectional port in the PIC16(L)F1707 device. The corresponding data direction register is TRISC (Register 11-18). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 11-1 shows how to initialize an I/O port. Reading the PORTC register (Register 11-17) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC). 11.5.2 DIRECTION CONTROL The TRISC register (Register 11-18) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 11.5.3 INPUT THRESHOLD CONTROL The INLVLC register (Register 11-24) controls the input voltage threshold for each of the available PORTC input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTC register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 26-4 for more information on threshold levels. Note: Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. 2013-2015 Microchip Technology Inc. 11.5.4 OPEN DRAIN CONTROL The ODCONC register (Register 11-22) controls the open-drain feature of the port. Open drain operation is independently selected for each pin. When an ODCONC bit is set, the corresponding port output becomes an open drain driver capable of sinking current only. When an ODCONC bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.5.5 SLEW RATE CONTROL The SLRCONC register (Register 11-23) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONC bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONC bit is cleared, The corresponding port pin drive slews at the maximum rate possible. 11.5.6 ANALOG CONTROL The ANSELC register (Register 11-20) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: 11.5.7 The ANSELC bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. PORTC FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after reset. Other functions are selected with the peripheral pin select logic. See Section 12.0 “Peripheral Pin Select (PPS) Module” for more information. Analog input functions, such as ADC inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELC register. Digital output functions may continue to control the pin when it is in Analog mode. DS40001722C-page 123 PIC16(L)F1703/7 11.6 Register Definitions: PORTC REGISTER 11-17: PORTC: PORTC REGISTER R/W-x/u R/W-x/u (2) RC6 RC7 (2) R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RC<7:0>: PORTC General Purpose I/O Pin bits(1, 2) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: 2: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. RC<7:6> are available on PIC16(L)F1707 only. REGISTER 11-18: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared TRISC<7:0>: PORTC Tri-State Control bits(1) 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output bit 7-0 Note 1: TRISC<7:6> are available on PIC16(L)F1707 only. REGISTER 11-19: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC7(1) LATC6(1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: LATC<7:0>: PORTC Output Latch Value bits(1) LATC<7:6> are available on PIC16(L)F1707 only. DS40001722C-page 124 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 11-20: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSC7(2) ANSC6(2) ANSC5(3) ANSC4(3) ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared ANSC<7:0>: Analog Select between Analog or Digital Function on pins RC<7:0>, respectively(1) 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 7-0 When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. ANSC<7:6> are available on PIC16(L)F1707 only. ANSC<5:4> are available on PIC16(L)F1703 only. Note 1: 2: 3: REGISTER 11-21: WPUC: WEAK PULL-UP PORTC REGISTER R/W-1/1 WPUC7 R/W-1/1 (3) (3) WPUC6 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: 2: 3: WPUC<7:0>: Weak Pull-up Register bits(3) 1 = Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. WPUC<7:6> are available on PIC16(L)F1707 only. 2013-2015 Microchip Technology Inc. DS40001722C-page 125 PIC16(L)F1703/7 REGISTER 11-22: ODCONC: PORTC OPEN DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODC7(1) ODC6(1) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared ODC<7:0>: PORTC Open Drain Enable bits(1) For RC<7:0> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) bit 7-0 Note 1: ODC<7:6> are available on PIC16(L)F1707 only. REGISTER 11-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRC7(1) SLRC6(1) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared SLRC<7:0>: PORTC Slew Rate Enable bits(1) For RC<7:0> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate bit 7-0 Note 1: SLRC<7:6> are available on PIC16(L)F1707 only. REGISTER 11-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: INLVLC<7:0>: PORTC Input Level Select bits(1) For RC<7:0> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change INLVLC<7:6> are available on PIC16(L)F1707 only. DS40001722C-page 126 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 11-5: Name ANSELC ANSC6(1) LATC7 (1) SLRCONC Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 125 INLVLC1 INLVLC0 126 Bit 5 (1) INLVLC6 Bit 4 INLVLC5 INLVLC4 INLVLC3 INLVLC2 (1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 (1) LATC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 126 RC6(1) RC5 RC4 RC3 RC2 RC1 RC0 124 SLRC7(1) SLRC6(1) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 126 (1) (1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 124 (1) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 125 TRISC7 (1) WPUC7 ODC6 124 RC7(1) ODC7 PORTC Note 1: 2: ANSC7(1) (1) ODCONC Legend: Bit 6 INLVLC7 LATC WPUC Bit 7 (1) INLVLC TRISC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC TRISC6 WPUC6 x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. PIC16(L)F1707 only. PIC16(L)F1703 only. 2013-2015 Microchip Technology Inc. DS40001722C-page 127 PIC16(L)F1703/7 12.0 PERIPHERAL PIN SELECT (PPS) MODULE The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. Input and output selections are independent as shown in the simplified block diagram Figure 12-1. 12.1 PPS Inputs Each peripheral has a PPS register with which the inputs to the peripheral are selected. Inputs include the device pins. Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has associated analog functions, the ANSEL bit for that pin must be cleared to enable the digital input buffer. Although every peripheral has its own PPS input selection register, the selections are identical for every peripheral as shown in Register 12-1 for PIC16(L)F1703 devices and Register 12-2 for PIC16(L)F1707 devices. Note: 12.2 PPS Outputs Each I/O pin has a PPS register with which the pin output source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS control as needed. These peripherals include: • MSSP (I2C) Although every pin has its own PPS peripheral selection register, the selections are identical for every pin as shown in Register 12-3. Note: FIGURE 12-1: The notation “xxx” in the register name is a place holder for the peripheral identifier. For example, CCP1PPS. The notation “Rxy” is a place holder for the pin identifier. For example, RA0PPS. SIMPLIFIED PPS BLOCK DIAGRAM PPS Outputs RA0PPS PPS Inputs abcPPS RA0 RA0 Peripheral abc RxyPPS Rxy Peripheral xyz RC7 xyzPPS DS40001722C-page 128 RC7PPS RC7 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 12.3 Bidirectional Pins PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS input and PPS output select the same pin. Peripherals that have bidirectional signals include: • MSSP (I2C) Note: The I2C default input pins are I2C and SMBus compatible and are the only pins on the device with this compatibility. 12.5 The PPS can be permanently locked by setting the PPS1WAY Configuration bit. When this bit is set, the PPSLOCKED bit can only be cleared and set one time after a device Reset. This allows for clearing the PPSLOCKED bit so that the input and output selections can be made during initialization. When the PPSLOCKED bit is set after all selections have been made, it will remain set and cannot be cleared until after the next device Reset event. 12.6 12.4 PPS Lock The PPS includes a mode in which all input and output selections can be locked to prevent inadvertent changes. PPS selections are locked by setting the PPSLOCKED bit of the PPSLOCK register. Setting and clearing this bit requires a special sequence as an extra precaution against inadvertent changes. Examples of setting and clearing the PPSLOCKED bit are shown in Example 12-1. EXAMPLE 12-1: PPS Permanent Lock Operation During Sleep PPS input and output selections are unaffected by Sleep. 12.7 Effects of a Reset A device Power-On-Reset (POR) clears all PPS input and output selections to their default values. All other Resets leave the selections unchanged. Default input selections are shown in pin allocation Table 1 and Table 2. PPS LOCK/UNLOCK SEQUENCE ; suspend interrupts bcf INTCON,GIE ; BANKSEL PPSLOCK ; set bank ; required sequence, next 5 instructions movlw 0x55 movwf PPSLOCK movlw 0xAA movwf PPSLOCK ; Set PPSLOCKED bit to disable writes or ; Clear PPSLOCKED bit to enable writes bsf PPSLOCK,PPSLOCKED ; restore interrupts bsf INTCON,GIE 2013-2015 Microchip Technology Inc. DS40001722C-page 129 PIC16(L)F1703/7 12.8 Register Definitions: PPS Input Selection REGISTER 12-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION (PIC16(L)F1703) U-0 U-0 U-0 — — — R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u xxxPPS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 xxxPPS<4:0>: Peripheral xxx Input Selection bits 11xxx = Reserved. Do not use. 1011x = Reserved. Do not use. 10101 = Peripheral input is RC5 10100 = Peripheral input is RC4 10011 = Peripheral input is RC3 10010 = Peripheral input is RC2 10001 = Peripheral input is RC1 10000 = Peripheral input is RC0 01xxx = Reserved. Do not use. 0011X = Reserved. Do not use. 00101 = Peripheral input is RA5 00100 = Peripheral input is RA4 00011 = Peripheral input is RA3 00010 = Peripheral input is RA2 00001 = Peripheral input is RA1 00000 = Peripheral input is RA0 DS40001722C-page 130 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 12-2: xxxPPS: PERIPHERAL xxx INPUT SELECTION (PIC16(L)F1707) U-0 U-0 U-0 — — — R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u xxxPPS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 xxxPPS<4:0>: Peripheral xxx Input Selection bits 11xxx = Reserved. Do not use. 10111 = Peripheral input is RC7 10110 = Peripheral input is RC6 10101 = Peripheral input is RC5 10100 = Peripheral input is RC4 10011 = Peripheral input is RC3 10010 = Peripheral input is RC2 10001 = Peripheral input is RC1 10000 = Peripheral input is RC0 01111 = Peripheral input is RB7 01110 = Peripheral input is RB6 01101 = Peripheral input is RB5 01100 = Peripheral input is RB4 010xx = Reserved. Do not use. 0011X = Reserved. Do not use. 00101 = Peripheral input is RA5 00100 = Peripheral input is RA4 00011 = Peripheral input is RA3 00010 = Peripheral input is RA2 00001 = Peripheral input is RA1 00000 = Peripheral input is RA0 2013-2015 Microchip Technology Inc. DS40001722C-page 131 PIC16(L)F1703/7 REGISTER 12-3: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER U-0 U-0 U-0 — — — R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u RxyPPS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RxyPPS<4:0>: Pin Rxy Output Source Selection bits 11xxx = Reserved 10111 = Rxy source is C2OUT 10110 = Rxy source is C1OUT 10101 = Reserved 10100 = Reserved 10011 = Reserved 10010 = Rxy source is SDO 10001 = Rxy source is SDA(1) 10000 = Rxy source is SCK/SCL(1) 01111 = Reserved 01110 = Reserved 01101 = Rxy source is CCP2 01100 = Rxy source is CCP1 01011 = Reserved 01010 = Reserved 01001 = Reserved 01000 = Reserved 00111 = Reserved 00110 = Reserved 00101 = Reserved 00100 = Reserved 00011 = Reserved 00010 = Reserved 00001 = Reserved 00000 = Rxy source is LATxy Note 1: TRIS control is overridden by the peripheral as required. DS40001722C-page 132 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 12-4: PPSLOCK: PPS LOCK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 — — — — — — — PPSLOCKED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 PPSLOCKED: PPS Locked bit 1= PPS is locked. PPS selections can not be changed. 0= PPS is not locked. PPS selections can be changed. 2013-2015 Microchip Technology Inc. DS40001722C-page 133 PIC16(L)F1703/7 TABLE 12-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE Bit 2 Bit 1 Bit 0 Register on page — — PPSLOCKED 133 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PPSLOCK — — — — — INTPPS — — — INTPPS<4:0> 131 T0CKIPPS — — — T0CKIPPS<4:0> 131 T1CKIPPS — — — T1CKIPPS<4:0> 131 T1GPPS — — — T1GPPS<4:0> 131 CCP1PPS — — — CCP1PPS<4:0> 131 CCP2PPS — — — CCP2PPS<4:0> 131 SSPCLKPPS — — — SSPCLKPPS<4:0> 131 SSPDATPPS — — — SSPDATPPS<4:0> 131 SSPSSPPS — — — SSPSSPPS<4:0> 131 RA0PPS — — — RA0PPS<4:0> 132 RA1PPS — — — RA1PPS<4:0> 132 RA2PPS — — — RA2PPS<4:0> 132 RA4PPS — — — RA4PPS<4:0> 132 RA5PPS — — — RA5PPS<4:0> 132 RB4PPS(1) — — — RB4PPS<4:0> 132 (1) — — — RB5PPS<4:0> 132 RB6PPS(1) — — — RB6PPS<4:0> 132 RB7PPS(1) — — — RB7PPS<4:0> 132 RC0PPS — — — RC0PPS<4:0> 132 RC1PPS — — — RC1PPS<4:0> 132 RC2PPS — — — RC2PPS<4:0> 132 RC3PPS — — — RC3PPS<4:0> 132 RC4PPS — — — RC4PPS<4:0> 132 RC5PPS — — — RC5PPS<4:0> 132 (1) — — — RC6PPS<4:0> 132 RC7PPS(1) — — — RC7PPS<4:0> 132 RB5PPS RC6PPS Legend: — = unimplemented, read as ‘0’. Note 1: PIC16(L)F1707 only. DS40001722C-page 134 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 13.0 INTERRUPT-ON-CHANGE All pins on all ports can be configured to operate as Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual pin, or combination of pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: • • • • Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags Figure 13-1 is a block diagram of the IOC module. 13.1 Enabling the Module 13.3 Interrupt Flags The bits located in the IOCxF registers are status flags that correspond to the interrupt-on-change pins of each port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCxF bits. 13.4 Clearing Interrupt Flags The individual status flags, (IOCxF register bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. To allow individual pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. 13.2 Individual Pin Configuration EXAMPLE 13-1: For each pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set. MOVLW XORWF ANDWF A pin can be configured to detect rising and falling edges simultaneously by setting the associated bits in both of the IOCxP and IOCxN registers. 13.5 CLEARING INTERRUPT FLAGS (PORTA EXAMPLE) 0xff IOCAF, W IOCAF, F Operation in Sleep The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the affected IOCxF register will be updated prior to the first instruction executed out of Sleep. 2013-2015 Microchip Technology Inc. DS40001722C-page 135 PIC16(L)F1703/7 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) IOCANx D Q R Q4Q1 edge detect RAx IOCAPx D data bus = 0 or 1 Q write IOCAFx R D S to data bus IOCAFx Q R IOCIE Q2 IOC interrupt to CPU core from all other IOCnFx individual pin detectors FOSC Q1 Q1 Q3 Q2 Q3 Q4 Q4Q1 Q1 Q2 Q2 Q3 Q4 Q4Q1 DS40001722C-page 136 Q4 Q4Q1 Q4Q1 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 13.6 Register Definitions: Interrupt-on-Change Control REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx. 0 = No change was detected, or the user cleared the detected change. 2013-2015 Microchip Technology Inc. DS40001722C-page 137 PIC16(L)F1703/7 IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER(1) REGISTER 13-4: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 3-0 Unimplemented: Read as ‘0’ Note 1: PIC16(L)F1707 only. IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER(1) REGISTER 13-5: R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 3-0 Note Unimplemented: Read as ‘0’ 1: PIC16(L)F1707 only. IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER(1) REGISTER 13-6: R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 U-0 U-0 U-0 U-0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-4 IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. bit 3-0 Unimplemented: Read as ‘0’ Note 1: PIC16(L)F1707 only. DS40001722C-page 138 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 13-7: IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 IOCCP<7:0>: Interrupt-on-Change PORTC Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCCFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. PIC16(L)F1707 only. Note 1: REGISTER 13-8: IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared IOCCN<7:0>: Interrupt-on-Change PORTC Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 7-0 PIC16(L)F1707 only. Note 1: REGISTER 13-9: R/W/HS-0/0 (1) IOCCF7 IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER R/W/HS-0/0 (1) IOCCF6 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-0 Note 1: U = Unimplemented bit, read as ‘0’ IOCCF<7:0>: Interrupt-on-Change PORTC Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling edge was detected on RCx. 0 = No change was detected, or the user cleared the detected change. PIC16(L)F1707 only. 2013-2015 Microchip Technology Inc. DS40001722C-page 139 PIC16(L)F1703/7 TABLE 13-1: Name ANSELA (1) ANSELB SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 114 ANSB4 — — — — 120 125 — — (1) ANSB5 (1) ANSC3 ANSC2 ANSC1 ANSC0 PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 77 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 137 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 137 ANSC7 ANSC5 (2) GIE ANSELC INTCON ANSC6 (2) ANSC4 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 137 IOCBF(1) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 138 IOCBN(1) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 138 (1) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 138 IOCAP IOCBP IOCCF IOCCF7 IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 139 IOCCN IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 139 IOCCP IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 139 TRISA2 TRISA1 TRISA0 113 TRISA (1) TRISB TRISC Legend: Note 1: 2: 3: (1) — TRISB7 TRISC7 (1) — TRISA5 TRISA4 —(3) TRISB6 TRISB5 TRISB4 — — — — 119 TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 124 — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. PIC16(L)F1707 only. PIC16(L)F1703 only. Unimplemented, read as ‘1’. DS40001722C-page 140 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 14.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • ADC input channel • ADC positive reference Independent Gain Amplifiers The output of the FVR supplied to the ADC is routed through two independent programmable gain amplifiers. Each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. FIGURE 14-1: The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings supplied to the Op Amp. 14.2 The FVR can be enabled by setting the FVREN bit of the FVRCON register. 14.1 The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 16.0 “Analog-to-Digital Converter (ADC) Module” for additional information. FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Figure 27-62. VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> 2 X1 X2 X4 FVR_buffer1 (To ADC Module) X1 X2 X3 FVR_buffer2 (To Op Amp Module) HFINTOSC Enable HFINTOSC To BOR, LDO FVREN + _ FVRRDY Any peripheral requiring the Fixed Reference (See Table 14-1) TABLE 14-1: Peripheral HFINTOSC PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Conditions Description FOSC<1:0> = 00 and IRCF<3:0> 000x INTOSC is active and device is not in Sleep BOREN<1:0> = 11 BOR always enabled BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled LDO All PIC16F1703/7 devices, when VREGPM = 1 and not in Sleep The device runs off of the ULP regulator when in Sleep mode 2013-2015 Microchip Technology Inc. D40001722C-page 141 PIC16(L)F1703/7 14.3 Register Definitions: FVR Control REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q FVREN FVRRDY(1) R/W-0/0 TSEN (3) R/W-0/0 TSRNG R/W-0/0 (3) R/W-0/0 R/W-0/0 CDAFVR<1:0> R/W-0/0 ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 CDAFVR<1:0>: Op Amp Fixed Voltage Reference Selection bit 11 = Op Amp Fixed Voltage Reference Peripheral output is 4x (4.096V)(2) 10 = Op Amp Fixed Voltage Reference Peripheral output is 2x (2.048V)(2) 01 = Op Amp Fixed Voltage Reference Peripheral output is 1x (1.024V) 00 = Op Amp Fixed Voltage Reference Peripheral is off. bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit 11 = ADC FVR Buffer Gain is 4x, with output VADFVR = 4x VFVR(2) 10 = ADC FVR Buffer Gain is 2x, with output VADFVR = 2x VFVR(2) 01 = ADC FVR Buffer Gain is 1x, with output VADFVR = 1x VFVR 00 = ADC FVR Buffer is off Note 1: 2: 3: FVRRDY is always ‘1’ on PIC16F1703/7 only. Fixed Voltage Reference output cannot exceed VDD. See Section 15.0 “Temperature Indicator Module” for additional information. TABLE 14-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 142 Shaded cells are not used with the Fixed Voltage Reference. D40001722C-page 142 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. VDD TSEN TSRNG The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal Temperature Indicator” (DS01333) for more details regarding the calibration process. 15.1 Circuit Operation Figure 15-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 15-1 describes the output characteristics of the temperature indicator. EQUATION 15-1: VOUT RANGES TEMPERATURE CIRCUIT DIAGRAM VOUT Temp. Indicator 15.2 To ADC Minimum Operating VDD When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 15-1 shows the recommended minimum VDD vs. range setting. High Range: VOUT = VDD - 4VT TABLE 15-1: Low Range: VOUT = VDD - 2VT The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 15.3 Temperature Output The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to Section 16.0 “Analog-to-Digital Converter (ADC) Module” for detailed information. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2013-2015 Microchip Technology Inc. DS40001722C-page 143 PIC16(L)F1703/7 15.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output. TABLE 15-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 142 Shaded cells are unused by the temperature indicator module. DS40001722C-page 144 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 16.0 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 16-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 16-1: ADC BLOCK DIAGRAM VDD ADPREF = 11 ADPREF = 00 VREF+ FVR_Buffer1 ADPREF = 10 VREF- = VSS AN0 00000 VREF+/AN1 00001 AN2 00010 AN3 00011 AN4 00100 AN5 00101 AN6 00110 AN7 00111 Ref+ Ref- AN8 01000 ADC AN9 01001 AN10 01010 AN11 01011 10 GO/DONE ADFM 0 = Left Justify 1 = Right Justify 16 ADON Temp Indicator 11101 FVR_Buffer1 11111 VSS ADRESH ADRESL CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2013-2015 Microchip Technology Inc. DS40001722C-page 145 PIC16(L)F1703/7 16.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 16.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 11.0 “I/O Ports” for more information. Note: 16.1.2 Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. CHANNEL SELECTION There are up to 17 channel selections available: • • • • 16.1.4 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: • • • • • • • FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (internal RC oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 16-2. For correct conversion, the appropriate TAD specification must be met. Refer to Table 26-15 for more information. Table 16-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. AN<13:8, 4:0> pins (PIC16(L)F1703 only) AN<21,13:0> pins (PIC16(L)F1707 only) Temperature Indicator FVR_buffer1 The CHS bits of the ADCON0 register (Register 16-1) determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 16.2 “ADC Operation” for more information. 16.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: • • • • • VREF+ pin VDD FVR 2.048V FVR 4.096V (Not available on LF devices) VSS See Section 16.0 “Analog-to-Digital Converter (ADC) Module” for more details on the Fixed Voltage Reference. DS40001722C-page 146 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 16-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 125 ns (2) (2) (2) (2) FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) FOSC/16 101 800 ns 800 ns 010 1.0 s FOSC/64 110 FRC x11 FOSC/32 Legend: Note 1: 2: 3: 4: 1.0 s 4.0 s 1.0 s 2.0 s 8.0 s(3) 1.0 s 2.0 s 4.0 s 16.0 s(3) 1.6 s 2.0 s 4.0 s 2.0 s 3.2 s 4.0 s 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 200 ns 250 ns 500 ns 8.0 s 32.0 s(2) (3) 8.0 s 16.0 s (3) 64.0 s(2) (2) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Shaded cells are outside of recommended range. See TAD parameter for FRC source typical TAD value. These values violate the required TAD time. Outside the recommended TAD time. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 16-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 THCD Conversion Starts TACQ Holding capacitor disconnected from analog input (THCD). Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. Enable ADC (ADON bit) and Select channel (ACS bits) 2013-2015 Microchip Technology Inc. DS40001722C-page 147 PIC16(L)F1703/7 16.1.5 INTERRUPTS 16.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 16-3 shows the two output formats. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the ADIE bit of the PIE1 register and the PEIE bit of the INTCON register must both be set and the GIE bit of the INTCON register must be cleared. If all three of these bits are set, the execution will switch to the Interrupt Service Routine. FIGURE 16-3: 10-BIT ADC CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit ADC Result (ADFM = 1) Unimplemented: Read as ‘0’ MSB bit 7 Unimplemented: Read as ‘0’ DS40001722C-page 148 bit 0 LSB bit 0 bit 7 bit 0 10-bit ADC Result 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 16.2 16.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 16.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 16.2.6 “ADC Conversion Procedure”. COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF Interrupt Flag bit • Update the ADRESH and ADRESL registers with new conversion result 16.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 16.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC oscillator source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 16.2.5 AUTO-CONVERSION TRIGGER The Auto-conversion Trigger allows periodic ADC measurements without software intervention. When a rising edge of the selected source occurs, the GO/DONE bit is set by hardware. The Auto-conversion Trigger source is selected with the TRIGSEL<3:0> bits of the ADCON2 register. Using the Auto-conversion Trigger does not assure proper ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met. See Table 16-2 for auto-conversion sources. TABLE 16-2: AUTO-CONVERSION SOURCES Source Peripheral Signal Name CCP1 CCP2 2013-2015 Microchip Technology Inc. Timer0 T0_overflow Timer1 T1_overflow Timer2 T2_match DS40001722C-page 149 PIC16(L)F1703/7 16.2.6 ADC CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: • Disable pin output driver (Refer to the TRIS register) • Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: • Select ADC conversion clock • Configure voltage reference • Select ADC input channel • Turn on ADC module Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 16-1: ADC CONVERSION ;This code block configures the ADC ;for polling, Vdd and Vss references, FRC ;oscillator and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B’11110000’ ;Right justify, FRC ;oscillator MOVWF ADCON1 ;Vdd and Vss Vref BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B’00000001’ ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 16.4 “ADC Acquisition Requirements”. DS40001722C-page 150 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 16.3 Register Definitions: ADC Control REGISTER 16-1: U-0 ADCON0: ADC CONTROL REGISTER 0 R/W-0/0 R/W-0/0 — R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> R/W-0/0 R/W-0/0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 11111 = FVR (Fixed Voltage Reference) Buffer 1 Output(1) 11110 = Reserved 11101 = Temperature Indicator(2) 11100 = Reserved. No channel connected. • • • 01100 = Reserved. No channel connected. 01011 = AN11 01010 = AN10 01001 = AN9 01000 = AN8 00111 = AN7 00110 = AN6 00101 = AN5 00100 = AN4 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0 bit 1 GO/DONE: ADC Conversion Status bit 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC conversion has completed. 0 = ADC conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. See Section 15.0 “Temperature Indicator Module” for more information. 2013-2015 Microchip Technology Inc. DS40001722C-page 151 PIC16(L)F1703/7 REGISTER 16-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 R/W-0/0 — ADNREF R/W-0/0 bit 7 R/W-0/0 ADPREF<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded. bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits 111 = FRC (clock supplied from an internal RC oscillator) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock supplied from an internal RC oscillator) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 bit 3 Unimplemented: Read as ‘0’ bit 2 ADNREF: ADC Negative Voltage Reference Configuration bit 0 = VREF- is connected to VSS 1 = VREF- is connected to VREF- pin bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits 11 = VREF+ is connected to internal FVR_Buffer1(1) 10 = VREF+ is connected to external VREF+ pin(1) 01 = Reserved 00 = VREF+ is connected to VDD Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Table 26-15 for details. DS40001722C-page 152 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 16-3: R/W-0/0 ADCON2: ADC CONTROL REGISTER 2 R/W-0/0 R/W-0/0 TRIGSEL<3:0> R/W-0/0 (1) U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 bit 3-0 Note 1: 2: TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1) 0000 = No auto-conversion trigger selected 0001 = CCP1 0010 = CCP2 0011 = Timer0 – T0_overflow(2) 0100 = Timer1 – T1_overflow(2) 0101 = Timer2 – T2_match 0110 = Reserved 0111 = Reserved 1000 = Reserved 1001 = Reserved 1010 = Reserved 1011 = Reserved 1100 = Reserved 1101 = Reserved 1110 = Reserved 1111 = Reserved Unimplemented: Read as ‘0’ This is a rising edge sensitive input for all sources. Signal also sets its corresponding interrupt flag. 2013-2015 Microchip Technology Inc. DS40001722C-page 153 PIC16(L)F1703/7 REGISTER 16-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 16-5: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u ADRES<1:0> R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. DS40001722C-page 154 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 16-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 16-7: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result 2013-2015 Microchip Technology Inc. DS40001722C-page 155 PIC16(L)F1703/7 16.4 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 16-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 16-1: Assumptions: source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an ADC acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 16-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50°C and external impedance of 10k 5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2µs + T C + Temperature - 25°C 0.05µs/°C The value for TC can be approximated with the following equations: 1 = V CHOLD V AP P LI ED 1 – -------------------------n+1 2 –1 ;[1] VCHOLD charged to within 1/2 lsb –TC ---------- RC V AP P LI ED 1 – e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED – Tc --------- 1 RC ;combining [1] and [2] V AP P LI ED 1 – e = V A PP LIE D 1 – -------------------------n+1 2 –1 Note: Where n = number of bits of the ADC. Solving for TC: T C = – C HOLD R IC + R SS + R S ln(1/2047) = – 10pF 1k + 7k + 10k ln(0.0004885) = 1.37 µs Therefore: T A CQ = 2µs + 892ns + 50°C- 25°C 0.05 µs/°C = 4.62µs Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. DS40001722C-page 156 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 16-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.6V CHOLD = 10 pF Ref- 6V 5V VDD 4V 3V 2V = Sample/Hold Capacitance = Input Capacitance Legend: CHOLD CPIN RSS I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC = Resistance of Sampling Switch RSS SS = Sampling Switch VT = Threshold Voltage Note 1: FIGURE 16-5: 5 6 7 8 9 10 11 Sampling Switch (k) Refer to Table 26-4 (parameter D060). ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 3FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB Ref- 2013-2015 Microchip Technology Inc. Zero-Scale Transition 1.5 LSB Full-Scale Transition Ref+ DS40001722C-page 157 PIC16(L)F1703/7 TABLE 16-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 — ADCON1 ADFM ADCON2 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> ADCS<2:0> TRIGSEL<3:0> Bit 1 Bit 0 Register on Page GO/DONE ADON 151 ADNREF<1:0> ADPREF<1:0> 152 — — 153 — — ADRESH ADRES<7:0> 154, 155 ADRESL ADRES<7:0> 154, 155 ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 114 — — ANSB5 ANSB4 — — — — 120 ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 125 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 81 PIE1 TMR1GIE ADIE — — SSP1IE CCP1IE TMR2IE TMR1IE 78 PIR1 TMR1GIF ADIF — — SSP1IF CCP1IF TMR2IF TMR1IF 81 — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 113 TRISB7 TRISB6 TRISB5 TRISB4 — — — — 119 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 124 ANSELB (1) TRISA TRISB(1) TRISC Legend: Note 1: 2: 3: x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for the ADC module. PIC16(L)F1707 only. PIC16(L)F1703 only. Unimplemented, read as ‘1’. DS40001722C-page 158 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 17.0 OPERATIONAL AMPLIFIER (OPA) MODULES The Operational Amplifier (OPA) is a standard 3-terminal device requiring external feedback to operate. The OPA module has the following features: • External connections to I/O ports • Low leakage inputs • Factory Calibrated Input Offset Voltage FIGURE 17-1: OPAx MODULE BLOCK DIAGRAM OPAxIN+ 0x Reserved 10 FVR_Buffer2 11 OPAXEN OPAXSP(1) OPAxIN- 0 OPA OPAXOUT 1 OPAxNCH<1:0> Note 1: OPAXUG The OPAxSP bit must be set. Low-Power mode is not supported. 2013-2015 Microchip Technology Inc. DS40001722C-page 159 PIC16(L)F1703/7 17.1 OPA Module Performance Common AC and DC performance specifications for the OPA module: • • • • • Common-Mode Voltage Range Leakage Current Input Offset Voltage Open Loop Gain Gain Bandwidth Product Common-mode voltage range is the specified voltage range for the OPA+ and OPA- inputs, for which the OPA module will perform to within its specifications. The OPA module is designed to operate with input voltages between VSS and VDD. Behavior for common-mode voltages greater than VDD, or below VSS, are not guaranteed. Leakage current is a measure of the small source or sink currents on the OPA+ and OPA- inputs. To minimize the effect of leakage currents, the effective impedances connected to the OPA+ and OPA- inputs should be kept as small as possible and equal. Input offset voltage is a measure of the voltage difference between the OPA+ and OPA- inputs in a closed loop circuit with the OPA in its linear region. The offset voltage will appear as a DC offset in the output equal to the input offset voltage, multiplied by the gain of the circuit. The input offset voltage is also affected by the common-mode voltage. The OPA is factory calibrated to minimize the input offset voltage of the module. 17.1.1 OPA Module Control The OPA module is enabled by setting the OPAxEN bit of the OPAxCON register. When enabled, the OPA forces the output driver of OPAxOUT pin into tri-state to prevent contention between the driver and the OPA output. Note: 17.1.2 When the OPA module is enabled, the OPAxOUT pin is driven by the Op Amp output, not by the PORT digital driver. Refer to Table 26-16 for the Op Amp output drive capability. UNITY GAIN MODE The OPAxUG bit of the OPAxCON register selects the Unity Gain mode. When unity gain is selected, the OPA output is connected to the inverting input and the OPAxIN pin is relinquished, releasing the pin for general purpose input and output. 17.2 Effects of Reset A device Reset forces all registers to their Reset state. This disables the OPA module. Open loop gain is the ratio of the output voltage to the differential input voltage, (OPA+) - (OPA-). The gain is greatest at DC and falls off with frequency. Gain Bandwidth Product or GBWP is the frequency at which the open loop gain falls off to 0 dB. DS40001722C-page 160 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 17.3 Register Definitions: Op Amp Control REGISTER 17-1: OPAxCON: OPERATIONAL AMPLIFIERS (OPAx) CONTROL REGISTERS R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 U-0 OPAxEN OPAxSP — OPAxUG — — R/W-0/0 R/W-0/0 OPAxPCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 OPAxEN: Op Amp Enable bit 1 = Op Amp is enabled 0 = Op Amp is disabled and consumes no active power bit 6 OPAxSP: Op Amp Speed/Power Select bit 1 = Op Amp operates in high GBWP mode 0 = Reserved. Do not use. bit 5 Unimplemented: Read as ‘0’ bit 4 OPAxUG: Op Amp Unity Gain Select bit 1 = OPA output is connected to inverting input. OPAxIN- pin is available for general purpose I/O. 0 = Inverting input is connected to the OPAxIN- pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 OPAxPCH<1:0>: Non-inverting Channel Selection bits 11 = Non-inverting input connects to FVR_Buffer2 output 10 = Reserved 0x = Non-inverting input connects to OPAxIN+ pin TABLE 17-1: Name ANSELB(1) SUMMARY OF REGISTERS ASSOCIATED WITH OP AMPS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSB5 ANSB4 — — — — 120 ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 125 FVRCON FVREN FVRRDY TSEN TSRNG OPA1CON OPA1EN OPA1SP — OPA1UG — OPA2CON OPA2EN OPA2SP — OPA2UG — TRISB7 TRISB6 TRISB5 TRISB4 — — — — 119 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 124 TRISB(1) TRISC Legend: Note 1: 2: 3: CDAFVR<1:0> ADFVR<1:0> 142 — OPA1PCH<1:0> 161 — OPA2PCH<1:0> 161 — = unimplemented location, read as ‘0’. Shaded cells are not used by Op Amps. PIC16(L)F1707 only. PIC16(L)F1703 only. Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001722C-page 161 PIC16(L)F1703/7 18.0 ZERO-CROSS DETECTION (ZCD) MODULE 18.1 The ZCD module detects when an A/C signal crosses through the ground potential. The actual zero crossing threshold is the zero crossing reference voltage, VREF, which is typically 0.75V above ground. The connection to the signal to be detected is through a series current limiting resistor. The module applies a current source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby preventing the pin voltage from forward biasing the ESD protection diodes. When the applied voltage is greater than the reference voltage, the module sinks current. When the applied voltage is less than the reference voltage, the module sources current. The current source and sink action keeps the pin voltage constant over the full range of the applied voltage. The ZCD module is shown in the simplified block diagram Figure 18-2. The ZCD module requires a current limiting resistor in series with the external voltage source. The impedance and rating of this resistor depends on the external source peak voltage. Select a resistor value that will drop all of the peak voltage when the current through the resistor is nominally 300 A. Refer to Equation 18-1 and Figure 18-1. Make sure that the ZCD I/O pin internal weak pull-up is disabled so it does not interfere with the current source and sink. EQUATION 18-1: FIGURE 18-1: VMAXPEAK VMINPEAK VREF SIMPLIFIED ZCD BLOCK DIAGRAM optional VDD Vpullup Rpullup External current limiting resistor Vref EXTERNAL VOLTAGE VPEAK A/C period measurement Accurate long term time measurement Dimmer phase delayed drive Low EMI cycle switching FIGURE 18-2: EXTERNAL RESISTOR V PEAK R SERIES = ---------------–4 3 10 The ZCD module is useful when monitoring an A/C waveform for, but not limited to, the following purposes: • • • • External Resistor Selection + Rseries ZCD pin Rpulldown optional External voltage source ZCDx_output D ZCDxPOL Q1 Q ZCDxOUT LE Interrupt det ZCDxINTP Sets ZCDIF flag ZCDxINTN Interrupt det DS40001722C-page 162 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 18.2 ZCD Logic Output The ZCD module includes a Status bit, which can be read to determine whether the current source or sink is active. The ZCDxOUT bit of the ZCDCON register is set when the current sink is active, and cleared when the current source is active. The ZCDxOUT bit is affected by the polarity bit. 18.3 ZCD Logic Polarity The ZCDxPOL bit of the ZCDxCON register inverts the ZCDxOUT bit relative to the current source and sink output. When the ZCDxPOL bit is set, a ZCDxOUT high indicates that the current source is active, and a low output indicates that the current sink is active. The ZCDxPOL bit affects the ZCD interrupts. See Section 18.4 “ZCD Interrupts”. 18.5 Correcting for VREF offset The actual voltage at which the ZCD switches is the reference voltage at the non-inverting input of the ZCD Op Amp. For external voltage source waveforms other than square waves, this voltage offset from zero causes the zero-cross event to occur either too early or too late. When the waveform is varying relative to VSS, then the zero cross is detected too early as the waveform falls and too late as the waveform rises. When the waveform is varying relative to VDD, then the zero cross is detected too late as the waveform rises and too early as the waveform falls. The actual offset time can be determined for sinusoidal waveforms with the corresponding equations shown in Equation 18-2. EQUATION 18-2: ZCD EVENT OFFSET When External Voltage Source is relative to Vss: 18.4 ZCD Interrupts An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in the ZCD for this purpose. The ZCDIF bit of the PIR3 register will be set when either edge detector is triggered and its associated enable bit is set. The ZCDxINTP enables rising edge interrupts and the ZCDxINTN bit enables falling edge interrupts. Both are located in the ZCDxCON register. To fully enable the interrupt, the following bits must be set: • ZCDIE bit of the PIE3 register • ZCDxINTP bit of the ZCDxCON register (for a rising edge detection) • ZCDxINTN bit of the ZCDxCON register (for a falling edge detection) • PEIE and GIE bits of the INTCON register Changing the ZCDxPOL bit will cause an interrupt, regardless of the level of the ZCDxEN bit. The ZCDIF bit of the PIR3 register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. T OFFSET V REF asin ---------------- V PEAK = -------------------------------2 Freq When External Voltage Source is relative to VDD: T OFFSET V DD – V REF asin --------------------------- V PEAK = ------------------------------------------2 Freq This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin. A pull-up resistor is used when the external voltage source is varying relative to VSS. A pull-down resistor is used when the voltage is varying relative to VDD. The resistor adds a bias to the ZCD pin so that the target external voltage source must go to zero to pull the pin voltage to the VREF switching voltage. The pull-up or pull-down value can be determined with the equations shown in Equation 18-3 or Equation 18-4. EQUATION 18-3: ZCD PULL-UP/DOWN When External Signal is relative to Vss: R SERIE S V PULLUP – V REF R PULLUP = ----------------------------------------------------------------V REF When External Signal is relative to VDD: R SERIES V REF R PULLDOWN = ------------------------------------ V DD – V REF 2013-2015 Microchip Technology Inc. DS40001722C-page 163 PIC16(L)F1703/7 The pull-up and pull-down resistor values are significantly affected by small variations of VREF. Measuring VREF can be difficult, especially when the waveform is relative to VDD. However, by combining Equations 18-2 and 18-3, the resistor value can be determined from the time difference between the ZCDx_output high and low periods. Note that the time difference, ∆T, is 4*TOFFSET. The equation for determining the pull-up and pull-down resistor values from the high and low ZCDx_output periods is shown in Equation 18-4. The ZCDx_output signal can be directly observed on a pin by routing the ZCDx_output signal through one of the CLCs. EQUATION 18-4: V BI A S R = R SERIES ---------------------------------------------------------------- – 1 T V PE AK sin Freq ---------- 2 18.6 Handling VPEAK variations If the peak amplitude of the external voltage is expected to vary, the series resistor must be selected to keep the ZCD current source and sink below the design maximum range of ± 600 A and above a reasonable minimum range. A general rule of thumb is that the maximum peak voltage can be no more than six times the minimum peak voltage. To ensure that the maximum current does not exceed ± 600 A and the minimum is at least ± 100 A, compute the series resistance as shown in Equation 18-5. The compensating pull-up for this series resistance can be determined with Equation 18-3 because the pull-up value is independent from the peak voltage. EQUATION 18-5: SERIES R FOR V RANGE V MAXPEAK + V MINPEAK R SERIES = --------------------------------------------------------–4 7 10 R is pull-up or pull-down resistor. VBIAS is VPULLUP when R is pull-up or VDD when R is pull-down. ∆T is the ZCDx_output high and low period difference. 18.7 Operation During Sleep The ZCD current sources and interrupts are unaffected by Sleep. 18.8 Effects of a Reset The ZCD circuit can be configured to default to the active or inactive state on Power-On-Reset (POR). When the ZCDDIS Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCDDIS Configuration bit is set, the ZCDxEN bit of the ZCDxCON register must be set to enable the ZCD module. DS40001722C-page 164 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 18.9 Register Definitions: ZCD Control REGISTER 18-1: ZCDxCON: ZERO CROSS DETECTION CONTROL REGISTER R/W-q/q U-0 R-x/x R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 ZCDxEN — ZCDxOUT ZCDxPOL — — ZCDxINTP ZCDxINTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits bit 7 ZCDxEN: Zero-Cross Detection Enable bit 1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current. 0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls. bit 6 Unimplemented: Read as ‘0’ bit 5 ZCDxOUT: Zero-Cross Detection Logic Level bit ZCDxPOL bit = 0: 1 = ZCD pin is sinking current 0 = ZCD pin is sourcing current ZCDxPOL bit = 1: 1 = ZCD pin is sourcing current 0 = ZCD pin is sinking current bit 4 ZCDxPOL: Zero-Cross Detection Logic Output Polarity bit 1 = ZCD logic output is inverted 0 = ZCD logic output is not inverted bit 3-2 Unimplemented: Read as ‘0’ bit 1 ZCDxINTP: Zero-Cross Positive Edge Interrupt Enable bit 1 = ZCDIF bit is set on low-to-high ZCDx_output transition 0 = ZCDIF bit is unaffected by low-to-high ZCDx_output transition bit 0 ZCDxINTN: Zero-Cross Negative Edge Interrupt Enable bit 1 = ZCDIF bit is set on high-to-low ZCDx_output transition 0 = ZCDIF bit is unaffected by high-to-low ZCDx_output transition TABLE 18-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page PIE3 — — — ZCDIE — — — — 80 PIR3 — — — ZCDIF — — — — 83 ZCD1EN — ZCD1OUT ZCD1POL — — Name ZCD1CON Legend: TABLE 18-2: Name CONFIG2 Legend: ZCD1INTP ZCD1INTN 165 — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module. Bits SUMMARY OF CONFIGURATION BITS ASSOCIATED WITH THE ZCD MODULE Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 — — LVP DEBUG 7:0 ZCDDIS — — — LPBOR BORV STVREN PLLEN — PPS1WAY WRT<1:0> Register on Page 50 — = unimplemented location, read as ‘0’. Shaded cells are not used by ZCD module. 2013-2015 Microchip Technology Inc. DS40001722C-page 165 PIC16(L)F1703/7 19.0 19.1.2 TIMER0 MODULE 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. • • • • • • 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’. 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION_REG register. Figure 19-1 is a block diagram of the Timer0 module. 19.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 19.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 19-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 Sync 2 TCY 1 TMR0 0 TMR0SE TMR0CS 8-bit Prescaler PSA Set Flag bit TMR0IF on Overflow Overflow to Timer1 8 PS<2:0> DS40001722C-page 166 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 19.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 19.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: 19.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Table 26-12. 19.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. 2013-2015 Microchip Technology Inc. DS40001722C-page 167 PIC16(L)F1703/7 19.2 Register Definitions: Option Register REGISTER 19-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA R/W-1/1 R/W-1/1 R/W-1/1 PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-Up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits TABLE 19-1: Name INTCON Bit Value Timer0 Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 GIE OPTION_REG WPUEN Bit 6 PEIE INTEDG Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF TMR0CS TMR0SE TMR0 TRISA PSA Bit 1 Bit 0 INTF IOCIF PS<2:0> — TRISA5 TRISA4 77 168 TMR0 — Register on Page 166* —(1) TRISA2 TRISA1 TRISA0 113 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. Note 1: Unimplemented, read as ‘1’. DS40001722C-page 168 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 20.0 • Gate Single-pulse mode • Gate Value Status • Gate Event Interrupt TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: • • • • • • • • • • • Figure 20-1 is a block diagram of the Timer1 module. 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 2-bit prescaler Dedicated 32 kHz oscillator circuit Multiple Timer1 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) Time base for the Capture/Compare function Auto-conversion Trigger (with CCP) Selectable Gate Source Polarity Gate Toggle mode FIGURE 20-1: TIMER1 BLOCK DIAGRAM T1GSS<1:0> PPS T1G From Timer0 Overflow 01 Reserved 10 Reserved T1GSPM 00 0 t1g_in T1GVAL 0 Single-Pulse D Q CK R Q 11 TMR1ON T1GTM T1GPOL 1 Acq. Control 1 Q1 Data Bus D Q RD T1GCON EN Interrupt T1GGO/DONE det Set TMR1GIF TMR1GE Set flag bit TMR1IF on Overflow To ADC Auto-Conversion TMR1ON TMR1(2) TMR1H EN TMR1L Q D T1CLK Synchronized clock input 0 1 TMR1CS<1:0> LFINTOSC T1CKI PPS T1SYNC 11 (1) Synchronize(3) Prescaler 1, 2, 4, 8 det 10 FOSC Internal Clock 01 FOSC/4 Internal Clock 00 2 T1CKPS<1:0> FOSC/2 Internal Clock Sleep input To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2013-2015 Microchip Technology Inc. DS40001722C-page 169 PIC16(L)F1703/7 20.1 Timer1 Operation 20.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 20-1 displays the Timer1 enable selections. TABLE 20-1: TIMER1 ENABLE SELECTIONS Clock Source Selection The TMR1CS<1:0> bits of the T1CON register are used to select the clock source for Timer1. Table 20-2 displays the clock source selections. 20.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. The following asynchronous sources may be used: Timer1 Operation • Asynchronous event on the T1G pin to Timer1 gate TMR1ON TMR1GE 0 0 Off 20.2.2 0 1 Off 1 0 Always On When the external clock source is selected, the Timer1 module may work as a timer or a counter. 1 1 Count Enabled EXTERNAL CLOCK SOURCE When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI, which can be synchronized to the microcontroller system clock or can run asynchronously. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • • • • TABLE 20-2: Timer1 enabled after POR Write to TMR1H or TMR1L Timer1 is disabled Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. CLOCK SOURCE SELECTIONS TMR1CS<1:0> Clock Source 11 LFINTOSC 10 External Clocking on T1CKI Pin 01 System Clock (FOSC) 00 Instruction Clock (FOSC/4) DS40001722C-page 170 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 20.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 20.5 Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 Gate Enable. Timer1 gate can also be driven by multiple selectable sources. 20.5.1 20.4 Timer1 Operation in Asynchronous Counter Mode If the control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 20.4.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). Note: 20.4.1 When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. Timer1 Gate TIMER1 GATE ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 20-3 for timing details. TABLE 20-3: TIMER1 GATE ENABLE SELECTIONS T1CLK T1GPOL T1G Timer1 Operation 0 0 Counts 0 1 Holds Count 1 0 Holds Count 1 1 Counts READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. 2013-2015 Microchip Technology Inc. DS40001722C-page 171 PIC16(L)F1703/7 20.5.2 TIMER1 GATE SOURCE SELECTION Timer1 gate source selections are shown in Table 20-4. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 20-4: TIMER1 GATE SOURCES T1GSS Timer1 Gate Source 00 Timer1 Gate Pin 01 Overflow of Timer0 (TMR0 increments from FFh to 00h) 10 Reserved 11 Reserved 20.5.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 20.5.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 20.5.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 20-4 for timing details. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: 20.5.4 TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. See Figure 20-5 for timing details. If the Single-Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE bit should also be cleared. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 20-6 for timing details. 20.5.5 TIMER1 GATE VALUE STATUS When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). 20.5.6 TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. DS40001722C-page 172 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 20.6 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. Note: 20.7 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external or LFINTOSC clock source can be used to increment the counter. To set up the timer to wake the device: • • • • • TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. 20.8 CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be an Auto-conversion Trigger. For more information, see “Capture/Compare/PWM Modules”. 20.9 Section 22.0 CCP Auto-Conversion Trigger When any of the CCP’s are configured to trigger an auto-conversion, the trigger will clear the TMR1H:TMR1L register pair. This auto-conversion does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1. Timer1 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Auto-conversion Trigger. Asynchronous operation of Timer1 can cause an Auto-conversion Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with an Auto-conversion Trigger from the CCP, the write will take precedence. For more information, see Section 22.2.4 “Auto-Conversion Trigger”. Secondary oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 20-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2013-2015 Microchip Technology Inc. DS40001722C-page 173 PIC16(L)F1703/7 FIGURE 20-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 20-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N DS40001722C-page 174 N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 20-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software 2013-2015 Microchip Technology Inc. N+1 N+2 Set by hardware on falling edge of T1GVAL Cleared by software DS40001722C-page 175 PIC16(L)F1703/7 FIGURE 20-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS40001722C-page 176 N Cleared by software N+1 N+2 N+3 N+4 Set by hardware on falling edge of T1GVAL Cleared by software 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 20.10 Register Definitions: Timer1 Control REGISTER 20-1: R/W-0/u T1CON: TIMER1 CONTROL REGISTER R/W-0/u R/W-0/u TMR1CS<1:0> R/W-0/u T1CKPS<1:0> U-0 R/W-0/u U-0 R/W-0/u — T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 = LFINTOSC 10 = External clock from T1CKI pin (on rising edge) 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 Unimplemented: Read as ‘0’ bit 2 T1SYNC: Timer1 Synchronization Control bit 1 = Do not synchronize asynchronous clock input 0 = Synchronize asynchronous clock input with system clock (FOSC) bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop 2013-2015 Microchip Technology Inc. DS40001722C-page 177 PIC16(L)F1703/7 REGISTER 20-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Value Status bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L Unaffected by Timer1 Gate Enable (TMR1GE) bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 11 = Reserved 10 = Reserved 01 = Timer0 overflow output 00 = Timer1 gate pin DS40001722C-page 178 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 20-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 114 CCP1CON — — DC1B<1:0> CCP1M<3:0> CCP2CON — — DC2B<1:0> CCP2M<3:0> GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 77 TMR1GIE ADIE — — SSP1IE CCP1IE TMR2IE TMR1IE 78 TMR1GIF ADIF — — SSP1IF CCP1IF TMR2IF TMR1IF Name INTCON PIE1 PIR1 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register TRISA T1CON T1GCON Legend: * Note 1: — — TMR1CS<1:0> TMR1GE T1GPOL TRISA5 TRISA4 T1CKPS<1:0> T1GTM T1GSPM 193 193 81 169* 169* —(1) TRISA2 TRISA1 TRISA0 113 — T1SYNC — TMR1ON 177 T1GGO/ DONE T1GVAL T1GSS<1:0> 178 — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. Page provides register information. Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001722C-page 179 PIC16(L)F1703/7 21.0 TIMER2 MODULE The Timer2 module is an 8-bit timer that incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP module See Figure 21-1 for a block diagram of Timer2. FIGURE 21-1: Fosc/4 TIMER2 BLOCK DIAGRAM Prescaler 1:1, 1:4, 1:16, 1:64 T2_match TMR2 R To Peripherals 2 T2CKPS<1:0> Comparator Postscaler 1:1 to 1:16 set bit TMR2IF 4 PR2 DS40001722C-page 180 T2OUTPS<3:0> 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 21.1 Timer2 Operation The clock input to the Timer2 modules is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section 21.2 “Timer2 Interrupt”). 21.3 Timer2 Output The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP module operating in SPI mode. Additional information is provided in Section 23.0 “Master Synchronous Serial Port (MSSP) Module” 21.4 Timer2 Operation During Sleep The Timer2 timers cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 registers will remain unchanged while the processor is in Sleep mode. The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • • • • • • • • • a write to the TMR2 register a write to the T2CON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: 21.2 TMR2 is not cleared when T2CON is written. Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE, of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register. 2013-2015 Microchip Technology Inc. DS40001722C-page 181 PIC16(L)F1703/7 21.5 Register Definitions: Timer2 Control REGISTER 21-1: U-0 T2CON: TIMER2 CONTROL REGISTER R/W-0/0 — R/W-0/0 R/W-0/0 R/W-0/0 T2OUTPS<3:0> R/W-0/0 R/W-0/0 TMR2ON bit 7 R/W-0/0 T2CKPS<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits 1111 = 1:16 Postscaler 1110 = 1:15 Postscaler 1101 = 1:14 Postscaler 1100 = 1:13 Postscaler 1011 = 1:12 Postscaler 1010 = 1:11 Postscaler 1001 = 1:10 Postscaler 1000 = 1:9 Postscaler 0111 = 1:8 Postscaler 0110 = 1:7 Postscaler 0101 = 1:6 Postscaler 0100 = 1:5 Postscaler 0011 = 1:4 Postscaler 0010 = 1:3 Postscaler 0001 = 1:2 Postscaler 0000 = 1:1 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 11 = Prescaler is 64 10 = Prescaler is 16 01 = Prescaler is 4 00 = Prescaler is 1 DS40001722C-page 182 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 21-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 CCP2CON — — GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 77 TMR1GIE ADIE — — SSP1IE CCP1IE TMR2IE TMR1IE 78 PIR1 TMR1GIF ADIF — — SSP1IF CCP1IF TMR2IF TMR1IF 81 PR2 Timer2 Module Period Register INTCON PIE1 T2CON TMR2 — Bit 5 Bit 4 Bit 3 DC2B<1:0> T2OUTPS<3:0> Bit 2 Bit 1 Bit 0 Register on Page Name CCP2M<3:0> 193 180* TMR2ON T2CKPS<1:0> Holding Register for the 8-bit TMR2 Register 182 180* Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information. 2013-2015 Microchip Technology Inc. DS40001722C-page 183 PIC16(L)F1703/7 22.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains two standard Capture/Compare/PWM modules (CCP1 and CCP2). The Capture and Compare functions are identical for all CCP modules. Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required. DS40001722C-page 184 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 22.1 22.1.2 Capture Mode The Capture mode function described in this section is available and identical for all CCP modules. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value. Figure 22-1 shows a simplified diagram of the capture operation. 22.1.1 CCP PIN CONFIGURATION In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. FIGURE 22-1: Prescaler 1, 4, 16 CAPTURE MODE OPERATION BLOCK DIAGRAM Set Flag bit CCPxIF (PIRx register) CCPx pin CCPRxH TIMER1 MODE RESOURCE Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. See Section 20.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. 22.1.3 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. Note: 22.1.4 Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. CCP PRESCALER There are four prescaler settings specified by the CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. Example 22-1 demonstrates the code to perform this function. EXAMPLE 22-1: CCPRxL CHANGING BETWEEN CAPTURE PRESCALERS BANKSEL CCPxCON and Edge Detect Capture Enable TMR1H CCPxM<3:0> System Clock (FOSC) 2013-2015 Microchip Technology Inc. TMR1L CLRF MOVLW MOVWF ;Set Bank bits to point ;to CCPxCON CCPxCON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCPxCON ;Load CCPxCON with this ;value DS40001722C-page 185 PIC16(L)F1703/7 22.1.5 CAPTURE DURING SLEEP Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. DS40001722C-page 186 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 22.2 22.2.2 Compare Mode The Compare mode function described in this section is available and identical for all CCP modules. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: • • • • • In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section 20.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. Note: Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate an Auto-conversion Trigger Generate a Software Interrupt The action on the pin is based on the value of the CCPxM<3:0> control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. All Compare modes can generate an interrupt. Figure 22-2 shows a simplified diagram of the compare operation. FIGURE 22-2: COMPARE MODE OPERATION BLOCK DIAGRAM CCPxM<3:0> Mode Select Q S R Output Logic Match TRIS Output Enable Comparator TMR1H TMR1L Auto-conversion Trigger 22.2.1 CCPX PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the associated TRIS bit. Note: 22.2.3 Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register). 22.2.4 AUTO-CONVERSION TRIGGER When Auto-conversion Trigger mode is chosen (CCPxM<3:0> = 1011), the CCPx module does the following: • Resets Timer1 • Starts an ADC conversion if ADC is enabled Set CCPxIF Interrupt Flag (PIRx) 4 CCPRxH CCPRxL CCPx Pin TIMER1 MODE RESOURCE Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. 2013-2015 Microchip Technology Inc. The CCPx module does not assert control of the CCPx pin in this mode. The Auto-conversion Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPRxH, CCPRxL register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The Auto-conversion Trigger output starts an ADC conversion (if the ADC module is enabled). This allows the CCPRxH, CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1. Refer to Section 16.2.5 “Auto-Conversion Trigger” for more information. Note 1: The Auto-conversion Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Auto-conversion Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. DS40001722C-page 187 PIC16(L)F1703/7 22.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. DS40001722C-page 188 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 22.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. FIGURE 22-3: Period Pulse Width 22.3.1 TMR2 = 0 FIGURE 22-4: The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty Cycle Registers CCPR1L CCPR1H(2) (Slave) CCP1 R Comparator (1) TMR2 Q S TRIS Comparator STANDARD PWM OPERATION The standard PWM function described in this section is available and identical for all CCP modules. TMR2 = PR2 TMR2 = CCPRxH:CCPxCON<5:4> The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. Figure 22-3 shows a typical waveform of the PWM signal. CCP PWM OUTPUT SIGNAL PR2 Note 1: 2: Clear Timer, toggle CCP1 pin and latch duty cycle The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPR1H is a read-only register. PR2 registers T2CON registers CCPRxL registers CCPxCON registers Figure 22-4 shows a simplified block diagram of PWM operation. Note: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 2013-2015 Microchip Technology Inc. DS40001722C-page 189 PIC16(L)F1703/7 22.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. Use the desired output pin RxyPPS control to select CCPx as the source and disable the CCPx pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIRx register. See Note below. • Configure the T2CKPS bits of the T2CON register with the Timer prescale value. • Enable the Timer by setting the TMR2ON bit of the T2CON register. Enable PWM output pin: • Wait until the Timer overflows and the TMR2IF bit of the PIR1 register is set. See Note below. • Enable the CCPx pin output driver by clearing the associated TRIS bit. Note: 22.3.3 • TMR2 is cleared • The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: 22.3.5 The Timer postscaler (see Section 21.1 “Timer2 Operation”) is not used in the determination of the PWM frequency. PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB<1:0> bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPRxH register is read-only. Equation 22-2 is used to calculate the PWM pulse width. Equation 22-3 is used to calculate the PWM duty cycle ratio. In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. EQUATION 22-2: TIMER2 TIMER RESOURCE EQUATION 22-3: The PWM standard mode makes use of the 8-bit Timer2 timer resources to specify the PWM period. 22.3.4 When TMR2 is equal to PR2, the following three events occur on the next increment cycle: PULSE WIDTH Pulse Width = CCPRxL:CCPxCON<5:4> T OSC (TMR2 Prescale Value) DUTY CYCLE RATIO CCPRxL:CCPxCON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------4 PR2 + 1 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 22-1. EQUATION 22-1: PWM PERIOD PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) Note 1: TOSC = 1/FOSC DS40001722C-page 190 The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 22-4). 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 22.3.6 PWM RESOLUTION EQUATION 22-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 22-4. TABLE 22-1: log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 1.22 kHz Timer Prescale PR2 Value Maximum Resolution (bits) TABLE 22-2: PWM RESOLUTION 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Timer Prescale PR2 Value Maximum Resolution (bits) 2013-2015 Microchip Technology Inc. DS40001722C-page 191 PIC16(L)F1703/7 22.3.7 OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 22.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional details. 22.3.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. TABLE 22-3: Name CCP1CON SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Bit 7 Bit 6 — — Bit 5 PIE1 Bit 3 DC1B<1:0> CCPR1L INTCON Bit 4 Bit 2 Bit 1 Bit 0 CCP1M<3:0> Register on Page 193 CCPR1L<7:0> 190* GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 77 TMR1GIE ADIE — — SSP1IE CCP1IE TMR2IE TMR1IE 78 PIE2 — — — — BCL1IE — — CCP2IE 79 PIR1 TMR1GIF ADIF — — SSP1IF CCP1IF TMR2IF TMR1IF 81 PIR2 — — — — BCL1IF — — CCP2IF PR2 PR2 RxyPPS — T2CON — TMR2 — — RxyPPS<4:0> T2OUTPS<3:0> 82 180* TMR2ON 132 T2CKPS<1:0> TMR2 182 180 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. Note 1: Unimplemented, read as ‘1’. DS40001722C-page 192 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 22.4 Register Definitions: CCP Control REGISTER 22-1: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 DCxB<1:0> R/W-0/0 R/W-0/0 R/W-0/0 CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Mode Select bits 11xx = PWM mode 1011 = Compare mode: Auto-conversion Trigger (sets CCPxIF bit), starts ADC conversion if TRIGSEL = CCPx (see Register 16-3) 1010 = Compare mode: generate software interrupt only 1001 = Compare mode: clear output on compare match (set CCPxIF) 1000 = Compare mode: set output on compare match (set CCPxIF) 0111 = 0110 = 0101 = 0100 = Capture mode: every 16th rising edge Capture mode: every 4th rising edge Capture mode: every rising edge Capture mode: every falling edge 0011 = 0010 = 0001 = 0000 = Reserved Compare mode: toggle output on match Reserved Capture/Compare/PWM off (resets CCPx module) 2013-2015 Microchip Technology Inc. DS40001722C-page 193 PIC16(L)F1703/7 23.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 23.1 MSSP Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, ADC converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) The SPI interface supports the following modes and features: • • • • • Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices Figure 23-1 is a block diagram of the SPI interface module. FIGURE 23-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SDI SSPSR Reg SDO bit 0 SS SS Control Enable Shift Clock 2 (CKP, CKE) Clock Select Edge Select SSPM<3:0> 4 SCK Edge Select TRIS bit DS40001722C-page 194 ( T2_match 2 ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD) 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 The I2C interface supports the following modes and features: • • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 23-2 is a block diagram of the I2C interface module in Master mode. Figure 23-3 is a diagram of the I2C interface module in Slave mode. MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal data bus Read [SSPM<3:0>] Write SSP1BUF Shift Clock SDA in Receive Enable (RCEN) SCL SCL in Bus Collision 2013-2015 Microchip Technology Inc. LSb Start bit, Stop bit, Acknowledge Generate (SSPCON2) Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Clock Cntl SSPSR MSb (Hold off clock source) SDA Baud Rate Generator (SSPxADD) Clock arbitrate/BCOL detect FIGURE 23-2: Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV Reset SEN, PEN (SSPCON2) Set SSP1IF, BCL1IF DS40001722C-page 195 PIC16(L)F1703/7 FIGURE 23-3: MSSP BLOCK DIAGRAM (I2C SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect DS40001722C-page 196 Set, Reset S, P bits (SSPxSTAT Reg) 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: • • • • Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) Figure 23-1 shows the block diagram of the MSSP module when operating in SPI mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 23-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDO pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its shift register. After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: • Master sends useful data and slave sends dummy data. • Master sends useful data and slave sends useful data. • Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. Figure 23-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. 2013-2015 Microchip Technology Inc. DS40001722C-page 197 PIC16(L)F1703/7 FIGURE 23-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 23.2.1 SPI MODE REGISTERS The MSSP module has five registers for SPI mode operation. These are: • • • • • • MSSP STATUS register (SSPxSTAT) MSSP Control register 1 (SSPxCON1) MSSP Control register 3 (SSPxCON3) MSSP Data Buffer register (SSPxBUF) MSSP Address register (SSPxADD) MSSP Shift register (SSPSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control STATUS registers in SPI mode operation. SSPxCON1 register is readable and writable. lower six bits of the SSPxSTAT are read-only. upper two bits of the SSPxSTAT are read/write. and The The The In one SPI master mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 23.7 “Baud Rate Generator”. SSPSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPxBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR. DS40001722C-page 198 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.2.2 SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: • • • • Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) To enable the serial port, SSP Enable bit, SSPEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: • SDI must have corresponding TRIS bit set • SDO must have corresponding TRIS bit cleared • SCK (Master mode) must have corresponding TRIS bit cleared • SCK (Slave mode) must have corresponding TRIS bit set • SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPxBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF of the SSPxSTAT register, and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSPxCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various Status conditions. 2013-2015 Microchip Technology Inc. DS40001722C-page 199 PIC16(L)F1703/7 FIGURE 23-5: SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx = 1010 SPI Slave SSPM<3:0> = 010x SDO SDI Serial Input Buffer (BUF) SDI Shift Register (SSPSR) MSb Serial Input Buffer (SSPxBUF) LSb SCK General I/O Processor 1 DS40001722C-page 200 SDO Serial Clock Slave Select (optional) Shift Register (SSPSR) MSb LSb SCK SS Processor 2 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 23-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as shown in Figure 23-6, Figure 23-8, Figure 23-9 and Figure 23-10, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: FIGURE 23-6: • • • • • FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 FOSC/(4 * (SSPxADD + 1)) Figure 23-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. Note: In Master mode, the clock signal output to the SCK pin is also the clock signal input to the peripheral. The pin selected for output with the RxyPPS register must also be selected as the peripheral input with the SSPCLKPPS register. SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 bit 0 Input Sample (SMP = 1) SSPIF SSPSR to SSPxBUF 2013-2015 Microchip Technology Inc. DS40001722C-page 201 PIC16(L)F1703/7 23.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 23.2.4.1 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. Figure 23-7 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. 23.2.5 SLAVE SELECT SYNCHRONIZATION The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPxCON1<3:0> = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPxCON1<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Slave mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. DS40001722C-page 202 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 23-7: SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI SPI Slave #1 SDO General I/O SS SCK SDI SPI Slave #2 SDO SS SCK SDI SPI Slave #3 SDO SS FIGURE 23-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPSR and bit count are reset SSPxBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPxBUF 2013-2015 Microchip Technology Inc. DS40001722C-page 203 PIC16(L)F1703/7 FIGURE 23-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active FIGURE 23-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSPIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active DS40001722C-page 204 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP interrupts should be disabled. TABLE 23-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 114 ANSELC ANSC7(2) ANSC6(2) ANSC5(3) ANSC4(3) ANSC3 ANSC2 ANSC1 ANSC0 125 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 77 PIE1 TMR1GIE ADIE — — SSP1IE CCP1IE TMR2IE TMR1IE 78 PIR1 — SSP1IF CCP1IF TMR2IF TMR1IF INTCON TMR1GIF ADIF — RxyPPS — — — RxyPPS<4:0> 132 SSPCLKPPS — — — SSPCLKPPS<4:0> 130, 131 SSPDATPPS — — — SSPDATPPS<4:0> 130, 131 SSPSSPPS — — — SSPSSPPS<4:0> 130, 131 SSP1BUF BUF<7:0> 198* SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON3 ACKTIM PCIE SCIE BOEN SSP1STAT SMP CKE D/A P S R/W — — TRISA5 TRISA4 —(1) TRISA2 TRISB7 TRISB6 TRISB5 TRISB4 — — TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISA TRISB(2) TRISC Legend: * Note 1: 2: 3: 81 SSPM<3:0> SDAHT SBCDE 244 AHEN DHEN 246 UA BF 242 TRISA1 TRISA0 113 — — 119 TRISC1 TRISC0 124 — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Page provides register information. Unimplemented, read as ‘1’. PIC16(L)F1707 only. PIC16(L)F1703 only. 2013-2015 Microchip Technology Inc. DS40001722C-page 205 PIC16(L)F1703/7 23.3 I2C MODE OVERVIEW The Inter-Integrated Circuit (I2C) bus is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 23-11 shows the block diagram of the MSSP module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Figure 23-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: • Master Transmit mode (master is transmitting data to a slave) • Master Receive mode (master is receiving data from a slave) • Slave Transmit mode (slave is transmitting data to a master) • Slave Receive mode (slave is receiving data from the master) To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. DS40001722C-page 206 I2C MASTER/ SLAVE CONNECTION FIGURE 23-11: SCL VDD Master Slave SDA SDA The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols; • Single message where a master writes data to a slave. • Single message where a master reads data from a slave. • Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. 23.3.1 CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 23.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. 2013-2015 Microchip Technology Inc. DS40001722C-page 207 PIC16(L)F1703/7 23.4 I2C MODE OPERATION All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 23.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the eighth falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 23.4.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C specification. 23.4.3 SDA AND SCL PINS Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note 1: Data is tied to output zero when an I2C mode is enabled. 2: Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These functions are bidirectional. The SDA input is selected with the SSPDATPPS registers. The SCL input is selected with the SSPCLKPPS registers. Outputs are selected with the RxyPPS registers. It is the user’s responsibility to make the selections so that both the input and the output for each function is on the same pin. 23.4.4 TABLE 23-2: TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Slave device that has received a Addressed Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPxADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state. SDA HOLD TIME The hold time of the SDA pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. DS40001722C-page 208 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.4.5 23.4.7 START CONDITION The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 23-12 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. Figure 23-13 shows the wave form for a Restart condition. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 23.4.6 RESTART CONDITION In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. STOP CONDITION A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained until a Stop condition, a high address with R/W clear, or high address match fails. 23.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 23-12: I2C START AND STOP CONDITIONS SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 23-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition 2013-2015 Microchip Technology Inc. DS40001722C-page 209 PIC16(L)F1703/7 23.4.9 ACKNOWLEDGE SEQUENCE The ninth SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSPCON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPxCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPxSTAT register or the SSPOV bit of the SSPxCON1 register are set when a byte is received. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit of the SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. 23.5 I2C SLAVE MODE OPERATION The MSSP Slave mode operates in one of four modes selected by the SSPM bits of SSPxCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operate the same as the other modes with SSPIF additionally getting set upon detection of a Start, Restart, or Stop condition. 23.5.1 SLAVE MODE ADDRESSES The SSPxADD register (Register 23-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSP Mask register (Register 23-5) affects the address matching process. See Section 23.5.9 “SSP Mask Register” for more information. 23.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 23.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb’s of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPIF and UA are set, and SCL is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS40001722C-page 210 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.5.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see Register 23-4. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPIF, must be cleared by software. When the SEN bit of the SSPCON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except sometimes in 10-bit mode. See Section 23.5.6.2 “10-bit Addressing Mode” for more detail. 23.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit Addressing mode. Figure 23-14 and Figure 23-15 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSPIF bit. Software clears the SSPIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSPIF bit. Software clears SSPIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the master. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes idle. 2013-2015 Microchip Technology Inc. 23.5.2.2 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 23-16 displays a module using both address and data holding. Figure 23-17 includes the operation with the SEN bit of the SSPCON2 register set. 1. S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPIF is set and CKP cleared after the eighth falling edge of SCL. 3. Slave clears the SSPIF. 4. Slave can look at the ACKTIM bit of the SSPxCON3 register to determine if the SSPIF was after or before the ACK. 5. Slave reads the address value from SSPxBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPIF. Note: SSPIF is still set after the ninth falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSPIF not set 11. SSPIF set and CKP cleared after eighth falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPxBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. DS40001722C-page 211 DS40001722C-page 212 SSPOV BF SSPIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 3 D5 Receiving Data From Slave to Master 8 D0 9 P SSPIF set on 9th falling edge of SCL ACK = 1 FIGURE 23-14: SCL SDA Receiving Address Bus Master sends Stop condition PIC16(L)F1703/7 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. CKP SSPOV BF SSPIF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSPxBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 2 D6 CKP is written to ‘1’ in software, releasing SCL 1 D7 Receive Data 8 D0 9 ACK SCL is not held low because ACK= 1 SSPIF set on 9th falling edge of SCL P FIGURE 23-15: SDA Receive Address Bus Master sends Stop condition PIC16(L)F1703/7 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS40001722C-page 213 DS40001722C-page 214 P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPIF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL SSPIF is set on 9th falling edge of SCL, after ACK 1 8 ACK D7 D6 D5 D4 D3 D2 D1 D0 Received Data 1 2 4 5 6 ACKTIM set by hardware on 8th falling edge of SCL CKP set by software, SCL is released 8 Slave software sets ACKDT to not ACK 7 Cleared by software 3 D7 D6 D5 D4 D3 D2 D1 D0 Data is read from SSPxBUF 9 ACK 9 P No interrupt after not ACK from Slave ACK=1 Master sends Stop condition FIGURE 23-16: SCL SDA Master Releases SDA to slave for ACK sequence PIC16(L)F1703/7 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPxBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCL 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCL When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared Received data is available on SSPxBUF Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK Receive Data 1 3 4 5 6 7 8 Set by software, release SCL Slave sends not ACK SSPxBUF can be read any time before next byte is loaded 2 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK CKP is not cleared if not ACK No interrupt after if not ACK from Slave P Master sends Stop condition FIGURE 23-17: SCL SDA R/W = 0 Master releases SDA to slave for ACK sequence PIC16(L)F1703/7 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) DS40001722C-page 215 PIC16(L)F1703/7 23.5.3 SLAVE TRANSMISSION 23.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 23-18 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 23.5.6 “Clock Stretching” for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSPxBUF register which also loads the SSPSR register. Then the SCL pin should be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSPCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. 23.5.3.1 Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCLIF bit of the PIR register is set. Once a bus collision is detected, the slave goes idle and waits to be addressed again. User software can use the BCLIF bit to handle a slave bus collision. DS40001722C-page 216 Master sends a Start condition on SDA and SCL. 2. S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSPIF bit. 4. Slave hardware generates an ACK and sets SSPIF. 5. SSPIF bit is cleared by user. 6. Software reads the received address from SSPxBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPxBUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSPIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. P S D/A R/W ACKSTAT CKP BF SSPIF S Receiving Address 1 2 5 6 7 8 Indicates an address has been received R/W is copied from the matching address byte 9 R/W = 1 Automatic ACK Received address is read from SSPxBUF 4 When R/W is set SCL is always held low after 9th SCL falling edge 3 A7 A6 A5 A4 A3 A2 A1 Transmitting Data Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPxBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters not ACK is copied to ACKSTAT BF is automatically cleared after 8th falling edge of SCL 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P FIGURE 23-18: SCL SDA Master sends Stop condition PIC16(L)F1703/7 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) DS40001722C-page 217 PIC16(L)F1703/7 23.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 23-19 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled. 1. 2. Bus starts Idle. Master sends Start condition; the S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSPIF interrupt is generated. 4. Slave software clears SSPIF. 5. Slave software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSPCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPIF after the ACK if the R/W bit is set. 11. Slave software clears SSPIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets the CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the ninth SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS40001722C-page 218 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address. 1 A7 A6 A5 A4 A3 A2 A1 3 4 5 6 Cleared by software 2 Set by software, releases SCL Data to transmit is loaded into SSPxBUF 1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK ACKTIM is cleared on 9th rising edge of SCL Automatic Transmitting Data 1 3 4 5 6 7 after not ACK CKP not cleared Master’s ACK response is copied to SSPxSTAT BF is automatically cleared after 8th falling edge of SCL 2 8 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P Master sends Stop condition FIGURE 23-19: SCL SDA Master releases SDA to slave for ACK sequence PIC16(L)F1703/7 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) DS40001722C-page 219 PIC16(L)F1703/7 23.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 23-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. Slave sends ACK and SSPIF is set. Software clears the SSPIF bit. Software reads received address from SSPxBUF clearing the BF flag. Slave loads low address into SSPxADD, releasing SCL. Master sends matching low address byte to the slave; UA bit is set. 23.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 23-21 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 23-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPIF is set. Note: If the low address does not match, SSPIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSPIF is set. 14. If SEN bit of SSPCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS40001722C-page 220 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. CKP UA BF SSPIF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCL is held low 9 ACK If address matches SSPxADD it is loaded into SSPxBUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSPxADD and releases SCL 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPxBUF SCL is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte Receive address is read from SSPxBUF Cleared by software 2 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data P FIGURE 23-20: SCL SDA Master sends Stop condition PIC16(L)F1703/7 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS40001722C-page 221 DS40001722C-page 222 ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPxADD is not allowed until 9th falling edge of SCL SSPxBUF can be read anytime before the next received byte Cleared by software 1 A7 Receive Second Address Byte 8 A0 9 ACK UA 2 D6 3 D5 4 D4 6 D2 Set CKP with software releases SCL 7 D1 Update of SSPxADD, clears UA and releases SCL 5 D3 Receive Data Cleared by software 1 D7 8 9 2 Received data is read from SSPxBUF 1 D6 D5 Receive Data D0 ACK D7 FIGURE 23-21: SSPIF 1 SCL S 1 SDA Receive First Address Byte PIC16(L)F1703/7 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. D/A R/W ACKSTAT CKP UA BF SSPIF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPxADD must be updated SSPxBUF loaded with received address 2 8 9 1 SCL S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSPxADD is updated, UA is cleared and SCL is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the matching address byte When R/W = 1; CKP is cleared on 9th falling edge of SCL High address is loaded back into SSPxADD Received address is read from SSPxBUF Sr 1 1 1 1 0 A9 A8 Receive First Address Byte 9 ACK 2 3 4 5 6 7 8 Masters not ACK is copied Set by software releases SCL Data to transmit is loaded into SSPxBUF 1 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data Byte 9 P Master sends Stop condition ACK = 1 Master sends not ACK FIGURE 23-22: SDA Master sends Restart event PIC16(L)F1703/7 I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) DS40001722C-page 223 PIC16(L)F1703/7 23.5.6 CLOCK STRETCHING 23.5.6.2 Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 23.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit of SSPCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the ninth falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the ninth falling edge of SCL. It is now always cleared for read requests. FIGURE 23-23: 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD. Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 23.5.6.3 Byte NACKing When AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the eighth falling edge of SCL for a received matching address byte. When DHEN bit of SSPxCON3 is set; CKP is cleared after the eighth falling edge of SCL for received data. Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 23.5.7 CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 23-23). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX ‚ – 1 DX SCL CKP Master device asserts clock Master device releases clock WR SSPxCON1 DS40001722C-page 224 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the eighth falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. Figure 23-24 shows a general call reception sequence. FIGURE 23-24: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPIF BF (SSPxSTAT<0>) Cleared by software GCEN (SSPCON2<7>) SSPxBUF is read ’1’ 23.5.9 SSP MASK REGISTER An SSP Mask (SSPMSK) register (Register 23-5) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the reception of the first (high) byte of the address. 2013-2015 Microchip Technology Inc. DS40001722C-page 225 PIC16(L)F1703/7 23.6 I2C Master Mode 23.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP interrupt, if enabled): • • • • • Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 23.7 “Baud Rate Generator” for more detail. 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. DS40001722C-page 226 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 23-25). FIGURE 23-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX ‚ – 1 DX SCL deasserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 23.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle. Note: Because queuing of events is not allowed, writing to the lower five bits of SSPCON2 is disabled until the Start condition is complete. 2013-2015 Microchip Technology Inc. DS40001722C-page 227 PIC16(L)F1703/7 23.6.4 I2C MASTER MODE START hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. CONDITION TIMING To initiate a Start condition (Figure 23-26), the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPCON2 register will be automatically cleared by FIGURE 23-26: Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPxSTAT<3>) At completion of Start bit, hardware clears SEN bit and sets SSPIF bit SDA = 1, SCL = 1 TBRG TBRG Write to SSPxBUF occurs here SDA 2nd bit 1st bit TBRG SCL S DS40001722C-page 228 TBRG 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.6.5 I2C MASTER MODE REPEATED SSPCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPxSTAT register will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. START CONDITION TIMING A Repeated Start condition (Figure 23-27) occurs when the RSEN bit of the SSPCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the FIGURE 23-27: Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. REPEATED START CONDITION WAVEFORM S bit set by hardware Write to SSPCON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears RSEN bit and sets SSPIF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPxBUF occurs here TBRG SCL Sr TBRG Repeated Start 2013-2015 Microchip Technology Inc. DS40001722C-page 229 PIC16(L)F1703/7 23.6.6 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCL low and SDA unchanged (Figure 23-28). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCL low and allowing SDA to float. 23.6.6.1 BF Status Flag 23.6.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 23.6.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Typical transmit sequence: The user generates a Start condition by setting the SEN bit of the SSPCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted out. 23.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. DS40001722C-page 230 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. S R/W PEN SEN BF (SSPxSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPxBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written by software Cleared by software service routine from SSP interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address From slave, clear ACKSTAT bit SSPCON2<6> P Cleared by software 9 ACK ACKSTAT in SSPCON2 = 1 FIGURE 23-28: SEN = 0 Write SSPCON2<0> SEN = 1 Start condition begins PIC16(L)F1703/7 I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) DS40001722C-page 231 PIC16(L)F1703/7 23.6.7 I2C MASTER MODE RECEPTION Master mode reception (Figure 23-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSP1CON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPCON2 register. 23.6.7.1 BF Status Flag 23.6.7.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPSR. It is cleared when the SSPxBUF register is read. 11. 23.6.7.2 12. SSPOV Status Flag In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 13. 14. 23.6.7.3 15. WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). DS40001722C-page 232 Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSPCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software. User writes SSPxBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. User sets the RCEN bit of the SSPCON2 register and the master clocks in a byte from the slave. After the eighth falling edge of SCL, SSPIF and BF are set. Master clears SSPIF and reads the received byte from SSPUF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSPCON2 register and initiates the ACK by setting the ACKEN bit. Master’s ACK is clocked out to the slave and SSPIF is set. User clears SSPIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. S RCEN ACKEN SSPOV BF (SSPxSTAT<0>) SDA = 0, SCL = 1 while CPU responds to SSPIF SSPIF SCL SDA 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDA = ACKDT = 0 Cleared in software Set SSPIF at end of receive 9 ACK is not sent ACK RCEN cleared automatically P Set SSPIF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPxSTAT<4>) and SSPIF PEN bit = 1 written here SSPOV is set because SSPxBUF is still full 8 D0 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 D7 D6 D5 D4 D3 D2 D1 Last bit is shifted into SSPSR and contents are unloaded into SSPxBUF Cleared by software Set SSPIF interrupt at end of receive 4 Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) A1 R/W RCEN = 1, start next receive ACK from Master SDA = ACKDT = 0 FIGURE 23-29: RCEN cleared automatically Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT Write to SSPCON2<0> (SEN = 1), begin Start condition Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 PIC16(L)F1703/7 I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS40001722C-page 233 PIC16(L)F1703/7 23.6.8 ACKNOWLEDGE SEQUENCE TIMING 23.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSPxSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 23-31). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPCON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 23-30). 23.6.8.1 23.6.9.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 23-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSPIF SSPIF set at the end of receive Cleared in software Cleared in software SSPIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 23-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPCON2, set PEN PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS40001722C-page 234 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.6.10 SLEEP OPERATION 23.6.13 the I2C slave While in Sleep mode, module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 23.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 23.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the I2C port to its Idle state (Figure 23-32). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 23-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF 2013-2015 Microchip Technology Inc. DS40001722C-page 235 PIC16(L)F1703/7 23.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 23-33). SCL is sampled low before SDA is asserted low (Figure 23-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 23-35). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: • the Start condition is aborted, • the BCLIF flag is set and • the MSSP module is reset to its Idle state (Figure 23-33). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 23-33: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSP module reset into Idle state. SEN BCLIF SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared by software S SSPIF SSPIF and BCLIF are cleared by software DS40001722C-page 236 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 23-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared by software S ’0’ ’0’ SSPIF ’0’ ’0’ FIGURE 23-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPIF TBRG SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN BCLIF Set SEN, enable Start sequence if SDA = 1, SCL = 1 ’0’ S SSPIF SDA = 0, SCL = 1, set SSPIF 2013-2015 Microchip Technology Inc. Interrupts cleared by software DS40001722C-page 237 PIC16(L)F1703/7 23.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 23-36). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level (Case 1). SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’ (Case 2). If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition, see Figure 23-37. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 23-36: If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared by software S ’0’ SSPIF ’0’ FIGURE 23-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLIF SCL goes low before SDA, set BCLIF. Release SDA and SCL. Interrupt cleared by software RSEN S ’0’ SSPIF DS40001722C-page 238 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 23-38). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 23-39). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out (Case 1). After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2). FIGURE 23-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA SDA sampled low after TBRG, set BCLIF SDA asserted low SCL PEN BCLIF P ’0’ SSPIF ’0’ FIGURE 23-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL SCL goes low before SDA goes high, set BCLIF PEN BCLIF P ’0’ SSPIF ’0’ 2013-2015 Microchip Technology Inc. DS40001722C-page 239 PIC16(L)F1703/7 TABLE 23-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION Bit 7 Bit 6 ANSELA — ANSELB(1) — ANSELC INTCON Reset Values on Page: Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — ANSA4 — ANSA2 ANSA1 ANSA0 114 — ANSB5 ANSB4 — — — — 120 ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 125 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 77 PIE1 TMR1GIE ADIE — — SSP1IE CCP1IE TMR2IE TMR1IE 78 PIE2 — — — — BCL1IE — — CCP2IE 79 PIR1 TMR1GIF ADIF — — SSP1IF CCP1IF TMR2IF TMR1IF 81 PIR2 — — — — BCL1IF — — CCP2IF RxyPPS — — — 82 RxyPPS<4:0> 132 SSPCLKPPS — — — SSPCLKPPS<4:0> 130, 131 SSPDATPPS — — — SSPDATPPS<4:0> 130, 131 SSPSSPPS — — — SSPSSPPS<4:0> 130, 131 SSP1ADD ADD<7:0> SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register SSP1CON1 248 198* WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 245 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 246 SMP CKE D/A P S R/W UA BF 242 — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 113 TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 119 TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 124 SSP1MSK SSP1STAT TRISA (1) Legend: * Note 1: 2: 3: SSPM<3:0> 244 MSK<7:0> 248 2 — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I C mode. Page provides register information. PIC16(L)F1707 only. PIC16(L)F1703 only. Unimplemented, read as ‘1’. DS40001722C-page 240 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 23.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 23-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. Table 23-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. EQUATION 23-1: FOSC FCLOCK = ------------------------------------------------ SSPxADD + 1 4 An internal signal “Reload” in Figure 23-40 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the FIGURE 23-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPM<3:0> Reload SSPxADD<7:0> Reload Control SCL SSPCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 23-4: Note: MSSP CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Refer to the I/O port electrical specifications in Table 26-4 to ensure the system is designed to support IOL requirements. 2013-2015 Microchip Technology Inc. DS40001722C-page 241 PIC16(L)F1703/7 23.8 Register Definitions: MSSP Control REGISTER 23-1: SSP1STAT: SSP STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 C™ mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated DS40001722C-page 242 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 23-1: bit 0 SSP1STAT: SSP STATUS REGISTER (CONTINUED) BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty 2013-2015 Microchip Technology Inc. DS40001722C-page 243 PIC16(L)F1703/7 REGISTER 23-2: SSP1CON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV(1) SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software). 0 = No overflow 2 In I C mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2C Master mode: Unused in this mode bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1101 = Reserved 1100 = Reserved 1011 = I2C firmware controlled Master mode (slave idle) 1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))(5) 1001 = Reserved 1000 = I2C Master mode, clock = FOSC / (4 * (SSPxADD+1))(4) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = T2_match/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: 2: 3: 4: 5: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as input or output. Use SSPSSPPS, SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins. When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins. SSPxADD values of 0, 1 or 2 are not supported for I2C mode. SSPxADD value of ‘0’ is not supported. Use SSPM = 0000 instead. DS40001722C-page 244 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 SSP1CON2: SSP CONTROL REGISTER 2(1) REGISTER 23-3: R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKMSSP Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). 2013-2015 Microchip Technology Inc. DS40001722C-page 245 PIC16(L)F1703/7 REGISTER 23-4: SSP1CON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on ninth rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the SSPxCON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPxBUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the SSPxCON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCL is held low. 0 = Data holding is disabled DS40001722C-page 246 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 REGISTER 23-4: Note 1: 2: 3: SSP1CON3: SSP CONTROL REGISTER 3 (CONTINUED) For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. 2013-2015 Microchip Technology Inc. DS40001722C-page 247 PIC16(L)F1703/7 REGISTER 23-5: R/W-1/1 SSP1MSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 23-6: R/W-0/0 SSPxADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode – Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode – Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. DS40001722C-page 248 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 24.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16(L)F170X Memory Programming Specification” (DS41683). 24.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 24.2 Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC® Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. 24.3 Common Programming Interfaces Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 24-1. FIGURE 24-1: VDD ICD RJ-11 STYLE CONNECTOR INTERFACE ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VPP/MCLR VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 24-2. For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 24-3 for more information. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 5.5 “MCLR” for more information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. 2013-2015 Microchip Technology Inc. DS40001722C-page 249 PIC16(L)F1703/7 FIGURE 24-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * FIGURE 24-3: The 6-pin header (0.100" spacing) accepts 0.025" square pins. TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). DS40001722C-page 250 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 25.0 INSTRUCTION SET SUMMARY 25.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. The literal and control category contains the most varied instruction word format. TABLE 25-1: Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. Table 25-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: • Subroutine takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) • Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) • One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. OPCODE FIELD DESCRIPTIONS Field f Description Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. n FSR or INDF number. (0-1) mm Pre-post increment-decrement mode selection TABLE 25-2: ABBREVIATION DESCRIPTIONS Field Program Counter TO Time-Out bit C DC Z PD 2013-2015 Microchip Technology Inc. Description PC Carry bit Digit Carry bit Zero bit Power-Down bit DS40001722C-page 251 PIC16(L)F1703/7 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k = 11-bit immediate value MOVLP instruction only 13 OPCODE 7 6 0 k (literal) k = 7-bit immediate value MOVLB instruction only 13 OPCODE 5 4 0 k (literal) k = 5-bit immediate value BRA instruction only 13 OPCODE 9 8 0 k (literal) k = 9-bit immediate value FSR Offset instructions 13 OPCODE 7 6 n 5 0 k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE 3 2 1 0 n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE DS40001722C-page 252 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 25-3: PIC16(L)F1703/7 INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ f, d f, d Decrement f, Skip if 0 Increment f, Skip if 0 BCF BSF f, b f, b Bit Clear f Bit Set f 1(2) 1(2) 00 00 1, 2 1, 2 1011 dfff ffff 1111 dfff ffff BIT-ORIENTED FILE REGISTER OPERATIONS 1 1 01 01 00bb bfff ffff 01bb bfff ffff 2 2 1, 2 1, 2 BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 (2) 1 (2) 01 01 10bb bfff ffff 11bb bfff ffff 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 LITERAL OPERATIONS ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW k k k k k k k k Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 2: Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W 2013-2015 Microchip Technology Inc. kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z C, DC, Z Z DS40001722C-page 253 PIC16(L)F1703/7 TABLE 25-3: PIC16(L)F1703/7 INSTRUCTION SET (CONTINUED) 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine 2 2 2 2 2 2 2 2 CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W ADDFSR MOVIW n, k n mm MOVWI k[n] n mm Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 TO, PD 0000 0010 0001 0011 TO, PD 0fff INHERENT OPERATIONS 1 1 1 1 1 1 C-COMPILER OPTIMIZED k[n] Note 1: 2: 3: 1 1 11 00 0001 0nkk kkkk 0000 0001 0nmm Z 2, 3 1 1 11 00 1111 0nkk kkkk Z 0000 0001 1nmm 2 2, 3 1 11 1111 1nkk kkkk 2 If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. See Table in the MOVIW and MOVWI instruction descriptions. DS40001722C-page 254 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 25.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the 8-bit literal ‘k’. The result is placed in the W register. ANDWF AND W with f FSRn is limited to the range 0000h-FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: Status Affected: Syntax: [ label ] ANDWF Operands: 0 f 127 d 0,1 (W) + k (W) Operation: (W) .AND. (f) (destination) C, DC, Z Status Affected: Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the result is placed in the W register. Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ASRF Arithmetic Right Shift ADDWF Add W and f Syntax: [ label ] ADDWF Operands: 0 f 127 d 0,1 Operation: (W) + (f) (destination) Status Affected: C, DC, Z Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWFC k f,d ADD W and CARRY bit to f Syntax: [ label ] ADDWFC Operands: 0 f 127 d [0,1] Operation: (W) + (f) + (C) dest Syntax: [ label ] ASRF Operands: 0 f 127 d [0,1] f {,d} Operation: (f<7>) dest<7> (f<7:1>) dest<6:0>, (f<0>) C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. register f C f {,d} Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. 2013-2015 Microchip Technology Inc. f,d DS40001722C-page 255 PIC16(L)F1703/7 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label [ label ] BRA $+k Syntax: [ label ] BTFSS f,b Operands: 0 f 127 0b<7 Operands: -256 label - PC + 1 255 -256 k 255 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k PC Status Affected: None Status Affected: None Description: Description: Add the signed 9-bit literal ‘k’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a 2-cycle instruction. This branch has a limited range. If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W) PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a 2-cycle instruction. BSF Bit Set f Syntax: [ label ] BSF Operands: 0 f 127 0b7 Operation: 1 (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. DS40001722C-page 256 f,b 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The 11-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a 2-cycle instruction. Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF Operands: None Operands: Operation: (PC) +1 TOS, (W) PC<7:0>, (PCLATH<6:0>) PC<14:8> 0 f 127 d [0,1] Operation: (f) (destination) Status Affected: Z Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DECF Decrement f Syntax: [ label ] DECF f,d Status Affected: None Description: Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a 2-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF f f,d Operands: 0 f 127 Operands: Operation: 00h (f) 1Z 0 f 127 d [0,1] Operation: (f) - 1 (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared and the Z bit is set. Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h (W) 1Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. 2013-2015 Microchip Technology Inc. DS40001722C-page 257 PIC16(L)F1703/7 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a NOP is executed instead, making it a 2-cycle instruction. Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, a NOP is executed instead, making it a 2-cycle instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] Syntax: [ label ] GOTO k INCFSZ f,d IORLW k Operands: 0 k 2047 Operands: 0 k 255 Operation: k PC<10:0> PCLATH<6:3> PC<14:11> Operation: (W) .OR. k (W) Status Affected: Z Status Affected: None Description: Description: GOTO is an unconditional branch. The 11-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. The contents of the W register are OR’ed with the 8-bit literal ‘k’. The result is placed in the W register. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination) Operation: (W) .OR. (f) (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. DS40001722C-page 258 INCF f,d IORWF f,d 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 LSLF Logical Left Shift MOVF f {,d} Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. C register f 0 Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Example: Logical Right Shift Syntax: [ label ] LSRF Operands: 0 f 127 d [0,1] Operation: 0 dest<7> (f<7:1>) dest<6:0>, (f<0>) C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘0’ is shifted into the MSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. f {,d} register f 2013-2015 Microchip Technology Inc. MOVF FSR, 0 After Instruction W = value in FSR register Z = 1 LSRF 0 MOVF f,d C DS40001722C-page 259 PIC16(L)F1703/7 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Status Affected: MOVLP Syntax: [ label ] MOVLP k Operands: 0 k 127 Operation: k PCLATH Status Affected: None Description: The 7-bit literal ‘k’ is loaded into the PCLATH register. MOVLW Move literal to W Syntax: [ label ] 0 k 255 Operation: k (W) Status Affected: None Description: The 8-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as ‘0’s. Words: 1 1 Mode Syntax mm Cycles: Preincrement ++FSRn 00 Example: --FSRn 01 Postincrement FSRn++ 10 Postdecrement FSRn-- 11 Description: This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. MOVLB Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0 k 31 Operation: k BSR Status Affected: None Description: The 5-bit literal ‘k’ is loaded into the Bank Select Register (BSR). DS40001722C-page 260 MOVLW k Operands: Z Predecrement Move literal to PCLATH MOVLW 0x5A After Instruction W = MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 f 127 Operation: (W) (f) 0x5A f Status Affected: None Description: Move data from W register to register ‘f’. Words: 1 Cycles: 1 Example: MOVWF OPTION_REG Before Instruction OPTION_REG = 0xFF W = 0x4F After Instruction OPTION_REG = 0x4F W = 0x4F 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged None No Operation Syntax: [ label ] Operands: None Operation: No operation Status Affected: None Description: No operation. Words: 1 Cycles: 1 Example: OPTION Load OPTION_REG Register with W Syntax: [ label ] OPTION Operands: None Operation: (W) OPTION_REG Status Affected: None Description: Move data from W register to OPTION_REG register. 1 Syntax Preincrement ++FSRn 00 Predecrement --FSRn 01 Postincrement FSRn++ 10 Words: Postdecrement FSRn-- 11 Cycles: 1 Example: OPTION Before Instruction OPTION_REG = 0xFF W = 0x4F After Instruction OPTION_REG = 0x4F W = 0x4F This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h-FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. The increment/decrement operation on FSRn WILL NOT affect any Status bits. 2013-2015 Microchip Technology Inc. NOP NOP Mode Description: mm NOP RESET Software Reset Syntax: [ label ] RESET Operands: None Operation: Execute a device Reset. Resets the RI flag of the PCON register. Status Affected: None Description: This instruction provides a way to execute a hardware Reset by software. DS40001722C-page 261 PIC16(L)F1703/7 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] None RETFIE k RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = GIE = TOS 1 RETLW Return with literal in W Syntax: [ label ] Operands: 0 k 255 Operation: k (W); TOS PC Status Affected: None Description: The W register is loaded with the 8-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: TABLE RETLW k RLF Rotate Left f through Carry Syntax: [ label ] Operands: 0 f 127 d [ 0, 1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. RLF C CALL TABLE;W contains table ;offset value • ;W now has table value • • ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table Before Instruction W = After Instruction W = DS40001722C-page 262 Words: 1 Cycles: 1 Example: RLF f,d Register f REG1,0 Before Instruction REG1 C After Instruction REG1 W C = = 1110 0110 0 = = = 1110 0110 1100 1100 1 0x07 value of k8 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. The W register is subtracted (2’s complement method) from the 8-bit literal ‘k’. The result is placed in the W register. RRF f,d C Register f SUBLW k C=0 Wk C=1 Wk DC = 0 W<3:0> k<3:0> DC = 1 W<3:0> k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) - (W) destination) Status Affected: C, DC, Z Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f. SLEEP Operands: None Operation: 00h WDT, 0 WDT prescaler, 1 TO, 0 PD Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. 2013-2015 Microchip Technology Inc. SUBWF f,d C=0 Wf C=1 Wf DC = 0 W<3:0> f<3:0> DC = 1 W<3:0> f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB Operands: 0 f 127 d [0,1] Operation: (f) – (W) – (B) dest f {,d} Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001722C-page 263 PIC16(L)F1703/7 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the 8-bit literal ‘k’. The result is placed in the W register. XORWF TRIS Load TRIS Register with W XORLW k Exclusive OR W with f Syntax: [ label ] Operands: 0 f 127 d [0,1] XORWF f,d (W) .XOR. (f) destination) Syntax: [ label ] TRIS f Operands: 5f7 Operation: Operation: (W) TRIS register ‘f’ Status Affected: Z Status Affected: None Description: Description: Move data from W register to TRIS register. When ‘f’ = 5, TRISA is loaded. When ‘f’ = 6, TRISB is loaded. When ‘f’ = 7, TRISC is loaded. Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001722C-page 264 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 26.0 ELECTRICAL SPECIFICATIONS 26.1 Absolute Maximum Ratings(†) Ambient temperature under bias...................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on pins with respect to VSS on VDD pin PIC16F1703/7 ........................................................................................................... -0.3V to +6.5V PIC16LF1703/7 ......................................................................................................... -0.3V to +4.0V on MCLR pin ........................................................................................................................... -0.3V to +9.0V on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V) Maximum current on VSS pin(1) -40°C TA +85°C .............................................................................................................. 250 mA +85°C TA +125°C ............................................................................................................. 85 mA on VDD pin(1) -40°C TA +85°C .............................................................................................................. 250 mA +85°C TA +125°C ............................................................................................................. 85 mA sunk by any I/O pin ............................................................................................................................... 50 mA sourced by any I/O pin ........................................................................................................................... 50 mA sourced by any Op Amp output pin ...................................................................................................... 100 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA Total power dissipation(2) ............................................................................................................................. 800 mW Note 1: 2: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Table 26-6 to calculate device specifications. Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOl x IOL). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 2013-2015 Microchip Technology Inc. DS40001722C-page 265 PIC16(L)F1703/7 26.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC16LF1703/7 VDDMIN (Fosc 16 MHz).......................................................................................................... +1.8V VDDMIN (Fosc 16 MHz).......................................................................................................... +2.5V VDDMAX .................................................................................................................................... +3.6V PIC16F1703/7 VDDMIN (Fosc 16 MHz).......................................................................................................... +2.3V VDDMIN (Fosc 16 MHz).......................................................................................................... +2.5V VDDMAX .................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................... +85°C Extended Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................. +125°C Note 1: See Parameter D001, DS Characteristics: Supply Voltage. DS40001722C-page 266 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16F1703/7 ONLY FIGURE 26-1: VDD (V) 5.5 2.5 2.3 0 10 4 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 26-7 for each Oscillator mode’s supported frequencies. VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16LF1703/7 ONLY VDD (V) FIGURE 26-2: 3.6 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 26-7 for each Oscillator mode’s supported frequencies. 2013-2015 Microchip Technology Inc. DS40001722C-page 267 PIC16(L)F1703/7 26.3 DC Characteristics TABLE 26-1: SUPPLY VOLTAGE PIC16LF1703/7 Standard Operating Conditions (unless otherwise stated) PIC16F1703/7 Param. No. D001 Sym. VDD Characteristic Typ† Max. Units VDDMIN 1.8 2.5 — — VDDMAX 3.6 3.6 V V FOSC 16 MHz FOSC 32 MHz (Note 2) 2.3 2.5 — — 5.5 5.5 V V FOSC 16 MHz: FOSC 32 MHz (Note 2) 1.5 — — V Device in Sleep mode 1.7 — — V Device in Sleep mode — 1.6 — V — 1.6 — V — 0.8 — V — 1.5 — V 1x (1.024 typical) -4 — +4 % VDD 2.5V, -40°C to +85°C 2x (2.048 typical) -4 — +4 % VDD 2.5V, -40°C to +85°C 4x (4.096 typical) -5 — +5 % VDD 4.75V, -40°C to +85°C 0.05 — — PIC16F1703/7 VDR RAM Data Retention Voltage(1) D002* D002A* VPOR Conditions Supply Voltage D001 D002* Min. Power-on Reset Release Voltage(3) D002A* D002B* VPORR* Power-on Reset Rearm Voltage(3) D002B* D003 D004* VFVR SVDD Fixed Voltage Reference Voltage VDD Rise Rate(2) V/ms Ensures that the Power-on Reset signal is released properly. * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2: PLL required for 32 MHz operation. 3: See Figure 26-3: POR and POR Rearm with Slow Rising VDD. DS40001722C-page 268 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 26-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2013-2015 Microchip Technology Inc. DS40001722C-page 269 PIC16(L)F1703/7 TABLE 26-2: SUPPLY CURRENT (IDD)(1,2) PIC16LF1703/7 (unless otherwise stated) Standard Operating Conditions PIC16F1703/7 Param No. Device Characteristics LDO Regulator D009 D014 D014 D015 D015 D017 D017 D019 D019 D020 D020 Conditions Min. Typ† Max. Units VDD Note — 75 — A — High-Power mode, normal operation — 15 — A — Sleep, VREGCON<1> = 0 — 0.3 — A — Sleep, VREGCON<1> = 1 — 120 180 A 1.8 — 210 300 A 3.0 FOSC = 4 MHz, External Clock (ECM), Medium-Power mode — 185 280 A 2.3 — 245 350 A 3.0 — 305 420 A 5.0 — 1.6 2.3 mA 3.0 — 2 2.6 mA 3.6 — 2 2.3 mA 3.0 — 2 2.5 mA 5.0 — 115 170 A 1.8 — 135 200 A 3.0 — 150 200 A 2.3 — 170 220 A 3.0 — 215 280 A 5.0 — 0.7 0.9 mA 1.8 — 1.2 1.4 mA 3.0 — 0.9 1.1 mA 2.3 — 1.1 1.5 mA 3.0 — 1.2 1.6 mA 5.0 — 2 2.5 mA 3.0 — 2.4 3.0 mA 3.6 — 2 2.6 mA 3.0 — 2.2 2.8 mA 5.0 FOSC = 4 MHz, External Clock (ECM), Medium-Power mode FOSC = 32 MHz, External Clock (ECH), High-Power mode (Note 3) FOSC = 32 MHz, External Clock (ECH), High-Power mode (Note 3) FOSC = 500 kHz, MFINTOSC mode FOSC = 500 kHz, MFINTOSC mode FOSC = 16 MHz, HFINTOSC mode FOSC = 16 MHz, HFINTOSC mode FOSC = 32 MHz, HFINTOSC mode (Note 3) FOSC = 32 MHz, HFINTOSC mode (Note 3) † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The test conditions for all IDD measurements in active operation mode are: all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: 8 MHz clock with 4x PLL enabled. DS40001722C-page 270 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 26-3: POWER-DOWN CURRENTS (IPD)(1,2) PIC16LF1703/7 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1703/7 Low-Power Sleep Mode, VREGPM = 1 Param No. Device Characteristics D022 Base IPD D022 Base IPD D022A Base IPD D024 D024 D025 D025 Conditions Min. Typ† Max. +85°C Max. +125°C Units — 0.05 1.0 8.0 A 1.8 — 0.08 2.0 9.0 A 3.0 — 0.3 3 11 A 2.3 — 0.4 4 12 A 3.0 — 0.5 6 15 A 5.0 — 9.8 16 18 A 2.3 — 10.3 18 20 A 3.0 Note VDD — 11.5 21 26 A 5.0 — 0.5 6 14 A 1.8 — 0.8 7 17 A 3.0 — 0.8 6 15 A 2.3 — 0.9 7 20 A 3.0 — 1.0 8 22 A 5.0 — 15 28 30 A 1.8 — 18 30 33 A 3.0 — 18 33 35 A 2.3 — 19 35 37 A 3.0 WDT, BOR and FVR disabled, all Peripherals Inactive WDT, BOR and FVR disabled, all Peripherals Inactive, Low-Power Sleep mode VREGPM = 1 WDT, BOR and FVR disabled, all Peripherals inactive, Normal-Power Sleep mode WDT Current WDT Current FVR Current FVR Current — 20 37 39 A 5.0 D026 — 7.5 25 28 A 3.0 BOR Current D026 — 10 25 28 A 3.0 BOR Current — 12 28 31 A 5.0 D027 — 0.5 4 10 A 3.0 LPBOR Current D027 — 0.8 6 14 A 3.0 LPBOR Current — 1 8 17 A 5.0 — 0.05 2 9 A 1.8 — 0.08 3 10 A 3.0 — 0.3 4 12 A 2.3 — 0.4 5 13 A 3.0 D029 D029 D030 D030 * † Note 1: 2: 3: — 0.5 7 16 A 5.0 — 250 — — A 1.8 — 250 — — A 3.0 — 280 — — A 2.3 — 280 — — A 3.0 — 280 — — A 5.0 ADC Current (Note 3), no conversion in progress ADC Current (Note 3), no conversion in progress ADC Current (Note 3), conversion in progress ADC Current (Note 3), conversion in progress These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. ADC clock source is FRC. 2013-2015 Microchip Technology Inc. DS40001722C-page 271 PIC16(L)F1703/7 TABLE 26-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED) PIC16LF1703/7 Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1703/7 Low-Power Sleep Mode, VREGPM = 1 Param No. Device Characteristics Min. Typ† Conditions Max. +85°C Max. +125°C Units VDD Note D031 — 250 650 — A 3.0 Op Amp (High-power) D031 — 250 650 — A 3.0 Op Amp (High-power) — 350 850 — A 5.0 * † Note 1: 2: 3: These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. ADC clock source is FRC. DS40001722C-page 272 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 26-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. VIL Characteristic Min. Typ† Max. Units — — with Schmitt Trigger buffer Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 1.8V VDD 4.5V — — 0.2 VDD V 2.0V VDD 5.5V with I2C levels — — 0.3 VDD V with SMBus levels — — 0.8 V — — 0.2 VDD V Input Low Voltage I/O PORT: D034 with TTL buffer D034A D035 D036 MCLR VIH 2.7V VDD 5.5V Input High Voltage I/O ports: D040 2.0 — — V 4.5V VDD 5.5V 0.25 VDD + 0.8 — — V 1.8V VDD 4.5V with Schmitt Trigger buffer 0.8 VDD — — V 2.0V VDD 5.5V with I2C levels 0.7 VDD — — V with TTL buffer D040A D041 with SMBus levels D042 MCLR IIL D060 MCLR(2) IPUR Weak Pull-up Current VOL Output Low Voltage D070* D080 — — V — — V — ±5 ± 125 nA VSS VPIN VDD, Pin at high-impedance, 85°C — ±5 ± 1000 nA VSS VPIN VDD, Pin at high-impedance, 125°C — ± 50 ± 200 nA VSS VPIN VDD, Pin at high-impedance, 85°C 25 100 200 A VDD = 3.0V, VPIN = VSS — — 0.6 V IOL = -8mA, VDD = 5V IOL = -6mA, VDD = 3.3V IOL = -1.8mA, VDD = 1.8V VDD - 0.7 — — V IOH = 3.5mA, VDD = 5V IOH = 3mA, VDD = 3.3V IOH = 1mA, VDD = 1.8V — 50 pF Input Leakage Current(1) I/O Ports D061 I/O ports VOH D090 Output High Voltage I/O ports CIO D101A* 2.7V VDD 5.5V 2.1 0.8 VDD Capacitive Loading Specs on Output Pins All I/O pins — * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Negative current is defined as current sourced by the pin. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2013-2015 Microchip Technology Inc. DS40001722C-page 273 PIC16(L)F1703/7 TABLE 26-5: MEMORY PROGRAMMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VBE VDD for Bulk Erase 2.7 — VDDMAX V D113 VPEW VDD for Write or Row Erase VDDMIN — VDDMAX V D114 IPPGM Current on MCLR/VPP during Erase/Write — 1.0 — mA D115 IDDPGM Current on VDD during Erase/Write — 5.0 — mA D121 EP Cell Endurance 10K — — E/W D122 VPRW VDD for Read/Write VDDMIN — VDDMAX V D123 TIW Self-timed Write Cycle Time — 2 2.5 ms D124 TRETD Characteristic Retention — 40 — Year Provided no other specifications are violated D125 EHEFC High-Endurance Flash Cell 100K — — E/W -0C TA +60°C, Lower byte last 128 addresses (Note 3, Note 4) Program Flash Memory -40C TA +85C (Note 1) † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Self-write and Block Erase. 2: Refer to Section Section 3.2 “High-Endurance Flash” for a more detailed discussion on data EEPROM endurance. 3: Required only if single-supply programming is disabled. 4: The MPLAB ICD 2 does not support variable VPP output. Circuitry to limit the ICD 2 VPP voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2. DS40001722C-page 274 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 26-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic Typ. Units JA Thermal Resistance Junction to Ambient 70.0 C/W 14-pin PDIP package 95.3 C/W 14-pin SOIC package 100.0 C/W 14-pin TSSOP package 51.5 C/W 16-pin QFN 4x4mm package 62.2 C/W 20-pin PDIP package 87.3 C/W 20-pin SSOP 77.7 C/W 20-pin SOIC package JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Conditions 43.0 C/W 20-pin QFN 4x4mm package 32.75 C/W 14-pin PDIP package 31.0 C/W 14-pin SOIC package 24.4 C/W 14-pin TSSOP package 5.4 C/W 16-pin QFN 4x4mm package 27.5 C/W 20-pin PDIP package 31.1 C/W 20-pin SSOP 23.1 C/W 20-pin SOIC package 5.3 C/W 20-pin QFN 4x4mm package 150 C — W PD = PINTERNAL + PI/O — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature, TJ = Junction Temperature 2013-2015 Microchip Technology Inc. DS40001722C-page 275 PIC16(L)F1703/7 26.4 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 26-4: T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins DS40001722C-page 276 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 26-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS12 OS02 OS11 OS03 CLKOUT (CLKOUT Mode) Note 1: See Table 26-10. TABLE 26-7: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. OS01 Sym. FOSC Characteristic External CLKIN Frequency(1) Min. Typ† Max. Units Conditions DC — 0.5 MHz External Clock (ECL) DC — 4 MHz External Clock (ECM) DC — 20 MHz External Clock (ECH) OS02 TOSC External CLKIN Period(1) 50 — ns External Clock (EC) OS03 TCY Instruction Cycle Time(1) 125 TCY DC ns TCY = 4/FOSC * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to CLKIN pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2013-2015 Microchip Technology Inc. DS40001722C-page 277 PIC16(L)F1703/7 TABLE 26-8: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Freq. Tolerance Min. Typ† Max. Units OS08 HFOSC Internal Calibrated HFINTOSC Frequency(1) ±2% — 16.0 — MHz OS08A MFOSC Internal Calibrated MFINTOSC Frequency(1) ±2% — 500 — kHz OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time MFINTOSC Wake-up from Sleep Start-up Time — — 3.2 8 s — — 24 35 s — — 0.5 — ms OS10A* TLFOSC ST * † LFINTOSC Wake-up from Sleep Start-up Time Conditions -40°C TA +125°C -40°C TA +125°C These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2: See Figure 27-43: LFINTOSC Frequency, PIC16LF1703/7 Only., and Figure 27-44: LFINTOSC Frequency, PIC16F1703/7 Only.. FIGURE 26-6: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 Temperature (°C) ± 3% 60 ± 2% 25 0 -20 -40 1.8 ± 5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) DS40001722C-page 278 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 26-9: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param No. Sym. F10 Characteristic Min. Typ† Max. Units FOSC Oscillator Frequency Range 4 — 8 MHz F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz F12 TRC PLL Start-up Time (Lock Time) F13* CLK CLKOUT Stability (Jitter) — — 2 ms -0.25% — +0.25% % Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. 2013-2015 Microchip Technology Inc. DS40001722C-page 279 PIC16(L)F1703/7 FIGURE 26-7: CLKOUT AND I/O TIMING Cycle Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 26-10: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ† Max. Units Conditions OS11* TosH2ckL FOSC to CLKOUT (1) — — 70 ns 3.3V VDD 5.0V OS12* TosH2ckH FOSC to CLKOUT (1) — — 72 ns 3.3V VDD 5.0V OS13* TckL2ioV CLKOUT to Port out valid OS14* TioV2ckH Port input valid before CLKOUT(1) OS15* TosH2ioV OS16* (1) — — 20 ns TOSC + 200 ns — — ns Fosc (Q1 cycle) to Port out valid — 50 70* ns 3.3V VDD 5.0V TosH2ioI Fosc (Q2 cycle) to Port input invalid (I/O in hold time) 50 — — ns 3.3V VDD 5.0V OS17* TioV2osH Port input valid to Fosc(Q2 cycle) (I/O in setup time) 20 — — ns OS18* TioR Port output rise time — — 40 15 72 32 ns VDD = 1.8V 3.3V VDD 5.0V OS19* TioF Port output fall time — — 28 15 55 30 ns VDD = 1.8V 3.3V VDD 5.0V OS20* Tinp INT pin input high or low time 25 — — ns OS21* Tioc Interrupt-on-change new input level time 25 — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in EXTRC mode where CLKOUT output is 4 x TOSC. 2: Slew rate limited. DS40001722C-page 280 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 26-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) 31 34 34 I/O pins Note 1: Asserted low. TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ† Max. Units Conditions 2 — — s 10 16 27 ms Power-up Timer Period, PWRTE = 0 40 65 140 ms I/O high-impedance from MCLR Low or Watchdog Timer Reset — — 2.0 s 2.55 2.70 2.85 V BORV = 0 2.30 1.80 2.45 1.90 2.60 2.10 V V BORV = 1 (PIC16F1703/7) BORV = 1 (PIC16LF1703/7) 1.8 2.1 2.5 V LPBOR = 1 0 25 75 mV -40°C TA +85°C 1 3 35 s VDD VBOR 30 TMCL 31 TWDTLP Low-Power Watchdog Timer Time-out Period MCLR Pulse Width (low) 33* TPWRT 34* TIOZ 35 VBOR Brown-out Reset Voltage(1) 35A VLPBOR Low-Power Brown-out 36* VHYST 37* TBORDC Brown-out Reset DC Response Time Brown-out Reset Hysteresis VDD = 3.3V-5V 1:16 Prescaler used * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. 2013-2015 Microchip Technology Inc. DS40001722C-page 281 PIC16(L)F1703/7 FIGURE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 FIGURE 26-10: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) 33(1) Note 1: 64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘0’; 2 ms delay if PWRTE = 0. DS40001722C-page 282 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 26-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width No Prescaler With Prescaler TT0L 41* T0CKI Low Pulse Width No Prescaler With Prescaler 42* TT0P T0CKI Period 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler TT1L 46* Typ† Max. Units 0.5 TCY + 20 — — ns 10 — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or (TCY + 40)*N — — ns 0.5 TCY + 20 — — ns 15 — — ns Asynchronous 30 — — ns T1CKI Low Synchronous, No Prescaler Time Synchronous, with Prescaler 0.5 TCY + 20 — — ns 15 — — ns Asynchronous 30 — — ns Greater of: 30 or (TCY + 40)*N — — ns 60 — — ns 2 TOSC — 7 TOSC — 47* TT1P 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment T1CKI Input Synchronous Period Asynchronous * † Min. Conditions N = prescale value N = prescale value Timers in Sync mode These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2013-2015 Microchip Technology Inc. DS40001722C-page 283 PIC16(L)F1703/7 FIGURE 26-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Refer to Figure 26-4 for load conditions. Note: TABLE 26-13: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Operating Temperature -40°C TA +125°C Param Sym. No. Characteristic CC01* TccL CCPx Input Low Time No Prescaler CC02* TccH CCPx Input High Time No Prescaler Min. Typ† Max. Units 0.5TCY + 20 — — ns ns With Prescaler 20 — — 0.5TCY + 20 — — ns 20 — — ns (3TCY + 40)*N — — ns With Prescaler CC03* TccP * † CCPx Input Period Conditions N = prescale value These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. TABLE 26-14: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C, Single-ended, 2 s TAD, VREF+ = 3V, VREF- = VSS Param Sym. No. Characteristic Min. Typ† Max. Units Conditions AD01 NR Resolution — — 10 AD02 EIL Integral Error — — ±1.7 bit Differential Error — — ±1 — — ±2.5 LSb VREF = 3.0V LSb VREF = 3.0V LSb VREF = 3.0V AD03 EDL AD04 EOFF Offset Error AD05 EGN Gain Error — — ±2.0 AD06 VREF Reference Voltage 1.8 — VDD V AD07 VAIN Full-Scale Range VSS — VREF V AD08 ZAIN Recommended Impedance of Analog Voltage Source — — 10 k * † Note 1: 2: 3: LSb No missing codes, VREF = 3.0V VREF = (VREF+ minus VREF-) Can go higher if external 0.01F capacitor is present on input pin. These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. ADC VREF is from external VREF+ pin, VDD pin or FVR, whichever is selected as reference input. See Section 27.0 “DC and AC Characteristics Graphs and Charts” for operating characterization. DS40001722C-page 284 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 26-15: ADC CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param Sym. No. Characteristic Min. Typ† Max. Units Conditions ADC Clock Period (TADC) 1.0 — 9.0 s FOSC-based ADC Internal FRC Oscillator Period (TFRC) 1.0 2 6.0 s ADCS<1:0> = 11 (ADC FRC mode) Conversion Time (not including Acquisition Time)(1) — 11 — TAD Set GO/DONE bit to conversion complete AD132* TACQ Acquisition Time — 5.0 — s AD133* THCD Holding Capacitor Disconnect Time — 1/2 TAD — ADCS<2:0> x11 (FOSC based) — 1/2 TAD + 1TCY — ADCS<2:0> = x11 (FRC based) AD130* TAD AD131 TCNV * † These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. 2013-2015 Microchip Technology Inc. DS40001722C-page 285 PIC16(L)F1703/7 FIGURE 26-12: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 FIGURE 26-13: ADC CONVERSION TIMING (ADC CLOCK FROM FRC) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 2 1 0 NEW_DATA 1 TCY ADIF GO Sample 3 DONE AD132 Sampling Stopped Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. DS40001722C-page 286 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 TABLE 26-16: OPERATIONAL AMPLIFIER (OPA) Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C, OPAxSP = 1 (High GBWP mode) Param No. Symbol OPA01* GBWP Parameters Min. Typ. Max. Units Gain Bandwidth Product — 3.5 — MHz OPA02* TON Turn-on Time — 10 — s OPA03* PM Phase Margin — 40 — degrees OPA04* SR Slew Rate — 3 — V/s OPA05 OFF Offset — ±3 ±9 mV OPA06 CMRR Common-Mode Rejection Ratio 52 70 — dB OPA07* AOL Open Loop Gain — 90 — dB OPA08 VICM Input Common-Mode Voltage 0 — VDD V OPA09* PSRR Power Supply Rejection Ratio — 80 — dB Min. Typ. Max. * Conditions VDD > 2.5V These parameters are characterized but not tested. TABLE 26-17: ZERO CROSS PIN SPECIFICATIONS Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. Sym. Characteristics Units ZC01 ZCPINV Voltage on Zero Cross Pin — 0.75 — V ZC02 ZCSRC Source current — — -600 A ZC03 ZCSNK Sink current 600 — — A ZC04 ZCISW ZC05 ZCOUT * Response Time Rising Edge — 1 — s Response Time Falling Edge — 1 — s Response Time Rising Edge — 1 — s Response Time Falling Edge — 1 — s Comments These parameters are characterized but not tested. 2013-2015 Microchip Technology Inc. DS40001722C-page 287 PIC16(L)F1703/7 FIGURE 26-14: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 26-4 for load conditions. FIGURE 26-15: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 SP78 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 26-4 for load conditions. DS40001722C-page 288 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 26-16: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 26-4 for load conditions. FIGURE 26-17: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 26-4 for load conditions. 2013-2015 Microchip Technology Inc. DS40001722C-page 289 PIC16(L)F1703/7 TABLE 26-18: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Symbol Characteristic Min. Typ† Max. Units 2.25 TCY — — ns SP70* TSSL2SCH, TSSL2SCL SS to SCK or SCK input SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SCK input low time (Slave mode) TCY + 20 — — ns SP72* TSCL Conditions SP73* TDIV2SCH, TDIV2SCL Setup time of SDI data input to SCK edge 100 — — ns SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge 100 — — ns SP75* TDOR SDO data output rise time — 10 25 ns 3.0V VDD 5.5V — 25 50 ns 1.8V VDD 5.5V SP76* TDOF SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time (Master mode) — 10 25 ns 3.0V VDD 5.5V — 25 50 ns 1.8V VDD 5.5V SP79* TSCF SCK output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, TSCL2DOV SDO data output valid after SCK edge — — 50 ns 3.0V VDD 5.5V 1.8V VDD 5.5V SP81* TDOV2SCH, SDO data output setup to SCK edge TDOV2SCL SP82* TSSL2DOV SDO data output valid after SS edge SP83* TSCH2SSH, TSCL2SSH SS after SCK edge — — 145 ns 1 Tcy — — ns — — 50 ns 1.5 TCY + 40 — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001722C-page 290 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 FIGURE 26-18: I2C BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 26-4 for load conditions. TABLE 26-19: I2C BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Symbol Characteristic SP90* TSU:STA Start condition SP91* THD:STA SP92* TSU:STO SP93* THD:STO Stop condition Typ 4700 — Max. Units — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time Hold time * 100 kHz mode Min. 400 kHz mode 600 — — 100 kHz mode 4000 — — 400 kHz mode 600 — — Conditions ns Only relevant for Repeated Start condition ns After this period, the first clock pulse is generated ns ns These parameters are characterized but not tested. FIGURE 26-19: I2C BUS DATA TIMING SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note: Refer to Figure 26-4 for load conditions. 2013-2015 Microchip Technology Inc. DS40001722C-page 291 PIC16(L)F1703/7 TABLE 26-20: I2C BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.5TCY — SSP module SP101* TLOW Clock low time SSP module SP102* TR SP103* TF SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1CB 300 ns SDA and SCL fall time 100 kHz mode — 250 ns 400 kHz mode 20 + 0.1CB 250 ns 0 — ns SP106* THD:DAT Data input hold time 100 kHz mode 400 kHz mode 0 0.9 s SP107* TSU:DAT Data input setup time 100 kHz mode 250 — ns 400 kHz mode 100 — ns SP109* TAA Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns SP110* Bus free time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF SP111* * Note 1: 2: TBUF CB Conditions Bus capacitive loading CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS40001722C-page 292 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 27.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the L and LF devices. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.” represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range. 2013-2015 Microchip Technology Inc. DS40001722C-page 293 PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. , , , 12 60 Max. Max: 85°C + 3ı Typical: 25°C 10 Max. Max: 85°C + 3ı Typical: 25°C 50 Typical 40 IDD (μA) IDD (μA) 8 Typical 6 30 4 20 2 10 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 27-1: IDD, EC Oscillator, Low-Power Mode, FOSC = 32 kHz, PIC16LF1703/7 Only. FIGURE 27-4: IDD, EC Oscillator, Low-Power Mode, FOSC = 500 kHz, PIC16F1703/7 Only. 350 25 Max. 300 Max: 85°C + 3ı Typical: 25°C 20 Typical: 25°C 4 MHz Typical 15 IDD (μA) IDD (μA) 250 200 150 10 100 1 MHz 5 50 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 2.6 FIGURE 27-2: IDD, EC Oscillator, Low-Power Mode, FOSC = 32 kHz, PIC16F1703/7 Only. , , 3.0 3.2 3.4 3.6 3.8 FIGURE 27-5: IDD Typical, EC Oscillator, Medium-Power Mode, PIC16LF1703/7 Only. , , , 350 50 Max. 45 4 MHz Max: 85°C + 3ı 300 Max: 85°C + 3ı Typical: 25°C 40 250 30 IDD (μA) 35 IDD (μA) 2.8 VDD (V) VDD (V) Typical 25 200 150 20 15 1 MHz 100 10 50 5 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 VDD (V) FIGURE 27-3: IDD, EC Oscillator, Low-Power Mode, FOSC = 500 kHz, PIC16LF1703/7 Only. DS40001722C-page 294 3.6 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 27-6: IDD Maximum, EC Oscillator, Medium-Power Mode, PIC16LF1703/7 Only. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 3.0 400 350 Max: 85°C + 3ı Typical: 25°C 2.5 4 MHz 32 MHz 300 IDD (mA) IDD (μA) 2.0 250 200 1 MHz 1.5 16 MHz 150 1.0 100 8 MHz 0.5 50 0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 FIGURE 27-7: IDD Typical, EC Oscillator, Medium-Power Mode, PIC16F1703/7 Only. , 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 27-10: IDD Maximum, EC Oscillator, High-Power Mode, PIC16LF1703/7 Only. , 2.5 450 32 MHz 400 Typical: 25°C Max: 85°C + 3ı 2.0 350 4 MHz 1.5 IDD (mA) IDD (μA) 300 250 200 1 MHz 16 MHz 1.0 8 MHz 150 100 0.5 50 0.0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 6.0 2.5 3.0 3.5 FIGURE 27-8: IDD Maximum, EC Oscillator, Medium-Power Mode, PIC16F1703/7 Only. 4.5 5.0 5.5 6.0 FIGURE 27-11: IDD Typical, EC Oscillator, High-Power Mode, PIC16F1703/7 Only. 2.5 2.5 Max: 85°C + 3ı 32 MHz Typical: 25°C 2.0 2.0 1.5 1.5 IDD (mA) IDD (mA) 4.0 VDD (V) VDD (V) 16 MHz 32 MHz 16 MHz 1.0 1.0 8 MHz 8 MHz 0.5 0.5 0.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 27-9: IDD Typical, EC Oscillator, High-Power Mode, PIC16LF1703/7 Only. 2013-2015 Microchip Technology Inc. 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 27-12: IDD Maximum, EC Oscillator, High-Power Mode, PIC16F1703/7 Only. DS40001722C-page 295 PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 7 260 Max. Max: 85°C + 3ı Typical: 25°C 240 Max: 85°C + 3ı Typical: 25°C 6 5 Max. 220 Typical IDD (μA) IDD (μA) Typical 200 4 180 3 160 2 140 1 120 100 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 27-16: IDD, MFINTOSC Mode, Fosc = 500 kHz, PIC16F1703/7 Only. FIGURE 27-13: IDD, LFINTOSC Mode, Fosc = 31 kHz, PIC16LF1703/7 Only. 25 1.6 16 MHz Max. 1.4 Typical: 25°C 20 1.2 15 IDD (mA) IDD (μA) Typical 10 1.0 8 MHz 0.8 4 MHz 0.6 2 MHz 0.4 5 1 MHz Max: 85°C + 3ı Typical: 25°C 0.2 0.0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 27-14: IDD, LFINTOSC Mode, Fosc = 31 kHz, PIC16F1703/7 Only. FIGURE 27-17: IDD Typical, HFINTOSC Mode, PIC16LF1703/7 Only. 180 1.8 1.6 170 Max: 85°C + 3ı Typical: 25°C 160 Max. 16 MHz Max: 85°C + 3ı 1.4 1.2 140 IDD (mA) IDD (μA) 150 Typical 8 MHz 1.0 0.8 4 MHz 130 2 MHz 0.6 120 0.4 110 1 MHz 0.2 0.0 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) FIGURE 27-15: IDD, MFINTOSC Mode, Fosc = 500 kHz, PIC16LF1703/7 Only. DS40001722C-page 296 3.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 27-18: IDD Maximum, HFINTOSC Mode, PIC16LF1703/7 Only. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. p 1.6 , ( ) 1.2 16 MHz 1.4 Ma Max. Typical: 25°C 1 1.2 0.8 8 MHz IPD (μA (μA) IDD (mA) 1.0 0.8 4 MHz 0.6 2 MHz 0.4 1 MHz Max: 85°C + 3ı Typical: 25°C 0.6 0.4 Typical 0.2 0.2 0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 6.0 2.5 3.0 3.5 4.0 5.0 5.5 6.0 FIGURE 27-22: IPD Base, Low-Power Sleep Mode (VREGPM = 1), PIC16F1703/7 Only. FIGURE 27-19: IDD Typical, HFINTOSC Mode, PIC16F1703/7 Only. 1.6 3 16 MHz 1.4 4.5 VDD (V) VDD (V) Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı 2.5 1.2 IPD (μA) IDD (mA) 0.8 Max. 2 8 MHz 1.0 4 MHz 1.5 2 MHz 0.6 1 1 MHz 0.4 Typical 0.5 0.2 0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 2.6 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 27-20: IDD Maximum, HFINTOSC Mode, PIC16F1703/7 Only. p 2.8 FIGURE 27-23: IPD, Watchdog Timer (WDT), PIC16LF1703/7 only. p , 450 ( ) 2.5 400 Max: 85°C + 3ı Typical: 25°C Max. 2 350 Max. IPD (μA) IDD (nA (nA) 300 250 Max: 85°C + 3ı Typical: 25°C 200 1.5 1 150 Typical 100 0.5 Typical 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 27-21: IPD Base, Low-Power Sleep Mode, PIC16LF1703/7 Only. 2013-2015 Microchip Technology Inc. 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 27-24: IPD, Watchdog Timer (WDT), PIC16F1703/7 only. DS40001722C-page 297 PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. p , ( p ) ( ) 13 35 Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı Typical: 25°C 12 30 Max. 11 Max. 10 IDD D (nA) IDD (nA) 25 20 Typical 9 Typical 8 7 15 6 10 5 4 5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.8 3.8 3.0 3.2 3.4 3.6 3.8 4.0 ( 4.4 4.6 4.8 5.0 5.2 5.4 5.6 FIGURE 27-28: IPD, Brown-Out Reset (BOR), BORV = 1, PIC16F1703/7 only. FIGURE 27-25: IPD, Fixed Voltage Reference (FVR), PIC16LF1703/7 only. p , 4.2 VDD (V) VDD (V) ) p , ( ) 1.8 35 Max. Max. 1.6 30 1.4 25 1.2 IDD (nA (nA) IDD (nA (nA) Typical 20 15 Max: 85°C + 3ı Typical: 25 C 25°C 1 0.8 0.6 10 Typical 0.4 Max: 85°C + 3ı Typical: 25°C 5 0.2 0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.9 6.0 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 VDD (V) VDD (V) FIGURE 27-26: IPD, Fixed Voltage Reference (FVR), PIC16F1703/7 only. FIGURE 27-29: IPD, Low-Power Brown-Out Reset (BOR), LPBOR = 0, PIC16LF1703/7 only. 1.8 11 Max: 85°C + 3ı Typical: 25°C 10 Max. Max: 85°C + 3ı T i l 25°C Typical: 16 1.6 Max. 1.4 9 IDD (μA (μA) IDD ((nA) 1.2 Typical 8 7 1.0 08 0.8 0.6 6 Typical 0.4 5 0.2 0.0 4 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VDD (V) FIGURE 27-27: IPD, Brown-Out Reset (BOR), BORV = 1, PIC16LF1703/7 only. DS40001722C-page 298 3.7 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 VDD (V) FIGURE 27-30: IPD, Low-Power Brown-Out Reset (BOR), LPBOR = 0, PIC16F1703/7 only. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. p p , 7 , ( ) 900 Max: 85°C + 3ı Typical: 25°C 6 Max: 85°C + 3ı Typical: 25°C 800 Max. Max. 700 5 IDD (μA) IDD (μA (μA) 600 4 3 Typical 500 Typical 400 300 2 200 1 100 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1.5 3.8 2.0 2.5 3.0 3.5 4.5 5.0 5.5 6.0 FIGURE 27-34: IPD, Op Amp, High GBWP Mode (OPAxSP = 1), PIC16F1703/7 Only. FIGURE 27-31: IPD, Timer1 Oscillator, Fosc = 32 kHz, PIC16LF1703/7 Only. p , 4.0 VDD (V) VDD (V) , p , 12 g 500 Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı Typical: 25°C 450 10 Max. 400 Max. 350 IDD (μA) IDD (μA) 8 6 Typical 300 250 200 4 150 100 2 Typical 50 0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 27-32: IPD, Timer1 Oscillator, Fosc = 32 kHz, PIC16F1703/7 Only. FIGURE 27-35: IPD, ADC Non-Converting, PIC16LF1703/7 only 700 1.4 Max: 85°C + 3ı Typical: 25°C 600 Max: 85°C + 3ı Typical: 25°C 1.2 Max. Max. 500 400 IDD (μA) IDD (μA) 1 Typical 300 0.8 0.6 200 0.4 100 0.2 Typical 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 27-33: IPD, Op Amp, High GBWP Mode (OPAxSP = 1), PIC16LF1703/7 Only. 2013-2015 Microchip Technology Inc. 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 27-36: IPD, ADC Non-Converting, PIC16F1703/7 only DS40001722C-page 299 PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. , 6 3.0 Graph represents 3ı Limits Graph represents 3ı Limits 5 2.5 2.0 VOL (V) VOH (V) 4 -40°C 3 -40°C Typical 1.5 125°C 125°C 2 1.0 Typical 1 0.5 0 0.0 -30 -25 -20 -15 -10 -5 0 0 5 10 15 IOH (mA) FIGURE 27-37: VOH vs. IOH Over Temperature, VDD = 5.0V, PIC16F1703/7 Only. e Vol vs. Iol OVER TEMPERATURE, Vdd 20 25 30 IOL (mA) FIGURE 27-40: VOL vs. IOL Over Temperature, VDD = 3.0V. 5.0V 2.0 5 Graph represents 3ı Limits Graph represents 3ı Limits 1.8 1.6 4 1.4 VOH (V) VOL (V) 3 -40°C 2 1.2 125°C 1.0 0.8 Typical Typical -40°C 0.6 125°C 0.4 1 0.2 0.0 -4.0 0 0 10 20 30 40 IOL (mA) 50 60 70 80 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 IOH (mA) FIGURE 27-38: VOL vs. IOL Over Temperature, VDD = 5.0V, PIC16F1703/7 Only. FIGURE 27-41: VOH vs. IOH Over Temperature, VDD = 1.8V, PIC16LF1703/7 Only. , 3.5 1.8 Graph represents 3ı Limits 1.6 Graph represents 3ı Limits 3.0 1.4 2.5 Vol (V) VOH (V) 1.2 2.0 1.5 1.0 125°C Typical 0.8 125°C -40°C 0.6 Typical 1.0 0.4 -40°C 0.5 0.2 0.0 0.0 -14 -12 -10 -8 -6 -4 IOH (mA) FIGURE 27-39: VOH vs. IOH Over Temperature, VDD = 3.0V. DS40001722C-page 300 -2 0 0 1 2 3 4 5 6 7 8 9 10 IOL (mA) FIGURE 27-42: VOL vs. IOL Over Temperature, VDD = 1.8V, PIC16F1703/7 Only. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. q y 24 40,000 38,000 22 Max. Max. 36,000 20 34,000 Time (mS) Frequency (Hz) Typical 32,000 30,000 Min. 18 Typical 16 28,000 26,000 14 24,000 Min. Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 22,000 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 12 10 20,000 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1.6 3.8 1.8 2 2.2 2.4 VDD (V) 2.8 3 3.2 3.4 3.6 3.8 FIGURE 27-46: WDT Time-Out Period, PIC16LF1703/7 Only. FIGURE 27-43: LFINTOSC Frequency, PIC16LF1703/7 Only. q 2.6 VDD (V) , y 40,000 ( ) 2.00 38,000 Max. Max. 36,000 1.95 Typical Typical 32,000 Voltage (V) Frequency (Hz) 34,000 30,000 Min. 28,000 1.90 Min. 26,000 1.85 24,000 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 22,000 20,000 1.80 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -60 -40 -20 0 20 VDD (V) 40 60 80 24 70 22 60 140 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı Max. Max. 50 Voltage (mV) 20 Time (mS) 120 FIGURE 27-47: Brown-Out Reset Voltage, Low Trip Point (BORV = 1), PIC16LF1703/7 only. FIGURE 27-44: LFINTOSC Frequency, PIC16F1703/7 Only. 18 100 Temperature (°C) Typical 16 Min. 40 30 Typical 20 14 Min. Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 12 10 0 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 27-45: WDT Time-Out Period, PIC16F1703/7 Only. 2013-2015 Microchip Technology Inc. 6.0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 27-48: Brown-Out Reset Hysteresis, Low Trip Point (BORV = 1), PIC16LF1703/7 only. DS40001722C-page 301 PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. , 2.60 ( ) 80 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 70 2.55 Max. Max. 60 Typical Voltage (mV) Voltage (V) 2.50 Min. 2.45 2.40 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 2.35 50 Typical 40 30 20 Min. 10 2.30 -60 -40 -20 0 20 40 60 80 100 120 0 140 -60 -40 -20 0 20 40 60 FIGURE 27-49: Brown-Out Reset Voltage, Low Trip Point (BORV = 1), PIC16F1703/7 only. 100 120 140 FIGURE 27-52: Brown-Out Reset Hysteresis, High Trip Point (BORV = 0). 70 2.6 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı Max. 60 Max. 2.5 2.4 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 50 Voltage (V) 2.3 Voltage (mV) 80 Temperature (°C) Temperature (°C) 40 Typical 30 2.2 Typical 2.1 2.0 20 1.9 Min. Min. 10 1.8 0 1.7 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 FIGURE 27-53: FIGURE 27-50: Brown-Out Reset Hysteresis, Low Trip Point (BORV = 1), PIC16F1703/7 only. 2.85 40 60 80 100 120 140 LPBOR Reset Voltage. 50 Max. 40 Max. 35 Voltage (mV) 2.75 Typical Min. 2.70 Max: Typical + 3ı Typical: statistical mean 45 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 2.80 Voltage (V) 20 Temperature (°C) Temperature (°C) 30 25 20 Typical 15 2.65 10 5 2.60 0 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 FIGURE 27-51: Brown-Out Reset Voltage, High Trip Point (BORV = 0). DS40001722C-page 302 0 20 40 60 80 100 120 140 Temperature (°C) Temperature (°C) FIGURE 27-54: LPBOR Reset Hysteresis. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 1.58 1.58 100 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 90 Max: Typical + 3ı Typical: 25°C Max. Min: Typical - 3ı 1.561.56 Max. 1.541.54 Voltage (V) Typical 70 Typical Voltage (V) Time (mS) 80 1.521.52 1.51.50 Min. Min. 60 1.481.48 50 Max: Typical + 3ı Typical: statistical mean Min:-20 Typical - 3ı0 1.46 1.46 -40 20 40 60 80 100 120 Temperature (°C) 1.44 40 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -50 6.0 -25 0 25 50 75 100 125 Temperature (°C) VDD (V) FIGURE 27-55: PWRT Period, PIC16F1703/7 Only. FIGURE 27-58: POR REARM Voltage, Normal-Power Mode (VREGPM1 = 0), PIC16F1703/7 Only. , 110 1.4 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 100 1.3 Max. 1.2 90 Voltage (V) Time (mS) Max. 80 Typical 70 1.1 Typical 1.0 0.9 Min. 60 Min. 0.8 50 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 0.7 40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0.6 3.8 -50 -25 0 25 50 75 100 125 Temperature (°C) VDD (V) FIGURE 27-59: POR REARM Voltage, Normal-Power Mode, PIC16LF1703/7 Only. FIGURE 27-56: PWRT Period, PIC16LF1703/7 Only. 12 1.70 1.68 Max. 10 Typical 8 Voltage (V) 1.64 Time (μs) 1.66 1.62 1.60 Min. Max. 6 Typical 1.58 4 1.56 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 1.54 1.52 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 2 0 1.50 -50 -25 0 25 50 75 100 125 1.5 2.0 2.5 Temperature (°C) FIGURE 27-57: POR Release Voltage. 2013-2015 Microchip Technology Inc. 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 27-60: VREGPM = 0. Wake From Sleep, DS40001722C-page 303 PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 1.0 50 45 40 0.5 Max. DNL(LSb) Time (μs) 35 30 Typical 25 0.0 20 15 Ͳ0.5 10 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 5 Ͳ1.0 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 6.0 128 256 384 FIGURE 27-61: VREGPM = 1. 512 640 768 896 1024 OutputCode VDD (V) Wake From Sleep, FIGURE 27-64: ADC 10-bit Mode, Single-ended DNL, VDD = 3.0V, TAD = 4 µS, 25°C. 1.0 40 Max: Typical + 3ı Typical: statistical mean @ 25°C 35 0.5 Max. INL(LSb) Time (μs) 30 Typical 25 0.0 20 Ͳ0.5 Note: The FVR Stabiliztion Period applies when coming out of Reset or exiting Sleep mode. 15 Ͳ1.0 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0 3.8 128 256 384 512 640 768 896 1024 OutputCode VDD (mV) FIGURE 27-65: ADC 10-bit Mode, Single-ended INL, VDD = 3.0V, TAD = 1 µS, 25°C. FIGURE 27-62: FVR Period, PIC16LF1703/7 Only. 2.0 1.0 1.0 1.5 1.0 INL(LSb) DNL(LSb) DNL(LSb) 0.5 0.0 0.5 0.5 0.0 Ͳ0.5 0.0 Ͳ1.0 Ͳ1.5 Ͳ0.5 Ͳ0.5 Ͳ2.0 0 512 1024 1536 2048 2560 3072 3584 4096 640 768 896 1024 OutputCode Ͳ1.0 0 128 256 384 512 640 768 896 OutputCode FIGURE 27-63: ADC 10-bit Mode, Single-ended DNL, VDD = 3.0V, TAD = 1 µS, 25°C. DS40001722C-page 304 1024 Ͳ1.0 0 128 256 384 512 OutputCode FIGURE 27-66: ADC 10-bit Mode, Single-ended INL, VDD = 3.0V, TAD = 4 µS, 25°C. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 1.5 1.5 1.0 MinͲ40°C MaxͲ40°C 1.0 Min25°C Max25°C DNL(LSb) Min125°C 0.0 Min125°C INL(LSb) 0.5 0.5 Max125°C 0.0 Min25°C Ͳ0.5 Min125°C MinͲ40°C MinͲ40°C Ͳ0.5 Ͳ1.0 Ͳ1.5 5.00EͲ07 1.00EͲ06 2.00EͲ06 4.00EͲ06 Min25°C Ͳ1.0 8.00EͲ06 1.8 2.3 TADs FIGURE 27-67: ADC 10-bit Mode, Single-ended DNL, VDD = 3.0V, VREF = 3.0V. FIGURE 27-70: ADC 10-bit Mode, Single-ended INL, VDD = 3.0V, TAD = 1 µS. 1.5 800 MaxͲ40°C INL(LSb) 0.5 700 Max 600 Max125°C Typical 0.0 Ͳ0.5 ADC VREF+ SET TO VDD ADC VREF- SET TO GND Max25°C Min25°C Min125°C MinͲ40°C ADC Output Codes 1.0 3 VREF 500 Min 400 300 200 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı Ͳ1.0 100 Ͳ1.5 0 5.00EͲ07 1.00EͲ06 2.00EͲ06 4.00EͲ06 8.00EͲ06 2.5 3.0 3.5 4.0 TADs 4.5 5.0 5.5 6.0 VDD (V) FIGURE 27-68: ADC 10-bit Mode, Single-ended INL, VDD = 3.0V, VREF = 3.0V. FIGURE 27-71: Temperature Indicator Initial Offset, High Range, Temp. = 20°C, PIC16F1703/7 only. 1.5 900 1.0 800 ADC VREF+ SET TO VDD ADC VREF- SET TO GND Max Typical MaxͲ40°C Max25°C Max125°C 0.0 Min125°C Ͳ0.5 Min25°C MinͲ40°C Ͳ1.0 700 ADC Output Codes DNL(LSb) 0.5 Min 600 500 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı 400 300 Ͳ1.5 1.8 2.3 3 VREF FIGURE 27-69: ADC 10-bit Mode, Single-ended DNL, VDD = 3.0V, TAD = 1 µS. 2013-2015 Microchip Technology Inc. 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 VDD (V) FIGURE 27-72: Temperature Indicator Initial Offset, Low Range, Temp. = 20°C, PIC16F1703/7 only. DS40001722C-page 305 PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 800 150 ADC VREF+ SET TO VDD ADC VREF- SET TO GND ADC VREF+ SET TO VDD ADC VREF- SET TO GND Max 700 Typical Typical Min 600 Min ADC Output Codes ADC Output Codes Max 100 500 400 300 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı 200 50 0 -50 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı 100 -100 1.6 2.0 2.4 2.8 3.2 3.6 4.0 -60 -40 -20 0 20 VDD (V) FIGURE 27-73: Temperature Indicator Initial Offset, Low Range, Temp. = 20°C, PIC16LF1703/7 only. 80 100 120 140 160 250 Max ADC VREF+ SET TO VDD ADC VREF- SET TO GND 125 Max Typical Min 150 ADC Output Codes 75 50 25 0 -25 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -50 ADC VREF+ SET TO VDD ADC VREF- SET TO GND 200 Typical 100 ADC Output Codes 60 FIGURE 27-76: Temperature Indicator Slope Normalized to 20°C, Low Range, VDD = 3.0, PIC16F1703/7 only. 150 Min 100 50 0 -50 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -100 -150 -75 -60 -40 -20 0 20 40 60 80 100 120 140 -60 160 -40 -20 0 20 40 60 80 100 120 140 160 Temperature (°C) Temperature (°C) FIGURE 27-74: Temperature Indicator Slope Normalized to 20°C, High Range, VDD = 5.0, PIC16F1703/7 only. FIGURE 27-77: Temperature Indicator Slope Normalized to 20°C, Low Range, VDD = 1.8, PIC16LF1703/7 only. 250 150 ADC VREF+ SET TO VDD ADC VREF- SET TO GND 200 ADC VREF+ SET TO VDD ADC VREF- SET TO GND Max Typical 150 Max Typical Min 100 Min 100 ADC Output Codes ADC Output Codes 40 Temperature (°C) 50 0 -50 50 0 -50 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -100 -150 -100 -60 -40 -20 0 20 40 60 80 100 120 140 160 Temperature (°C) FIGURE 27-75: Temperature Indicator Slope Normalized to 20°C, High Range, VDD = 3.0, PIC16F1703/7 only. DS40001722C-page 306 -60 -40 -20 0 20 40 60 80 100 120 140 160 Temperature (°C) FIGURE 27-78: Temperature Indicator Slope Normalized to 20°C, Low Range, VDD = 3.0, PIC16LF1703/7 only. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. g 250 8 Max ADC VREF+ SET TO VDD ADC VREF- SET TO GND 200 Typical 6 Min 4 ADC Output Codes 100 50 0 Max Typical Offset Voltage (V) 150 2 0 Min -2 -50 -4 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -100 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -6 -150 -8 -60 -40 -20 0 20 40 60 80 100 120 140 160 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 Common Mode Voltage (V) Temperature (°C) FIGURE 27-79: Temperature Indicator Slope Normalized to 20°C, High Range, VDD = 3.0, PIC16LF1703/7 only. FIGURE 27-82: Op Amp, Offset Over Common-Mode Voltage, VDD = 3.0V, Temp. = 25°C 8 80 Max Max 6 75 4 70 Typical Offset Voltage (V) CMRR (dB) p 65 60 Min 55 Typical 2 0 -2 -4 50 Min Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı 45 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -6 -8 40 -50 -30 -10 10 30 50 70 90 110 0.0 130 0.5 1.0 1.5 FIGURE 27-80: Op Amp, Common-Mode Rejection Ratio (CMRR), VDD = 3.0V , 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Common Mode Voltage (V) Temperature (°C) , FIGURE 27-83: Op Amp, Offset Over Common-Mode Voltage, VDD = 5.0V, Temp. = 25°C, PIC16F1703/7 only. , , , 35% 7.75 Sample Size = 3,200 7.70 30% VDD = 3V 7.65 7.60 Slew Rate (V/μs) Percent of Units 25% 20% -40°C 15% 25°C 10% 7.55 VDD = 3.6V 7.50 7.45 85°C 7.40 125°C 7.35 7.30 5% VDD = 2.3V 7.25 7.20 0% -7 -5 -4 -3 -2 -1 0 1 2 Offset Voltage (mV) 3 4 5 6 FIGURE 27-81: Op Amp, Offset Voltage Histogram, VDD = 3.0V, VCM = VDD/2 2013-2015 Microchip Technology Inc. 7 -60 -40 -20 0 20 40 60 80 100 120 140 VDD (V) FIGURE 27-84: Op Amp, Output Slew Rate, Rising Edge, PIC16LF1703/7 only. DS40001722C-page 307 PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. g , 4.0 0.85 0.80 VDD = 3.6V -40°C VDD= 3V 3.4 VDD = 2.3V ZCD Pin Voltage (V) Slew Rate (V/μs) 3.7 0.75 25°C 0.70 85°C 3.1 0.65 2.8 125° 0.60 -60 -40 -20 0 20 40 60 80 100 120 140 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 27-85: Op Amp, Output Slew Rate, Falling Edge, PIC16LF1703/7 only. FIGURE 27-88: Zero-Cross Detection (ZCD) Pin Voltage, Typical Measured Values. 1.4 8.0 Fall-2.3V 1.2 7.8 Fall-3.0V VDD = 3V Fall-5.5V 7.6 7.4 VDD = 3.6V 7.2 Time (us) Slew Rate (V/μs) 1.0 VDD = 2.3V 0.8 0.6 0.4 Rise-2.3V Rise-3.0V 7.0 0.2 Rise-5.5V VDD = 5V 6.8 0.0 -60 -40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 VDD (V) 40 60 80 100 120 140 160 Temperature (°C) FIGURE 27-86: Op Amp, Output Slew Rate, Rising Edge, PIC16F1703/7 only. FIGURE 27-89: Zero-Cross Detection (ZCD) Time Over Voltage, Typical Measured Values. 8 4.4 VDD = 5V Slew Rate (V/μs) 4.0 3.8 VDD = 3.6V 3.6 VDD = 3V 3.4 3.2 ZCD Source/Sink Current (mA) 5.5V 4.2 3.0V 6 2.3V 4 2 1.8V 0 VDD = 2.3V -2 3.0 -4 2.8 -60 -40 -20 0 20 40 60 80 100 120 140 VDD (V) FIGURE 27-87: Op Amp, Output Slew Rate, Falling Edge, PIC16F1703/7 only. DS40001722C-page 308 0.0 0.5 1.0 1.5 2.0 ZCD Pin Voltage (V) FIGURE 27-90: Zero-Cross Detection (ZCD) Pin Current Over ZCD Pin Voltage, Typical Measured Values from -40°C to 125°C. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 1.0 0.9 0.8 Time (us) 0.7 0.6 0.5 0.4 1.8V 0.3 2.3V 3.0V 0.2 5.5V 0.1 0 50 100 150 200 250 300 350 400 450 500 ZCD Source/Sink Current (uA) FIGURE 27-91: Zero-Cross Detection (ZCD) Pin Response Time Over Current, Typical Measured Values from -40°C to 125°C. 2013-2015 Microchip Technology Inc. DS40001722C-page 309 PIC16(L)F1703/7 28.0 DEVELOPMENT SUPPORT The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® X IDE Software • Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB X SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkit™ 3 • Device Programmers - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits • Third-party development tools 28.1 MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: • Color syntax highlighting • Smart code completion makes suggestions and provides hints as you type • Automatic code formatting based on user-defined rules • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • • • • Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker DS40001722C-page 310 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 28.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 28.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: 28.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 28.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process 2013-2015 Microchip Technology Inc. DS40001722C-page 311 PIC16(L)F1703/7 28.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 28.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradeable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. DS40001722C-page 312 28.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 28.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial Programming™ (ICSP™). 28.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 28.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. 28.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. • Device Programmers and Gang Programmers from companies, such as SoftLog and CCS • Software Tools from companies, such as Gimpel and Trace Systems • Protocol Analyzers from companies, such as Saleae and Total Phase • Demonstration Boards from companies, such as MikroElektronika, Digilent® and Olimex • Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 2013-2015 Microchip Technology Inc. DS40001722C-page 313 PIC16(L)F1703/7 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 14-Lead PDIP (300 mil) Example PIC16F1703 -I/P e3 1331017 28-Lead SOIC (7.50 mm) 14-Lead SOIC (3.90 mm) Example Example PIC16F1703 -I/SL e3 1331017 14-Lead TSSOP (4.4 mm) XXXXXXXX YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: DS40001722C-page 314 Example F1703IST 1331 017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Package Marking Information (Continued) 16-Lead QFN (4x4x0.9 mm) PIN 1 Example PIN 1 PIC16 F1703 -I/ML 331017 e3 20-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SSOP (5.30 mm) Example PIC16F1707 -E/P e3 1331017 Example PIC16F1707 -E/SS e3 1331017 20-Lead SOIC (7.50 mm) Example PIC16F1707 -E/SO e3 1331017 2013-2015 Microchip Technology Inc. DS40001722C-page 315 PIC16(L)F1703/7 Package Marking Information (Continued) 20-Lead QFN (4x4x0.9 mm) PIN 1 Example PIN 1 PIC16 F1707 E/ML 331017 e3 DS40001722C-page 316 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 29.2 Package Details The following sections give the technical details of the packages. 3 %& %!%4") ' % 4$% %"% %%255)))& &54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 6% & 9&% 7!&( $ 7+8- 7 7 7: ; % % % < < ""44 0 , 0 1 % % 0 < < !"% !"="% - , ,0 ""4="% - 0 > :9% ,0 0 0 % % 9 0 , 0 9"4 > 0 ( 0 ? ( > 1 < < 69"="% 9 )9"="% : )* 1+ , !"#$%!&'(!%&! %( %")%%%" *$%+% % , & "-" %!"& "$ %! "$ %! %#". " & "% -/0 1+21 & %#%! ))% !%% ) +01 2013-2015 Microchip Technology Inc. DS40001722C-page 317 PIC16(L)F1703/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001722C-page 318 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc. DS40001722C-page 319 PIC16(L)F1703/7 3 %& %!%4") ' % 4$% %"% %%255)))& &54 DS40001722C-page 320 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc. DS40001722C-page 321 PIC16(L)F1703/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001722C-page 322 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc. DS40001722C-page 323 PIC16(L)F1703/7 ! "#$ %&'(()*"# 3 %& %!%4") ' % 4$% %"% %%255)))& &54 D2 D EXPOSED PAD e E2 E 2 2 1 1 b TOP VIEW K N N NOTE 1 L BOTTOM VIEW A3 A A1 6% & 9&% 7!&( $ 99-- 7 7 7: ; ? % :8% > %" $$ 0 + %%4 , :="% - -# ""="% - :9% -# ""9% ?01+ -3 1+ 0 ?0 > 1+ 0 ?0 + %%="% ( 0 , ,0 + %%9% 9 , 0 + %%% -# "" V < !"#$%!&'(!%&! %( %")%%%" 4 ) !%" , & "% -/0 1+2 1 & %#%! ))% !%% -32 $& '! !)% !%% '$ $ &% ! > < ) +1 DS40001722C-page 324 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc. DS40001722C-page 325 PIC16(L)F1703/7 + 3 %& %!%4") ' % 4$% %"% %%255)))& &54 N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e 6% & 9&% 7!&( $ 7+8- 7 7 7: ; % % % < < ""44 0 , 0 1 % % 0 < < !"% !"="% - , , ,0 ""4="% - 0 > :9% > , ? % % 9 0 , 0 9"4 > 0 ( 0 ? ( > 1 < < 69"="% 9 )9"="% : )* 1+ , !"#$%!&'(!%&! %( %")%%%" *$%+% % , & "-" %!"& "$ %! "$ %! %#". " & "% -/0 1+2 1 & %#%! ))% !%% ) +1 DS40001722C-page 326 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 + ,-.%,/,,0),,/ 3 %& %!%4") ' % 4$% %"% %%255)))& &54 D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 6% & 9&% 7!&( $ L 99-- 7 7 7: ; % :8% < ?01+ < ""44 ?0 0 >0 %" $$ 0 < < :="% - > > ""4="% - 0 0, 0? :9% ? 0 3 %9% 9 00 0 0 3 %% 9 0-3 9"4 < 3 % W W 0 >W 9"="% ( < ,> !"#$%!&'(!%&! %( %")%%%" & "-" %!"& "$ %! "$ %! %#"&& " , & "% -/0 1+2 1 & %#%! ))% !%% -32 $& '! !)% !%% '$ $ &% ! ) +1 2013-2015 Microchip Technology Inc. DS40001722C-page 327 PIC16(L)F1703/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001722C-page 328 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc. DS40001722C-page 329 PIC16(L)F1703/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001722C-page 330 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc. DS40001722C-page 331 PIC16(L)F1703/7 + "#$ %&'(()*"# 3 %& %!%4") ' % 4$% %"% %%255)))& &54 D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 6% & 9&% 7!&( $ 99-- 7 7 7: ; % :8% > %" $$ 0 + %%4 , :="% - -# ""="% - :9% -# ""9% 01+ -3 1+ ? > 1+ ? > + %%="% ( > 0 , + %%9% 9 , 0 + %%% -# "" V < < !"#$%!&'(!%&! %( %")%%%" 4 ) !%" , & "% -/0 1+2 1 & %#%! ))% !%% -32 $& '! !)% !%% '$ $ &% ! ) +?1 DS40001722C-page 332 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 3 %& %!%4") ' % 4$% %"% %%255)))& &54 2013-2015 Microchip Technology Inc. DS40001722C-page 333 PIC16(L)F1703/7 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (10/2013) Initial release of this document. Revision B (02/2015) Changed from Preliminary to Final data sheet. Added Section 3.2: High-Endurance Flash. Removed Figures 6-3, 6-4, 6-6, 6-10. Removed Sections 6.2.1.2, 6.2.1.3, 6.2.1.6, 6.3.2, 6.4, 6.4.2, 6.5. Replaced Section 18.0. Updated Figures 2-1, 6-1, 6-2, 6-10, 7-2, 7-3, 14-1, 16-1, 17-1. Updated PIC16(L)F170x Family Types Table. Updated Registers 4-1, 6-1, 6-2, 14-1, 16-1, 16-2, 17-1. Updated Section 23.0 from SSP to SSPx. Updated Sections 6.1, 6.2, 6.2.1, 6.2.1.1, 6.2.2, 6.2.2.1, 6.2.2.2, 6.2.2.4, 6.2.2.6, 6.3.1, 8.2.2, 11.3.6, 16.1.3, 17.0, 17.1, 17.1.1. Updated Tables 1, 2, 1-2, 1-3, 3-1, 6-1, 6-2, 26-18. Revision C (09/2015) Added High Endurance Flash Data Memory (HEF) bullet on front page. Updated PIC16(L)F170x Family Types Table. Updated graphs 27-63 through 27-70. DS40001722C-page 334 2013-2015 Microchip Technology Inc. PIC16(L)F1703/7 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. 2013-2015 Microchip Technology Inc. DS40001722C-page 335 PIC16(L)F1703/7 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) Device: PIC16F1703, PIC16LF1703, PIC16F1707, 7PIC16LF1707 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package:(2) ML P SL SO SS ST = = = = = = Pattern: (Industrial) (Extended) QFN PDIP SOIC SOIC SSOP TSSOP QTP, SQTP, Code or Special Requirements (blank otherwise) DS40001722C-page 336 PIC16LF1703- I/P Industrial temperature PDIP package PIC16F1707- E/SS Extended temperature, SSOP package Note 1: 2: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Small form-factor packaging options may be available. Please check www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office. 2013-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-846-8 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2013-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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