PIC16(L)F1705/9 Cost-Effective 8-Bit Intelligent Analog Flash Microcontrollers Description PIC16(L)F1705/9 microcontrollers combine Intelligent analog integration with low cost and extreme low-power (XLP) to suit a variety of general purpose applications. These 14- and 20-pin devices deliver on-chip op amps, core independent peripherals (CLC and COG), Peripheral Pin Select and Zero-Cross Detect, providing for increased design flexibility. Core Features Digital Peripherals • C Compiler Optimized RISC Architecture • Only 49 Instructions • Operating Speed: - 0-32 MHz - 125 ns minimum instruction cycle • Interrupt Capability • 16-Level Deep Hardware Stack • Four 8-bit Timers • One 16-bit Timer • Power-on Reset (POR) • Power-up Timer (PWRT) • Low-Power Brown-Out Reset (LPBOR) • Programmable Watchdog Timer (WDT) up to 256s • Programmable Code Protection • Configurable Logic Cell (CLC): - Integrated combinational and sequential logic • Complementary Output Generator (COG): - Rising/falling edge dead-band control/ blanking • Capture/Compare/PWM (CCP) module • PWM: Two 10-bit Pulse-Width Modulators • Serial Communications: - SPI, I2C, RS-232, RS-485, LIN compatible - Auto-Baud Detect, auto-wake-up on start • Up to 17 I/O Pins plus One Input-Only Pin: - Individually programmable pull-ups - Slew rate control - Interrupt-on-change with edge-select • Peripheral Pin Select (PPS): - Enables pin mapping of digital I/O • Timer0: 8-Bit Timer/Counter with 8-Bit Prescaler • Enhanced Timer1: - 16-bit timer/counter with prescaler - External Gate Input mode - Low-power 32 kHz secondary oscillator driver • Timer2/4/6: 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler and Postscaler Memory • • • • 8 Kwords Flash Program Memory 1024 Bytes Data SRAM Memory Direct, Indirect and Relative Addressing modes High Endurance Flash Data Memory (HEF) - 128 bytes of nonvolatile data storage - 100k erase/write cycles Operating Characteristics • Operating Voltage Range: - 1.8V to 3.6V (PIC16LF1705/9) - 2.3V to 5.5V (PIC16F1705/9) • Temperature Range: - Industrial: -40°C to 85°C - Extended: -40°C to 125°C eXtreme Low-Power (XLP) Features • • • • Sleep mode: 50 nA @ 1.8V, typical Watchdog Timer: 500 nA @ 1.8V, typical Secondary Oscillator: 500 nA @ 32 kHz Operating Current: - 8 uA @ 32 kHz, 1.8V, typical - 32 uA/MHz @ 1.8V, typical 2013-2015 Microchip Technology Inc. Intelligent Analog Peripherals • Operational Amplifiers: - Two configurable rail-to-rail op amps - Selectable internal and external channels - 2 MHz gain bandwidth product • High-Speed Comparators: - Two comparators - 50 ns response time - Rail-to-rail inputs • 10-Bit Analog-to-Digital Converter (ADC): - Up to 12 external channels - Conversion available during Sleep - Temperature indicator DS40001729C-page 1 PIC16(L)F1705/9 Intelligent Analog Peripherals (Cont.) Programming/Debug Features • Zero-Cross Detector (ZCD): - Detect when AC signal on pin crosses ground • 8-Bit Digital-to-Analog Converter (DAC): - Output available externally - Internal connections to comparators, op amps, Fixed Voltage Reference (FVR) and ADC • Internal Voltage Reference module • In-Circuit Debug Integrated On-Chip • Emulation Header for Advanced Debug: - Provides trace, background debug and up to 32 hardware break points • In-Circuit Serial Programming™ (ICSP™) via Two Pins Clocking Structure • 16 MHz Internal Oscillator Block: - ±1% at calibration - Selectable frequency range from 0 to 32 MHz • 31 kHz Low-Power Internal Oscillator • External Oscillator Block with: - Three crystal/resonator modes up to 20 MHz - Two external clock modes up to 20 MHz • Fail-Safe Clock Monitor • Two-Speed Oscillator Start-up • Oscillator Start-up Timer (OST) Device Data Sheet Index Program Memory Flash (words) Data SRAM (bytes) High-Endurance Flash (bytes) I/O’s(2) 10-bit ADC (ch) 8-bit DAC High-Speed/ Comparators Op Amp Zero Cross Timers (8/16-bit) CCP PWM COG EUSART MSSP (I2C/SPI) CLC PPS Debug(1) XLP PIC16(L)F170x Family Types PIC16(L)F1703 (3) 2048 256 128 12 8 0 0 2 1 2/1 2 0 0 0 1 0 Y I/E Y PIC16(L)F1704 (1) 4096 512 128 12 8 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y PIC16(L)F1705 (2) 8192 1024 128 12 8 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y PIC16(L)F1707 (3) 2048 256 128 18 12 0 0 2 1 2/1 2 0 0 0 1 0 Y I/E Y PIC16(L)F1708 (1) 4096 512 128 18 12 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y PIC16(L)F1709 (2) 8192 1024 128 18 12 1 2 2 1 4/1 2 2 1 1 1 3 Y I/E Y Note 1: 2: Debugging Methods: (I) – Integrated on Chip; (H) – using Debug Header; E – using Emulation Header. One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document.) 1: DS40001715 PIC16(L)F1704/8 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers. 2: DS40001729 PIC16(L)F1705/9 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers. 3: DS40001722 PIC16(L)F1703/7 Data Sheet, 14/20-Pin Flash, 8-bit Microcontrollers Note: For other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office. DS40001729C-page 2 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Pin Diagrams VDD RA5 RA4 VPP/MCLR/RA3 RC5 RC4 RC3 14 13 12 11 10 9 8 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 16-PIN QFN 16 15 14 13 VDD NC FIGURE 2: 1 2 3 4 5 6 7 PIC16(L)F1705 14-PIN PDIP, SOIC, TSSOP NC VSS FIGURE 1: 1 12 RA0/ICSPDAT 2 11 RA1/ICSPCLK 3 PIC16(L)F1705 10 RA2 9 RC0 4 RC4 RC3 RC2 RC1 5 6 7 8 RA5 RA4 RA3/MCLR/VPP RC5 2013-2015 Microchip Technology Inc. DS40001729C-page 3 PIC16(L)F1705/9 20-PIN PDIP, SOIC, SSOP VDD 20 VSS RA5 2 19 ICSPDAT/RA0 RA4 3 18 ICSPCLK/RA1 VPP/MCLR/RA3 4 17 RA2 RC5 5 16 RC0 15 RC1 14 RC2 13 RB4 9 12 RB5 10 11 RB6 RC4 RC3 RC6 RC7 RB7 6 7 8 20-PIN QFN 20 19 18 17 16 RA4 RA5 VDD VSS RA0/ICSPDAT FIGURE 4: 1 PIC16(L)F1709 FIGURE 3: 1 15 RA1/ICSPCLK 2 14 RA2 3 PIC16(L)F1709 13 RC0 4 12 RC1 5 11 RC2 RC7 RB7 RB6 RB5 RB4 6 7 8 9 10 VPP/MCLR/RA3 RC5 RC4 RC3 RC6 DS40001729C-page 4 2013-2015 Microchip Technology Inc. Comparator Op Amp DAC Zero Cross Timers CCP PWM COG MSSP EUSART CLC Interrupt Pull-up 13 12 AN0 VREF- C1IN+ — DAC1OUT1 — — — — — — — — IOC Y ICSPDAT RA1 12 11 AN1 VREF+ C1IN0C2IN0- — — — — — — — — — — IOC Y ICSPCLK RA2 11 10 AN2 — — — DAC1OUT2 ZCD T0CKI(1) — — COGIN(1) — — — INT(1) IOC Y — RA3 4 3 — — — — — — — — — — — — — IOC Y MCLR VPP RA4 3 2 AN3 — — — — — T1G(1) SOSCO — — — — — — IOC Y CLKOUT OSC2 RA5 2 1 — — — — — — T1CKI(1) SOSCI — — — — — CLCIN3(1) IOC Y CLKIN OSC1 RC0 10 9 AN4 — C2IN+ OPA1IN+ — — — — — — SCK(1) SCL(3) — — IOC Y — RC1 9 8 AN5 — C1IN1C2IN1- OPA1IN- — — — — — — SDI(1) SDA(3) — CLCIN2(1) IOC Y — RC2 8 7 AN6 — C1IN2C2IN2- OPA1OUT — — — — — — — — — IOC Y — RC3 7 6 AN7 — C1IN3C2IN3- OPA2OUT — — — CCP2(1) — — SS(1) — CLCIN0(1) IOC Y — RC4 6 5 — — — OPA2IN- — — — — — — — CK(1) CLCIN1(1) IOC Y — — — — RX(1,3) — IOC Y — — — — — — — — VDD Basic ADC RA0 Reference 16-Pin QFN 14/16-PIN ALLOCATION TABLE (PIC16(L)F1705) 14-Pin PDIP/SOIC/TSSOP TABLE 1: I/O(2) 2013-2015 Microchip Technology Inc. Pin Allocation Tables 5 4 — — — OPA2IN+ — — — VDD 1 16 — — — — — — — — VSS 14 13 — — — — — — — — — — — — — — — VSS — — — — C1OUT — — — — CPP1 PWM3OUT COGA SDA(3) CK CLC1OUT — — — — — — — C2OUT — — — — CPP2 PWM4OUT COGB SCL(3) DT(3) CLC2OUT — — — — — — — — — — — — — — COGC SDO TX CLC3OUT — — — — — — — — — — — — — — COGD SCK — — — — — OUT(2) Note 1: 2: 3: Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1705/9 DS40001729C-page 5 RC5 CCP1(1) 20-Pin QFN ADC Comparator Op Amp DAC Zero Cross Timers CCP PWM COG MSSP EUSART CLC Interrupt Pull-up 19 16 AN0 VREF- C1IN+ — DAC1OUT1 — — — — — — — — IOC Y ICSPDAT RA1 18 15 AN1 VREF+ C1IN0C2IN0- — — — — — — — — — — IOC Y ICSPCLK RA2 17 14 AN2 — — — DAC1OUT2 ZCD T0CKI(1) — — COGIN(1) — — — INT(1) IOC Y — RA3 4 1 — — — — — — — — — — — — — IOC Y MCLR VPP RA4 3 20 AN3 — — — — — T1G(1) SOSCO — — — — — — IOC Y CLKOUT OSC2 RA5 2 19 — — — — — — T1CKI SOSCI — — — — — CLCIN3(1) IOC Y CLKIN OSC1 RB4 13 10 AN10 — — OPA1IN- — — — — — — SDI(1) SDA(3) — — IOC Y — RB5 12 9 AN11 — — OPA1IN+ — — — — — — — RX(1,3) — IOC Y — RB6 11 8 — — IOC Y — RB7 10 CK(1) — IOC Y — RC0 16 — — IOC Y — IOC Y — — — — — — — — — SCK(1) SCL(3) — — — — — — — — — — — C2IN+ — — 7 — 13 AN4 — — — — — — — — Basic 20-Pin PDIP/ SOIC/SSOP RA0 Reference I/O(2) 20-PIN ALLOCATION TABLE (PIC16(L)F1709) 2013-2015 Microchip Technology Inc. RC1 15 12 AN5 — C1IN1C2IN1- — — — — — — — — — CLCIN2(1) RC2 14 11 AN6 — C1IN2C2IN2- OPA1OUT — — — — — — — — — IOC Y — RC3 7 4 AN7 — C1IN3C2IN3- OPA2OUT — — — CCP2(1) — — — — CLCIN0(1) IOC Y — RC4 6 3 — — — — — — — — — — — — CLCIN1(1) IOC Y — — — — — — IOC Y — — (1) RC5 5 2 — — — — — — — RC6 8 5 AN8 — — OPA2IN- — — — — — — SS(1) — — IOC Y RC7 9 6 AN9 — — OPA2IN+ — — — — — — — — — IOC Y — VDD 1 18 — — — — — — — — — — — — — — — VDD VSS 20 17 — — — — — — — — — — — — — — — VSS — OUT Note (2) 1: 2: 3: CCP1 (3) — — — — C1OUT — — — — CPP1 PWM3OUT COGA SDA CK CLC1OUT — — — — — — C2OUT — — — — CPP2 PWM4OUT COGB SCL(3) DT(3) CLC2OUT — — — — — — — — — — — — — — COGC SDO TX CLC3OUT — — — — — — — — — — — — — — COGD SCK — — — — — Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. PIC16(L)F1705/9 DS40001729C-page 6 TABLE 2: PIC16(L)F1705/9 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 17 3.0 Memory Organization ................................................................................................................................................................. 19 4.0 Device Configuration .................................................................................................................................................................. 47 5.0 Resets ........................................................................................................................................................................................ 53 6.0 Oscillator Module (with Fail-Safe Clock Monitor) ....................................................................................................................... 61 7.0 PIC16(L)F1705/9 Interrupts........................................................................................................................................................ 79 8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 92 9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 96 10.0 Flash Program Memory Control ............................................................................................................................................... 101 11.0 I/O Ports ................................................................................................................................................................................... 118 12.0 Peripheral Pin Select (PPS) Module ........................................................................................................................................ 137 13.0 Interrupt-On-Change ................................................................................................................................................................ 144 14.0 Fixed Voltage Reference (FVR) .............................................................................................................................................. 151 15.0 Temperature Indicator Module ................................................................................................................................................. 154 16.0 Comparator Module.................................................................................................................................................................. 156 17.0 Pulse-Width Modulation (PWM) ............................................................................................................................................... 165 18.0 Complementary Output Generator (COG) Module................................................................................................................... 171 19.0 Configurable Logic Cell (CLC).................................................................................................................................................. 203 20.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 218 21.0 Operational Amplifier (OPA) Modules ...................................................................................................................................... 232 22.0 8-Bit Digital-to-Analog Converter (DAC1) Module.................................................................................................................... 235 23.0 Zero-Cross Detection (ZCD) Module........................................................................................................................................ 239 24.0 Timer0 Module ......................................................................................................................................................................... 243 25.0 Timer1 Module with Gate Control............................................................................................................................................. 246 26.0 Timer2/4/6 Module ................................................................................................................................................................... 257 27.0 Capture/Compare/PWM Modules ............................................................................................................................................ 262 28.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 270 29.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 323 30.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 354 31.0 Instruction Set Summary .......................................................................................................................................................... 356 32.0 Electrical Specifications............................................................................................................................................................ 370 33.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 403 34.0 Development Support............................................................................................................................................................... 425 35.0 Packaging Information.............................................................................................................................................................. 429 Appendix A: Data Sheet Revision History.......................................................................................................................................... 450 The Microchip Website ...................................................................................................................................................................... 451 Customer Change Notification Service .............................................................................................................................................. 451 Customer Support .............................................................................................................................................................................. 451 Product Identification System ............................................................................................................................................................ 452 Worldwide Sales and Service ............................................................................................................................................................ 454 2013-2015 Microchip Technology Inc. DS40001729C-page 7 PIC16(L)F1705/9 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at [email protected]. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Website; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our website at www.microchip.com to receive the most current information on all of our products. DS40001729C-page 8 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 1.0 DEVICE OVERVIEW The PIC16(L)F1705/9 are described within this data sheet. They are available in 14-pin and 20-pin DIP packages and 16-pin and 20-pin QFN packages. Figure 1-1 shows a block diagram of the PIC16(L)F1705/9 devices. Table 1-2 shows the pinout descriptions. Reference Table 1-1 for peripherals available per device. Peripheral PIC16(L)F1709 DEVICE PERIPHERAL SUMMARY PIC16(L)F1705 TABLE 1-1: Analog-to-Digital Converter (ADC) ● ● Digital-to-Analog Converter (DAC) ● ● Complementary Output Generator (COG) ● ● Fixed Voltage Reference (FVR) ● ● Zero-Cross Detection (ZCD) ● ● Temperature Indicator ● ● Capture/Compare/PWM (CCP/ECCP) Modules CCP1 ● ● CCP2 ● ● C1 ● ● C2 ● ● CLC1 ● ● CLC2 ● ● CLC3 ● ● Comparators Configurable Logic Cell (CLC) Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter (EUSART) EUSART ● ● MSSP ● ● Op Amp 1 ● ● Op Amp 2 ● ● PWM3 ● ● PWM4 ● ● Timer0 ● ● Timer1 ● ● Timer2 ● ● Master Synchronous Serial Ports Op Amp Pulse-Width Modulator (PWM) Timers 2013-2015 Microchip Technology Inc. DS40001729C-page 9 PIC16(L)F1705/9 FIGURE 1-1: PIC16(L)F1705/9 BLOCK DIAGRAM Program Flash Memory RAM PORTA PORTB(1) CLKOUT Timing Generation HFINTOSC/ LFINTOSC Oscillator CLKIN PORTC CPU Figure 2-1 MCLR ZCD Op Amps PWM Timer0 Timer1 Timer2 MSSP Comparators COG Temp. Indicator Note 1: 2: DS40001729C-page 10 ADC 10-Bit FVR DAC CCPs EUSART CLCs PIC16(L)F1709 only. See applicable chapters for more information on peripherals. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 1-2: PIC16(L)F1705 PINOUT DESCRIPTION Name Function Input Type Output Type RA0 TTL/ST CMOS General purpose I/O. AN0 AN — ADC Channel 0 input. RA0/AN0/VREF-/C1IN+/ DAC1OUT/ICSPDAT VREF- AN — ADC Negative Voltage Reference input. C1IN+ AN — Comparator C1 positive input. DAC1OUT — AN ICSPDAT ST CMOS ICSP™ Data I/O. RA1 TTL/ST CMOS General purpose I/O. AN1 AN — ADC Channel 1 input. RA1/AN1/VREF+/C1IN0-/C2IN0-/ ICSPCLK Digital-to-Analog Converter output. VREF+ AN — ADC Voltage Reference input. C1IN0- AN — Comparator C2 negative input. C2IN0- AN — Comparator C3 negative input. ICSPCLK ST — Serial Programming Clock. RA2 TTL/ST CMOS General purpose I/O. AN2 AN — ADC Channel 2 input. DAC1OUT2 — AN Digital-to-Analog Converter output. ZCD — AN Zero-Cross Detection Current Source/Sink. RA2/AN2/DAC1OUT2/ZCD/ T0CKI(1)/COGIN(1)/INT(1) T0CKI TTL/ST — COGIN TTL/ST CMOS INT TTL/ST — RA3 TTL/ST CMOS RA3/MCLR/VPP Timer0 clock input. Complementary Output Generator input. External interrupt. General purpose I/O. MCLR ST — Master Clear with internal pull-up. VPP HV — Programming voltage. RA4 TTL/ST CMOS General purpose I/O. AN3 AN — ADC Channel 3 input. T1G TTL/ST — Timer1 gate input. SOSCO XTAL XTAL RA4/AN3/T1G(1)/SOSCO/ OSC2/CLKOUT RA5/T1CKI(1)/SOSCI/ CLCIN3(1)/OSC1/CLKIN Description Secondary Oscillator Connection. OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. RA5 TTL/ST CMOS General purpose I/O. T1CKI TTL/ST — SOSCI XTAL XTAL CLCIN3 TTL/ST — OSC1 — XTAL CLKIN ST — Timer1 clock input. Secondary Oscillator Connection. Configurable Logic Cell source input. Crystal/Resonator (LP, XT, HS modes). External clock input (EC mode). Legend: AN = Analog input or output CMOS= CMOS compatible input or output TTL = TTL compatible input ST I2C = Schmitt Trigger input with I2C Note 1: 2: 3: OD = Open-Drain = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal levels Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. 2013-2015 Microchip Technology Inc. DS40001729C-page 11 PIC16(L)F1705/9 TABLE 1-2: PIC16(L)F1705 PINOUT DESCRIPTION (CONTINUED) Name Function Input Type Output Type RC0 TTL/ST CMOS RC0/AN4/C2IN+/OPA1IN+/ SCK(1)/SCL(3) RC1/AN5/C1IN1-/C2IN1-/ OPA1IN-/SDI(1)/SDA(3)/ CLCIN2(1) General purpose I/O. AN4 AN — ADC Channel 4 input. C2IN+ AN — Comparator positive input. OPA1IN+ AN — Operational Amplifier 1 non-inverting input. SCK TTL/ST — SPI clock. SCL 2 I C — I2C clock. RC1 TTL/ST CMOS General purpose I/O. AN5 AN — ADC Channel 5 input. C1IN1- AN — Comparator C1 negative input. C2IN1- AN — Comparator C2 negative input. OPA1IN- AN — Operational Amplifier 1 inverting input. SDI CMOS — SPI data input. SDA I2C — I2C data input. CLCIN2 TTL/ST — RC2 TTL/ST CMOS RC2/AN6/C1IN2-/C2IN2-/ OPA1OUT RC3/AN7/C1IN3-/C2IN3-/ OPA2OUT/CCP2(1)/SS(1)/ CLCIN0(1) Description Configurable Logic Cell source input. General purpose I/O. AN6 AN — ADC Channel 6 input. C1IN2- AN — Comparator C1 negative input. Comparator C2 negative input. C2IN2- AN — OPA1OUT — AN RC3 TTL/ST CMOS General purpose I/O. AN7 AN — ADC Channel 7 input. C1IN3- AN — Comparator C1 negative input. C2IN3- AN — Comparator C2 negative input. OPA2OUT — AN Operational Amplifier 2 output. CCP2 TTL/ST — Capture/Compare/PWM2. SS TTL/ST — Slave Select input. CLCIN0 TTL/ST — Configurable Logic Cell source input. RC4/OPA2IN-/CK(1)/CLCIN1(1) RC4 TTL/ST CMOS OPA2IN- AN — Operational Amplifier 1 output. General purpose I/O. Operational Amplifier 2 inverting input. CK TTL/ST — USART synchronous clock. CLCIN1 TTLST — Configurable Logic Cell source input. RC5 TTL/ST CMOS OPA2IN+ AN — CCP1 TTL/ST — Capture/Compare/PWM1. RX TTL/ST — USART asynchronous input. RC5/OPA2IN+/CCP1(1)/RX(1) General purpose I/O. Operational Amplifier 2 non-inverting input. Legend: AN = Analog input or output CMOS= CMOS compatible input or output TTL = TTL compatible input ST I2C = Schmitt Trigger input with I2C Note 1: 2: 3: OD = Open-Drain = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal levels Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001729C-page 12 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 1-2: PIC16(L)F1705 PINOUT DESCRIPTION (CONTINUED) Function Input Type Output Type VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. C1OUT — CMOS Comparator output. Name OUT(2) Description C2OUT — CMOS Comparator output. CCP1 — CMOS Capture/Compare/PWM1 output. CCP2 — CMOS Capture/Compare/PWM2 output. PWM3OUT — CMOS PWM3 output. PWM4OUT — CMOS PWM4 output. COGA — CMOS Complementary Output Generator Output A. COGB — CMOS Complementary Output Generator Output B. COGC — CMOS Complementary Output Generator Output C. COGD — CMOS Complementary Output Generator Output D. SDA(3) — OD I2C data input/output. SDO — CMOS SPI data output. SCK — CMOS SPI clock output. SCL(3) — OD I2C clock output. TX/CK — CMOS USART asynchronous TX data/synchronous clock output. DT — CMOS USART synchronous data output. CLC1OUT — CMOS Configurable Logic Cell 1 source output. CLC2OUT — CMOS Configurable Logic Cell 2 source output. CLC3OUT — CMOS Configurable Logic Cell 3 source output. Legend: AN = Analog input or output CMOS= CMOS compatible input or output TTL = TTL compatible input 2C I Note 1: 2: 3: ST = Schmitt Trigger input with I2C OD = Open-Drain = Schmitt Trigger input with CMOS levels HV = High Voltage XTAL = Crystal levels Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-1. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. 2013-2015 Microchip Technology Inc. DS40001729C-page 13 PIC16(L)F1705/9 TABLE 1-3: PIC16(L)F1709 PINOUT DESCRIPTION Name RA0/AN0/VREF-/C1IN+/ DAC1OUT/ICSPDAT RA1/AN1/VREF+/C1IN0-/C2IN0-/ ICSPCLK RA2/AN2/DAC1OUT2/ZCD/ T0CKI(1)/COGIN(1)/INT(1) RA3/MCLR/VPP Function Input Type Output Type RA0 TTL/ST CMOS General purpose I/O. AN0 AN — ADC Channel 0 input. VREF- AN — ADC Negative Voltage Reference input. C1IN+ AN — Comparator C1 positive input. Digital-to-Analog Converter output. Description DAC1OUT — AN ICSPDAT ST CMOS ICSP™ Data I/O. RA1 TTL/ST CMOS General purpose I/O. AN1 AN — ADC Channel 1 input. VREF+ AN — ADC Voltage Reference input. C1IN0- AN — Comparator C2 negative input. C2IN0- AN — Comparator C3 negative input. ICSPCLK ST — Serial Programming Clock. RA2 TTL/ST CMOS General purpose I/O. AN2 AN — ADC Channel 2 input. DAC1OUT 2 — AN Digital-to-Analog Converter output. ZCD — AN Zero-Cross Detection Current Source/Sink. T0CKI ST — Timer0 clock input. COGIN ST CMOS Complementary Output Generator input. INT ST — RA3 TTL/ST CMOS External interrupt. MCLR ST — Master Clear with internal pull-up. General purpose I/O. VPP HV — Programming voltage. RA4/AN3/T1G(1)/SOSCO/ RA4 TTL/ST CMOS General purpose I/O. OSC2/CLKOUT AN3 AN — ADC Channel 3 input. Timer1 gate input. RA5/T1CKI/SOSCI/ CLCIN3(1)/OSC1/CLKIN T1G ST — SOSCO XTAL XTAL Secondary Oscillator Connection. OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes). CLKOUT — CMOS FOSC/4 output. RA5 TTL/ST CMOS T1CKI ST — SOSCI XTAL XTAL CLCIN3 ST — OSC1 — XTAL CLKIN ST — Legend: AN = Analog input or output TTL= TTL compatible input I2C Note 1: 2: 3: General purpose I/O. Timer1 clock input. Secondary Oscillator Connection. Configurable Logic Cell source input. Crystal/Resonator (LP, XT, HS modes). External clock input (EC mode). CMOS= CMOS compatible input or output OD = Open-Drain ST = Schmitt Trigger input with CMOS levels = Schmitt Trigger input with I2C HV = High Voltage XTAL=Crystal levels Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001729C-page 14 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 1-3: PIC16(L)F1709 PINOUT DESCRIPTION (CONTINUED) Name RB4/AN10/OPA1IN-/SCK(1)/ SDA(3) RB5/AN11/OPA1IN+/RX(1) RB6/SDI(1)/SCL(3) Function Input Type Output Type RB4 TTL/ST CMOS AN10 AN — ADC Channel 10 input. OPA1IN- AN — Operational Amplifier 1 inverting input. SCK ST CMOS SDA I2C OD I2C data input/output. General purpose I/O. Description General purpose I/O. SPI clock. RB5 TTL/ST CMOS AN11 AN — OPA1IN+ AN — Operational Amplifier 1 non-inverting input. RX ST — USART asynchronous input. RB6 TTL/ST CMOS SDI CMOS — SPI data input. SCL 2C OD I2C clock. TTL/ST CMOS I ADC Channel 11 input. General purpose I/O. RB7/CK(1) RB7 CK ST CMOS USART synchronous clock. RC0/AN4/C2IN+ RC0 TTL/ST CMOS General purpose I/O. RC1/AN5/C1IN1-/C2IN1-/ CLCIN2(1) RC2/AN6/C1IN2-/C2IN2-/ OPA1OUT RC3/AN7/C1IN3-/C2IN3-/ OPA2OUT/CCP2(1)/CLCIN0(1) RC4/CLCIN1(1) AN4 AN — ADC Channel 4 input. C2IN+ AN — Comparator positive input. RC1 TTL/ST CMOS General purpose I/O. AN5 AN — ADC Channel 5 input. C1IN1- AN — Comparator C1 negative input. C2IN1- AN — Comparator C2 negative input. CLCIN2 ST — RC2 TTL/ST CMOS Note 1: 2: 3: Configurable Logic Cell source input. General purpose I/O. AN6 AN — ADC Channel 6 input. C1IN2- AN — Comparator C1 negative input. C2IN2- AN — Comparator C2 negative input. OPA1OUT — AN Operational Amplifier 1 output. RC3 TTL/ST CMOS General purpose I/O. AN7 AN — ADC Channel 7 input. C1IN3- AN — Comparator C1 negative input. C2IN3- AN — Comparator C2 negative input. Operational Amplifier 2 output. OPA2OUT — AN CCP2 ST CMOS CLCIN0 ST — RC4 TTL/ST CMOS CLCIN1 ST — Legend: AN = Analog input or output TTL= TTL compatible input I2C General purpose I/O. Capture/Compare/PWM2. Configurable Logic Cell source input. General purpose I/O. Configurable Logic Cell source input. CMOS= CMOS compatible input or output OD = Open-Drain ST = Schmitt Trigger input with CMOS levels = Schmitt Trigger input with I2C HV = High Voltage XTAL=Crystal levels Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. 2013-2015 Microchip Technology Inc. DS40001729C-page 15 PIC16(L)F1705/9 TABLE 1-3: PIC16(L)F1709 PINOUT DESCRIPTION (CONTINUED) Name RC5/CCP1(1) RC6/AN8/OPA2IN-/SS(1) RC7/AN9/OPA2IN+ Function Input Type Output Type RC5 TTL/ST CMOS CCP1 ST CMOS Capture/Compare/PWM1. RC6 TTL/ST CMOS General purpose I/O. AN8 AN — ADC Channel 8 input. OPA2IN- AN — Operational Amplifier 2 inverting input. Description General purpose I/O. SS ST — RC7 TTL/ST CMOS General purpose I/O. Slave Select input. AN9 AN — ADC Channel 9 input. OPA2IN+ AN — Operational Amplifier 2 non-inverting input. VDD VDD Power — Positive supply. VSS VSS Power — Ground reference. C1OUT — CMOS Comparator output. C2OUT — CMOS Comparator output. CCP1 — CMOS Capture/Compare/PWM1 output. CCP2 — CMOS Capture/Compare/PWM2 output. PWM3OUT — CMOS PWM3 output. PWM4OUT — CMOS PWM4 output. COGA — CMOS Complementary Output Generator Output A. COGB — CMOS Complementary Output Generator Output B. COGC — CMOS Complementary Output Generator Output C. COGD — CMOS Complementary Output Generator Output D. (3) — OD — CMOS OUT(2) SDA SDO Note 1: 2: 3: SPI data output. SCK — CMOS SPI clock output. SCL(3) I2C OD I2C clock output. TX/CK — CMOS USART asynchronous TX data/synchronous clock output. DT — CMOS USART synchronous data output. CLC1OUT — CMOS Configurable Logic Cell 1 source output. CLC2OUT — CMOS Configurable Logic Cell 2 source output. CLC3OUT — CMOS Configurable Logic Cell 3 source output. Legend: AN = Analog input or output TTL= TTL compatible input I2C I2C data input/output. CMOS= CMOS compatible input or output OD = Open-Drain ST = Schmitt Trigger input with CMOS levels = Schmitt Trigger input with I2C HV = High Voltage XTAL=Crystal levels Default peripheral input. Input can be moved to any other pin with the PPS input selection registers. See Register 12-2. All pin outputs default to PORT latch data. Any pin can be selected as a digital peripheral output with the PPS output selection registers. See Register 12-3. These I2C functions are bidirectional. The output pin selections must be the same as the input pin selections. DS40001729C-page 16 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 2.0 Relative Addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. ENHANCED MID-RANGE CPU This family of devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, Indirect, and FIGURE 2-1: • • • • Automatic Interrupt Context Saving 16-level Stack with Overflow and Underflow File Select Registers Instruction Set CORE BLOCK DIAGRAM 15 Configuration 15 MUX Flash Program Memory Program Bus 16-Level 8 Level Stack Stack (13-bit) (15-bit) 14 Instruction Instruction Reg reg 8 Data Bus Program Counter RAM Program Memory Read (PMR) 12 RAM Addr Addr MUX Direct Addr 7 5 Indirect Addr 12 12 BSR FSR Reg reg 15 FSR0reg Reg FSR FSR1 Reg FSR reg 15 STATUS Reg reg STATUS 8 3 Power-up Timer OSC1/CLKIN OSC2/CLKOUT Instruction Decodeand & Decode Control Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset MUX ALU 8 W reg Internal Oscillator Block VDD 2013-2015 Microchip Technology Inc. VSS DS40001729C-page 17 PIC16(L)F1705/9 2.1 Automatic Interrupt Context Saving During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 7.5 “Automatic Context Saving” for more information. 2.2 16-Level Stack with Overflow and Underflow These devices have a hardware stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled, will cause a software Reset. See Section 3.6 “Stack” for more details. 2.3 File Select Registers There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See Section 3.7 “Indirect Addressing” for more details. 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 31.0 “Instruction Set Summary” for more details. DS40001729C-page 18 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 3.0 MEMORY ORGANIZATION These devices contain the following types of memory: • Program Memory - Configuration Words - Device ID - User ID - Flash Program Memory • Data Memory - Core Registers - Special Function Registers - General Purpose RAM - Common RAM 3.1 The enhanced mid-range core has a 15-bit program counter capable of addressing a 32K x 14 program memory space. Table 3-1 shows the memory sizes implemented for the PIC16(L)F1705/9 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figure 3-1). 3.2 Note 1: The method to access Flash memory through the PMCON registers is described in Section 10.0 “Flash Program Memory Control”. The following features are associated with access and control of program memory and data memory: Program Memory Organization High-Endurance Flash This device has a 128-byte section of high-endurance program Flash memory (PFM) in lieu of data EEPROM. This area is especially well suited for nonvolatile data storage that is expected to be updated frequently over the life of the end product. See Section 10.2 “Flash Program Memory Overview” for more information on writing data to PFM. See Section 3.2.1.2 “Indirect Read with FSR” for more information about using the FSR registers to read byte data stored in PFM. • PCL and PCLATH • Stack • Indirect Addressing TABLE 3-1: DEVICE SIZES AND ADDRESSES Device Program Memory Space (Words) Last Program Memory Address High-Endurance Flash Memory Address Range(1) 8,192 1FFFh 1F80h-1FFFh PIC16(L)F1705/9 Note 1: High-endurance Flash applies to the low byte of each address in the range. 2013-2015 Microchip Technology Inc. DS40001729C-page 19 PIC16(L)F1705/9 FIGURE 3-1: PROGRAM MEMORY MAP AND STACK FOR PIC16(L)F1705/9 PC<14:0> CALL, CALLW RETURN, RETLW Interrupt, RETFIE 15 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory. 3.2.1.1 RETLW Instruction Stack Level 0 Stack Level 1 The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 3-1. Stack Level 15 EXAMPLE 3-1: Reset Vector 0000h Interrupt Vector 0004h 0005h Page 0 07FFh 0800h Page 1 On-chip Program Memory 3.2.1 0FFFh 1000h Page 2 17FFh 1800h Page 3 Rollover to Page 0 1FFFh 2000h constants BRW RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used. 3.2.1.2 Indirect Read with FSR The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower eight bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 3-2 demonstrates accessing the program memory via an FSR. Rollover to Page 3 DS40001729C-page 20 The high directive will set bit<7> if a label points to a location in program memory. 7FFFh 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 EXAMPLE 3-2: ACCESSING PROGRAM MEMORY VIA FSR constants RETLW DATA0 ;Index0 data RETLW DATA1 ;Index1 data RETLW DATA2 RETLW DATA3 my_function ;… LOTS OF CODE… MOVLW LOW constants MOVWF FSR1L MOVLW HIGH constants MOVWF FSR1H MOVIW 0[FSR1] ;THE PROGRAM MEMORY IS IN W 3.3 3.3.1 The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0Bh/x8Bh). These registers are listed below in Table 3-2. For detailed information, see Table 3-9. TABLE 3-2: Data Memory Organization The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of (Figure 3-2): • • • • 12 core registers 20 Special Function Registers (SFR) Up to 80 bytes of General Purpose RAM (GPR) 16 bytes of common RAM The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘0’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select Registers (FSR). See Section 3.7 “Indirect Addressing” for more information. Data memory uses a 12-bit address. The upper five bits of the address define the Bank address and the lower seven bits select the registers/RAM in that bank. CORE REGISTERS 3.3.1.1 CORE REGISTERS Addresses BANKx x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON STATUS Register The STATUS register, shown in Register 3-1, contains: • the arithmetic status of the ALU • the Reset status The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to Section 31.0 “Instruction Set Summary”). Note: 2013-2015 Microchip Technology Inc. The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. DS40001729C-page 21 PIC16(L)F1705/9 3.4 Register Definitions: Status REGISTER 3-1: U-0 STATUS: STATUS REGISTER U-0 — — U-0 R-1/q — TO R-1/q PD R/W-0/u R/W-0/u (1) Z DC R/W-0/u C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-5 Unimplemented: Read as ‘0’ bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT Time-out occurred bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. DS40001729C-page 22 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 3.4.1 SPECIAL FUNCTION REGISTER The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.4.2 FIGURE 3-2: 7-bit Bank Offset 0Bh 0Ch GENERAL PURPOSE RAM Core Registers (12 bytes) Special Function Registers (20 bytes maximum) 1Fh 20h Linear Access to GPR The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify access to large memory structures. See Section 3.7.2 “Linear Data Memory” for more information. 3.4.3 Memory Region 00h There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). 3.4.2.1 BANKED MEMORY PARTITIONING General Purpose RAM (80 bytes maximum) COMMON RAM There are 16 bytes of common RAM accessible from all banks. 6Fh 70h Common RAM (16 bytes) 7Fh 3.4.4 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Tables 3-3 through 3-8. 2013-2015 Microchip Technology Inc. DS40001729C-page 23 PIC16(L)F1705 MEMORY MAP (BANKS 0-7) BANK 0 000h BANK 1 080h Core Registers (Table 3-2) BANK 2 100h Core Registers (Table 3-2) BANK 3 180h Core Registers (Table 3-2) BANK 4 200h Core Registers (Table 3-2) BANK 5 280h Core Registers (Table 3-2) BANK 6 300h Core Registers (Table 3-2) BANK 7 380h Core Registers (Table 3-2) Core Registers (Table 3-2) 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h PORTA — PORTC — — PIR1 PIR2 PIR3 — TMR0 TMR1L 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h TRISA — TRISC — — PIE1 PIE2 PIE3 — OPTION_REG PCON 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h LATA — LATC — — CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h ANSELA — ANSELC — — PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h WPUA — WPUC — — SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON SSP1CON2 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h ODCONA — ODCONC — — CCPR1L CCPR1H CCP1CON — — — 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h SLRCONA — SLRCONC — — — — — — — — 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h INLVLA — INLVLC — — IOCAP IOCAN IOCAF — — — 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh TMR1H T1CON T1GCON TMR2 PR2 T2CON — — 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh FVRCON DAC1CON0 DAC1CON1 — — ZCD1CON — — 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh VREGCON(1) — RC1REG TX1REG SP1BRGL SP1BRGH RC1STA TX1STA 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh SSP1CON3 — — — — — — — 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh — CCPR2L CCPR2H CCP2CON — — — CCPTMRS 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh — — — — — — — — 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh IOCCP IOCCN IOCCF — — — — — 01Fh 020h — 09Fh 0A0h ADCON2 11Fh 120h — 19Fh 1A0h BAUD1CON 21Fh 220h — 29Fh 2A0h — 31Fh 320h — 39Fh 3A0h — General Purpose Register 80 Bytes 2013-2015 Microchip Technology Inc. 06Fh 070h 0EFh 0F0h Common RAM 70h – 7Fh 07Fh Note 16Fh 170h Accesses 70h – 7Fh 0FFh Legend: 1: 1EFh 1F0h Accesses 70h – 7Fh 17Fh = Unimplemented data memory locations, read as ‘0’. Unimplemented on PIC16LF1705. General Purpose Register 80 Bytes General Purpose Register 80 Bytes General Purpose Register 80 Bytes General Purpose Register 80 Bytes 26Fh 270h Accesses 70h – 7Fh 1FFh 36Fh 370h 2EFh 2F0h Accesses 70h – 7Fh 27Fh General Purpose Register 80 Bytes General Purpose Register 80 Bytes Accesses 70h – 7Fh 2FFh General Purpose Register 80 Bytes 3EFh 3F0h Accesses 70h – 7Fh 37Fh Accesses 70h – 7Fh 3FFh PIC16(L)F1705/9 DS40001729C-page 24 TABLE 3-3: 2013-2015 Microchip Technology Inc. TABLE 3-4: PIC16(L)F1709 MEMORY MAP (BANKS 0-7) BANK 0 000h BANK 1 080h Core Registers (Table 3-2) BANK 2 100h Core Registers (Table 3-2) BANK 3 180h Core Registers (Table 3-2) BANK 4 200h Core Registers (Table 3-2) BANK 5 280h Core Registers (Table 3-2) BANK 6 300h Core Registers (Table 3-2) BANK 7 380h Core Registers (Table 3-2) Core Registers (Table 3-2) 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h PORTA PORTB PORTC — — PIR1 PIR2 PIR3 — TMR0 TMR1L 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h TRISA TRISB TRISC — — PIE1 PIE2 PIE3 — OPTION_REG PCON 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h LATA LATB LATC — — CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h ANSELA ANSELB ANSELC — — PMADRL PMADRH PMDATL PMDATH PMCON1 PMCON2 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h WPUA WPUB WPUC — — SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON SSP1CON2 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h ODCONA ODCONB ODCONC — — CCPR1L CCPR1H CCP1CON — — — 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h SLRCONA SLRCONB SLRCONC — — — — — — — — 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h INLVLA INLVLB INLVLC — — IOCAP IOCAN IOCAF IOCBP IOCBN IOCBF 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh TMR1H T1CON T1GCON TMR2 PR2 T2CON — — 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh FVRCON DAC1CON0 DAC1CON1 — — ZCD1CON — — 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh VREGCON(1) — RC1REG TX1REG SP1BRGL SP1BRGH RC1STA TX1STA 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh SSP1CON3 — — — — — — — 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh — CCPR2L CCPR2H CCP2CON — — — CCPTMRS 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh — — — — — — — — 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh IOCCP IOCCN IOCCF — — — — — 01Fh 020h — 09Fh 0A0h ADCON2 11Fh 120h — 19Fh 1A0h BAUD1CON 21Fh 220h — 29Fh 2A0h — 31Fh 320h — 39Fh 3A0h — 06Fh 070h 0EFh 0F0h Common RAM 70h – 7Fh 07Fh 16Fh 170h Accesses 70h – 7Fh 0FFh Legend: DS40001729C-page 25 Note 1: General Purpose Register 80 Bytes General Purpose Register 80 Bytes 1EFh 1F0h Accesses 70h – 7Fh 17Fh = Unimplemented data memory locations, read as ‘0’. Unimplemented on PIC16LF1709. General Purpose Register 80 Bytes General Purpose Register 80 Bytes 26Fh 270h Accesses 70h – 7Fh 1FFh General Purpose Register 80 Bytes 27Fh 36Fh 370h 2EFh 2F0h Accesses 70h – 7Fh General Purpose Register 80 Bytes Accesses 70h – 7Fh 2FFh General Purpose Register 80 Bytes 3EFh 3F0h Accesses 70h – 7Fh 37Fh Accesses 70h – 7Fh 3FFh PIC16(L)F1705/9 General Purpose Register 80 Bytes PIC16(L)F1705/9 MEMORY MAP, BANK 8-23 BANK 8 400h BANK 9 480h Core Registers (Table 3-2) 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h — — — — — — — — — TMR4 PR4 T4CON — — — — TMR6 PR6 T6CON — Core Registers (Table 3-2) 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h General Purpose Register 80 Bytes 46Fh 470h — — — — — — — — — — — — — — — — — — — — Accesses 70h – 7Fh 2013-2015 Microchip Technology Inc. 80Bh 80Ch Unimplemented Read as ‘0’ 86Fh 870h 8EFh 8F0h Accesses 70h – 7Fh 87Fh Legend: Accesses 70h – 7Fh 97Fh = Unimplemented data memory locations, read as ‘0’. A7Fh 7FFh BANK 23 B80h Core Registers (Table 3-2) B0Bh B0Ch Unimplemented Read as ‘0’ Core Registers (Table 3-2) B8Bh B8Ch Unimplemented Read as ‘0’ Unimplemented Read as ‘0’ BEFh BF0h B6Fh B70h Accesses 70h – 7Fh AFFh Accesses 70h – 7Fh BANK 22 Core Registers (Table 3-2) Accesses 70h – 7Fh B7Fh — — — — — — — — — — — — — — — — — — — — Unimplemented Read as ‘0’ Accesses 70h – 7Fh B00h AEFh AF0h 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7EFh 7F0h 77Fh A8Bh A8Ch Core Registers (Table 3-2) Unimplemented Read as ‘0’ BANK 21 Accesses 70h – 7Fh — — — — — — — — — — — — — — — — — — — — 76Fh 770h A80h A6Fh A70h 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h Accesses 70h – 7Fh Unimplemented Read as ‘0’ Accesses 70h – 7Fh 9FFh 6EFh 6F0h Core Registers (Table 3-2) Unimplemented Read as ‘0’ — — — — — COG1PHR COG1PHF COG1BLKR COG1BLKF COG1DBR COG1DBF COG1CON0 COG1CON1 COG1RIS COG1RSIM COG1FIS COG1FSIM COG1ASD0 COG1ASD1 COG1STR BANK 15 780h Core Registers (Table 3-2) Unimplemented Read as ‘0’ BANK 20 A0Bh A0Ch 9EFh 9F0h 96Fh 970h Accesses 70h – 7Fh 8FFh 98Bh 98Ch 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h 6FFh A00h Core Registers (Table 3-2) Unimplemented Read as ‘0’ Unimplemented Read as ‘0 BANK 14 700h Core Registers (Table 3-2) Accesses 70h – 7Fh BANK 19 Core Registers (Table 3-2) Unimplemented Read as ‘0’ 64Fh 650h — — — — — — — — — — — PWM3DCL PWM3DCH PWM3CON PWM4DCL PWM4DCH PWM4CON — — — General Purpose Register 48 Bytes’ 67Fh 980h 90Bh 90Ch 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h Accesses 70h – 7Fh BANK 18 BANK 13 680h Core Registers (Table 3-2) 66Fh 670h 5FFh 900h Core Registers (Table 3-2) — — — — — — — — — — — — — — — — — — — — General Purpose Register 80 Bytes Accesses 70h – 7Fh BANK 17 88Bh 88Ch 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h 5EFh 5F0h 57Fh 880h Core Registers (Table 3-2) — — — — — OPA1CON — — — OPA2CON — — — — — — — — — — BANK 12 600h Core Registers (Table 3-2) General Purpose Register 80 Bytes Accesses 70h – 7Fh BANK 16 800h 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h 56Fh 570h 4FFh BANK 11 580h Core Registers (Table 3-2) General Purpose Register 80 Bytes 4EFh 4F0h 47Fh BANK 10 500h Accesses 70h – 7Fh BFFh PIC16(L)F1705/9 DS40001729C-page 26 TABLE 3-5: 2013-2015 Microchip Technology Inc. TABLE 3-6: PIC16(L)F1705/9 MEMORY MAP, BANK 24-31 BANK 24 C00h BANK 25 C80h Core Registers (Table 3-2) C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h — — — — — — — — — — — — — — — — — — — — Core Registers (Table 3-2) C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h Unimplemented Read as ‘0’ CFFh Core Registers (Table 3-2) D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h Unimplemented Read as ‘0’ CEFh CF0h Accesses 70h – 7Fh Legend: — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — D6Fh D70h D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h — — — — — — — — — — — — — — — — — — — — Accesses 70h – 7Fh D7Fh BANK 29 E80h Core Registers (Table 3-2) BANK 30 F00h Core Registers (Table 3-2) BANK 31 F80h Core Registers (Table 3-2) Core Registers (Table 3-2) E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h See Table 3-7 for E18h register mapping E19h details E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h See Table 3-7 for E98h register mapping E99h details E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h See Table 3-7 for F18h register mapping F19h details F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h See Table 3-8 for F98h register mapping F99h details F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h E6Fh E70h EEFh EF0h F6Fh F70h FEFh FF0h Unimplemented Read as ‘0’ DEFh DF0h = Unimplemented data memory locations, read as ‘0’. BANK 28 E00h Core Registers (Table 3-2) Unimplemented Read as ‘0’ Accesses 70h – 7Fh CFFh BANK 27 D80h Accesses 70h – 7Fh DFFh Accesses 70h – 7Fh E7Fh Accesses 70h – 7Fh EFFh Accesses 70h – 7Fh F7Fh Accesses 70h – 7Fh FFFh DS40001729C-page 27 PIC16(L)F1705/9 C6Fh C70h BANK 26 D00h PIC16(L)F1705/9 TABLE 3-7: PIC16(L)F1705/9 MEMORY MAP, BANK 28-30 Bank 28 E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h E21h E22h E23h E24h E25h E26h E27h E28h E29h E2Ah E2Bh E2Ch E2Dh E2Eh E2Fh E30h E31h E32h E33h E34h E35h E36h E37h E38h E39h E3Ah E3Bh E3Ch E3Dh E3Eh E3Fh E40h — — — PPSLOCK INTPPS T0CKIPPS T1CKIPPS T1GPPS CCP1PPS CCP2PPS — COGINPPS — — — — — — — — SSPCLKPPS SSPDATPPS SSPSSPPS — RXPPS CKPPS — — CLCIN0PPS CLCIN1PPS CLCIN2PPS CLCIN3PPS — — — — — — — — — — — — — — — — — — — — Bank 29 E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h EA1h EA2h EA3h EA4h EA5h EA6h EA7h EA8h EA9h EAAh EABh EACh EADh EAEh EAFh EB0h EB1h EB2h EB3h EB4h EB5h EB6h EB7h EB8h EB9h EBAh EBBh EBCh EBDh EBEh EBFh EC0h — E6Fh Legend: Note 1: DS40001729C-page 28 — — — — RA0PPS RA1PPS RA2PPS — RA4PPS RA5PPS — — — — — — RB4PPS(1) RB5PPS(1) RB6PPS(1) RB7PPS(1) RC0PPS RC1PPS RC2PPS RC3PPS RC4PPS RC5PPS RC6PPS(1) RC7PPS(1) — — — — — — — — — — — — — — — — — — — — — — — — Bank 30 F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h F21h F22h F23h F24h F25h F26h F27h F28h F29h F2Ah F2Bh F2Ch F2Dh F2Eh F2Fh F30h F31h F32h F33h F34h F35h F36h F37h F38h F39h F3Ah F3Bh F3Ch F3Dh F3Eh F3Fh F40h — — EEFh — — — CLCDATA CLC1CON CLC1POL CLC1SEL0 CLC1SEL1 CLC1SEL2 CLC1SEL3 CLC1GLS0 CLC1GLS1 CLC1GLS2 CLC1GLS3 CLC2CON CLC2POL CLC2SEL0 CLC2SEL1 CLC2SEL2 CLC2SEL3 CLC2GLS0 CLC2GLS1 CLC2GLS2 CLC2GLS3 CLC3CON CLC3POL CLC3SEL0 CLC3SEL1 CLC3SEL2 CLC3SEL3 CLC3GLS0 CLC3GLS1 CLC3GLS2 CLC3GLS3 — — — — — — — — — — — — — — — — — — F6Fh = Unimplemented data memory locations, read as ‘0’, Only available on PIC16(L)F1709 devices 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 3-8: PIC16(L)F1705/9 MEMORY MAP, BANK 31 Bank 31 F8Ch FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: Unimplemented Read as ‘0’ STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD — STKPTR TOSL TOSH = Unimplemented data memory locations, read as ‘0’, 2013-2015 Microchip Technology Inc. DS40001729C-page 29 PIC16(L)F1705/9 3.4.5 CORE FUNCTION REGISTERS SUMMARY The Core Function registers listed in Table 3-9 can be addressed from any Bank. TABLE 3-9: Addr CORE FUNCTION REGISTERS SUMMARY(1) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 0-31 x00h or INDF0 x80h Addressing this location uses contents of FSR0H/FSR0L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or INDF1 x81h Addressing this location uses contents of FSR1H/FSR1L to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or PCL x82h Program Counter (PC) Least Significant Byte 0000 0000 0000 0000 x03h or STATUS x83h — — — TO PD Z DC C ---1 1000 ---q quuu x04h or FSR0L x84h Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h or FSR0H x85h Indirect Data Memory Address 0 High Pointer 0000 0000 0000 0000 x06h or FSR1L x86h Indirect Data Memory Address 1 Low Pointer 0000 0000 uuuu uuuu x07h or FSR1H x87h Indirect Data Memory Address 1 High Pointer 0000 0000 0000 0000 x08h or BSR x88h x09h or WREG x89h — — x0Bh or INTCON x8Bh GIE Note 1: — BSR4 BSR3 BSR2 BSR1 BSR0 Working Register x0Ah or PCLATH x8Ah Legend: — 0000 0000 uuuu uuuu Write Buffer for the upper 7 bits of the Program Counter PEIE ---0 0000 ---0 0000 TMR0IE INTE IOCIE TMR0IF -000 0000 -000 0000 INTF IOCIF 0000 0000 0000 0000 x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. These registers can be addressed from any bank. DS40001729C-page 30 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets --uu uuuu Bank 0 00Ch PORTA 00Dh PORTB(3) 00Eh PORTC — — RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx RB7 RB6 RB5 RB4 — — — — xxxx ---- uuuu ---- RC7(3) RC6(3) RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu — 00Fh — Unimplemented — 010h — Unimplemented — — 011h PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 0000 0-00 0000 0-00 012h PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 000- 00-- 000- 00-- 013h PIR3 — — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF --00 -000 --00 -000 014h — Unimplemented 015h TMR0 — — Timer0 Module Register xxxx xxxx uuuu uuuu uuuu uuuu 016h TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx 017h TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 018h T1CON 0000 00-0 uuuu uu-u 019h T1GCON 0000 0x00 uuuu uxuu TMR1CS<1:0> TMR1GE T1GPOL T1CKPS<1:0> T1GTM T1GSPM T1OSCEN T1SYNC T1GGO/ DONE T1GVAL — TMR1ON T1GSS<1:0> 01Ah TMR2 Holding Register for the 8-bit TMR2 Register xxxx xxxx uuuu uuuu 01Bh PR2 TMR2 Period Register xxxx xxxx uuuu uuuu -000 0000 -000 0000 — — 01Ch T2CON 01Dh to — 01Fh — T2OUTPS<3:0> TMR2ON T2CKPS<1:0> Unimplemented Bank 1 — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 --11 1111 --11 1111 08Dh TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 1111 ---- 1111 ---- 08Eh TRISC TRISC7(3) TRISC6(3) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 08Ch TRISA (3) 1111 1111 1111 1111 08Fh — Unimplemented — — 090h — Unimplemented — — 091h PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 092h PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 000- 0000 000- 0000 093h PIE3 — — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE --00 -000 --00 -000 094h — 095h OPTION_REG WPUEN INTEDG TMR0CS TMR0SE 096h PCON STKOVF STKUNF — RWDT 097h WDTCON — — 098h OSCTUNE — — 099h OSCCON SPLLEN 09Ah OSCSTAT SOSCR Unimplemented PSA — 1111 1111 1111 1111 BOR 00-1 11qq qq-q qquu SWDTEN --01 0110 --01 0110 --00 0000 --00 0000 0011 1-00 0011 1-00 00q0 --00 qqqq --0q uuuu uuuu PS<2:0> RMCLR RI POR WDTPS<4:0> TUN<5:0> IRCF<3:0> PLLR — OSTS HFIOFR — HFIOFL MFIOFR SCS<1:0> LFIOFR HFIOFS 09Bh ADRESL ADC Result Register Low xxxx xxxx 09Ch ADRESH ADC Result Register High xxxx xxxx uuuu uuuu -000 0000 -000 0000 0000 -000 0000 -000 0000 ---- 0000 ---- 09Dh ADCON0 — 09Eh ADCON1 ADFM 09Fh ADCON2 Legend: Note 1: 2: 3: 4: CHS<4:0> ADCS<2:0> TRIGSEL<3:0> GO/DONE — ADNREF — — ADON ADREF<1:0> — — x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1705 only. PIC16(L)F1709 only. Unimplemented on PIC16LF1705/9. 2013-2015 Microchip Technology Inc. DS40001729C-page 31 PIC16(L)F1705/9 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 2 10Ch LATA 10Dh LATB(3) 10Eh LATC — — LATA5 LATA4 — LATA2 LATA1 LATA0 --xx -xxx --uu -uuu LATB7 LATB6 LATB5 LATB4 — — — — xxxx ---- uuuu ---- LATC7(3) LATC6(3) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 xxxx xxxx uuuu uuuu — 10Fh — Unimplemented — 110h — Unimplemented — — 111h CM1CON0 C1ON C1OUT 00-0 0100 00-0 0100 112h CM1CON1 C1INTP C1INTN 0000 0000 0000 0000 113h CM2CON0 C2ON C2OUT 00-0 0100 00-0 0100 114h CM2CON1 C2INTP C2INTN 0000 0000 0000 0000 115h CMOUT — — — — — — MC2OUT MC1OUT ---- --00 ---- --00 116h BORCON SBOREN BORFS — — — — — BORRDY 1x-- ---q uu-- ---u 117h FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> 118h DAC1CON0 DAC1EN --- DAC1OE1 DAC1OE2 DAC1PSS<1:0> 119h DAC1CON1 11Ah — Unimplemented 11Bh — Unimplemented — — 0-00 --00 0-00 --00 11Ch ZCD1CON — C1POL C1ZLF C1SP C2ZLF C2SP C1PCH<2:0> — C2POL C1HYS C1SYNC C1NCH<2:0> C2PCH<2:0> C2HYS C2SYNC C2NCH<2:0> ADFVR<1:0> --- DAC1NSS DAC1R<7:0> ZCD1EN — ZCD1OUT ZCD1POL — — ZCD1INTP ZCD1INTN 0q00 0000 0q00 0000 0-00 00-0 0-00 00-0 0000 0000 0000 0000 — — 11Dh — Unimplemented — — 11Eh — Unimplemented — — 11Fh — Unimplemented — — Bank 3 18Ch ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 ---1 1111 ---1 1111 18Dh ANSELB(3) — — ANSB5 ANSB4 — — — — --11 ---- --11 ---- ANSC7(3) ANSC6(3) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 18Eh ANSELC 1111 1111 1111 1111 18Fh — Unimplemented — — 190h — Unimplemented — — 191h PMADRL Program Memory Address Register Low Byte 0000 0000 0000 0000 192h PMADRH 1000 0000 1000 0000 193h PMDATL xxxx xxxx uuuu uuuu 194h PMDATH — — --xx xxxx --uu uuuu 195h PMCON1 — CFGS -000 x000 -000 q000 196h PMCON2 197h VREGCON(4) —(1) Program Memory Address Register High Byte Program Memory Read Data Register Low Byte Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR RD Program Memory Control Register 2 — — — 198h — Unimplemented 199h RC1REG USART Receive Data Register 19Ah TX1REG USART Transmit Data Register — — — VREGPM Reserved 0000 0000 0000 0000 ---- --01 ---- --01 — — 0000 0000 0000 0000 0000 0000 0000 0000 19Bh SP1BRGL BRG<7:0> 0000 0000 0000 0000 19Ch SP1BRGH BRG<15:8> 0000 0000 0000 0000 0000 0000 19Dh RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 19Eh TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 0000 0010 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 01-0 0-00 01-0 0-00 19Fh BAUD1CON Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1705 only. PIC16(L)F1709 only. Unimplemented on PIC16LF1705/9. DS40001729C-page 32 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets --11 1111 Bank 4 20Ch WPUA 20Dh WPUB(3) 20Eh WPUC — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 --11 1111 WPUB7 WPUB6 WPUB5 WPUB4 — — — — 1111 ---- 1111 ---- WPUC7(3) WPUC6(3) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 1111 1111 1111 1111 — 20Fh — Unimplemented — 210h — Unimplemented — — 211h SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 212h SSP1ADD 0000 0000 0000 0000 213h SSP1MSK 1111 1111 1111 1111 214h SSP1STAT SMP CKE D/A P 215h SSP1CON1 WCOL SSPOV SSPEN CKP 216h SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN 217h SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN 218h — — 21Fh ADD<7:0> MSK<7:0> S R/W UA BF 0000 0000 0000 0000 0000 0000 0000 0000 SEN 0000 0000 0000 0000 DHEN 0000 0000 0000 0000 — — SSPM<3:0> Unimplemented Bank 5 28Ch ODCONA 28Dh ODCONB(3) 28Eh ODCONC — — ODA5 ODA4 — ODA2 ODA1 ODA0 --00 -000 --00 -000 ODB7 ODB6 ODB5 ODB4 — — — — 0000 ---- 0000 ---- ODC7(3) ODC6(3) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 0000 0000 0000 0000 — 28Fh — Unimplemented — 290h — Unimplemented — — 291h CCPR1L Capture/Compare/PWM Register 1 (LSB) xxxx xxxx uuuu uuuu 292h CCPR1H Capture/Compare/PWM Register 1 (MSB) 293h CCP1CON — — DC1B<1:0> CCP1M<3:0> xxxx xxxx uuuu uuuu --00 0000 --00 0000 — — uuuu uuuu 294h — — 297h Unimplemented 298h CCPR2L Capture/Compare/PWM Register 2 (LSB) xxxx xxxx 299h CCPR2H Capture/Compare/PWM Register 2 (MSB) xxxx xxxx uuuu uuuu --00 0000 --00 0000 — — 0000 0000 0000 0000 — — --00 -000 29Ah CCP2CON 29Bh — — 29Dh — — DC2B<1:0> CCP2M<3:0> Unimplemented 29Eh CCPTMRS 29Fh — P4TSEL<1:0> P3TSEL<1:0> C2TSEL<1:0> C1TSEL<1:0> Unimplemented Bank 6 30Ch SLRCONA 30Dh SLRCONB(3) 30Eh SLRCONC 30Fh — — 31Fh Legend: Note 1: 2: 3: 4: — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 --00 -000 SLRB7 SLRB6 SLRB5 SLRB4 — — — — 0000 ---- 0000 ---- SLRC7(3) SLRC6(3) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 0000 0000 0000 0000 — — Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1705 only. PIC16(L)F1709 only. Unimplemented on PIC16LF1705/9. 2013-2015 Microchip Technology Inc. DS40001729C-page 33 PIC16(L)F1705/9 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 7 38Ch INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 --11 1111 --11 1111 INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 1111 ---- 1111 ---- 38Eh INLVLC INLVLC7(3) INLVLC6(3) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 1111 1111 1111 1111 38Fh — Unimplemented — — 390h — Unimplemented — — 391h IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 --00 0000 --00 0000 392h IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 --00 0000 --00 0000 393h IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 --00 0000 --00 0000 394h IOCBP(3) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 0000 ---- 0000 ---- 395h IOCBN(3) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 0000 ---- 0000 ---- 396h IOCBF(3) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 0000 ---- 0000 ---- 397h IOCCP IOCCP7(3) IOCCP6(3) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0000 0000 0000 0000 398h IOCCN IOCCN7(3) IOCCN6(3) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0000 0000 0000 0000 IOCCF IOCCF7(3) IOCCF6(3) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0000 0000 0000 0000 Unimplemented — — Unimplemented — — uuuu uuuu 38Dh INLVLB(3) 399h 39Ah — — 39Fh Bank 8 40Ch — — 414h 415h TMR4 Holding Register for the 8-bit TMR4 Register xxxx xxxx 416h PR4 TMR4 Period Register xxxx xxxx uuuu uuuu 417h T4CON -000 0000 -000 0000 — — uuuu uuuu — T4OUTPS<3:0> TMR4ON T4CKPS<1:0> 418h — — 41Bh Unimplemented 41Ch TMR6 Holding Register for the 8-bit TMR6 Register xxxx xxxx 41Dh PR6 TMR6 Period Register xxxx xxxx uuuu uuuu -000 0000 -000 0000 Unimplemented — — Unimplemented — — Unimplemented — — 00-0 --00 00-0 --00 — — 00-0 --00 00-0 --00 — — 41Eh T6CON 41Fh — — T6OUTPS<3:0> TMR6ON T6CKPS<1:0> Bank 9 48Ch to — 49Fh Bank 10 50Ch — — 510h 511h OPA1CON 512h — 514h — 515h OPA2CON 516h — — 51Fh Legend: Note 1: 2: 3: 4: OPA1EN OPA1SP — OPA1UG — — OPA1PCH<1:0> Unimplemented OPA2EN OPA2SP — OPA2UG — — OPA2PCH<1:0> Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1705 only. PIC16(L)F1709 only. Unimplemented on PIC16LF1705/9. DS40001729C-page 34 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on POR, BOR Value on all other Resets Unimplemented — — Unimplemented — — xx-- ---- uu-- ---- xxxx xxxx uuuu uuuu Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bank 11 D8Ch to — DADh Bank 12 60Ch to — 616h 617h PWM3DCL 618h PWM3DCH 619h PWM3CON 61Ah PWM4DCL PWMxDCL<1:0> — 61Dh — — 61Fh — — — — PWMxDCH<9:2> PWM3EN — — — — — 0-x0 ---- u-uu ---- — — — — 00-- ---- uu-- ---- 0000 0000 uuuu uuuu 0-x0 ---- u-uu ---- Unimplemented — — Unimplemented — — PWMxDCL<1:0> PWM3OUT PWM3POL — 61Bh PWM4DCH 61Ch PWM4CON — — PWMxDCH<9:2> PWM4EN — PWM4OUT PWM4POL — — — — Bank 13 68Ch to — 690h 691h COG1PHR — — COG Rising Edge Phase Delay Count Register --xx xxxx --uu uuuu 692h COG1PHF — — COG Falling Edge Phase Delay Count Register --xx xxxx --uu uuuu 693h COG1BLKR — — COG Rising Edge Blanking Count Register --xx xxxx --uu uuuu 694h COG1BLKF — — COG Falling Edge Blanking Count Register --xx xxxx --uu uuuu 695h COG1DBR — — COG Rising Edge Dead-band Count Register --xx xxxx --uu uuuu 696h COG1DBF — — COG Falling Edge Dead-band Count Register --xx xxxx --uu uuuu 697h COG1CON0 G1EN G1LD — 00-0 0000 00-0 0000 698h COG1CON1 G1RDBS G1FDBS — — G1POLD G1POLC G1POLB G1POLA 00-- 0000 00-- 0000 — G1RIS6 G1RIS5 G1RIS4 G1RIS3 G1RIS2 G1RIS1 G1RIS0 -000 0000 -000 0000 69Ah COG1RSIM — G1RSIM6 G1RSIM5 G1RSIM4 G1RSIM3 G1RSIM2 G1RSIM1 G1RSIM0 -000 0000 -000 0000 69Bh COG1FIS — -000 0000 -000 0000 699h COG1RIS G1FIS5 G1FIS4 G1FIS3 G1FIS2 G1FIS1 G1FIS0 G1FSIM5 G1FSIM4 G1FSIM3 G1FSIM2 G1FSIM1 G1FSIM0 -000 0000 -000 0000 — — 0001 01-- 0001 01-- G1AS1E G1AS0E ---- 0000 ---- 0000 G1STRA 0000 0001 0000 0001 — — — G1FSIM6 69Dh COG1ASD0 G1ASE G1ARSEN 69Eh COG1ASD1 — — G1SDATD G1MD<2:0> G1FIS6 69Ch COG1FSIM 69Fh COG1STR G1CS<1:0> G1SDATC G1ASDBD<1:0> — G1SDATB — G1SDATA G1ASDAC<1:0> G1AS3E G1STRD G1AS2E G1STRC G1STRB Bank 14-27 x0Ch/ — x8Ch — x1Fh/ x9Fh Legend: Note 1: 2: 3: 4: Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1705 only. PIC16(L)F1709 only. Unimplemented on PIC16LF1705/9. 2013-2015 Microchip Technology Inc. DS40001729C-page 35 PIC16(L)F1705/9 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — ---- ---0 ---- ---0 Bank 28 E0Ch — — E0Eh Unimplemented E0Fh PPSLOCK — — — E10h INTPPS — — — INTPPS<4:0> ---0 0010 ---u uuuu E11h T0CKIPPS — — — T0CKIPPS<4:0> ---0 0010 ---u uuuu E12h T1CKIPPS — — — T1CKIPPS<4:0> ---0 0101 ---u uuuu E13h T1GPPS — — — T1GPPS<4:0> ---0 0100 ---u uuuu E14h CCP1PPS — — — CCP1PPS<4:0> ---1 0101 ---u uuuu E15h CCP2PPS — — — CCP2PPS<4:0> ---1 0011 ---u uuuu — — — — PPSLOCKED Unimplemented E16h — E17h COGINPPS E18h — — E1Fh — — — COGINPPS<4:0> Unimplemented E20h SSPCLKPPS E21h SSPDATPPS E22h SSPSSPPS E23h — E25h CKPPS — ---0 0010 ---u uuuu — — — — — SSPCLKPPS<4:0> ---1 0000(3) ---u uuuu — — — SSPCLKPPS<4:0> ---0 1110(4) ---u uuuu — — — SSPDATPPS<4:0> ---1 0001(3) ---u uuuu — — — SSPDATPPS<4:0> ---0 1100(4) ---u uuuu — — — SSPSSPPS<4:0> ---1 0011(3) ---u uuuu — — — SSPSSPPS<4:0> ---1 0110(4) ---u uuuu — — — RXPPS<4:0> ---1 0101(3) ---u uuuu — — — RXPPS<4:0> ---0 1101(4) ---u uuuu — — — CKPPS<4:0> ---1 0100(3) ---u uuuu — — — CKPPS<4:0> ---0 1111(4) ---u uuuu Unimplemented E24h RXPPS — E26h — Unimplemented E27h — Unimplemented — — — — — — E28h CLCIN0PPS — — — CLCIN0PPS<4:0> ---1 0011 ---u uuuu E29h CLCIN1PPS — — — CLCIN1PPS<4:0> ---1 0100 ---u uuuu E2Ah CLCIN2PPS — — — CLCIN2PPS<4:0> ---1 0001 ---u uuuu E2Bh CLCIN3PPS — — — CLCIN3PPS<4:0> ---0 0101 ---u uuuu — — E2Ch to — E7Fh Legend: Note 1: 2: 3: 4: Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1705 only. PIC16(L)F1709 only. Unimplemented on PIC16LF1705/9. DS40001729C-page 36 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets Bank 29 E8Ch — E8Fh — — — E90h RA0PPS Unimplemented — — — RA0PPS<4:0> ---0 0000 ---u uuuu E91h RA1PPS — — — RA1PPS<4:0> ---0 0000 ---u uuuu E92h RA2PPS — — — RA2PPS<4:0> ---0 0000 ---u uuuu E93h — Unimplemented E94h RA4PPS E95h RA5PPS — — — — — RA4PPS<4:0> ---0 0000 ---u uuuu — — — RA5PPS<4:0> ---0 0000 ---u uuuu E96h — Unimplemented — — E97h — Unimplemented — — E98h — Unimplemented — — E99h — Unimplemented — — E9Ah — Unimplemented — — E9Bh — Unimplemented — — (3) E9Ch RB4PPS — — — RB4PPS<4:0> ---0 0000 ---u uuuu E9Dh RB5PPS(3) — — — RB5PPS<4:0> ---0 0000 ---u uuuu (3) E9Eh RB6PPS — — — RB6PPS<4:0> ---0 0000 ---u uuuu E9Fh RB7PPS(3) — — — RB7PPS<4:0> ---0 0000 ---u uuuu EA0h RC0PPS — — — RC0PPS<4:0> ---0 0000 ---u uuuu EA1h RC1PPS — — — RC1PPS<4:0> ---0 0000 ---u uuuu EA2h RC2PPS — — — RC2PPS<4:0> ---0 0000 ---u uuuu EA3h RC3PPS — — — RC3PPS<4:0> ---0 0000 ---u uuuu EA4h RC4PPS — — — RC4PPS<4:0> ---0 0000 ---u uuuu EA5h RC5PPS — — — RC5PPS<4:0> ---0 0000 ---u uuuu EA6h RC6PPS(3) — — — RC6PPS<4:0> ---0 0000 ---u uuuu EA7h — — — RC7PPS<4:0> ---0 0000 ---u uuuu — — RC7PPS(3) EA8h — EEFh — Legend: Note 1: 2: 3: 4: Unimplemented x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1705 only. PIC16(L)F1709 only. Unimplemented on PIC16LF1705/9. 2013-2015 Microchip Technology Inc. DS40001729C-page 37 PIC16(L)F1705/9 TABLE 3-10: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Value on all other Resets Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR — — — — — — — MLC3OUT MLC2OUT MLC1OUT ---- -000 ---- -000 F10h CLC1CON LC1EN — LC1OUT LC1INTP 0-x0 0000 0-00 0000 F11h LC1POL — — — LC1G1POL x--- xxxx 0--- uuuu F12h CLC1SEL0 — — — LC1D1S<4:0> ---x xxxx ---u uuuu F13h CLC1SEL1 — — — LC1D2S<4:0> ---x xxxx ---u uuuu F14h CLC1SEL2 — — — LC1D3S<4:0> ---x xxxx ---u uuuu F15h CLC1SEL3 — — — LC1D4S<4:0> ---x xxxx ---u uuuu Addr Name Bit 7 Bank 30 F0Ch — F0Eh — Unimplemented F0Fh CLCDATA CLC1POL LC1INTN LC1MODE<2:0> LC1G4POL LC1G3POL LC1G2POL F16h CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N xxxx xxxx uuuu uuuu F17h CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N xxxx xxxx uuuu uuuu F18h CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N xxxx xxxx uuuu uuuu F19h CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N xxxx xxxx uuuu uuuu F1Ah CLC2CON LC2EN — LC2OUT LC2INTP F1Bh CLC2POL LC2POL — — — F1Ch CLC2SEL0 — — — F1Dh CLC2SEL1 — — — F1Eh CLC2SEL2 — — F1Fh CLC2SEL3 — — LC2INTN LC2MODE<2:0> 0-00 0000 0-00 0000 0--- xxxx 0--- uuuu LC2D1S<4:0> ---x xxxx ---u uuuu LC2D2S<4:0> ---x xxxx ---u uuuu — LC2D3S<4:0> ---x xxxx ---u uuuu — LC2D4S<4:0> ---x xxxx ---u uuuu LC2G4POL LC2G3POL LC2G2POL LC2G1POL F20h CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N xxxx xxxx uuuu uuuu F21h CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N xxxx xxxx uuuu uuuu F22h CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N xxxx xxxx uuuu uuuu F23h CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N xxxx xxxx uuuu uuuu F24h CLC3CON LC3EN — LC3OUT LC3INTP F25h CLC3POL LC3POL — — — F26h CLC3SEL0 — — — F27h CLC3SEL1 — — — F28h CLC3SEL2 — — F29h CLC3SEL3 — — LC3INTN LC3MODE<2:0> 0-00 0000 0-00 0000 0--- xxxx 0--- uuuu LC3D1S<4:0> ---x xxxx ---u uuuu LC3D2S<4:0> ---x xxxx ---u uuuu — LC3D3S<4:0> ---x xxxx ---u uuuu — LC3D4S<4:0> ---x xxxx ---u uuuu LC3G4POL LC3G3POL LC3G2POL LC3G1POL F2Ah CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N xxxx xxxx uuuu uuuu F2Bh CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N xxxx xxxx uuuu uuuu F2Ch CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N xxxx xxxx uuuu uuuu F2Dh CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N xxxx xxxx uuuu uuuu F2Eh — — F6Fh Unimplemented — — Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1705 only. PIC16(L)F1709 only. Unimplemented on PIC16LF1705/9. DS40001729C-page 38 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 3-10: Addr Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other Resets — — ---- -xxx ---- -uuu xxxx xxxx uuuu uuuu ---x xxxx ---u uuuu -xxx xxxx uuuu uuuu Bank 31 F8Ch to — FE3h Unimplemented FE4h STATUS_ SHAD FE5h WREG_ SHAD — — — — — Z DC Working Register Shadow FE6h BSR_SHAD — FE7h PCLATH_ SHAD — — — Bank Select Register Shadow Program Counter Latch High Register Shadow C FE8h FSR0L_ SHAD Indirect Data Memory Address 0 Low Pointer Shadow xxxx xxxx uuuu uuuu FE9h FSR0H_ SHAD Indirect Data Memory Address 0 High Pointer Shadow xxxx xxxx uuuu uuuu FEAh FSR1L_ SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu FEBh FSR1H_ SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu FECh — Unimplemented FEDh STKPTR FEEh TOSL FEFh TOSH Legend: Note 1: 2: 3: 4: — — — Current Stack Pointer Top of Stack Low byte — Top of Stack High byte — — ---1 1111 ---1 1111 xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved. Shaded locations are unimplemented, read as ‘0’. Unimplemented, read as ‘1’. PIC16(L)F1705 only. PIC16(L)F1709 only. Unimplemented on PIC16LF1705/9. 2013-2015 Microchip Technology Inc. DS40001729C-page 39 PIC16(L)F1705/9 3.5 3.5.3 PCL and PCLATH COMPUTED FUNCTION CALLS The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 3-3 shows the five situations for the loading of the PC. A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). FIGURE 3-3: If using the CALL instruction, the PCH<2:0> and PCL registers are loaded with the operand of the CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>. PC LOADING OF PC IN DIFFERENT SITUATIONS 14 PCH 6 7 14 PCH PCL 0 PCLATH PC 8 ALU Result PCL 0 4 0 11 OPCODE <10:0> PC 14 PCH PCL 0 CALLW 6 PCLATH PC Instruction with PCL as Destination GOTO, CALL 6 PCLATH 0 14 7 0 PCH 8 W PCL 0 BRW PC + W 14 PCH 3.5.4 BRANCHING The branching instructions add an offset to the PC. This allows relocatable code and code that crosses page boundaries. There are two forms of branching, BRW and BRA. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed. If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will be loaded with the address PC + 1 + W. If using BRA, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the BRA instruction. 15 PC The CALLW instruction enables computed calls by combining PCLATH and W to form the destination address. A computed CALLW is accomplished by loading the W register with the desired address and executing CALLW. The PCL register is loaded with the value of W and PCH is loaded with PCLATH. PCL 0 BRA 15 PC + OPCODE <8:0> 3.5.1 MODIFYING PCL Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 3.5.2 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to Application Note AN556, “Implementing a Table Read” (DS00556). DS40001729C-page 40 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 3.6 3.6.1 Stack The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to TOSH:TOSL. STKPTR is five bits to allow detection of overflow and underflow. All devices have a 16-level x 15-bit wide hardware stack (refer to Figure 3-1). The stack space is not part of either program or data space. The PC is PUSHed onto the stack when CALL or CALLW instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer if the STVREN bit is programmed to ‘0‘ (Configuration Words). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled. Note: Note: Care should be taken when modifying the STKPTR while interrupts are enabled. During normal program operation, CALL, CALLW and Interrupts will increment STKPTR while RETLW, RETURN, and RETFIE will decrement STKPTR. At any time, STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a CALL or CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the STKPTR. There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, CALLW, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK Reference Figure 3-4 through Figure 3-7 for examples of accessing the stack. ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL 0x0F STKPTR = 0x1F Stack Reset Disabled (STVREN = 0) 0x0E 0x0D 0x0C 0x0B 0x0A Initial Stack Configuration: 0x09 After Reset, the stack is empty. The empty stack is initialized so the Stack Pointer is pointing at 0x1F. If the Stack Overflow/Underflow Reset is enabled, the TOSH/TOSL registers will return ‘0’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F. 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 TOSH:TOSL 2013-2015 Microchip Technology Inc. 0x1F 0x0000 STKPTR = 0x1F Stack Reset Enabled (STVREN = 1) DS40001729C-page 41 PIC16(L)F1705/9 FIGURE 3-5: ACCESSING THE STACK EXAMPLE 2 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 This figure shows the stack configuration after the first CALL or a single interrupt. If a RETURN instruction is executed, the return address will be placed in the Program Counter and the Stack Pointer decremented to the empty state (0x1F). 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 TOSH:TOSL FIGURE 3-6: 0x00 Return Address STKPTR = 0x00 ACCESSING THE STACK EXAMPLE 3 0x0F 0x0E 0x0D 0x0C After seven CALLs or six CALLs and an interrupt, the stack looks like the figure on the left. A series of RETURN instructions will repeatedly place the return addresses into the Program Counter and pop the stack. 0x0B 0x0A 0x09 0x08 0x07 TOSH:TOSL DS40001729C-page 42 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address STKPTR = 0x06 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 3-7: ACCESSING THE STACK EXAMPLE 4 TOSH:TOSL 3.6.2 0x0F Return Address 0x0E Return Address 0x0D Return Address 0x0C Return Address 0x0B Return Address 0x0A Return Address 0x09 Return Address 0x08 Return Address 0x07 Return Address 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address When the stack is full, the next CALL or an interrupt will set the Stack Pointer to 0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack Overflow/Underflow Reset is enabled, a Reset will occur and location 0x00 will not be overwritten. STKPTR = 0x10 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.7 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory 2013-2015 Microchip Technology Inc. DS40001729C-page 43 PIC16(L)F1705/9 FIGURE 3-8: INDIRECT ADDRESSING 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x1000 0x1FFF 0x0FFF Reserved 0x2000 Linear Data Memory 0x29AF 0x29B0 FSR Address Range 0x7FFF 0x8000 Reserved 0x0000 Program Flash Memory 0xFFFF Note: 0x7FFF Not all memory regions are completely implemented. Consult device memory tables for memory limits. DS40001729C-page 44 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 3.7.1 TRADITIONAL DATA MEMORY The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers. FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing 4 BSR 0 6 Indirect Addressing From Opcode 0 7 0 Bank Select Location Select FSRxH 0 0 0 7 FSRxL 0 0 Bank Select 00000 00001 00010 11111 Bank 0 Bank 1 Bank 2 Bank 31 Location Select 0x00 0x7F 2013-2015 Microchip Technology Inc. DS40001729C-page 45 PIC16(L)F1705/9 3.7.2 3.7.3 LINEAR DATA MEMORY The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the banks. Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank. The 16 bytes of common memory are not included in the linear data memory region. FIGURE 3-10: 7 FSRnH 0 0 1 LINEAR DATA MEMORY MAP 0 7 FSRnL 0 PROGRAM FLASH MEMORY To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower eight bits of each memory location is accessible via INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the FSR/INDF interface will require one additional instruction cycle to complete. FIGURE 3-11: 7 1 FSRnH PROGRAM FLASH MEMORY MAP 0 Location Select Location Select 0x2000 7 FSRnL 0x8000 0 0x0000 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Program Flash Memory (low 8 bits) Bank 2 0x16F 0xF20 Bank 30 0x29AF DS40001729C-page 46 0xF6F 0xFFFF 0x7FFF 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 4.0 DEVICE CONFIGURATION Device configuration consists of Configuration Words, Code Protection and Device ID. 4.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h. Note: The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. 2013-2015 Microchip Technology Inc. DS40001729C-page 47 PIC16(L)F1705/9 4.2 Register Definitions: Configuration Words REGISTER 4-1: CONFIG1: CONFIGURATION WORD 1 R/P-1 R/P-1 R/P-1 FCMEN IESO CLKOUTEN R/P-1 R/P-1 U-1 BOREN<1:0> — bit 13 R/P-1 (1) CP R/P-1 R/P-1 MCLRE PWRTE bit 8 R/P-1 R/P-1 R/P-1 WDTE<1:0> R/P-1 R/P-1 FOSC<2:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor and internal/external switchover are both enabled. 0 = Fail-Safe Clock Monitor is disabled bit 12 IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled bit 11 CLKOUTEN: Clock Out Enable bit If FOSC Configuration bits are set to LP, XT, HS modes: This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin. All other FOSC modes: 1 = CLKOUT function is disabled. I/O function on the CLKOUT pin. 0 = CLKOUT function is enabled on the CLKOUT pin bit 10-9 BOREN<1:0>: Brown-out Reset Enable bits 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the BORCON register 00 = BOR disabled bit 8 Unimplemented: Read as ‘1’ bit 7 CP: Code Protection bit(1) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled bit 6 MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUA3 bit. bit 5 PWRTE: Power-up Timer Enable bit 1 = PWRT disabled 0 = PWRT enabled bit 4-3 WDTE<1:0>: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled DS40001729C-page 48 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 4-1: bit 2-0 Note 1: CONFIG1: CONFIGURATION WORD 1 (CONTINUED) FOSC<2:0>: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode (4-20 MHz): device clock supplied to CLKIN pin 110 = ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin 101 = ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin 100 = INTOSC oscillator: I/O function on CLKIN pin 011 = EXTRC oscillator: External RC circuit connected to CLKIN pin 010 = HS oscillator: High-speed crystal/resonator connected between OSC1 and OSC2 pins 001 = XT oscillator: Crystal/resonator connected between OSC1 and OSC2 pins 000 = LP oscillator: Low-power crystal connected between OSC1 and OSC2 pins The entire Flash program memory will be erased when the code protection is turned off during an erase. When a Bulk Erase Program Memory Command is executed, the entire program Flash memory and configuration memory will be erased. 2013-2015 Microchip Technology Inc. DS40001729C-page 49 PIC16(L)F1705/9 REGISTER 4-2: CONFIG2: CONFIGURATION WORD 2 R/P-1 LVP (1) R/P-1 DEBUG R/P-1 (2) LPBOR R/P-1 (3) BORV R/P-1 R/P-1 STVREN PLLEN bit 13 bit 8 R/P-1 U-1 U-1 U-1 U-1 R/P-1 ZCDDIS — — — — PPS1WAY R/P-1 R/P-1 WRT<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘1’ ‘0’ = Bit is cleared ‘1’ = Bit is set -n = Value when blank or after Bulk Erase bit 13 LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = High-voltage on MCLR must be used for programming bit 12 DEBUG: In-Circuit Debugger Mode bit(2) 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger bit 11 LPBOR: Low-Power BOR Enable bit 1 = Low-Power Brown-out Reset is disabled 0 = Low-Power Brown-out Reset is enabled bit 10 BORV: Brown-out Reset Voltage Selection bit(3) 1 = Brown-out Reset voltage (VBOR), low trip point selected 0 = Brown-out Reset voltage (VBOR), high trip point selected bit 9 STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack Overflow or Underflow will cause a Reset 0 = Stack Overflow or Underflow will not cause a Reset bit 8 PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled bit 7 ZCDDIS: ZCD Disable bit 1 = ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON 0 = ZCD always enabled bit 6-3 Unimplemented: Read as ‘1’ bit 2 PPS1WAY: PPSLOCK Bit One-Way Set Enable bit 1 = The PPSLOCK bit can only be set once after an unlocking sequence is executed; once PPSLOCK is set, all future changes to PPS registers are prevented 0 = The PPSLOCK bit can be set and cleared as needed (provided an unlocking sequence is executed) bit 1-0 WRT<1:0>: Flash Memory Self-Write Protection bits 8 kW Flash memory 11 = Write prot0ection off 10 = 0000h to 1FFh write protected, 0200h to 1FFFh may be modified by PMCON control 01 = 0000h to 0FFFh write protected, 1000h to 1FFFh may be modified by PMCON control 00 = 0000h to 1FFFh write protected, no addresses may be modified by PMCON control Note 1: 2: 3: The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. The DEBUG bit in Configuration Words is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. See VBOR parameter for specific trip point voltages. DS40001729C-page 50 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 4.3 Code Protection Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting. 4.3.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in Configuration Words. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See Section 4.4 “Write Protection” for more information. 4.4 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. The WRT<1:0> bits in Configuration Words define the size of the program memory block that is protected. 4.5 User ID Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. For more information on checksum calculation, see the “PIC16(L)F170X Memory Programming Specification” (DS41683). 2013-2015 Microchip Technology Inc. DS40001729C-page 51 PIC16(L)F1705/9 4.6 Device ID and Revision ID The 14-bit device ID word is located at 8006h and the 14-bit revision ID is located at 8005h. These locations are read-only and cannot be erased or modified. See Section 10.4 “User ID, Device ID and Configuration Word Access” for more information on accessing these memory locations. Development tools, such as device programmers and debuggers, may be used to read the Device ID and Revision ID. 4.7 Register Definitions: Device and Revision REGISTER 4-3: DEVID: DEVICE ID REGISTER R R R R R R DEV<13:8> bit 13 R R bit 8 R R R R R R DEV<7:0> bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 ‘0’ = Bit is cleared DEV<13:0>: Device ID bits Device DEVID<13:0> Values PIC16F1705 11 0000 0101 0101 (3055h) PIC16LF1705 11 0000 0101 0111 (3057h) PIC16F1709 11 0000 0101 0100 (3054h) PIC16LF1709 11 0000 0101 0110 (3056h) REGISTER 4-4: REVID: REVISION ID REGISTER R R R R R R REV<13:8> bit 13 R R bit 8 R R R R R R REV<7:0> bit 7 bit 0 Legend: R = Readable bit ‘1’ = Bit is set bit 13-0 ‘0’ = Bit is cleared REV<13:0>: Revision ID bits DS40001729C-page 52 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 5.0 A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 5-1. RESETS There are multiple ways to reset this device: • • • • • • • • • Power-On Reset (POR) Brown-Out Reset (BOR) Low-Power Brown-Out Reset (LPBOR) MCLR Reset WDT Reset RESET instruction Stack Overflow Stack Underflow Programming mode exit To allow VDD to stabilize, an optional Power-up Timer can be enabled to extend the Reset time after a BOR or POR event. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Rev. 10-000006A 8/14/2013 ICSP™ Programming Mode Exit RESET Instruction Stack Underflow Stack Overlfow MCLRE VPP/MCLR Sleep WDT Time-out Device Reset Power-on Reset VDD BOR Active(1) Brown-out Reset LPBOR Reset Note 1: R LFINTOSC Power-up Timer PWRTE See Table 5-1 for BOR active conditions. 2013-2015 Microchip Technology Inc. DS40001729C-page 53 PIC16(L)F1705/9 5.1 Power-On Reset (POR) 5.2 Brown-Out Reset (BOR) The POR circuit holds the device in Reset until VDD has reached an acceptable level for minimum operation. Slow rising VDD, fast operating speeds or analog performance may require greater than minimum VDD. The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met. The BOR circuit holds the device in Reset when VDD reaches a selectable minimum level. Between the POR and BOR, complete voltage range coverage for execution protection can be implemented. 5.1.1 • • • • POWER-UP TIMER (PWRT) The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset. The device is held in Reset as long as PWRT is active. The PWRT delay allows additional time for the VDD to rise to an acceptable level. The Power-up timer is enabled by clearing the PWRTE bit in Configuration Words. The Power-up Timer starts after the release of the POR and BOR. For additional information, refer to Application Note AN607, “Power-up Trouble Shooting” (DS00607). TABLE 5-1: The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Words. The four operating modes are: BOR is always on BOR is off when in Sleep BOR is controlled by software BOR is always off Refer to Table 5-1 for more information. The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Words. A VDD noise rejection filter prevents the BOR from triggering on small events. If VDD falls below VBOR for a duration greater than parameter TBORDC, the device will reset. See Figure 5-2 for more information. BOR OPERATING MODES BOREN<1:0> SBOREN Device Mode BOR Mode 11 X X Active Awake Active 10 X Sleep Disabled 1 X Active 0 X Disabled X X Disabled 01 00 Instruction Execution upon: Release of POR or Wake-up from Sleep Waits for BOR ready(1) (BORRDY = 1) Waits for BOR ready (BORRDY = 1) Waits for BOR ready(1) (BORRDY = 1) Begins immediately (BORRDY = x) Note 1: In these specific cases, “Release of POR” and “Wake-up from Sleep”, there is no delay in start-up. The BOR ready flag, (BORRDY = 1), will be set before the CPU is ready to execute instructions because the BOR circuit is forced on by the BOREN<1:0> bits. 5.2.1 BOR IS ALWAYS ON When the BOREN bits of Configuration Words are programmed to ‘11’, the BOR is always on. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep. 5.2.2 BOR IS OFF IN SLEEP When the BOREN bits of Configuration Words are programmed to ‘10’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and VDD is higher than the BOR threshold. 5.2.3 BOR CONTROLLED BY SOFTWARE When the BOREN bits of Configuration Words are programmed to ‘01’, the BOR is controlled by the SBOREN bit of the BORCON register. The device start-up is not delayed by the BOR ready condition or the VDD level. BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the BORRDY bit of the BORCON register. BOR protection is unchanged by Sleep. BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready. DS40001729C-page 54 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 5-2: BROWN-OUT SITUATIONS VDD VBOR Internal Reset TPWRT(1) VDD VBOR Internal Reset < TPWRT TPWRT(1) VDD VBOR Internal Reset Note 1: 5.3 TPWRT(1) TPWRT delay only if PWRTE bit is programmed to ‘0’. Register Definitions: BOR Control REGISTER 5-1: BORCON: BROWN-OUT RESET CONTROL REGISTER R/W-1/u R/W-0/u U-0 U-0 U-0 U-0 U-0 R-q/u SBOREN BORFS(1) — — — — — BORRDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 SBOREN: Software Brown-out Reset Enable bit If BOREN <1:0> in Configuration Words 01: SBOREN is read/write, but has no effect on the BOR. If BOREN <1:0> in Configuration Words = 01: 1 = BOR Enabled 0 = BOR Disabled bit 6 BORFS: Brown-out Reset Fast Start bit(1) If BOREN<1:0> = 11 (Always on) or BOREN<1:0> = 00 (Always off) BORFS is Read/Write, but has no effect. If BOREN <1:0> = 10 (Disabled in Sleep) or BOREN<1:0> = 01 (Under software control): 1 = Band gap is forced on always (covers sleep/wake-up/operating cases) 0 = Band gap operates normally, and may turn off bit 5-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive Note 1: BOREN<1:0> bits are located in Configuration Words. 2013-2015 Microchip Technology Inc. DS40001729C-page 55 PIC16(L)F1705/9 5.4 Low-Power Brown-Out Reset (LPBOR) The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to Figure 5-1 to see how the BOR interacts with other modules. The LPBOR is used to monitor the external VDD pin. When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred. The same bit is set for both the BOR and the LPBOR. Refer to Register 5-2. 5.4.1 ENABLING LPBOR The LPBOR is controlled by the LPBOR bit of Configuration Words. When the device is erased, the LPBOR module defaults to disabled. 5.4.1.1 LPBOR Module Output The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is OR’d together with the Reset signal of the BOR module to provide the generic BOR signal, which goes to the PCON register and to the power control block. 5.5 MCLR 5.6 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. See Section 9.0 “Watchdog Timer (WDT)” for more information. 5.7 RESET Instruction A RESET instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘0’. See Table 5-4 for default conditions after a RESET instruction has occurred. 5.8 Stack Overflow/Underflow Reset The device can reset when the Stack Overflows or Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Words. See Section 3.6.2 “Overflow/Underflow Reset” for more information. 5.9 Programming Mode Exit Upon exit of Programming mode, the device will behave as if a POR had just occurred. The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the MCLRE bit of Configuration Words and the LVP bit of Configuration Words (Table 5-2). 5.10 TABLE 5-2: The Power-up Timer is controlled by the PWRTE bit of Configuration Words. MCLR CONFIGURATION MCLRE LVP MCLR 0 0 Disabled 1 0 Enabled x 1 Enabled 5.5.1 MCLR ENABLED When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to VDD through an internal weak pull-up. The device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. Note: 5.5.2 A Reset does not drive the MCLR pin low. MCLR DISABLED When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See Section 11.1 “PORTA Registers” for more information. DS40001729C-page 56 Power-Up Timer The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. 5.11 Start-up Sequence Upon the release of a POR or BOR, the following must occur before the device will begin executing: 1. 2. 3. Power-up Timer runs to completion (if enabled). Oscillator start-up timer runs to completion (if required for oscillator source). MCLR must be released (if enabled). The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for more information. The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution after 10 FOSC cycles (see Figure 5-3). This is useful for testing purposes or to synchronize more than one device operating in parallel. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 5-3: RESET START-UP SEQUENCE VDD Internal POR TPWRT Power-up Timer MCLR TMCLR Internal RESET Oscillator Modes External Crystal TOST Oscillator Start-up Timer Oscillator FOSC Internal Oscillator Oscillator FOSC External Clock (EC) CLKIN FOSC 2013-2015 Microchip Technology Inc. DS40001729C-page 57 PIC16(L)F1705/9 5.12 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Table 5-3 and Table 5-4 show the Reset conditions of these registers. TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD Condition 0 0 1 1 1 0 x 1 1 Power-on Reset 0 0 1 1 1 0 x 0 x Illegal, TO is set on POR 0 0 1 1 1 0 x x 0 Illegal, PD is set on POR 0 0 u 1 1 u 0 1 1 Brown-out Reset u u 0 u u u u 0 u WDT Reset u u u u u u u 0 0 WDT Wake-up from Sleep u u u u u u u 1 0 Interrupt Wake-up from Sleep u u u 0 u u u u u MCLR Reset during normal operation u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset (STVREN = 1) u 1 u u u u u u u Stack Underflow Reset (STVREN = 1) TABLE 5-4: RESET CONDITION FOR SPECIAL REGISTERS Program Counter STATUS Register PCON Register Power-on Reset 0000h ---1 1000 00-- 110x MCLR Reset during normal operation 0000h ---u uuuu uu-- 0uuu MCLR Reset during Sleep 0000h ---1 0uuu uu-- 0uuu WDT Reset 0000h ---0 uuuu uu-- uuuu WDT Wake-up from Sleep PC + 1 ---0 0uuu uu-- uuuu Brown-out Reset 0000h ---1 1uuu 00-- 11u0 ---1 0uuu uu-- uuuu ---u uuuu uu-- u0uu Condition Interrupt Wake-up from Sleep RESET Instruction Executed PC + 1 (1) 0000h Stack Overflow Reset (STVREN = 1) 0000h ---u uuuu 1u-- uuuu Stack Underflow Reset (STVREN = 1) 0000h ---u uuuu u1-- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. DS40001729C-page 58 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 5.13 Power Control (PCON) Register The PCON register bits are shown in Register 5-2. The Power Control (PCON) register contains flag bits to differentiate between a: • • • • • • • Power-on Reset (POR) Brown-out Reset (BOR) Reset Instruction Reset (RI) MCLR Reset (RMCLR) Watchdog Timer Reset (RWDT) Stack Underflow Reset (STKUNF) Stack Overflow Reset (STKOVF) 5.14 Register Definitions: Power Control REGISTER 5-2: PCON: POWER CONTROL REGISTER R/W/HS-0/q R/W/HS-0/q U-0 STKOVF STKUNF — R/W/HC-1/q R/W/HC-1/q RWDT R/W/HC-1/q R/W/HC-q/u R/W/HC-q/u RI POR BOR RMCLR bit 7 bit 0 Legend: HC = Bit is cleared by hardware HS = Bit is set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 STKOVF: Stack Overflow Flag bit 1 = A Stack Overflow occurred 0 = A Stack Overflow has not occurred or cleared by firmware bit 6 STKUNF: Stack Underflow Flag bit 1 = A Stack Underflow occurred 0 = A Stack Underflow has not occurred or cleared by firmware bit 5 Unimplemented: Read as ‘0’ bit 4 RWDT: Watchdog Timer Reset Flag bit 1 = A Watchdog Timer Reset has not occurred or set to ‘1’ by firmware 0 = A Watchdog Timer Reset has occurred (cleared by hardware) bit 3 RMCLR: MCLR Reset Flag bit 1 = A MCLR Reset has not occurred or set to ‘1’ by firmware 0 = A MCLR Reset has occurred (cleared by hardware) bit 2 RI: RESET Instruction Flag bit 1 = A RESET instruction has not been executed or set to ‘1’ by firmware 0 = A RESET instruction has been executed (cleared by hardware) bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2013-2015 Microchip Technology Inc. DS40001729C-page 59 PIC16(L)F1705/9 TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BORCON SBOREN BORFS — — — — — BORRDY 55 PCON STKOVF STKUNF — RWDT RMCLR RI POR BOR 59 STATUS — — — TO PD Z DC C 22 WDTCON — — SWDTEN 99 WDTPS<4:0> Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Resets. DS40001729C-page 60 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 6.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 6.1 Overview The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. Figure 6-1 illustrates a block diagram of the oscillator module. Clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and Resistor-Capacitor (RC) circuits. In addition, the system clock source can be supplied from one of two internal oscillators and PLL circuits, with a choice of speeds selectable via software. Additional clock features include: • Selectable system clock source between external or internal sources via software. • Two-Speed Start-up mode, which minimizes latency between external oscillator start-up and code execution. • Fail-Safe Clock Monitor (FSCM) designed to detect a failure of the external clock source (LP, XT, HS, ECH, ECM, ECL or EXTRC modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources. 2013-2015 Microchip Technology Inc. The oscillator module can be configured in one of the following clock modes. 1. 2. 3. 4. 5. 6. 7. 8. ECL – External Clock Low-Power mode (0 MHz to 0.5 MHz) ECM – External Clock Medium-Power mode (0.5 MHz to 4 MHz) ECH – External Clock High-Power mode (4 MHz to 32 MHz) LP – 32 kHz Low-Power Crystal mode. XT – Medium Gain Crystal or Ceramic Resonator Oscillator mode (up to 4 MHz) HS – High Gain Crystal or Ceramic Resonator mode (4 MHz to 20 MHz) EXTRC – External Resistor-Capacitor INTOSC – Internal oscillator (31 kHz to 32 MHz) Clock Source modes are selected by the FOSC<2:0> bits in the Configuration Words. The FOSC bits determine the type of oscillator that will be used when the device is first powered. The ECH, ECM, and ECL clock modes rely on an external logic level signal as the device clock source. The LP, XT, and HS clock modes require an external crystal or resonator to be connected to the device. Each mode is optimized for a different frequency range. The EXTRC clock mode requires an external resistor and capacitor to set the oscillator frequency. The INTOSC internal oscillator block produces low, medium, and high-frequency clock sources, designated LFINTOSC, MFINTOSC and HFINTOSC. (see Internal Oscillator Block, Figure 6-1). A wide selection of device clock frequencies may be derived from these three clock sources. DS40001729C-page 61 PIC16(L)F1705/9 SIMPLIFIED PIC® MCU CLOCK SOURCE BLOCK DIAGRAM FIGURE 6-1: Secondary Oscillator Timer1 Timer1 Clock Source Option for other modules SOSCO T1OSCEN Enable Oscillator SOSCI T1OSC 01 External Oscillator LP, XT, HS, RC, EC OSC2 0 Sleep 00 PRIMUX OSC1 4 x PLL 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz 31.25 kHz PLLMUX 500 kHz Source 16 MHz (HFINTOSC) 500 kHz (MFINTOSC) 31 kHz Source INTOSC SCS<1:0> 31 kHz 0000 31 kHz (LFINTOSC) WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Inputs FOSC<2:0> PLLEN or SPLLEN 0 =100 1 =00 ≠100 ≠00 X DS40001729C-page 62 0 1X 1111 MUX HFPLL Postscaler Internal Oscillator Block FOSC To CPU and Peripherals 1 IRCF<3:0> SCS Sleep 0 1 Outputs IRCF PRIMUX PLLMUX x 1 0 =1110 1 1 ≠1110 1 0 x 0 0 1 x 0 1 X X X X 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 6.2 Clock Source Types Clock sources can be classified as external or internal. External clock sources rely on external circuitry for the clock source to function. Examples are: oscillator modules (ECH, ECM, ECL mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and Resistor-Capacitor (EXTRC) mode circuits. Internal clock sources are contained within the oscillator module. The internal oscillator block has two internal oscillators and a dedicated Phase Lock Loop (HFPLL) that are used to generate three internal system clock sources: the 16 MHz High-Frequency Internal Oscillator (HFINTOSC), 500 kHz (MFINTOSC) and the 31 kHz Low-Frequency Internal Oscillator (LFINTOSC). The system clock can be selected between external or internal clock sources via the System Clock Select (SCS) bits in the OSCCON register. See Section 6.3 “Clock Switching” for additional information. 6.2.1 FIGURE 6-2: OSC1/CLKIN Clock from Ext. System PIC® MCU FOSC/4 or I/O(1) Note 1: EXTERNAL CLOCK (EC) MODE OPERATION OSC2/CLKOUT Output depends upon CLKOUTEN bit of the Configuration Words. EXTERNAL CLOCK SOURCES An external clock source can be used as the device system clock by performing one of the following actions: • Program the FOSC<2:0> bits in the Configuration Words to select an external clock source that will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to: - Secondary oscillator during run-time, or - An external clock source determined by the value of the FOSC bits. See Section 6.3 “Clock Switching” for more information. 6.2.1.1 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC® MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. Upon restarting the external clock, the device will resume operation as if no time had elapsed. EC Mode The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the OSC1 input. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. Figure 6-2 shows the pin connections for EC mode. 6.2.1.2 LP, XT, HS Modes The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 6-3). The three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. LP Oscillator mode selects the lowest gain setting of the internal inverter-amplifier. LP mode current consumption is the least of the three modes. This mode is designed to drive only 32.768 kHz tuning-fork type crystals (watch crystals). XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. This mode is best suited to drive resonators with a medium drive level specification. HS Oscillator mode selects the highest gain setting of the internal inverter-amplifier. HS mode current consumption is the highest of the three modes. This mode is best suited for resonators that require a high drive setting. Figure 6-3 and Figure 6-4 show typical circuits for quartz crystal and ceramic resonators, respectively. EC mode has three power modes to select from through Configuration Words: • ECH – High power, 4-32 MHz • ECM – Medium power, 0.5-4 MHz • ECL – Low power, 0-0.5 MHz 2013-2015 Microchip Technology Inc. DS40001729C-page 63 PIC16(L)F1705/9 FIGURE 6-3: QUARTZ CRYSTAL OPERATION (LP, XT OR HS MODE) FIGURE 6-4: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU PIC® MCU OSC1/CLKIN C1 To Internal Logic Quartz Crystal C2 Note 1: 2: OSC1/CLKIN RS(1) RF(2) C1 Sleep OSC2/CLKOUT A series resistor (RS) may be required for quartz crystals with low drive level. RP(3) C2 Ceramic RS(1) Resonator Note 1: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Application Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) DS40001729C-page 64 To Internal Logic RF(2) Sleep OSC2/CLKOUT A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. 6.2.1.3 Oscillator Start-up Timer (OST) If the oscillator module is configured for LP, XT or HS modes, the Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following a Power-on Reset (POR) and when the Power-up Timer (PWRT) has expired (if configured), or a wake-up from Sleep. During this time, the program counter does not increment and program execution is suspended, unless either FSCM or Two-Speed Start-Up are enabled. In this case, code will continue to execute at the selected INTOSC frequency while the OST is counting. The OST ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. In order to minimize latency between external oscillator start-up and code execution, the Two-Speed Clock Start-up mode can be selected (see Section 6.4 “Two-Speed Clock Start-up Mode”). 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 6.2.1.4 4x PLL The oscillator module contains a 4x PLL that can be used with both external and internal clock sources to provide a system clock source. The input frequency for the 4x PLL must fall within specifications. See the PLL Clock Timing Specifications in Table 32-9. The 4x PLL may be enabled for use by one of two methods: 1. 2. Program the PLLEN bit in Configuration Words to a ‘1’. Write the SPLLEN bit in the OSCCON register to a ‘1’. If the PLLEN bit in Configuration Words is programmed to a ‘1’, then the value of SPLLEN is ignored. 6.2.1.5 Secondary Oscillator The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. The secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. Refer to Section 6.3 “Clock Switching” for more information. FIGURE 6-5: Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application. 2: Always verify oscillator performance over the VDD and temperature range that is expected for the application. 3: For oscillator design assistance, reference the following Microchip Application Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PIC® Devices” (DS00826) • AN849, “Basic PIC® Oscillator Design” (DS00849) • AN943, “Practical PIC® Oscillator Analysis and Design” (DS00943) • AN949, “Making Your Oscillator Work” (DS00949) • TB097, “Interfacing a Micro Crystal MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) QUARTZ CRYSTAL OPERATION (SECONDARY OSCILLATOR) PIC® MCU SOSCI C1 To Internal Logic 32.768 kHz Quartz Crystal C2 SOSCO 2013-2015 Microchip Technology Inc. DS40001729C-page 65 PIC16(L)F1705/9 6.2.1.6 External RC Mode 6.2.2 The external Resistor-Capacitor (EXTRC) mode supports the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. The RC circuit connects to OSC1. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. Figure 6-6 shows the external RC mode connections. FIGURE 6-6: EXTERNAL RC MODES VDD PIC® MCU The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: • Program the FOSC<2:0> bits in Configuration Words to select the INTOSC clock source, which will be used as the default system clock upon a device Reset. • Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See Section 6.3 “Clock Switching” for more information. In INTOSC mode, OSC1/CLKIN is available for general purpose I/O. OSC2/CLKOUT is available for general purpose I/O or CLKOUT. The function of the OSC2/CLKOUT pin is determined by the CLKOUTEN bit in Configuration Words. REXT OSC1/CLKIN Internal Clock CEXT VSS The internal oscillator block has two independent oscillators and a dedicated Phase Lock Loop, HFPLL that can produce one of three internal system clock sources. 1. FOSC/4 or I/O(1) OSC2/CLKOUT Recommended values: 10 k REXT 100 k, <3V 3 k REXT 100 k, 3-5V CEXT > 20 pF, 2-5V Note 1: INTERNAL CLOCK SOURCES Output depends upon CLKOUTEN bit of the Configuration Words. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. Other factors affecting the oscillator frequency are: • threshold voltage variation • component tolerances • packaging variations in capacitance 2. 3. The HFINTOSC (High-Frequency Internal Oscillator) is factory calibrated and operates at 16 MHz. The HFINTOSC source is generated from the 500 kHz MFINTOSC source and the dedicated Phase Lock Loop, HFPLL. The frequency of the HFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3). The MFINTOSC (Medium-Frequency Internal Oscillator) is factory calibrated and operates at 500 kHz. The frequency of the MFINTOSC can be user-adjusted via software using the OSCTUNE register (Register 6-3). The LFINTOSC (Low-Frequency Internal Oscillator) is uncalibrated and operates at 31 kHz. The user also needs to take into account variation due to tolerance of external RC components used. DS40001729C-page 66 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 6.2.2.1 HFINTOSC The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source. The frequency of the HFINTOSC can be altered via software using the OSCTUNE register (Register 6-3). The output of the HFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of multiple frequencies derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The HFINTOSC is enabled by: • Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ A fast start-up oscillator allows internal circuits to power up and stabilize before switching to HFINTOSC. The High-Frequency Internal Oscillator Ready bit (HFIOFR) of the OSCSTAT register indicates when the HFINTOSC is running. The High-Frequency Internal Oscillator Status Locked bit (HFIOFL) of the OSCSTAT register indicates when the HFINTOSC is running within 2% of its final value. The High-Frequency Internal Oscillator Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value. 6.2.2.2 MFINTOSC The Medium-Frequency Internal Oscillator (MFINTOSC) is a factory calibrated 500 kHz internal clock source. The frequency of the MFINTOSC can be altered via software using the OSCTUNE register (Register 6-3). The output of the MFINTOSC connects to a postscaler and multiplexer (see Figure 6-1). One of nine frequencies derived from the MFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The MFINTOSC is enabled by: • Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ The Medium-Frequency Internal Oscillator Ready bit (MFIOFR) of the OSCSTAT register indicates when the MFINTOSC is running. 2013-2015 Microchip Technology Inc. 6.2.2.3 Internal Oscillator Frequency Adjustment The 500 kHz internal oscillator is factory calibrated. This internal oscillator can be adjusted in software by writing to the OSCTUNE register (Register 6-3). Since the HFINTOSC and MFINTOSC clock sources are derived from the 500 kHz internal oscillator a change in the OSCTUNE register value will apply to both. The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number. A value of 1Fh will provide an adjustment to the maximum frequency. A value of 20h will provide an adjustment to the minimum frequency. When the OSCTUNE register is modified, the oscillator frequency will begin shifting to the new frequency. Code execution continues during this shift. There is no indication that the shift has occurred. OSCTUNE does not affect the LFINTOSC frequency. Operation of features that depend on the LFINTOSC clock source frequency, such as the Power-up Timer (PWRT), Watchdog Timer (WDT), Fail-Safe Clock Monitor (FSCM) and peripherals, are not affected by the change in frequency. 6.2.2.4 LFINTOSC The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source. The output of the LFINTOSC connects to a multiplexer (see Figure 6-1). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON register. See Section 6.2.2.7 “Internal Oscillator Clock Switch Timing” for more information. The LFINTOSC is also the frequency for the Power-up Timer (PWRT), Watchdog Timer (WDT) and Fail-Safe Clock Monitor (FSCM). The LFINTOSC is enabled by selecting 31 kHz (IRCF<3:0> bits of the OSCCON register = 000) as the system clock source (SCS bits of the OSCCON register = 1x), or when any of the following are enabled: • Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and • FOSC<2:0> = 100, or • Set the System Clock Source (SCS) bits of the OSCCON register to ‘1x’ Peripherals that use the LFINTOSC are: • Power-up Timer (PWRT) • Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running. DS40001729C-page 67 PIC16(L)F1705/9 6.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register. The postscaled output of the 16 MHz HFINTOSC, 500 kHz MFINTOSC, and 31 kHz LFINTOSC connect to a multiplexer (see Figure 6-1). The Internal Oscillator Frequency Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software: - 32 MHz (requires 4x PLL) 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz (default after Reset) 250 kHz 125 kHz 62.5 kHz 31.25 kHz 31 kHz (LFINTOSC) Note: Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to ‘0111’ and the frequency selection is set to 500 kHz. The user can modify the IRCF bits to select a different frequency. 6.2.2.6 32 MHz Internal Oscillator Frequency Selection The Internal Oscillator Block can be used with the 4x PLL associated with the External Oscillator Block to produce a 32 MHz internal system clock source. The following settings are required to use the 32 MHz internal clock source: • The FOSC bits in Configuration Words must be set to use the INTOSC source as the device system clock (FOSC<2:0> = 100). • The SCS bits in the OSCCON register must be cleared to use the clock determined by FOSC<2:0> in Configuration Words (SCS<1:0> = 00). • The IRCF bits in the OSCCON register must be set to the 8 MHz HFINTOSC set to use (IRCF<3:0> = 1110). • The SPLLEN bit in the OSCCON register must be set to enable the 4x PLL, or the PLLEN bit of the Configuration Words must be programmed to a ‘1’. Note: When using the PLLEN bit of the Configuration Words, the 4x PLL cannot be disabled by software and the SPLLEN option will not be available. The 4x PLL is not available for use with the internal oscillator when the SCS bits of the OSCCON register are set to ‘1x’. The SCS bits must be set to ‘00’ to use the 4x PLL with the internal oscillator. The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source. DS40001729C-page 68 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 6.2.2.7 Internal Oscillator Clock Switch Timing When switching between the HFINTOSC, MFINTOSC and the LFINTOSC, the new oscillator may already be shut down to save power (see Figure 6-7). If this is the case, there is a delay after the IRCF<3:0> bits of the OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC, MFINTOSC and LFINTOSC oscillators. The sequence of a frequency selection is as follows: 1. 2. 3. 4. 5. 6. 7. IRCF<3:0> bits of the OSCCON register are modified. If the new clock is shut down, a clock start-up delay is started. Clock switch circuitry waits for a falling edge of the current clock. The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. The new clock is now active. The OSCSTAT register is updated as required. Clock switch is complete. See Figure 6-7 for more details. If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in Table 6-1. Start-up delay specifications are located in the oscillator tables of Section 32.0 “Electrical Specifications”. 2013-2015 Microchip Technology Inc. DS40001729C-page 69 PIC16(L)F1705/9 FIGURE 6-7: INTERNAL OSCILLATOR SWITCH TIMING HFINTOSC/ MFINTOSC LFINTOSC (FSCM and WDT disabled) HFINTOSC/ MFINTOSC Oscillator Delay(1) 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock HFINTOSC/ MFINTOSC LFINTOSC (Either FSCM or WDT enabled) HFINTOSC/ MFINTOSC 2-cycle Sync Running LFINTOSC 0 IRCF <3:0> 0 System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC turns off unless WDT or FSCM is enabled LFINTOSC Oscillator Delay(1) 2-cycle Sync Running HFINTOSC/ MFINTOSC IRCF <3:0> =0 0 System Clock Note: See Table 6-1: Oscillator Switching Delays for more information. DS40001729C-page 70 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 6.3 Clock Switching 6.3.3 SECONDARY OSCILLATOR The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits: The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the SOSCO and SOSCI device pins. • Default system oscillator determined by FOSC bits in Configuration Words • Timer1 32 kHz crystal oscillator • Internal Oscillator Block (INTOSC) The secondary oscillator is enabled using the T1OSCEN control bit in the T1CON register. See Section 25.0 “Timer1 Module with Gate Control” for more information about the Timer1 peripheral. 6.3.1 SYSTEM CLOCK SELECT (SCS) BITS The System Clock Select (SCS) bits of the OSCCON register select the system clock source that is used for the CPU and peripherals. • When the SCS bits of the OSCCON register = 00, the system clock source is determined by the value of the FOSC<2:0> bits in the Configuration Words. • When the SCS bits of the OSCCON register = 01, the system clock source is the secondary oscillator. • When the SCS bits of the OSCCON register = 1x, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the SCS bits of the OSCCON register are always cleared. Note: 6.3.4 SECONDARY OSCILLATOR READY (SOSCR) BIT The user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. The Secondary Oscillator Ready (SOSCR) bit of the OSCSTAT register indicates whether the secondary oscillator is ready to be used. After the SOSCR bit is set, the SCS bits can be configured to select the secondary oscillator. Any automatic clock switch, which may occur from Two-Speed Start-up or Fail-Safe Clock Monitor, does not update the SCS bits of the OSCCON register. The user can monitor the OSTS bit of the OSCSTAT register to determine the current system clock source. When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscillator delays are shown in Table 6-1. 6.3.2 OSCILLATOR START-UP TIMER STATUS (OSTS) BIT The Oscillator Start-up Timer Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or from the internal clock source. In particular, OSTS indicates that the Oscillator Start-up Timer (OST) has timed out for LP, XT or HS modes. The OST does not reflect the status of the secondary oscillator. 2013-2015 Microchip Technology Inc. DS40001729C-page 71 PIC16(L)F1705/9 6.4 6.4.1 Two-Speed Clock Start-up Mode Two-Speed Start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. In applications that make heavy use of the Sleep mode, Two-Speed Start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. This mode allows the application to wake-up from Sleep, perform a few instructions using the INTOSC internal oscillator block as the clock source and go back to Sleep without waiting for the external oscillator to become stable. Two-Speed Start-up provides benefits when the oscillator module is configured for LP, XT or HS modes. The Oscillator Start-up Timer (OST) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Words) = 1; Internal/External Switchover bit (Two-Speed Start-up mode enabled). • SCS (of the OSCCON register) = 00. • FOSC<2:0> bits in the Configuration Words configured for LP, XT or HS mode. Two-Speed Start-up mode is entered after: • Power-on Reset (POR) and, if enabled, after Power-up Timer (PWRT) has expired, or • Wake-up from Sleep. If the oscillator module is configured for any mode other than LP, XT or HS mode, then Two-Speed Start-up is disabled. This is because the external clock oscillator does not require any stabilization time after POR or an exit from Sleep. If the OST count reaches 1024 before the device enters Sleep mode, the OSTS bit of the OSCSTAT register is set and program execution switches to the external oscillator. However, the system may never operate from the external oscillator if the time spent awake is very short. Note: Executing a SLEEP instruction will abort the oscillator start-up time and will cause the OSTS bit of the OSCSTAT register to remain clear. TABLE 6-1: OSCILLATOR SWITCHING DELAYS Switch From Switch To Frequency Oscillator Delay LFINTOSC(1) Sleep/POR MFINTOSC(1) HFINTOSC(1) 31 kHz 31.25 kHz-500 kHz 31.25 kHz-16 MHz 2 cycles Sleep/POR EC, RC(1) DC – 32 MHz 2 cycles LFINTOSC EC, RC(1) DC – 32 MHz 1 cycle of each Sleep/POR Secondary Oscillator 32 kHz-20 MHz LP, XT, HS(1) 1024 Clock Cycles (OST) Any clock source MFINTOSC(1) HFINTOSC(1) 31.25 kHz-500 kHz 31.25 kHz-16 MHz 2 s (approx.) Any clock source LFINTOSC(1) 31 kHz Any clock source Secondary Oscillator 32 kHz 1024 Clock Cycles (OST) PLL inactive PLL active 2 ms (approx.) Note 1: 16-32 MHz 1 cycle of each PLL inactive. DS40001729C-page 72 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 6.4.2 1. 2. 3. 4. 5. 6. 7. TWO-SPEED START-UP SEQUENCE 6.4.3 Wake-up from Power-on Reset or Sleep. Instructions begin execution by the internal oscillator at the frequency set in the IRCF<3:0> bits of the OSCCON register. OST enabled to count 1024 clock cycles. OST timed out, wait for falling edge of the internal oscillator. OSTS is set. System clock held low until the next falling edge of new clock (LP, XT or HS mode). System clock is switched to external clock source. FIGURE 6-8: CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Words, or the internal oscillator. TWO-SPEED START-UP INTOSC TOST OSC1 0 1 1022 1023 OSC2 Program Counter PC - N PC PC + 1 System Clock 2013-2015 Microchip Technology Inc. DS40001729C-page 73 PIC16(L)F1705/9 6.5 6.5.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the Configuration Words. The FSCM is applicable to all external Oscillator modes (LP, XT, HS, EC, Secondary Oscillator and RC). FIGURE 6-9: FSCM BLOCK DIAGRAM Clock Monitor Latch External Clock LFINTOSC Oscillator ÷ 64 31 kHz (~32 s) 488 Hz (~2 ms) S Q R Q Sample Clock 6.5.1 FAIL-SAFE OPERATION When the external clock fails, the FSCM switches the device clock to an internal clock source and sets the bit flag OSFIF of the PIR2 register. Setting this flag will generate an interrupt if the OSFIE bit of the PIE2 register is also set. The device firmware can then take steps to mitigate the problems that may arise from a failed clock. The system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. RESET OR WAKE-UP FROM SLEEP The FSCM is designed to detect an oscillator failure after the Oscillator Start-up Timer (OST) has expired. The OST is used after waking up from Sleep and after any type of Reset. The OST is not used with the EC or RC Clock modes so that the FSCM will be active as soon as the Reset or wake-up has completed. When the FSCM is enabled, the Two-Speed Start-up is also enabled. Therefore, the device will always be executing code while the OST is operating. Note: FAIL-SAFE DETECTION The FSCM module detects a failed oscillator by comparing the external oscillator to the FSCM sample clock. The sample clock is generated by dividing the LFINTOSC by 64. See Figure 6-9. Inside the fail detector block is a latch. The external clock sets the latch on each falling edge of the external clock. The sample clock clears the latch on each rising edge of the sample clock. A failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 6.5.2 The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register. When the SCS bits are changed, the OST is restarted. While the OST is running, the device continues to operate from the INTOSC selected in OSCCON. When the OST times out, the Fail-Safe condition is cleared after successfully switching to the external clock source. The OSFIF bit should be cleared prior to switching to the external clock source. If the Fail-Safe condition still exists, the OSFIF flag will again become set by hardware. 6.5.4 Clock Failure Detected FAIL-SAFE CONDITION CLEARING 6.5.5 Due to the wide range of oscillator start-up times, the Fail-Safe circuit is not active during oscillator start-up (i.e., after exiting Reset or Sleep). After an appropriate amount of time, the user should check the Status bits in the OSCSTAT register to verify the oscillator start-up and that the system clock switchover has successfully completed. CLOCK SWITCH BEFORE SLEEP When a clock switch from an old clock to a new clock is requested just prior to entering Sleep mode, it is necessary to confirm that the switch is complete before the SLEEP instruction is executed. Failure to do so may result in an incomplete switch and consequential loss of the system clock altogether. Clock switching is confirmed by monitoring the clock Status bits in the OSCSTAT register. Switch confirmation can be accomplished by sensing that the Ready bit for the new clock is set or the Ready bit for the old clock is cleared. For example, when switching between the internal oscillator with the PLL and the internal oscillator without the PLL, monitor the PLLR bit. When PLLR is set, the switch to 32 MHz operation is complete. Conversely, when PLLR is cleared, the switch from 32 MHz operation to the selected internal clock is complete. The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. DS40001729C-page 74 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 6-10: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity. 2013-2015 Microchip Technology Inc. DS40001729C-page 75 PIC16(L)F1705/9 6.6 Register Definitions: Oscillator Control REGISTER 6-1: R/W-0/0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0/0 SPLLEN R/W-1/1 R/W-1/1 R/W-1/1 IRCF<3:0> U-0 R/W-0/0 — R/W-0/0 SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPLLEN: Software PLL Enable bit If PLLEN in Configuration Words = 1: SPLLEN bit is ignored. 4x PLL is always enabled (subject to oscillator requirements) If PLLEN in Configuration Words = 0: 1 = 4x PLL Is enabled 0 = 4x PLL is disabled bit 6-3 IRCF<3:0>: Internal Oscillator Frequency Select bits 1111 = 16 MHz HF 1110 = 8 MHz or 32 MHz HF(2) 1101 = 4 MHz HF 1100 = 2 MHz HF 1011 = 1 MHz HF 1010 = 500 kHz HF(1) 1001 = 250 kHz HF(1) 1000 = 125 kHz HF(1) 0111 = 500 kHz MF (default upon Reset) 0110 = 250 kHz MF 0101 = 125 kHz MF 0100 = 62.5 kHz MF 0011 = 31.25 kHz HF(1) 0010 = 31.25 kHz MF 000x = 31 kHz LF bit 2 Unimplemented: Read as ‘0’ bit 1-0 SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Secondary oscillator 00 = Clock determined by FOSC<2:0> in Configuration Words Note 1: 2: Duplicate frequency derived from HFINTOSC. 32 MHz when SPLLEN bit is set. Refer to Section 6.2.2.6 “32 MHz Internal Oscillator Frequency Selection”. DS40001729C-page 76 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 6-2: OSCSTAT: OSCILLATOR STATUS REGISTER R-1/q R-0/q R-q/q R-0/q R-0/q R-q/q R-0/0 R-0/q SOSCR PLLR OSTS HFIOFR HFIOFL MFIOFR LFIOFR HFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Conditional bit 7 SOSCR: Secondary Oscillator Ready bit If T1OSCEN = 1: 1 = Secondary oscillator is ready 0 = Secondary oscillator is not ready If T1OSCEN = 0: 1 = Secondary clock source is always ready bit 6 PLLR 4x PLL Ready bit 1 = 4x PLL is ready 0 = 4x PLL is not ready bit 5 OSTS: Oscillator Start-up Timer Status bit 1 = Running from the clock defined by the FOSC<2:0> bits of the Configuration Words 0 = Running from an internal oscillator (FOSC<2:0> = 100) bit 4 HFIOFR: High-Frequency Internal Oscillator Ready bit 1 = HFINTOSC is ready 0 = HFINTOSC is not ready bit 3 HFIOFL: High-Frequency Internal Oscillator Locked bit 1 = HFINTOSC is at least 2% accurate 0 = HFINTOSC is not 2% accurate bit 2 MFIOFR: Medium-Frequency Internal Oscillator Ready bit 1 = MFINTOSC is ready 0 = MFINTOSC is not ready bit 1 LFIOFR: Low-Frequency Internal Oscillator Ready bit 1 = LFINTOSC is ready 0 = LFINTOSC is not ready bit 0 HFIOFS: High-Frequency Internal Oscillator Stable bit 1 = HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate 2013-2015 Microchip Technology Inc. DS40001729C-page 77 PIC16(L)F1705/9 REGISTER 6-3: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: Frequency Tuning bits 100000 = Minimum frequency • • • 111111 = 000000 = Oscillator module is running at the factory-calibrated frequency 000001 = • • • 011110 = 011111 = Maximum frequency TABLE 6-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Bit 7 Bit 6 Bit 5 Bit 4 OSCCON SPLLEN OSCSTAT SOSCR PLLR OSCTUNE — — PIR2 OSFIF C2IF C1IF — PIE2 OSFIE C2IE C1IE — T1CON Legend: Bit 3 IRCF<3:0> TMR1CS<1:0> OSTS Bit 1 — HFIOFR HFIOFL Bit 0 SCS<1:0> MFIOFR LFIOFR 76 HFIOFS TUN<5:0> BCL1IF T1CKPS<1:0> Register on Page 77 78 TMR6IF TMR4IF CCP2IF 89 BCL1IE TMR6IE T1OSCEN T1SYNC TMR4IE CCP2IE 86 — TMR1ON 254 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. TABLE 6-3: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 CONFIG1 13:8 — — FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE Legend: Bit 2 WDTE<1:0> Bit 10/2 Bit 9/1 BOREN<1:0> FOSC<2:0> Bit 8/0 — Register on Page 48 — = unimplemented location, read as ‘0’. Shaded cells are not used by clock sources. DS40001729C-page 78 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 7.0 PIC16(L)F1705/9 INTERRUPTS The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. This chapter contains the following information for Interrupts: • • • • • Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts. Refer to the corresponding chapters for details. A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC TMR0IF TMR0IE Peripheral Interrupts (TMR1IF) PIR1<0> (TMR1IE) PIE1<0> Wake-up (If in Sleep mode) INTF INTE IOCIF IOCIE Interrupt to CPU PEIE PIRn<7> PIEn<7> 2013-2015 Microchip Technology Inc. GIE DS40001729C-page 79 PIC16(L)F1705/9 7.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt Enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the Interrupt Enable bit of the interrupt event is contained in the PIE1 or PIE2 registers) 7.2 Interrupt Latency Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is three or four instruction cycles. For asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. See Figure 7-2 and Figure 7-3 for more details. The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits. The following events happen when an interrupt event occurs while the GIE bit is set: • Current prefetched instruction is flushed • GIE bit is cleared • Current Program Counter (PC) is pushed onto the stack • Critical registers are automatically saved to the shadow registers (See “Section 7.5 “Automatic Context Saving”) • PC is loaded with the interrupt vector 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt’s operation, refer to its peripheral chapter. Note 1: Individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again. DS40001729C-page 80 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 7-2: INTERRUPT LATENCY OSC1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKR Interrupt Sampled during Q1 Interrupt GIE PC Execute PC-1 PC 1 Cycle Instruction at PC PC+1 0004h 0005h NOP NOP Inst(0004h) PC+1/FSR ADDR New PC/ PC+1 0004h 0005h Inst(PC) NOP NOP Inst(0004h) FSR ADDR PC+1 PC+2 0004h 0005h INST(PC) NOP NOP NOP Inst(0004h) Inst(0005h) FSR ADDR PC+1 0004h 0005h INST(PC) NOP NOP Inst(0004h) Inst(PC) Interrupt GIE PC Execute PC-1 PC 2 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC Interrupt GIE PC Execute PC-1 PC 3 Cycle Instruction at PC 2013-2015 Microchip Technology Inc. PC+2 NOP NOP DS40001729C-page 81 PIC16(L)F1705/9 FIGURE 7-3: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT (3) (4) INT pin (1) (1) INTF Interrupt Latency (2) (5) GIE INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: PC Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Forced NOP 0004h Inst (0004h) Forced NOP 0005h Inst (0005h) Inst (0004h) INTF flag is sampled here (every Q1). 2: Asynchronous interrupt latency = 3-5 TCY. Synchronous latency = 3-4 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT not available in all oscillator modes. 4: For minimum width of INT pulse, refer to AC specifications in Section 32.0 “Electrical Specifications””. 5: INTF is enabled to be set any time during the Q4-Q1 cycles. DS40001729C-page 82 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 7.3 Interrupts During Sleep Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep. On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the SLEEP instruction. The instruction directly after the SLEEP instruction will always be executed before branching to the ISR. Refer to Section 8.0 “Power-Down Mode (Sleep)” for more details. 7.4 INT Pin The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and INTE bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 Automatic Context Saving Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the shadow registers: • • • • • W register STATUS register (except for TO and PD) BSR register FSR registers PCLATH register Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the ISR. The shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved. 2013-2015 Microchip Technology Inc. DS40001729C-page 83 PIC16(L)F1705/9 7.6 Register Definitions: Interrupt Control REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all active interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all active peripheral interrupts 0 = Disables all peripheral interrupts bit 5 TMR0IE: Timer0 Overflow Interrupt Enable bit 1 = Enables the Timer0 interrupt 0 = Disables the Timer0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCIE: Interrupt-on-Change Enable bit 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 TMR0IF: Timer0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed 0 = TMR0 register did not overflow bit 1 INTF: INT External Interrupt Flag bit 1 = The INT external interrupt occurred 0 = The INT external interrupt did not occur bit 0 IOCIF: Interrupt-on-Change Interrupt Flag bit(1) 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins have changed state Note 1: Note: The IOCIF Flag bit is read-only and cleared when all the interrupt-on-change flags in the IOCxF registers have been cleared by software. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001729C-page 84 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 7-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIE: Timer1 Gate Interrupt Enable bit 1 = Enables the Timer1 gate acquisition interrupt 0 = Disables the Timer1 gate acquisition interrupt bit 6 ADIE: Analog-to-Digital Converter (ADC) Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3 SSP1IE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 2 CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the Timer2 to PR2 match interrupt 0 = Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 2013-2015 Microchip Technology Inc. DS40001729C-page 85 PIC16(L)F1705/9 REGISTER 7-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 OSFIE C2IE C1IE U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — BCL1IE TMR6IE TMR4IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIE: Oscillator Fail Interrupt Enable bit 1 = Enables the Oscillator Fail interrupt 0 = Disables the Oscillator Fail interrupt bit 6 C2IE: Comparator C2 Interrupt Enable bit 1 = Enables the Comparator C2 interrupt 0 = Disables the Comparator C2 interrupt bit 5 C1IE: Comparator C1 Interrupt Enable bit 1 = Enables the Comparator C1 interrupt 0 = Disables the Comparator C1 interrupt bit 4 Unimplemented: Read as ‘0’ bit 3 BCL1IE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision interrupt 0 = Disables the MSSP Bus Collision interrupt bit 2 TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enables the Timer6 to PR6 match interrupt 0 = Disables the Timer6 to PR6 match interrupt bit 1 TMR4IE: TMR4to PR4 Match Interrupt Enable bit 1 = Enables the Timer4 to PR4 match interrupt 0 = Disables the Timer4 to PR4 match interrupt bit 0 CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. DS40001729C-page 86 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 7-4: U-0 — PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 COGIE: COG Auto-Shutdown Interrupt Enable bit 1 = COG interrupt enabled 0 = COG interrupt disabled bit 4 ZCDIE: Zero-Cross Detection Interrupt Enable bit 1 = ZCD interrupt enabled 0 = ZCD interrupt disabled bit 3 Unimplemented: Read as ‘0’ bit 2 CLC3IE: CLC3 Interrupt Enable bit 1 = CLC3 interrupt enabled 0 = CLC3 interrupt disabled bit 1 CLC2IE: CLC2 Interrupt Enable bit 1 = CLC2 interrupt enabled 0 = CLC2 interrupt disabled bit 0 CLC1IE: CLC1 Interrupt Enable bit 1 = CLC1 interrupt enabled 0 = CLC1 interrupt disabled Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. 2013-2015 Microchip Technology Inc. DS40001729C-page 87 PIC16(L)F1705/9 REGISTER 7-5: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMR1GIF: Timer1 Gate Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 ADIF: Analog-to-Digital Converter (ADC) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 RCIF: USART Receive Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 TXIF: USART Transmit Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 SSP1IF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 CCP1IF: CCP1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR2IF: Timer2 to PR2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001729C-page 88 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 7-6: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0/0 R/W-0/0 R/W-0/0 OSFIF C2IF C1IF U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — BCL1IF TMR6IF TMR4IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSFIF: Oscillator Fail Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 6 C2IF: Comparator C2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 5 C1IF: Comparator C1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 Unimplemented: Read as ‘0’ bit 3 BCL1IF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 2 TMR6IF: Timer6 to PR6 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 TMR4IF: Timer4 to PR4 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 2013-2015 Microchip Technology Inc. DS40001729C-page 89 PIC16(L)F1705/9 REGISTER 7-7: U-0 — PIR3: PERIPHERAL INTERRUPT REQUEST REGISTER 3 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 COGIF: COG Auto-Shutdown Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 ZCDIF: Zero-Cross Detection Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 Unimplemented: Read as ‘0’ bit 2 CLC3IF: CLC3 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 1 CLC2IF: CLC2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 0 CLC1IF: CLC1 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. DS40001729C-page 90 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 7-1: Name INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PIE1 TMR1GIE ADIE PIE2 OSFIE C2IE PIE3 — — PIR1 TMR1GIF ADIF PIR2 OSFIF PIR3 — RCIE PSA PS<2:0> 245 TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 86 COGIE ZCDIE — CLC3IE CLC2IE CLC1IE 87 RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 89 — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF 90 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts. 2013-2015 Microchip Technology Inc. DS40001729C-page 91 PIC16(L)F1705/9 8.0 POWER-DOWN MODE (SLEEP) 8.1 Wake-up from Sleep The Power-down mode is entered by executing a SLEEP instruction. The device can wake-up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions exist: 1. 2. 3. 4. 5. 6. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT will be cleared but keeps running, if enabled for operation during Sleep. PD bit of the STATUS register is cleared. TO bit of the STATUS register is set. CPU clock is disabled. 31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in Sleep. Timer1 and peripherals that operate from Timer1 continue operation in Sleep when the Timer1 clock source selected is: • LFINTOSC • T1CKI • Secondary oscillator ADC is unaffected, if the dedicated FRC oscillator is selected. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). Resets other than WDT are not affected by Sleep mode. Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: • • • • • • External Reset input on MCLR pin, if enabled BOR Reset, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information) The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to Section 5.12 “Determining the Cause of a Reset”. When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction, the device will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. I/O pins should not be floating External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using 31 kHz LFINTOSC Modules using secondary oscillator I/O pins that are high-impedance inputs should be pulled to VDD or VSS externally to avoid switching currents caused by floating inputs. Examples of internal circuitry that might be sourcing current include modules such as the DAC and FVR modules. See Section 22.0 “8-Bit Digital-to-Analog Converter (DAC1) Module” and Section 14.0 “Fixed Voltage Reference (FVR)” for more information on these modules. DS40001729C-page 92 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 8.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP - WDT and WDT prescaler will not be cleared - TO bit of the STATUS register will not be set - PD bit of the STATUS register will not be cleared FIGURE 8-1: • If the interrupt occurs during or after the execution of a SLEEP instruction - SLEEP instruction will be completely executed - Device will immediately wake-up from Sleep - WDT and WDT prescaler will be cleared - TO bit of the STATUS register will be set - PD bit of the STATUS register will be cleared Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN(1) TOST(3) CLKOUT(2) Interrupt flag Interrupt Latency (4) GIE bit (INTCON reg.) Instruction Flow PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: Processor in Sleep PC Inst(PC) = Sleep Inst(PC - 1) PC + 1 PC + 2 PC + 2 Inst(PC + 1) Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Forced NOP 0004h 0005h Inst(0004h) Inst(0005h) Forced NOP Inst(0004h) External clock. High, Medium, Low mode assumed. CLKOUT is shown here for timing reference. TOST = 1024 TOSC. This delay does not apply to EC, RC and INTOSC Oscillator modes or Two-Speed Start-up (see Section 6.4 “Two-Speed Clock Start-up Mode”. GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. 2013-2015 Microchip Technology Inc. DS40001729C-page 93 PIC16(L)F1705/9 8.2 Low-Power Sleep Mode The PIC16F1705/9 devices contain an internal Low Dropout (LDO) voltage regulator, which allows the device I/O pins to operate at voltages up to 5.5V while the internal device logic operates at a lower voltage. The LDO and its associated reference circuitry must remain active when the device is in Sleep mode. The PIC16F1705/9 allow the user to optimize the operating current in Sleep, depending on the application requirements. A Low-Power Sleep mode can be selected by setting the VREGPM bit of the VREGCON register. With this bit set, the LDO and reference circuitry are placed in a low-power state when the device is in Sleep. 8.2.1 SLEEP CURRENT VS. WAKE-UP TIME In the default operating mode, the LDO and reference circuitry remain in the normal configuration while in Sleep. The device is able to exit Sleep mode quickly since all circuits remain active. In Low-Power Sleep mode, when waking up from Sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. 8.2.2 PERIPHERAL USAGE IN SLEEP Some peripherals that can operate in Sleep mode will not operate properly with the Low-Power Sleep mode selected. The Low-Power Sleep mode is intended for use only with the following peripherals: • • • • Brown-Out Reset (BOR) Watchdog Timer (WDT) External interrupt pin/Interrupt-on-change pins Timer1 (with external clock source <100 kHz) Note: The PIC16LF1705/9 do not have a configurable Low-Power Sleep mode. PIC16LF1705/9 are unregulated devices and are always in the lowest power state when in Sleep, with no wake-up time penalty. These devices have a lower maximum VDD and I/O voltage than the PIC16F1705/9. See Section 32.0 “Electrical Specifications” for more information. The Low-Power Sleep mode is beneficial for applications that stay in Sleep mode for long periods of time. The Normal mode is beneficial for applications that need to wake from Sleep quickly and frequently. DS40001729C-page 94 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 8.3 Register Definitions: Voltage Regulator Control VREGCON: VOLTAGE REGULATOR CONTROL REGISTER(1) REGISTER 8-1: U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 R/W-1/1 — — — — — — VREGPM Reserved bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 VREGPM: Voltage Regulator Power Mode Selection bit 1 = Low-Power Sleep mode enabled in Sleep(2) Draws lowest current in Sleep, slower wake-up 0 = Normal-Power mode enabled in Sleep(2) Draws higher current in Sleep, faster wake-up bit 0 Reserved: Read as ‘1’. Maintain this bit set. Note 1: 2: PIC16F1705/9 only. See Section 32.0 “Electrical Specifications”. TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 146 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 146 Name INTCON — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 147 IOCBP(1) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 147 (1) IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 148 IOCBF(1) IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 148 IOCCP IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 149 IOCCN IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 149 IOCCF IOCCF7(1) IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 149 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 86 PIE3 — — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE 87 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 89 IOCAF PIR3 — — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF 90 STATUS — — — TO PD Z DC C 22 VREGCON(2) — — — — — — VREGPM Reserved 95 WDTCON — — SWDTEN 99 Legend: Note 1: 2: WDTPS<4:0> — = unimplemented location, read as ‘0’. Shaded cells are not used in Power-Down mode. PIC16(L)F1709 only. PIC16F1705/9 only. 2013-2015 Microchip Technology Inc. DS40001729C-page 95 PIC16(L)F1705/9 9.0 WATCHDOG TIMER (WDT) The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The Watchdog Timer is typically used to recover the system from unexpected events. The WDT has the following features: • Independent clock source • Multiple operating modes - WDT is always on - WDT is off when in Sleep - WDT is controlled by software - WDT is always off • Configurable time-out period is from 1 ms to 256 seconds (nominal) • Multiple Reset conditions • Operation during Sleep FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> = 01 SWDTEN WDTE<1:0> = 11 LFINTOSC 23-bit Programmable Prescaler WDT WDT Time-out WDTE<1:0> = 10 Sleep DS40001729C-page 96 WDTPS<4:0> 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 9.1 Independent Clock Source 9.4 The WDT derives its time base from the 31 kHz LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See Table : for the LFINTOSC specification. 9.2 WDT Operating Modes The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration Words. See Table 9-1. 9.2.1 WDT IS ALWAYS ON WDT protection is active during Sleep. WDT IS OFF IN SLEEP WDT protection is not active during Sleep. WDT CONTROLLED BY SOFTWARE When the WDTE bits of Configuration Words are set to ‘01’, the WDT is controlled by the SWDTEN bit of the WDTCON register. WDT protection is unchanged by Sleep. See Table 9-1 for more details. TABLE 9-1: • • • • • • • Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep Oscillator fail WDT is disabled Oscillator Start-up Timer (OST) is running 9.5 Operation During Sleep When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting. When the WDTE bits of Configuration Words are set to ‘10’, the WDT is on, except in Sleep. 9.2.3 The WDT is cleared when any of the following conditions occur: See Table 9-2 for more information. When the WDTE bits of Configuration Words are set to ‘11’, the WDT is always on. 9.2.2 Clearing the WDT When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for more information on the OST. When a WDT time-out occurs while the device is in Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the event. See STATUS Register (Register 3-1) for more information. WDT OPERATING MODES WDTE<1:0> SWDTEN Device Mode 11 X X 10 X WDT Mode Active Awake Active 1 01 Sleep X 0 00 9.3 X X Disabled Active Disabled Disabled Time-Out Period The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal). After a Reset, the default time-out period is two seconds. 2013-2015 Microchip Technology Inc. DS40001729C-page 97 PIC16(L)F1705/9 TABLE 9-2: WDT CLEARING CONDITIONS Conditions WDT WDTE<1:0> = 00 WDTE<1:0> = 01 and SWDTEN = 0 WDTE<1:0> = 10 and enter Sleep CLRWDT Command Cleared Oscillator Fail Detected Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep + System Clock = XT, HS, LP Change INTOSC divider (IRCF bits) DS40001729C-page 98 Cleared until the end of OST Unaffected 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 9.6 Register Definitions: Watchdog Control REGISTER 9-1: U-0 WDTCON: WATCHDOG TIMER CONTROL REGISTER U-0 — R/W-0/0 R/W-1/1 R/W-0/0 R/W-1/1 R/W-1/1 (1) — WDTPS<4:0> bit 7 R/W-0/0 SWDTEN bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -m/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-1 WDTPS<4:0>: Watchdog Timer Period Select bits(1) Bit Value = Prescale Rate 11111 = Reserved. Results in minimum interval (1:32) • • • 10011 = Reserved. Results in minimum interval (1:32) 10010 10001 10000 01111 01110 01101 01100 01011 01010 01001 01000 00111 00110 00101 00100 00011 00010 00001 00000 bit 0 Note 1: = = = = = = = = = = = = = = = = = = = 1:8388608 (223) (Interval 256s nominal) 1:4194304 (222) (Interval 128s nominal) 1:2097152 (221) (Interval 64s nominal) 1:1048576 (220) (Interval 32s nominal) 1:524288 (219) (Interval 16s nominal) 1:262144 (218) (Interval 8s nominal) 1:131072 (217) (Interval 4s nominal) 1:65536 (Interval 2s nominal) (Reset value) 1:32768 (Interval 1s nominal) 1:16384 (Interval 512 ms nominal) 1:8192 (Interval 256 ms nominal) 1:4096 (Interval 128 ms nominal) 1:2048 (Interval 64 ms nominal) 1:1024 (Interval 32 ms nominal) 1:512 (Interval 16 ms nominal) 1:256 (Interval 8 ms nominal) 1:128 (Interval 4 ms nominal) 1:64 (Interval 2 ms nominal) 1:32 (Interval 1 ms nominal) SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 1x: This bit is ignored. If WDTE<1:0> = 01: 1 = WDT is turned on 0 = WDT is turned off If WDTE<1:0> = 00: This bit is ignored. Times are approximate. WDT time is based on 31 kHz LFINTOSC. 2013-2015 Microchip Technology Inc. DS40001729C-page 99 PIC16(L)F1705/9 TABLE 9-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Bit 7 Bit 6 OSCCON SPLLEN STATUS — — WDTCON — — Bit 5 Bit 4 Bit 3 IRCF<3:0> — Bit 2 Bit 1 — TO PD Bit 0 SCS<1:0> Z DC WDTPS<4:0> Register on Page 76 C 22 SWDTEN 99 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by Watchdog Timer. TABLE 9-4: Name CONFIG1 Bits SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 IESO CLKOUTEN 13:8 — — FCMEN 7:0 CP MCLRE PWRTE WDTE<1:0> Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> FOSC<2:0> — Register on Page 48 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Watchdog Timer. DS40001729C-page 100 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 10.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation over the full VDD range. Program memory is indirectly addressed using Special Function Registers (SFRs). The SFRs used to access program memory are: • • • • • • PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH When accessing the program memory, the PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the PMADRH:PMADRL register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read. The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. The Flash program memory can be protected in two ways; by code protection (CP bit in Configuration Words) and write protection (WRT<1:0> bits in Configuration Words). Code protection (CP = 0)(1), disables access, reading and writing, to the Flash program memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all Flash program memory, Configuration bits and User IDs. Write protection prohibits self-write and erase to a portion or all of the Flash program memory as defined by the bits WRT<1:0>. Write protection does not affect a device programmers ability to read, write or erase the device. Note 1: Code protection of the entire Flash program memory array is enabled by clearing the CP bit of Configuration Words. 10.1 PMADRL and PMADRH Registers The PMADRH:PMADRL register pair can address up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register. 2013-2015 Microchip Technology Inc. 10.1.1 PMCON1 AND PMCON2 REGISTERS PMCON1 is the control register for Flash program memory accesses. Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared by hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation. The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine. The PMCON2 register is a write-only register. Attempting to read the PMCON2 register will return all ‘0’s. To enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the PMCON2 register. The required unlock sequence prevents inadvertent writes to the program memory write latches and Flash program memory. 10.2 Flash Program Memory Overview It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum size that can be erased by user software. After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the PMDATH:PMDATL register pair. Note: If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase. Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations. See Table 10-1 for Erase Row size and the number of write latches for Flash program memory. DS40001729C-page 101 PIC16(L)F1705/9 TABLE 10-1: FLASH MEMORY ORGANIZATION BY DEVICE Device PIC16(L)F1705 PIC16(L)F1709 10.2.1 Row Erase (words) Write Latches (words) 32 32 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must: 1. 2. 3. Write the desired address to the PMADRH:PMADRL register pair. Clear the CFGS bit of the PMCON1 register. Then, set control bit RD of the PMCON1 register. Once the read control bit is set, the program memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF PMCON1,RD” instruction to be ignored. The data is available in the very next cycle, in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions. PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user. Note: The two instructions following a program memory read are required to be NOPs. This prevents the user from executing a 2-cycle instruction on the next instruction after the RD bit is set. FIGURE 10-1: FLASH PROGRAM MEMORY READ FLOWCHART Start Read Operation Select Program or Configuration Memory (CFGS) Select Word Address (PMADRH:PMADRL) Initiate Read operation (RD = 1) Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced Data read now in PMDATH:PMDATL End Read Operation DS40001729C-page 102 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PC Flash ADDR Flash Data PC + 1 INSTR (PC) INSTR(PC - 1) executed here PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD executed here PC +3 PC+3 PMDATH,PMDATL INSTR(PC + 1) instruction ignored Forced NOP executed here PC + 5 PC + 4 INSTR (PC + 3) INSTR(PC + 2) instruction ignored Forced NOP executed here INSTR (PC + 4) INSTR(PC + 3) executed here INSTR(PC + 4) executed here RD bit PMDATH PMDATL Register EXAMPLE 10-1: FLASH PROGRAM MEMORY READ * This code block will read 1 word of program * memory at the memory address: PROG_ADDR_HI : PROG_ADDR_LO * data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF MOVLW MOVWF PMADRL PROG_ADDR_LO PMADRL PROG_ADDR_HI PMADRH ; Select Bank for PMCON registers ; ; Store LSB of address ; ; Store MSB of address BCF BSF NOP NOP PMCON1,CFGS PMCON1,RD ; ; ; ; Do not select Configuration Space Initiate read Ignored (Figure 10-1) Ignored (Figure 10-1) MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location 2013-2015 Microchip Technology Inc. DS40001729C-page 103 PIC16(L)F1705/9 10.2.2 FLASH MEMORY UNLOCK SEQUENCE The unlock sequence is a mechanism that protects the Flash program memory from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations: • Row Erase • Load program memory write latches • Write of program memory write latches to program memory • Write of program memory write latches to User IDs The unlock sequence consists of the following steps: FIGURE 10-3: FLASH PROGRAM MEMORY UNLOCK SEQUENCE FLOWCHART Start Unlock Sequence Write 055h to PMCON2 Write 0AAh to PMCON2 1. Write 55h to PMCON2 2. Write AAh to PMCON2 3. Set the WR bit in PMCON1 Initiate Write or Erase operation (WR = 1) 4. NOP instruction 5. NOP instruction Once the WR bit is set, the processor will always force two NOP instructions. When an Erase Row or Program Row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. When the operation is loading the program memory write latches, the processor will always force the two NOP instructions and continue uninterrupted with the next instruction. Instruction Fetched ignored NOP execution forced Instruction Fetched ignored NOP execution forced End Unlock Sequence Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. DS40001729C-page 104 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 10.2.3 ERASING FLASH PROGRAM MEMORY While executing code, program memory can only be erased by rows. To erase a row: 1. 2. 3. 4. 5. Load the PMADRH:PMADRL register pair with any address within the row to be erased. Clear the CFGS bit of the PMCON1 register. Set the FREE and WREN bits of the PMCON1 register. Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence). Set control bit WR of the PMCON1 register to begin the erase operation. See Example 10-2. After the “BSF PMCON1,WR” instruction, the processor requires two cycles to set up the erase operation. The user must place two NOP instructions immediately following the WR bit set instruction. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. FIGURE 10-4: FLASH PROGRAM MEMORY ERASE FLOWCHART Start Erase Operation Disable Interrupts (GIE = 0) Select Program or Configuration Memory (CFGS) Select Row Address (PMADRH:PMADRL) Select Erase Operation (FREE = 1) Enable Write/Erase Operation (WREN = 1) Unlock Sequence Figure 10-3 (FIGURE x-x) CPU stalls while Erase operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Erase Operation 2013-2015 Microchip Technology Inc. DS40001729C-page 105 PIC16(L)F1705/9 EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY Required Sequence ; This row erase routine assumes the following: ; 1. A valid address within the erase row is loaded in ADDRH:ADDRL ; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF BCF BSF BSF INTCON,GIE PMADRL ADDRL,W PMADRL ADDRH,W PMADRH PMCON1,CFGS PMCON1,FREE PMCON1,WREN MOVLW MOVWF MOVLW MOVWF BSF NOP NOP 55h PMCON2 0AAh PMCON2 PMCON1,WR BCF BSF DS40001729C-page 106 PMCON1,WREN INTCON,GIE ; Disable ints so required sequences will execute properly ; Load lower 8 bits of erase address boundary ; Load upper 6 bits of erase address boundary ; Not configuration space ; Specify an erase operation ; Enable writes ; ; ; ; ; ; ; ; ; ; Start of required sequence to initiate erase Write 55h Write AAh Set WR bit to begin erase NOP instructions are forced as processor starts row erase of program memory. The processor stalls until the erase process is complete after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 10.2.4 WRITING TO FLASH PROGRAM MEMORY Program memory is programmed using the following steps: 1. 2. 3. 4. Load the address in PMADRH:PMADRL of the row to be programmed. Load each write latch with data. Initiate a programming operation. Repeat steps 1 through 3 until all data is written. The following steps should be completed to load the write latches and program a row of program memory. These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO = 1. When the last word to be loaded into the write latch is ready, the LWLO bit is cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash program memory. Note: Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write. Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See Figure 10-5 (row writes to program memory with 32 write latches) for more details. The write latches are aligned to the Flash row address boundary defined by the upper 10-bits of PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) with the lower five bits of PMADRL, (PMADRL<4:0>) determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF. The special unlock sequence is required to load a write latch with data or initiate a Flash programming operation. If the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. 1. 2. 3. Set the WREN bit of the PMCON1 register. Clear the CFGS bit of the PMCON1 register. Set the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is ‘1’, the write sequence will only load the write latches and will not initiate the write to Flash program memory. 4. Load the PMADRH:PMADRL register pair with the address of the location to be written. 5. Load the PMDATH:PMDATL register pair with the program memory data to be written. 6. Execute the unlock sequence (Section 10.2.2 “Flash Memory Unlock Sequence”). The write latch is now loaded. 7. Increment the PMADRH:PMADRL register pair to point to the next location. 8. Repeat steps 5 through 7 until all but the last write latch has been loaded. 9. Clear the LWLO bit of the PMCON1 register. When the LWLO bit of the PMCON1 register is ‘0’, the write sequence will initiate the write to Flash program memory. 10. Load the PMDATH:PMDATL register pair with the program memory data to be written. 11. Execute the unlock sequence (Section 10.2.2 “Flash Memory Unlock Sequence”). The entire program memory latch content is now written to Flash program memory. Note: The program memory write latches are reset to the blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state. An example of the complete write sequence is shown in Example 10-3. The initial address is loaded into the PMADRH:PMADRL register pair; the data is loaded using indirect addressing. 2013-2015 Microchip Technology Inc. DS40001729C-page 107 7 BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES 6 0 7 5 4 PMADRH - r9 r8 r7 r6 r5 0 7 PMADRL r4 r3 r2 r1 r0 c4 c3 c2 c1 - 5 - 0 7 PMDATH PMDATL 6 c0 Rev. 10-000004A_A0 0 8 14 Program Memory Write Latches 5 10 14 PMADRL<4:0> Write Latch #0 00h 14 CFGS = 0 2013-2015 Microchip Technology Inc. PMADRH<6:0>: PMADRL<7:5> Row Address Decode 14 14 Write Latch #1 01h 14 Write Latch #30 1Eh 14 Write Latch #31 1Fh 14 14 Row Addr Addr Addr Addr 000h 0000h 0001h 001Eh 001Fh 001h 0020h 0021h 003Eh 003Fh 002h 0040h 0041h 005Eh 005Fh 3FEh 7FC0h 7FC1h 7FDEh 7FDFh 3FFh 7FE0h 7FE1h 7FFEh 7FFFh Flash Program Memory 400h CFGS = 1 8000h - 8003h 8004h – 8005h 8006h 8007h – 8008h 8009h - 801Fh USER ID 0 - 3 reserved DEVICE ID Dev / Rev Configuration Words reserved Configuration Memory PIC16(L)F1705/9 DS40001729C-page 108 FIGURE 10-5: PIC16(L)F1705/9 FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART Start Write Operation Determine number of words to be written into Program or Configuration Memory. The number of words cannot exceed the number of words per row. (word_cnt) Disable Interrupts (GIE = 0) Select Program or Config. Memory (CFGS) Select Row Address (PMADRH:PMADRL) Enable Write/Erase Operation (WREN = 1) Load the value to write (PMDATH:PMDATL) Update the word counter (word_cnt--) Last word to write ? Yes No Unlock Sequence (Figure10-3 x-x) Figure Select Write Operation (FREE = 0) No delay when writing to Program Memory Latches Load Write Latches Only (LWLO = 1) Increment Address (PMADRH:PMADRL++) Write Latches to Flash (LWLO = 0) Unlock Sequence (Figure10-3 x-x) Figure CPU stalls while Write operation completes (2ms typical) Disable Write/Erase Operation (WREN = 0) Re-enable Interrupts (GIE = 1) End Write Operation 2013-2015 Microchip Technology Inc. DS40001729C-page 109 PIC16(L)F1705/9 EXAMPLE 10-3: ; ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR, stored in little endian format 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM) BCF BANKSEL MOVF MOVWF MOVF MOVWF MOVLW MOVWF MOVLW MOVWF BCF BSF BSF INTCON,GIE PMADRH ADDRH,W PMADRH ADDRL,W PMADRL LOW DATA_ADDR FSR0L HIGH DATA_ADDR FSR0H PMCON1,CFGS PMCON1,WREN PMCON1,LWLO ; ; ; ; ; ; ; ; ; ; ; ; ; Disable ints so required sequences will execute properly Bank 3 Load initial address MOVIW MOVWF MOVIW MOVWF FSR0++ PMDATL FSR0++ PMDATH ; Load first data byte into lower ; ; Load second data byte into upper ; MOVF XORLW ANDLW BTFSC GOTO PMADRL,W 0x1F 0x1F STATUS,Z START_WRITE ; Check if lower bits of address are '00000' ; Check if we're on the last of 32 addresses ; ; Exit if last of 32 words, ; MOVLW MOVWF MOVLW MOVWF BSF NOP 55h PMCON2 0AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; PMADRL,F LOOP ; Still loading latches Increment address ; Write next latches PMCON1,LWLO ; No more loading latches - Actually start Flash program ; memory write 55h PMCON2 0AAh PMCON2 PMCON1,WR ; ; ; ; ; ; ; ; ; ; ; ; ; Load initial data address Load initial data address Not configuration space Enable writes Only Load Write Latches Required Sequence LOOP NOP INCF GOTO Required Sequence START_WRITE BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF BSF DS40001729C-page 110 PMCON1,WREN INTCON,GIE Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor loads program memory write latches Start of required write sequence: Write 55h Write AAh Set WR bit to begin write NOP instructions are forced as processor writes all the program memory write latches simultaneously to program memory. After NOPs, the processor stalls until the self-write process in complete after write processor continues with 3rd instruction Disable writes Enable interrupts 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 10.3 Modifying Flash Program Memory When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps: 1. 2. 3. 4. 5. 6. 7. Load the starting address of the row to be modified. Read the existing data from the row into a RAM image. Modify the RAM image to contain the new data to be written into program memory. Load the starting address of the row to be rewritten. Erase the program memory row. Load the write latches with data from the RAM image. Initiate a programming operation. FIGURE 10-7: FLASH PROGRAM MEMORY MODIFY FLOWCHART Start Modify Operation Read Operation (Figure10-1 x.x) Figure An image of the entire row read must be stored in RAM Modify Image The words to be modified are changed in the RAM image Erase Operation (Figure10-4 x.x) Figure Write Operation use RAM image (Figure10-6 x.x) Figure End Modify Operation 2013-2015 Microchip Technology Inc. DS40001729C-page 111 PIC16(L)F1705/9 10.4 User ID, Device ID and Configuration Word Access Instead of accessing program memory, the User ID’s, Device ID/Revision ID and Configuration Words can be accessed when CFGS = 1 in the PMCON1 register. This is the region that would be pointed to by PC<15> = 1, but not all addresses are accessible. Different access may exist for reads and writes. Refer to Table 10-2. When read access is initiated on an address outside the parameters listed in Table 10-2, the PMDATH:PMDATL register pair is cleared, reading back ‘0’s. TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS = 1) Address Function Read Access Write Access 8000h-8003h 8005h-8006h 8007h-8008h User IDs Device ID/Revision ID Configuration Words 1 and 2 Yes Yes Yes Yes No No EXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS * This code block will read 1 word of program memory at the memory address: * PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables; * PROG_DATA_HI, PROG_DATA_LO BANKSEL MOVLW MOVWF CLRF PMADRL PROG_ADDR_LO PMADRL PMADRH ; Select correct Bank ; ; Store LSB of address ; Clear MSB of address BSF BCF BSF NOP NOP BSF PMCON1,CFGS INTCON,GIE PMCON1,RD INTCON,GIE ; ; ; ; ; ; Select Configuration Space Disable interrupts Initiate read Executed (See Figure 10-2) Ignored (See Figure 10-2) Restore interrupts MOVF MOVWF MOVF MOVWF PMDATL,W PROG_DATA_LO PMDATH,W PROG_DATA_HI ; ; ; ; Get LSB of word Store in user location Get MSB of word Store in user location DS40001729C-page 112 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 10.5 Write/Verify It is considered good programming practice to verify that program memory writes agree with the intended value. Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete. FIGURE 10-8: FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of data written was from an image saved in RAM. This image will be used to verify the data currently stored in Flash Program Memory. Read Operation (Figure x.x) Figure 10-1 PMDAT = RAM image ? Yes No No Fail Verify Operation Last Word ? Yes End Verify Operation 2013-2015 Microchip Technology Inc. DS40001729C-page 113 PIC16(L)F1705/9 10.6 Register Definitions: Flash Program Memory Control REGISTER 10-1: R/W-x/u PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMDAT<7:0>: Read/write value for Least Significant bits of program memory REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PMDAT<13:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PMDAT<13:8>: Read/write value for Most Significant bits of program memory REGISTER 10-3: R/W-0/0 PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PMADR<7:0>: Specifies the Least Significant bits for program memory address DS40001729C-page 114 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 10-4: U-1 PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 —(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 PMADR<14:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘1’ bit 6-0 PMADR<14:8>: Specifies the Most Significant bits for program memory address Note 1: Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001729C-page 115 PIC16(L)F1705/9 REGISTER 10-5: U-1 PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER R/W-0/0 (1) — CFGS R/W-0/0 LWLO R/W/HC-0/0 R/W/HC-x/q(2) R/W-0/0 R/S/HC-0/0 R/S/HC-0/0 FREE WRERR WREN WR RD (3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 Unimplemented: Read as ‘1’ bit 6 CFGS: Configuration Select bit 1 = Access Configuration, User ID and Device ID Registers 0 = Access Flash program memory bit 5 LWLO: Load Write Latches Only bit(3) 1 = Only the addressed program memory write latch is loaded/updated on the next WR command 0 = The addressed program memory write latch is loaded/updated and a write of all program memory write latches will be initiated on the next WR command bit 4 FREE: Program Flash Erase Enable bit 1 = Performs an erase operation on the next WR command (hardware cleared upon completion) 0 = Performs a write operation on the next WR command bit 3 WRERR: Program/Erase Error Flag bit 1 = Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘1’) of the WR bit). 0 = The program or erase operation completed normally bit 2 WREN: Program/Erase Enable bit 1 = Allows program/erase cycles 0 = Inhibits programming/erasing of program Flash bit 1 WR: Write Control bit 1 = Initiates a program Flash program/erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. The WR bit can only be set (not cleared) in software. 0 = Program/erase operation to the Flash is complete and inactive bit 0 RD: Read Control bit 1 = Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a program Flash read Note 1: 2: 3: Unimplemented bit, read as ‘1’. The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR = 1). The LWLO bit is ignored during a program memory erase operation (FREE = 1). DS40001729C-page 116 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 10-6: W-0/0 PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 W-0/0 Program Memory Control Register 2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ S = Bit can only be set x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Flash Memory Unlock Pattern bits To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the PMCON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes. TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY Register on Page Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PMCON1 —(1) CFGS LWLO FREE WRERR WREN WR RD 116 PMCON2 Program Memory Control Register 2 117 PMADRL<7:0> 114 PMADRL PMADRH —(1) PMADRH<6:0> PMDATL 115 PMDATL<7:0> — PMDATH — 114 PMDATH<5:0> 114 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory. Note 1: Unimplemented, read as ‘1’. TABLE 10-4: Name CONFIG1 CONFIG2 Legend: SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 — — — — CLKOUTEN 7:0 CP MCLRE PWRTE 13:8 — — LVP DEBUG LPBOR BORV 7:0 ZCDDIS — — — — PPS1WAY WDTE<1:0> Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> — — FOSC<1:0> STVREN PLLEN WRT<1:0> Register on Page 48 50 — = unimplemented location, read as ‘0’. Shaded cells are not used by Flash program memory. 2013-2015 Microchip Technology Inc. DS40001729C-page 117 PIC16(L)F1705/9 11.0 I/O PORTS FIGURE 11-1: GENERIC I/O PORT OPERATION Each port has six standard registers for its operation. These registers are: • TRISx registers (data direction) • PORTx registers (reads the levels on the pins of the device) • LATx registers (output latch) • INLVLx (input level control) • ODCONx registers (open-drain) • SLRCONx registers (slew rate Some ports may have one or more of the following additional registers. These registers are: D Write LATx Write PORTx TRISx Q CK VDD Data Register Data Bus I/O pin • ANSELx (analog select) • WPUx (weak pull-up) Read PORTx In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. However, the pin can still be read. To digital peripherals To analog peripherals ANSELx VSS PIC16(L)F1705 ● PIC16(L)F1709 ● PORTC Device PORTB PORT AVAILABILITY PER DEVICE PORTA TABLE 11-1: Read LATx ● ● ● The Data Latch (LATx registers) is useful for read-modify-write operations on the value that the I/O pins are driving. A write operation to the LATx register has the same effect as a write to the corresponding PORTx register. A read of the LATx register reads of the values held in the I/O PORT latches, while a read of the PORTx register reads the actual I/O pin value. Ports that support analog inputs have an associated ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled. Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 11-1. DS40001729C-page 118 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 11.1 11.1.1 PORTA Registers DATA REGISTER PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 11-2). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input-only and its TRIS bit will always read as ‘1’. Example 11-1 shows how to initialize PORTA. 11.1.5 The INLVLA register (Register 11-8) controls the input voltage threshold for each of the available PORTA input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTA register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 32-4: I/O Ports for more information on threshold levels. Note: Reading the PORTA register (Register 11-1) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA). 11.1.2 DIRECTION CONTROL The TRISA register (Register 11-2) controls the PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 11.1.3 OPEN-DRAIN CONTROL The ODCONA register (Register 11-6) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONA bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONA bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.1.4 SLEW RATE CONTROL The SLRCONA register (Register 11-7) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONA bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONA bit is cleared, The corresponding port pin drive slews at the maximum rate possible. 2013-2015 Microchip Technology Inc. INPUT THRESHOLD CONTROL 11.1.6 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELA register (Register 11-4) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. EXAMPLE 11-1: ; ; ; ; INITIALIZING PORTA This code example illustrates initializing the PORTA register. The other ports are initialized in the same manner. BANKSEL CLRF BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTA PORTA LATA LATA ANSELA ANSELA TRISA B'00111000' TRISA ; ;Init PORTA ;Data Latch ; ; ;digital I/O ; ;Set RA<5:3> as inputs ;and set RA<2:0> as ;outputs DS40001729C-page 119 PIC16(L)F1705/9 11.1.7 PORTA FUNCTIONS AND OUTPUT PRIORITIES Each PORTA pin is multiplexed with other functions. Each pin defaults to the PORT latch data after Reset. Other functions are selected with the peripheral pin select logic. See Section 12.0 “Peripheral Pin Select (PPS) Module” for more information. Analog input functions, such as ADC and comparator inputs are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELA register. Digital output functions may continue to control the pin when it is in Analog mode. DS40001729C-page 120 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 11.2 Register Definitions: PORTA REGISTER 11-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x/x R/W-x/x R-x/x R/W-x/x R/W-x/x R/W-x/x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Value bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 11-2: TRISA: PORTA TRI-STATE REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-1 R/W-1/1 R/W-1/1 R/W-1/1 — — TRISA5 TRISA4 —(1) TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 TRISA<5:4>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output bit 3 Unimplemented: Read as ‘1’ bit 2-0 TRISA<2:0>: PORTA Tri-State Control bit 1 = PORTA pin configured as an input (tri-stated) 0 = PORTA pin configured as an output Note 1: Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001729C-page 121 PIC16(L)F1705/9 REGISTER 11-3: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x/u R/W-x/u U-0 R/W-x/u R/W-x/u R/W-x/u — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA<5:4>: RA<5:4> Output Latch Value bits(1) bit 3 Unimplemented: Read as ‘0’ bit 2-0 LATA<2:0>: RA<2:0> Output Latch Value bits(1) Note 1: Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values. REGISTER 11-4: ANSELA: PORTA ANALOG SELECT REGISTER U-0 U-0 U-0 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — — ANSA4 — ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4 ANSA4: Analog Select between Analog or Digital Function on pin RA4 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. bit 3 Unimplemented: Read as ‘0’ bit 2-0 ANSA<2:0>: Analog Select between Analog or Digital Function on pins RA<2:0>, respectively 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. 0 = Digital I/O. Pin is assigned to port or digital special function. Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS40001729C-page 122 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 11-5: WPUA: WEAK PULL-UP PORTA REGISTER U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 — — WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 WPUA<5:0>: Weak Pull-up Register bits(1),(2) 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. REGISTER 11-6: ODCONA: PORTA OPEN-DRAIN CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 — — ODA5 ODA4 — ODA2 ODA1 ODA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 ODA<5:4>: PORTA Open-Drain Enable bits For RA<5:4> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) bit 3 Unimplemented: Read as ‘0’ bit 2-0 ODA<2:0>: PORTA Open-Drain Enable bits For RA<2:0> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) 2013-2015 Microchip Technology Inc. DS40001729C-page 123 PIC16(L)F1705/9 REGISTER 11-7: SLRCONA: PORTA SLEW RATE CONTROL REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-0 R/W-1/1 R/W-1/1 R/W-1/1 — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 SLRA<5:4>: PORTA Slew Rate Enable bits For RA<5:4> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate bit 3 Unimplemented: Read as ‘0’ bit 2-0 SLRA<2:0>: PORTA Slew Rate Enable bits For RA<2:0> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate REGISTER 11-8: INLVLA: PORTA INPUT LEVEL CONTROL REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 INLVLA<5:0>: PORTA Input Level Select bits For RA<5:0> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change DS40001729C-page 124 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 11-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122 INLVLA — — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 124 LATA — — LATA5 LATA4 — LATA2 LATA1 LATA0 122 ODA5 ODA4 — ODA2 ODA1 ODA0 123 Name — — WPUEN INTEDG PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 121 SLRCONA — — SLRA5 SLRA4 — SLRA2 SLRA1 SLRA0 124 ODCONA OPTION_REG TMR0CS TMR0SE TRISA — — TRISA5 TRISA4 WPUA — — WPUA5 WPUA4 PSA (1) — WPUA3 PS<2:0> 245 TRISA2 TRISA1 TRISA0 121 WPUA2 WPUA1 WPUA0 123 Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. Note 1: Unimplemented, read as ‘1’. TABLE 11-3: Name CONFIG1 Legend: SUMMARY OF CONFIGURATION WORD WITH PORTA Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 13:8 — — FCMEN IESO CLKOUTEN 7:0 CP MCLRE PWRTE Bit 10/2 Bit 9/1 Bit 8/0 BOREN<1:0> WDTE<1:0> — FOSC<2:0> Register on Page 48 — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. 2013-2015 Microchip Technology Inc. DS40001729C-page 125 PIC16(L)F1705/9 11.3 PORTB Registers (PIC16(L)F1709 only) PORTB is a 4-bit wide, bidirectional port. The corresponding data direction register is TRISB (Register 11-10). Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 11-1 shows how to initialize an I/O port. 11.3.4 The INLVLB register (Register 11-16) controls the input voltage threshold for each of the available PORTB input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTB register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 32-4: I/O Ports for more information on threshold levels. Note: Reading the PORTB register (Register 11-9) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATB). 11.3.1 DIRECTION CONTROL The TRISB register (Register 11-10) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 11.3.2 OPEN-DRAIN CONTROL The ODCONB register (Register 11-14) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONB bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONB bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.3.3 11.3.5 DS40001729C-page 126 Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. ANALOG CONTROL The ANSELB register (Register 11-12) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: SLEW RATE CONTROL The SLRCONB register (Register 11-15) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONB bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONB bit is cleared, The corresponding port pin drive slews at the maximum rate possible. INPUT THRESHOLD CONTROL 11.3.6 The ANSELB bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. PORTB FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after Reset. Other functions are selected with the peripheral pin select logic. See Section 12.0 “Peripheral Pin Select (PPS) Module” for more information. Analog input functions, such as ADC and op amp inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELB register. Digital output functions may continue to control the pin when it is in Analog mode. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 11.4 Register Definitions: PORTB REGISTER 11-9: PORTB: PORTB REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 RB7 RB6 RB5 RB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 RB<7:4>: PORTB General Purpose I/O Pin bits(1) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 3-0 Unimplemented: Read as ‘0’ Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 11-10: TRISB: PORTB TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 TRISB7 TRISB6 TRISB5 TRISB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 TRISB<7:4>: PORTB Tri-State Control bits 1 = PORTB pin configured as an input (tri-stated) 0 = PORTB pin configured as an output bit 3-0 Unimplemented: Read as ‘0’ 2013-2015 Microchip Technology Inc. DS40001729C-page 127 PIC16(L)F1705/9 REGISTER 11-11: LATB: PORTB DATA LATCH REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u U-0 U-0 U-0 U-0 LATB7 LATB6 LATB5 LATB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 LATB<7:4>: PORTB Output Latch Value bits(1) bit 3-0 Unimplemented: Read as ‘0’ Note 1: Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values. REGISTER 11-12: ANSELB: PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 — — ANSB5 ANSB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 ANSB<5:4>: Analog Select between Analog or Digital Function on pins RB<5:4>, respectively 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 3-0 Unimplemented: Read as ‘0’ Note 1: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. DS40001729C-page 128 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 11-13: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 WPUB7 WPUB6 WPUB5 WPUB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Register bits 1 = Pull-up enabled 0 = Pull-up disabled bit 3-0 Unimplemented: Read as ‘0’ Note 1: 2: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. REGISTER 11-14: ODCONB: PORTB OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 ODB7 ODB6 ODB5 ODB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 ODB<7:4>: PORTB Open-Drain Enable bits For RB<7:4> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) bit 3-0 Unimplemented: Read as ‘0’ 2013-2015 Microchip Technology Inc. DS40001729C-page 129 PIC16(L)F1705/9 REGISTER 11-15: SLRCONB: PORTB SLEW RATE CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 U-0 U-0 U-0 U-0 SLRB7 SLRB6 SLRB5 SLRB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 SLRB<7:4>: PORTB Slew Rate Enable bits For RB<7:4> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate bit 3-0 Unimplemented: Read as ‘0’ REGISTER 11-16: INLVLB: PORTB INPUT LEVEL CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 INLVLB<7:4>: PORTB Input Level Select bits For RB<7:4> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change bit 3-0 Unimplemented: Read as ‘0’ TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSB5 ANSB4 — — — — 128 INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 130 LATB LATB7 LATB6 LATB5 LATB4 — — — — 128 ODCONB ODB7 ODB6 ODB5 ODB4 — — — — 129 RB7 RB6 RB5 RB4 — — — — 127 SLRB7 SLRB6 SLRB5 SLRB4 — — — — 130 Name ANSELB INLVLB PORTB SLRCONB TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 130 WPUB WPUB7 WPUB6 WPUB5 WPUB4 — — — — 129 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTB. DS40001729C-page 130 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 11.5 11.5.1 PORTC Registers DATA REGISTER PORTC is a 6-bit wide bidirectional port in the PIC16(L)F1705 devices and 8-bit wide bidirectional port in the PIC16(L)F1709 devices. The corresponding data direction register is TRISC (Register 11-18). Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). Example 11-1 shows how to initialize an I/O port. Reading the PORTC register (Register 11-17) reads the status of the pins, whereas writing to it will write to the PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC). 11.5.2 DIRECTION CONTROL The TRISC register (Register 11-18) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog inputs always read ‘0’. 11.5.3 INPUT THRESHOLD CONTROL The INLVLC register (Register 11-24) controls the input voltage threshold for each of the available PORTC input pins. A selection between the Schmitt Trigger CMOS or the TTL Compatible thresholds is available. The input threshold is important in determining the value of a read of the PORTC register and also the level at which an interrupt-on-change occurs, if that feature is enabled. See Table 32-4: I/O Ports for more information on threshold levels. Note: Changing the input threshold selection should be performed while all peripheral modules are disabled. Changing the threshold level during the time a module is active may inadvertently generate a transition associated with an input pin, regardless of the actual voltage level on that pin. 2013-2015 Microchip Technology Inc. 11.5.4 OPEN-DRAIN CONTROL The ODCONC register (Register 11-22) controls the open-drain feature of the port. Open-drain operation is independently selected for each pin. When an ODCONC bit is set, the corresponding port output becomes an open-drain driver capable of sinking current only. When an ODCONC bit is cleared, the corresponding port output pin is the standard push-pull drive capable of sourcing and sinking current. 11.5.5 SLEW RATE CONTROL The SLRCONC register (Register 11-23) controls the slew rate option for each port pin. Slew rate control is independently selectable for each port pin. When an SLRCONC bit is set, the corresponding port pin drive is slew rate limited. When an SLRCONC bit is cleared, The corresponding port pin drive slews at the maximum rate possible. 11.5.6 ANALOG CONTROL The ANSELC register (Register 11-20) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELC bits has no effect on digital output functions. A pin with TRIS clear and ANSELC set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: 11.5.7 The ANSELC bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. PORTC FUNCTIONS AND OUTPUT PRIORITIES Each pin defaults to the PORT latch data after Reset. Other functions are selected with the peripheral pin select logic. See Section 12.0 “Peripheral Pin Select (PPS) Module” for more information. Analog input functions, such as ADC and comparator inputs, are not shown in the peripheral pin select lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELC register. Digital output functions may continue to control the pin when it is in Analog mode. DS40001729C-page 131 PIC16(L)F1705/9 11.6 Register Definitions: PORTC REGISTER 11-17: PORTC: PORTC REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u RC7(2) RC6(2) RC5 RC4 RC3 RC2 RC1 RC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared RC<7:0>: PORTC General Purpose I/O Pin bits(1, 2) 1 = Port pin is > VIH 0 = Port pin is < VIL bit 7-0 Note 1: 2: Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values. RC<7:6> are available on PIC16(L)F1709 only. REGISTER 11-18: TRISC: PORTC TRI-STATE REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: TRISC<7:0>: PORTC Tri-State Control bits(1) 1 = PORTC pin configured as an input (tri-stated) 0 = PORTC pin configured as an output TRISC<7:6> are available on PIC16(L)F1709 only. DS40001729C-page 132 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 11-19: LATC: PORTC DATA LATCH REGISTER R/W-x/u R/W-x/u (1) (1) LATC7 LATC6 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared LATC<7:0>: PORTC Output Latch Value bits(1) bit 7-0 Note 1: LATC<7:6> are available on PIC16(L)F1709 only. REGISTER 11-20: ANSELC: PORTC ANALOG SELECT REGISTER R/W-1/1 R/W-1/1 U-0 U-0 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 ANSC7(2) ANSC6(2) ANSC5(3) ANSC4(3) ANSC3 ANSC2 ANSC1 ANSC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared ANSC<7:0>: Analog Select between Analog or Digital Function on pins RC<7:0>, respectively(1) 0 = Digital I/O. Pin is assigned to port or digital special function. 1 = Analog input. Pin is assigned as analog input(1). Digital input buffer disabled. bit 7-0 Note 1: 2: 3: When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. ANSC<7:6> are available on PIC16(L)F1709 only. ANSC<5:4> are available on PIC16(L)F1705 only. 2013-2015 Microchip Technology Inc. DS40001729C-page 133 PIC16(L)F1705/9 REGISTER 11-21: WPUC: WEAK PULL-UP PORTC REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUC7(3) WPUC6(3) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared WPUC<7:0>: Weak Pull-up Register bits(1),(2) 1 = Pull-up enabled 0 = Pull-up disabled bit 7-0 Note 1: 2: 3: Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. The weak pull-up device is automatically disabled if the pin is configured as an output. WPUC<7:6> are available on PIC16(L)F1709 only. REGISTER 11-22: ODCONC: PORTC OPEN-DRAIN CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ODC7(1) ODC6(1) ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: ODC<7:0>: PORTC Open-Drain Enable bits(1) For RC<7:0> pins, respectively 1 = Port pin operates as open-drain drive (sink current only) 0 = Port pin operates as standard push-pull drive (source and sink current) ODC<7:6> are available on PIC16(L)F1709 only. DS40001729C-page 134 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 11-23: SLRCONC: PORTC SLEW RATE CONTROL REGISTER R/W-1/1 SLRC7 R/W-1/1 (1) SLRC6 (1) R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared SLRC<7:0>: PORTC Slew Rate Enable bits(1) For RC<7:0> pins, respectively 1 = Port pin slew rate is limited 0 = Port pin slews at maximum rate bit 7-0 Note 1: SLRC<7:6> are available on PIC16(L)F1709 only. REGISTER 11-24: INLVLC: PORTC INPUT LEVEL CONTROL REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 INLVLC7(1) INLVLC6(1) INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: INLVLC<7:0>: PORTC Input Level Select bits(1) For RC<7:0> pins, respectively 1 = ST input used for PORT reads and interrupt-on-change 0 = TTL input used for PORT reads and interrupt-on-change INLVLC<7:6> are available on PIC16(L)F1709 only. 2013-2015 Microchip Technology Inc. DS40001729C-page 135 PIC16(L)F1705/9 TABLE 11-5: Name ANSELC ANSC6(1) LATC7 (1) SLRCONC Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133 INLVLC1 INLVLC0 135 Bit 5 (1) INLVLC6 Bit 4 INLVLC5 INLVLC4 INLVLC3 INLVLC2 (1) LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 (1) LATC6 ODC5 ODC4 ODC3 ODC2 ODC1 ODC0 134 RC6(1) RC5 RC4 RC3 RC2 RC1 RC0 132 SLRC7(1) SLRC6(1) SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 135 (1) (1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 (1) WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 134 TRISC7 (1) WPUC7 ODC6 133 RC7(1) ODC7 PORTC Note 1: 2: ANSC7(1) (1) ODCONC Legend: Bit 6 INLVLC7 LATC WPUC Bit 7 (1) INLVLC TRISC SUMMARY OF REGISTERS ASSOCIATED WITH PORTC TRISC6 WPUC6 x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. PIC16(L)F1709 only. PIC16(L)F1705 only. DS40001729C-page 136 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 12.0 PERIPHERAL PIN SELECT (PPS) MODULE The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. Input and output selections are independent as shown in the simplified block diagram Figure 12-1. 12.1 PPS Inputs Each peripheral has a PPS register with which the inputs to the peripheral are selected. Inputs include the device pins. Multiple peripherals can operate from the same source simultaneously. Port reads always return the pin level regardless of peripheral PPS selection. If a pin also has associated analog functions, the ANSEL bit for that pin must be cleared to enable the digital input buffer. Although every peripheral has its own PPS input selection register, the selections are identical for every peripheral as shown in Register 12-1 for PIC16(L)F1705 devices and Register 12-2 for PIC16(L)F1709 devices. Note: 12.2 The notation “xxx” in the register name is a place holder for the peripheral identifier. For example, CLC1PPS. PPS Outputs Each I/O pin has a PPS register with which the pin output source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS control as needed. These peripherals include: • EUSART (synchronous operation) • MSSP (I2C) • COG (auto-shutdown) Although every pin has its own PPS peripheral selection register, the selections are identical for every pin as shown in Register 12-3. Note: FIGURE 12-1: The notation “Rxy” is a place holder for the pin identifier. For example, RA0PPS. SIMPLIFIED PPS BLOCK DIAGRAM PPS Outputs RA0PPS PPS Inputs abcPPS RA0 RA0 Peripheral abc RxyPPS Rxy Peripheral xyz RC7 xyzPPS 2013-2015 Microchip Technology Inc. RC7PPS RC7 DS40001729C-page 137 PIC16(L)F1705/9 12.3 Bidirectional Pins PPS selections for peripherals with bidirectional signals on a single pin must be made so that the PPS input and PPS output select the same pin. Peripherals that have bidirectional signals include: • EUSART (synchronous operation) • MSSP (I2C) Note: 12.4 The I2C default input pins are I2C and SMBus compatible and are the only pins on the device with this compatibility. PPS Permanent Lock The PPS can be permanently locked by setting the PPS1WAY Configuration bit. When this bit is set, the PPSLOCKED bit can only be cleared and set one time after a device Reset. This allows for clearing the PPSLOCKED bit so that the input and output selections can be made during initialization. When the PPSLOCKED bit is set after all selections have been made, it will remain set and cannot be cleared until after the next device Reset event. 12.6 Operation During Sleep PPS input and output selections are unaffected by Sleep. PPS Lock The PPS includes a mode in which all input and output selections can be locked to prevent inadvertent changes. PPS selections are locked by setting the PPSLOCKED bit of the PPSLOCK register. Setting and clearing this bit requires a special sequence as an extra precaution against inadvertent changes. Examples of setting and clearing the PPSLOCKED bit are shown in Example 12-1. EXAMPLE 12-1: 12.5 12.7 Effects of a Reset A device Power-On-Reset (POR) clears all PPS input and output selections to their default values. All other Resets leave the selections unchanged. Default input selections are shown in pin allocation Table and Table . PPS LOCK/UNLOCK SEQUENCE ; suspend interrupts bcf INTCON,GIE ; BANKSEL PPSLOCK ; set bank ; required sequence, next 5 instructions movlw 0x55 movwf PPSLOCK movlw 0xAA movwf PPSLOCK ; Set PPSLOCKED bit to disable writes or ; Clear PPSLOCKED bit to enable writes bsf PPSLOCK,PPSLOCKED ; restore interrupts bsf INTCON,GIE DS40001729C-page 138 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 12.8 Register Definitions: PPS Input Selection REGISTER 12-1: xxxPPS: PERIPHERAL xxx INPUT SELECTION (PIC16(L)F1705) U-0 U-0 U-0 — — — R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u xxxPPS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 xxxPPS<4:0>: Peripheral xxx Input Selection bits 11xxx = Reserved. Do not use. 1011x = Reserved. Do not use. 10101 = Peripheral input is RC5 10100 = Peripheral input is RC4 10011 = Peripheral input is RC3 10010 = Peripheral input is RC2 10001 = Peripheral input is RC1 10000 = Peripheral input is RC0 01xxx = Reserved. Do not use. 0011X = Reserved. Do not use. 00101 = Peripheral input is RA5 00100 = Peripheral input is RA4 00011 = Peripheral input is RA3 00010 = Peripheral input is RA2 00001 = Peripheral input is RA1 00000 = Peripheral input is RA0 2013-2015 Microchip Technology Inc. DS40001729C-page 139 PIC16(L)F1705/9 REGISTER 12-2: xxxPPS: PERIPHERAL xxx INPUT SELECTION (PIC16(L)F1709) U-0 U-0 U-0 — — — R/W-q/u R/W-q/u R/W-q/u R/W-q/u R/W-q/u xxxPPS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on peripheral bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 xxxPPS<4:0>: Peripheral xxx Input Selection bits 11xxx = Reserved. Do not use. 10111 = Peripheral input is RC7 10110 = Peripheral input is RC6 10101 = Peripheral input is RC5 10100 = Peripheral input is RC4 10011 = Peripheral input is RC3 10010 = Peripheral input is RC2 10001 = Peripheral input is RC1 10000 = Peripheral input is RC0 01111 = Peripheral input is RB7 01110 = Peripheral input is RB6 01101 = Peripheral input is RB5 01100 = Peripheral input is RB4 010xx = Reserved. Do not use. 0011X = Reserved. Do not use. 00101 = Peripheral input is RA5 00100 = Peripheral input is RA4 00011 = Peripheral input is RA3 00010 = Peripheral input is RA2 00001 = Peripheral input is RA1 00000 = Peripheral input is RA0 DS40001729C-page 140 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 12-3: RxyPPS: PIN Rxy OUTPUT SOURCE SELECTION REGISTER U-0 U-0 U-0 — — — R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W-0/u RxyPPS<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RxyPPS<4:0>: Pin Rxy Output Source Selection bits 11xxx = Reserved 10111 = Rxy source is C2OUT 10110 = Rxy source is C1OUT 10101 = Rxy source is DT(1) 10100 = Rxy source is TX/CK(1) 10011 = Reserved 10010 = Rxy source is SDO 10001 = Rxy source is SDA(1) 10000 = Rxy source is SCK/SCL(1) 01111 = Rxy source is PWM4OUT 01110 = Rxy source is PWM3OUT 01101 = Rxy source is CCP2 01100 = Rxy source is CCP1 01011 = Rxy source is COG1D(1) 01010 = Rxy source is COG1C(1) 01001 = Rxy source is COG1B(1) 01000 = Rxy source is COG1A(1) 00111 = Reserved 00110 = Rxy source is LC3OUT 00101 = Rxy source is LC2OUT 00100 = Rxy source is LC1OUT 00011 = Reserved 00010 = Reserved 00001 = Reserved 00000 = Rxy source is LATxy Note 1: TRIS control is overridden by the peripheral as required. 2013-2015 Microchip Technology Inc. DS40001729C-page 141 PIC16(L)F1705/9 REGISTER 12-4: PPSLOCK: PPS LOCK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0/0 — — — — — — — PPSLOCKED bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 Unimplemented: Read as ‘0’ bit 0 PPSLOCKED: PPS Locked bit 1 = PPS is locked. PPS selections can not be changed. 0 = PPS is not locked. PPS selections can be changed. DS40001729C-page 142 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 12-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE PPS MODULE Bit 2 Bit 1 Bit 0 Register on page — — PPSLOCKED 142 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 PPSLOCK — — — — — INTPPS — — — INTPPS<4:0> 140 T0CKIPPS — — — T0CKIPPS<4:0> 140 T1CKIPPS — — — T1CKIPPS<4:0> 140 T1GPPS — — — T1GPPS<4:0> 140 CCP1PPS — — — CCP1PPS<4:0> 140 CCP2PPS — — — CCP2PPS<4:0> 140 COGPPS — — — COGPPS<4:0> 140 SSPCLKPPS — — — SSPCLKPPS<4:0> 140 SSPDATPPS — — — SSPDATPPS<4:0> 140 SSPSSPPS — — — SSPSSPPS<4:0> 140 RXPPS — — — RXPPS<4:0> 140 CKPPS — — — CKPPS<4:0> 140 CLCIN0PPS — — — CLCIN0PPS<4:0> 140 CLCIN1PPS — — — CLCIN1PPS<4:0> 140 CLCIN2PPS — — — CLCIN2PPS<4:0> 140 CLCIN3PPS — — — CLCIN3PPS<4:0> 140 RA0PPS — — — RA0PPS<4:0> 141 RA1PPS — — — RA1PPS<4:0> 141 RA2PPS — — — RA2PPS<4:0> 141 RA4PPS — — — RA4PPS<4:0> 141 RA5PPS — — — RA5PPS<4:0> 141 RB4PPS(1) — — — RB4PPS<4:0> 141 RB5PPS(1) — — — RB5PPS<4:0> 141 RB6PPS(1) — — — RB6PPS<4:0> 141 (1) RB7PPS — — — RB7PPS<4:0> 141 RC0PPS — — — RC0PPS<4:0> 141 RC1PPS — — — RC1PPS<4:0> 141 RC2PPS — — — RC2PPS<4:0> 141 RC3PPS — — — RC3PPS<4:0> 141 RC4PPS — — — RC4PPS<4:0> 141 RC5PPS — — — RC5PPS<4:0> 141 RC6PPS(1) — — — RC6PPS<4:0> 141 RC7PPS(1) — — — RC7PPS<4:0> 141 Legend: Note 1: — = unimplemented, read as ‘0’. Shaded cells are unused by the PPS module. PIC16(L)F1709 only. 2013-2015 Microchip Technology Inc. DS40001729C-page 143 PIC16(L)F1705/9 13.0 INTERRUPT-ON-CHANGE All pins on all ports can be configured to operate as Interrupt-on-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual pin, or combination of pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features: • • • • Interrupt-on-Change enable (Master Switch) Individual pin configuration Rising and falling edge detection Individual pin interrupt flags Figure 13-1 is a block diagram of the IOC module. 13.1 Enabling the Module 13.3 Interrupt Flags The bits located in the IOCxF registers are status flags that correspond to the interrupt-on-change pins of each port. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCxF bits. 13.4 Clearing Interrupt Flags The individual status flags, (IOCxF register bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. To allow individual pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed. 13.2 Individual Pin Configuration EXAMPLE 13-1: For each pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated bit of the IOCxP register is set. To enable a pin to detect a falling edge, the associated bit of the IOCxN register is set. MOVLW XORWF ANDWF A pin can be configured to detect rising and falling edges simultaneously by setting the associated bits in both of the IOCxP and IOCxN registers. 13.5 CLEARING INTERRUPT FLAGS (PORTA EXAMPLE) 0xff IOCAF, W IOCAF, F Operation in Sleep The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set. If an edge is detected while in Sleep mode, the affected IOCxF register will be updated prior to the first instruction executed out of Sleep. DS40001729C-page 144 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 13-1: INTERRUPT-ON-CHANGE BLOCK DIAGRAM (PORTA EXAMPLE) Rev. 10-000 037A 6/2/201 4 IOCANx D Q R Q4Q1 edge detect RAx IOCAPx D data bus = 0 or 1 Q D S to data bus IOCAFx Q write IOCAFx R IOCIE Q2 IOC interrupt to CPU core from all other IOCnFx individual pin detectors FOSC Q1 Q1 Q1 Q3 Q3 Q4 Q4Q1 Q2 Q2 Q2 Q3 Q4 Q4Q1 2013-2015 Microchip Technology Inc. Q4 Q4Q1 Q4Q1 DS40001729C-page 145 PIC16(L)F1705/9 13.6 Register Definitions: Interrupt-on-Change Control REGISTER 13-1: IOCAP: INTERRUPT-ON-CHANGE PORTA POSITIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAP<5:0>: Interrupt-on-Change PORTA Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. REGISTER 13-2: IOCAN: INTERRUPT-ON-CHANGE PORTA NEGATIVE EDGE REGISTER U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAN<5:0>: Interrupt-on-Change PORTA Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCAFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. DS40001729C-page 146 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 13-3: IOCAF: INTERRUPT-ON-CHANGE PORTA FLAG REGISTER U-0 U-0 — — R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCAF5 IOCAF4 IOCAF3 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCAF2 IOCAF1 IOCAF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 IOCAF<5:0>: Interrupt-on-Change PORTA Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCAPx = 1 and a rising edge was detected on RAx, or when IOCANx = 1 and a falling edge was detected on RAx. 0 = No change was detected, or the user cleared the detected change. REGISTER 13-4: R/W-0/0 IOCBP: INTERRUPT-ON-CHANGE PORTB POSITIVE EDGE REGISTER(1) R/W-0/0 IOCBP7 R/W-0/0 IOCBP6 IOCBP5 R/W-0/0 U-0 U-0 U-0 U-0 IOCBP4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCBP<7:4>: Interrupt-on-Change PORTB Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 3-0 Unimplemented: Read as ‘0’ Note 1: PIC16(L)F1709 only. 2013-2015 Microchip Technology Inc. DS40001729C-page 147 PIC16(L)F1705/9 REGISTER 13-5: IOCBN: INTERRUPT-ON-CHANGE PORTB NEGATIVE EDGE REGISTER(1) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 U-0 U-0 U-0 U-0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCBN<7:4>: Interrupt-on-Change PORTB Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCBFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. bit 3-0 Unimplemented: Read as ‘0’ Note 1: PIC16(L)F1709 only. REGISTER 13-6: IOCBF: INTERRUPT-ON-CHANGE PORTB FLAG REGISTER(1) R/W/HS-0/0 R/W/HS-0/0 IOCBF7 IOCBF6 R/W/HS-0/0 R/W/HS-0/0 IOCBF5 IOCBF4 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-4 IOCBF<7:4>: Interrupt-on-Change PORTB Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCBPx = 1 and a rising edge was detected on RBx, or when IOCBNx = 1 and a falling edge was detected on RBx. 0 = No change was detected, or the user cleared the detected change. bit 3-0 Unimplemented: Read as ‘0’ Note 1: PIC16(L)F1709 only. DS40001729C-page 148 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 13-7: IOCCP: INTERRUPT-ON-CHANGE PORTC POSITIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: IOCCP<7:0>: Interrupt-on-Change PORTC Positive Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a positive going edge. IOCCFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. PIC16(L)F1709 only. REGISTER 13-8: IOCCN: INTERRUPT-ON-CHANGE PORTC NEGATIVE EDGE REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 IOCCN7(1) IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 Note 1: IOCCN<7:0>: Interrupt-on-Change PORTC Negative Edge Enable bits 1 = Interrupt-on-Change enabled on the pin for a negative going edge. IOCCFx bit and IOCIF flag will be set upon detecting an edge. 0 = Interrupt-on-Change disabled for the associated pin. PIC16(L)F1709 only. REGISTER 13-9: IOCCF: INTERRUPT-ON-CHANGE PORTC FLAG REGISTER R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0 IOCCF7(1) IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS - Bit is set in hardware bit 7-0 Note 1: U = Unimplemented bit, read as ‘0’ IOCCF<7:0>: Interrupt-on-Change PORTC Flag bits 1 = An enabled change was detected on the associated pin. Set when IOCCPx = 1 and a rising edge was detected on RCx, or when IOCCNx = 1 and a falling edge was detected on RCx. 0 = No change was detected, or the user cleared the detected change. PIC16(L)F1709 only. 2013-2015 Microchip Technology Inc. DS40001729C-page 149 PIC16(L)F1705/9 TABLE 13-1: Name ANSELA (1) ANSELB ANSELC INTCON SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 122 ANSB4 — — — — 128 ANSC3 ANSC2 ANSC1 ANSC0 133 — — (1) ANSC7 ANSB5 (1) ANSC6 (2) ANSC5 (2) ANSC4 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 IOCAF — — IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 147 IOCAN — — IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 146 IOCAP — — IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 146 (1) IOCBF IOCBF7 IOCBF6 IOCBF5 IOCBF4 — — — — 148 IOCBN(1) IOCBN7 IOCBN6 IOCBN5 IOCBN4 — — — — 148 IOCBP(1) IOCBP7 IOCBP6 IOCBP5 IOCBP4 — — — — 147 (1) IOCCF6(1) IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 149 IOCCN (1) IOCCN7 IOCCN6(1) IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 149 IOCCP IOCCP7(1) IOCCP6(1) IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 149 — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 IOCCF TRISA (1) TRISB TRISC Legend: Note 1: 2: 3: IOCCF7 — TRISB7 TRISC7 (1) — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. DS40001729C-page 150 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 14.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • • • • ADC input channel ADC positive reference Comparator positive input Digital-to-Analog Converter (DAC) The FVR can be enabled by setting the FVREN bit of the FVRCON register. 14.1 14.2 FVR Stabilization Period When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See Figure 33-76: FVR Stabilization Period. PIC16LF1705/9 Only. 14.3 FVR Buffer Stabilization Period When either FVR Buffer1 or Buffer2 is enabled then the buffer amplifier circuits require 30 us to stabilize.This stabilization time is required even when the FVR is already operating and stable. Independent Gain Amplifiers The output of the FVR supplied to the ADC, Comparators, and DAC is routed through two independent programmable gain amplifiers. Each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference Section 20.0 “Analog-to-Digital Converter (ADC) Module” for additional information. The CDAFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the DAC and comparator module. Reference Section 22.0 “8-Bit Digital-to-Analog Converter (DAC1) Module” and Section 16.0 “Comparator Module” for additional information. 2013-2015 Microchip Technology Inc. DS40001729C-page 151 PIC16(L)F1705/9 FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> 2 X1 X2 X4 FVR BUFFER1 (To ADC Module) X1 X2 X4 FVR BUFFER2 (To Comparators, DAC) 2 HFINTOSC Enable HFINTOSC To BOR, LDO FVREN + _ FVRRDY Any peripheral requiring the Fixed Reference (See Table 14-1) TABLE 14-1: PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR) Peripheral HFINTOSC Conditions Description FOSC<2:0> = 100 and IRCF<3:0> 000x INTOSC is active and device is not in Sleep BOREN<1:0> = 11 BOR always enabled BOR BOREN<1:0> = 10 and BORFS = 1 BOR disabled in Sleep mode, BOR Fast Start enabled BOREN<1:0> = 01 and BORFS = 1 BOR under software control, BOR Fast Start enabled LDO All PIC16F1705/9 devices, when VREGPM = 1 and not in Sleep The device runs off of the ULP regulator when in Sleep mode DS40001729C-page 152 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 14.4 Register Definitions: FVR Control REGISTER 14-1: FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0/0 R-q/q FVREN FVRRDY(1) R/W-0/0 TSEN (3) R/W-0/0 TSRNG R/W-0/0 (3) R/W-0/0 R/W-0/0 CDAFVR<1:0> R/W-0/0 ADFVR<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 FVREN: Fixed Voltage Reference Enable bit 1 = Fixed Voltage Reference is enabled 0 = Fixed Voltage Reference is disabled bit 6 FVRRDY: Fixed Voltage Reference Ready Flag bit(1) 1 = Fixed Voltage Reference output is ready for use 0 = Fixed Voltage Reference output is not ready or not enabled bit 5 TSEN: Temperature Indicator Enable bit(3) 1 = Temperature Indicator is enabled 0 = Temperature Indicator is disabled bit 4 TSRNG: Temperature Indicator Range Selection bit(3) 1 = VOUT = VDD - 4VT (High Range) 0 = VOUT = VDD - 2VT (Low Range) bit 3-2 CDAFVR<1:0>: Comparator FVR Buffer Gain Selection bits 11 = Comparator FVR Buffer Gain is 4x, with output VCDAFVR = 4x VFVR(2) 10 = Comparator FVR Buffer Gain is 2x, with output VCDAFVR = 2x VFVR(2) 01 = Comparator FVR Buffer Gain is 1x, with output VCDAFVR = 1x VFVR 00 = Comparator FVR Buffer is off bit 1-0 ADFVR<1:0>: ADC FVR Buffer Gain Selection bit 11 = ADC FVR Buffer Gain is 4x, with output VADFVR = 4x VFVR(2) 10 = ADC FVR Buffer Gain is 2x, with output VADFVR = 2x VFVR(2) 01 = ADC FVR Buffer Gain is 1x, with output VADFVR = 1x VFVR 00 = ADC FVR Buffer is off Note 1: 2: 3: FVRRDY is always ‘1’ on PIC16F1705/9 only. Fixed Voltage Reference output cannot exceed VDD. See Section 15.0 “Temperature Indicator Module” for additional information. TABLE 14-2: Name FVRCON Legend: SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDAFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 153 Shaded cells are not used with the Fixed Voltage Reference. 2013-2015 Microchip Technology Inc. DS40001729C-page 153 PIC16(L)F1705/9 15.0 TEMPERATURE INDICATOR MODULE FIGURE 15-1: This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. VDD TSEN TSRNG The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application Note AN1333, “Use and Calibration of the Internal Temperature Indicator” (DS01333) for more details regarding the calibration process. 15.1 Circuit Operation Figure 15-1 shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. Equation 15-1 describes the output characteristics of the temperature indicator. EQUATION 15-1: VOUT RANGES TEMPERATURE CIRCUIT DIAGRAM VOUT Temp. Indicator 15.2 To ADC Minimum Operating VDD When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. When the temperature circuit is operated in high range, the device operating voltage, VDD, must be high enough to ensure that the temperature circuit is correctly biased. Table 15-1 shows the recommended minimum VDD vs. range setting. High Range: VOUT = VDD - 4VT TABLE 15-1: Low Range: VOUT = VDD - 2VT The temperature sense circuit is integrated with the Fixed Voltage Reference (FVR) module. See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. The circuit is enabled by setting the TSEN bit of the FVRCON register. When disabled, the circuit draws no current. The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher VDD is needed. RECOMMENDED VDD VS. RANGE Min. VDD, TSRNG = 1 Min. VDD, TSRNG = 0 3.6V 1.8V 15.3 Temperature Output The output of the circuit is measured using the internal Analog-to-Digital Converter. A channel is reserved for the temperature circuit output. Refer to Section 20.0 “Analog-to-Digital Converter (ADC) Module” for detailed information. The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. DS40001729C-page 154 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 15.4 ADC Acquisition Time To ensure accurate temperature measurements, the user must wait at least 200 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200 s between sequential conversions of the temperature indicator output. TABLE 15-2: Name FVRCON SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Bit 7 Bit 6 Bit 5 Bit 4 FVREN FVRRDY TSEN TSRNG Bit 3 Bit 2 CDFVR<1:0> Bit 1 Bit 0 ADFVR<1:0> Register on page 153 Legend: Shaded cells are unused by the temperature indicator module. 2013-2015 Microchip Technology Inc. DS40001729C-page 155 PIC16(L)F1705/9 16.0 COMPARATOR MODULE FIGURE 16-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. Comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. The analog comparator module includes the following features: • • • • • • • • • Independent comparator control Programmable input selection Comparator output is available internally/externally Programmable output polarity Interrupt-on-change Wake-up from Sleep Programmable Speed/Power optimization PWM shutdown Programmable and Fixed Voltage Reference 16.1 Comparator Overview SINGLE COMPARATOR VIN+ + VIN- – Output VINVIN+ Output Note: The black areas of the output of the comparator represents the uncertainty due to input offsets and response time. A single comparator is shown in Figure 16-1 along with the relationship between the analog input levels and the digital output. When the analog voltage at VIN+ is less than the analog voltage at VIN-, the output of the comparator is a digital low level. When the analog voltage at VIN+ is greater than the analog voltage at VIN-, the output of the comparator is a digital high level. The comparators available for this device are located in Table 16-1. TABLE 16-1: AVAILABLE COMPARATORS Device PIC16(L)F1705/9 DS40001729C-page 156 C1 C2 ● ● 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 16-2: COMPARATOR MODULE SIMPLIFIED BLOCK DIAGRAM CxNCH<2:0> CxON(1) 3 CxINTP Interrupt det CXIN0- 0 CXIN1- 1 CXIN2- 2 MUX Set CxIF CXIN3- det 3 Reserved 4 Reserved 5 FVR Buffer2 6 CxINTN Interrupt (2) CXPOL CxVN - 0 D Cx CxVP ZLF + 1 EN Q1 7 CxHYS AGND CxSP to CMXCON0 (CXOUT) and CM2CON1 (MCXOUT) Q CxZLF async_CxOUT CXSYNC TRIS bit CXOUT 0 CXIN+ 0 Reserved 1 Reserved 2 Reserved 3 Reserved 4 DAC_Output 5 FVR Buffer2 6 D From Timer1 tmr1_clk MUX Q 1 sync_CxOUT To Timer1 (2) 7 AGND CxON CXPCH<2:0> 3 Note 1: 2: When CxON = 0, the comparator will produce a ‘0’ at the output. When CxON = 0, all multiplexer inputs are disconnected. 2013-2015 Microchip Technology Inc. DS40001729C-page 157 PIC16(L)F1705/9 16.2 Comparator Control Each comparator has two control registers: CMxCON0 and CMxCON1. The CMxCON0 register (see Register 16-1) contains Control and Status bits for the following: • • • • • • • Enable Output Output polarity Zero latency filter Speed/Power selection Hysteresis enable Output synchronization The CMxCON1 register (see Register 16-2) contains Control bits for the following: • • • • Interrupt enable Interrupt edge polarity Positive input channel selection Negative input channel selection 16.2.1 COMPARATOR ENABLE Setting the CxON bit of the CMxCON0 register enables the comparator for operation. Clearing the CxON bit disables the comparator resulting in minimum current consumption. 16.2.2 COMPARATOR OUTPUT SELECTION 16.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The polarity of the comparator output can be inverted by setting the CxPOL bit of the CMxCON0 register. Clearing the CxPOL bit results in a non-inverted output. Table 16-2 shows the output state versus input conditions, including polarity control. TABLE 16-2: COMPARATOR OUTPUT STATE VS. INPUT CONDITIONS Input Condition CxPOL CxOUT CxVN > CxVP 0 0 CxVN < CxVP 0 1 CxVN > CxVP 1 1 CxVN < CxVP 1 0 16.2.4 COMPARATOR SPEED/POWER SELECTION The trade-off between speed or power can be optimized during program execution with the CxSP control bit. The default state for this bit is ‘1’, which selects the Normal-Speed mode. Device power consumption can be optimized at the cost of slower comparator propagation delay by clearing the CxSP bit to ‘0’. The output of the comparator can be monitored by reading either the CxOUT bit of the CMxCON0 register or the MCxOUT bit of the CMOUT register. In order to make the output available for an external connection, the following conditions must be true: • Desired pin PPS control • Corresponding TRIS bit must be cleared • CxON bit of the CMxCON0 register must be set Note 1: The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. DS40001729C-page 158 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 16.3 Comparator Hysteresis A selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. Hysteresis is enabled by setting the CxHYS bit of the CMxCON0 register. The associated interrupt flag bit, CxIF bit of the PIR2 register, must be cleared in software. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Note: See Comparator Specifications in Table 32-18: Comparator Specifications for more information. 16.4 Timer1 Gate Operation The output resulting from a comparator operation can be used as a source for gate control of Timer1. See Section 25.6 “Timer1 Gate” for more information. This feature is useful for timing the duration or interval of an analog event. It is recommended that the comparator output be synchronized to Timer1. This ensures that Timer1 does not increment while a change in the comparator is occurring. 16.4.1 COMPARATOR OUTPUT SYNCHRONIZATION The output from a comparator can be synchronized with Timer1 by setting the CxSYNC bit of the CMxCON0 register. Once enabled, the comparator output is latched on the falling edge of the Timer1 source clock. If a prescaler is used with Timer1, the comparator output is latched after the prescaling function. To prevent a race condition, the comparator output is latched on the falling edge of the Timer1 clock source and Timer1 increments on the rising edge of its clock source. See the Comparator Block Diagram (Figure 16-2) and the Timer1 Block Diagram (Figure 25-1) for more information. 16.5 Comparator Interrupt An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of the CMxCON1 register), the Corresponding Interrupt Flag bit (CxIF bit of the PIR2 register) will be set. To enable the interrupt, you must set the following bits: • CxON, CxPOL and CxSP bits of the CMxCON0 register • CxIE bit of the PIE2 register • CxINTP bit of the CMxCON1 register (for a rising edge detection) • CxINTN bit of the CMxCON1 register (for a falling edge detection) • PEIE and GIE bits of the INTCON register 2013-2015 Microchip Technology Inc. 16.6 Although a comparator is disabled, an interrupt can be generated by changing the output polarity with the CxPOL bit of the CMxCON0 register, or by switching the comparator on or off with the CxON bit of the CMxCON0 register. Comparator Positive Input Selection Configuring the CxPCH<2:0> bits of the CMxCON1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: • • • • CxIN+ analog pin DAC output FVR (Fixed Voltage Reference) VSS (Ground) See Section 14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 22.0 “8-Bit Digital-to-Analog Converter (DAC1) Module” for more information on the DAC input signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. 16.7 Comparator Negative Input Selection The CxNCH<2:0> bits of the CMxCON0 register direct an analog input pin and internal reference voltage or analog ground to the inverting input of the comparator: • CxIN- pin • FVR (Fixed Voltage Reference) • Analog Ground Some inverting input selections share a pin with the operational amplifier output function. Enabling both functions at the same time will direct the operational amplifier output to the comparator inverting input. Note: To use CxINy+ and CxINy- pins as analog input, the appropriate bits must be set in the ANSEL register and the corresponding TRIS bits must also be set to disable the output drivers. DS40001729C-page 159 PIC16(L)F1705/9 16.8 the hardware and software relying on this signal. Therefore, a digital filter has been added to the comparator output to suppress the comparator output oscillation. Once the comparator output changes, the output is prevented from reversing the change for a nominal time of 20 ns. This allows the comparator output to stabilize without affecting other dependent devices. Refer to Figure 16-3. Comparator Response Time The comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. This period is referred to as the response time. The response time of the comparator differs from the settling time of the voltage reference. Therefore, both of these times must be considered when determining the total response time to a comparator input change. See the Comparator and Voltage Reference Specifications in Table 32-18: Comparator Specifications for more details. 16.9 Zero Latency Filter In high-speed operation, and under proper circuit conditions, it is possible for the comparator output to oscillate. This oscillation can have adverse effects on FIGURE 16-3: COMPARATOR ZERO LATENCY FILTER OPERATION CxOUT From Comparator CxOUT From ZLF TZLF Output waiting for TZLF to expire before an output change is allowed. TZLF has expired so output change of ZLF is immediate based on comparator output change. DS40001729C-page 160 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 16.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 16-4. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur. A maximum source impedance of 10 k is recommended for the analog sources. Also, any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current to minimize inaccuracies introduced. Note 1: When reading a PORT register, all pins configured as analog inputs will read as a ‘0’. Pins configured as digital inputs will convert as an analog input, according to the input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. FIGURE 16-4: ANALOG INPUT MODEL VDD Rs < 10K Analog Input pin VT 0.6V RIC To Comparator VA CPIN 5 pF VT 0.6V ILEAKAGE(1) Vss Legend: CPIN = Input Capacitance ILEAKAGE = Leakage Current at the pin due to various junctions RIC = Interconnect Resistance = Source Impedance RS = Analog Voltage VA VT = Threshold Voltage Note 1: See I/O Ports in Table 32-4: I/O Ports. 2013-2015 Microchip Technology Inc. DS40001729C-page 161 PIC16(L)F1705/9 16.11 Register Definitions: Comparator Control REGISTER 16-1: CMxCON0: COMPARATOR Cx CONTROL REGISTER 0 R/W-0/0 R-0/0 U-0 R/W-0/0 R/W-0/0 R/W-1/1 R/W-0/0 R/W-0/0 CxON CxOUT — CxPOL CxZLF CxSP CxHYS CxSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled and consumes no active power bit 6 CxOUT: Comparator Output bit If CxPOL = 1 (inverted polarity): 1 = CxVP < CxVN 0 = CxVP > CxVN If CxPOL = 0 (non-inverted polarity): 1 = CxVP > CxVN 0 = CxVP < CxVN bit 5 Unimplemented: Read as ‘0’ bit 4 CxPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 3 CxZLF: Comparator Zero Latency Filter Enable bit 1 = Comparator output is filtered 0 = Comparator output is unfiltered bit 2 CxSP: Comparator Speed/Power Select bit 1 = Comparator operates in Normal-Power, higher speed mode 0 = Comparator operates in Low-Power, Low-Speed mode bit 1 CxHYS: Comparator Hysteresis Enable bit 1 = Comparator hysteresis enabled 0 = Comparator hysteresis disabled bit 0 CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. 0 = Comparator output to Timer1 and I/O pin is asynchronous DS40001729C-page 162 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 16-2: CMxCON1: COMPARATOR Cx CONTROL REGISTER 1 R/W-0/0 R/W-0/0 CxINTP CxINTN R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 CxPCH<2:0> R/W-0/0 R/W-0/0 CxNCH<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CxINTP: Comparator Interrupt on Positive Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a positive going edge of the CxOUT bit 0 = No interrupt flag will be set on a positive going edge of the CxOUT bit bit 6 CxINTN: Comparator Interrupt on Negative Going Edge Enable bits 1 = The CxIF interrupt flag will be set upon a negative going edge of the CxOUT bit 0 = No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5-3 CxPCH<2:0>: Comparator Positive Input Channel Select bits 111 = CxVP connects to AGND 110 = CxVP connects to FVR Buffer 2 101 = CxVP connects to VDAC 100 = CxVP unconnected, input floating 011 = CxVP unconnected, input floating 010 = CxVP unconnected, input floating 001 = CxVN unconnected, input floating 000 = CxVP connects to CxIN+ pin bit 2-0 CxNCH<2:0>: Comparator Negative Input Channel Select bits 111 = CxVN connects to AGND 110 = CxVN connects to FVR Buffer 2 101 = CxVN unconnected, input floating 100 = CxVN unconnected, input floating 011 = CxVN connects to CxIN3- pin 010 = CxVN connects to CxIN2- pin 001 = CxVN connects to CxIN1- pin 000 = CxVN connects to CxIN0- pin 2013-2015 Microchip Technology Inc. DS40001729C-page 163 PIC16(L)F1705/9 REGISTER 16-3: CMOUT: COMPARATOR OUTPUT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R-0/0 R-0/0 — — — — — — MC2OUT MC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 MC2OUT: Mirror Copy of C2OUT bit bit 0 MC1OUT: Mirror Copy of C1OUT bit TABLE 16-3: Name ANSELA ANSELB(1) SUMMARY OF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 122 — — ANSB5 ANSB4 — — — — 128 ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133 CM1CON0 C1ON C1OUT — C1POL C1ZLF C1SP C1HYS C1SYNC 162 CM2CON0 C2ON C2OUT — C2POL C2ZLF C2SP C2HYS C2SYNC 162 CM1CON1 C1INTP C1INTN C1PCH<2:0> C1NCH<2:0> CM2CON1 C2INTP C2INTN C2PCH<2:0> C2NCH<2:0> CMOUT — — — — FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> ANSELC DAC1CON0 DAC1CON1 — — MC2OUT 163 163 MC1OUT ADFVR<1:0> — DAC1NSS DAC1R<7:0> 164 153 238 238 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 86 PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 89 — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121 INTCON TRISA TRISB(1) TRISC Legend: Note 1: 2: 3: TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. DS40001729C-page 164 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 17.0 Figure 17-1 shows a simplified block diagram of PWM operation. PULSE-WIDTH MODULATION (PWM) Figure 17-2 shows a typical waveform of the PWM signal. The PWM module generates a Pulse-Width Modulated signal determined by the duty cycle, period, and resolution that are configured by the following registers: • • • • • PR2 T2CON PWMxDCH PWMxDCL PWMxCON FIGURE 17-1: SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle registers PWMxDCL<7:6> PWMxDCH Latched (Not visible to user) Comparator PWMxOUT to other peripherals: CLC and CWG R Q 0 S Q 1 PWMx TMR2 Module TMR2 (1) Output Polarity (PWMxPOL) Comparator PR2 Note 1: Clear Timer, PWMx pin and latch Duty Cycle 8-bit timer is concatenated with the two Least Significant bits of 1/FOSC adjusted by the Timer2 prescaler to create a 10-bit time base. For a step-by-step procedure on how to set up this module for PWM operation, refer to Section 17.1.9 “Setup for PWM Operation using PWMx Pins”. FIGURE 17-2: PWM OUTPUT Period Pulse Width TMR2 = 0 TMR2 = PR2 TMR2 = PWMxDCH<7:0>:PWMxDCL<7:6> 2013-2015 Microchip Technology Inc. DS40001729C-page 165 PIC16(L)F1705/9 17.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. 17.1.1 FUNDAMENTAL OPERATION The PWM module produces a 10-bit resolution output. Timer2 and PR2 set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is common to all PWM modules, whereas the duty cycle is independently controlled. Note: The Timer2 postscaler is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. All PWM outputs associated with Timer2 are set when TMR2 is cleared. Each PWMx is cleared when TMR2 is equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL<7:6> (2 LSb) registers. When the value is greater than or equal to PR2, the PWM output is never cleared (100% duty cycle). Note: The PWMxDCH and PWMxDCL registers are double buffered. The buffers are updated when Timer2 matches PR2. Care should be taken to update both registers before the timer match occurs. 17.1.2 PWM OUTPUT POLARITY The output polarity is inverted by setting the PWMxPOL bit of the PWMxCON register. 17.1.3 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 17-1. EQUATION 17-1: PWM PERIOD PWM Period = PR2 + 1 4 T OSC When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The PWM output is active. (Exception: When the PWM duty cycle = 0%, the PWM output will remain inactive.) • The PWMxDCH and PWMxDCL register values are latched into the buffers. Note: 17.1.4 The Timer2 postscaler has no effect on the PWM operation. PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair. The PWMxDCH register contains the eight MSbs and the PWMxDCL<7:6>, the two LSbs. The PWMxDCH and PWMxDCL registers can be written to at any time. Equation 17-2 is used to calculate the PWM pulse width. Equation 17-3 is used to calculate the PWM duty cycle ratio. EQUATION 17-2: PULSE WIDTH Pulse Width = PWMxDCH:PWMxDCL<7:6> T OS C (TMR2 Prescale Value) Note: TOSC = 1/FOSC EQUATION 17-3: DUTY CYCLE RATIO PWMxDCH:PWMxDCL<7:6> Duty Cycle Ratio = ----------------------------------------------------------------------------------4 PR2 + 1 The 8-bit timer TMR2 register is concatenated with the two Least Significant bits of 1/FOSC, adjusted by the Timer2 prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. (TMR2 Prescale Value) Note: TOSC = 1/FOSC DS40001729C-page 166 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 17.1.5 PWM RESOLUTION The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 17-4. EQUATION 17-4: PWM RESOLUTION log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. TABLE 17-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency 0.31 kHz Timer Prescale PR2 Value 78.12 kHz 156.3 kHz 208.3 kHz 64 4 1 1 1 1 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 0.31 kHz Timer Prescale PR2 Value 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 64 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Maximum Resolution (bits) 17.1.6 19.53 kHz 0xFF Maximum Resolution (bits) TABLE 17-2: 4.88 kHz OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the PWMx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 17.1.7 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency. Refer to Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional details. 17.1.8 EFFECTS OF RESET Any Reset will force all ports to Input mode and the PWM registers to their Reset states. 2013-2015 Microchip Technology Inc. DS40001729C-page 167 PIC16(L)F1705/9 17.1.9 SETUP FOR PWM OPERATION USING PWMx PINS The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). 2. Clear the PWMxCON register. 3. Load the PR2 register with the PWM period value. 4. Load the PWMxDCH register and bits <7:6> of the PWMxDCL register with the PWM duty cycle value. 5. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below. • Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. • Enable Timer2 by setting the TMR2ON bit of the T2CON register. 6. Enable PWM output pin and wait until Timer2 overflows, TMR2IF bit of the PIR1 register is set. See Note below. 7. Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the desired pin PPS control bits. 8. Configure the PWM module by loading the PWMxCON register with the appropriate values. Note 1: In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed in the order given. If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4. 17.1.10 SETUP FOR PWM OPERATION TO OTHER DEVICE PERIPHERALS The following steps should be taken when configuring the module for PWM operation to be used by other device peripherals: 1. 2. 3. 4. 5. • • • 6. • 7. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the PR2 register with the PWM period value. Load the PWMxDCH register and bits <7:6> of the PWMxDCL register with the PWM duty cycle value. Configure and start Timer2: Clear the TMR2IF interrupt flag bit of the PIR1 register. See Note below. Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. Enable Timer2 by setting the TMR2ON bit of the T2CON register. Enable PWM output pin: Wait until Timer2 overflows, TMR2IF bit of the PIR1 register is set. See Note below. Configure the PWM module by loading the PWMxCON register with the appropriate values. Note: In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. 2: For operation with other peripherals only, disable PWMx pin outputs. DS40001729C-page 168 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 17.2 Register Definitions: PWM Control REGISTER 17-1: PWMxCON: PWM CONTROL REGISTER R/W-0/0 U-0 R-0/0 R/W-0/0 U-0 U-0 U-0 U-0 PWMxEN — PWMxOUT PWMxPOL — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PWMxEN: PWM Module Enable bit 1 = PWM module is enabled 0 = PWM module is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 PWMxOUT: PWM module output level when bit is read. bit 4 PWMxPOL: PWMx Output Polarity Select bit 1 = PWM output is active-low 0 = PWM output is active-high bit 3-0 Unimplemented: Read as ‘0’ 2013-2015 Microchip Technology Inc. DS40001729C-page 169 PIC16(L)F1705/9 REGISTER 17-2: R/W-x/u PWMxDCH: PWM DUTY CYCLE HIGH BITS R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u PWMxDCH<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 PWMxDCH<7:0>: PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle. The two LSbs are found in the PWMxDCL Register. REGISTER 17-3: R/W-x/u PWMxDCL: PWM DUTY CYCLE LOW BITS R/W-x/u PWMxDCL<7:6> U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PWMxDCL<7:6>: PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle. The MSbs are found in the PWMxDCH Register. bit 5-0 Unimplemented: Read as ‘0’ TABLE 17-3: Name CCPTMRS SUMMARY OF REGISTERS ASSOCIATED WITH PWM Bit 7 Bit 6 P4TSEL<1:0> Bit 5 P3TSEL<1:0> PR2 PWM3CON PWM4CON Bit 3 Bit 2 Bit 1 C2TSEL<1:0> Bit 0 Register on Page C1TSEL<1:0> Timer2 module Period Register PWM3EN — PWM3OUT PWM3POL PWM3DCH PWM3DCL Bit 4 — — — — PWMxDCH<7:0> PWMxDCL<7:6> PWM4EN — — — PWM4OUT PWM4POL PWM4DCH PWMxDCL<7:6> — RxyPPS — — T2CON — TMR2 — — 169 170 — — — — 170 — — — — 169 — — — PWMxDCH<7:0> PWM4DCL 261 257 170 — RxyPPS<4:0> T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON 170 141 T2CKPS1 T2CKPS0 Timer2 module Register 259 257 Legend: - = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the PWM. DS40001729C-page 170 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 18.0 COMPLEMENTARY OUTPUT GENERATOR (COG) MODULE The primary purpose of the Complementary Output Generator (COG) is to convert a single output PWM signal into a two-output complementary PWM signal. The COG can also convert two separate input events into a single or complementary PWM output. The COG PWM frequency and duty cycle are determined by a rising event input and a falling event input. The rising event and falling event may be the same source. Sources may be synchronous or asynchronous to the COG_clock. The rate at which the rising event occurs determines the PWM frequency. The time from the rising event input to the falling event input determines the duty cycle. A selectable clock input is used to generate the phase delay, blanking, and dead-band times. Dead-band time can also be generated with a programmable time delay, which is independent from all clock sources. Simplified block diagrams of the various COG modes are shown in Figure 18-2 through Figure 18-6. The COG module has the following features: • Six modes of operation: - Steered PWM mode - Synchronous Steered PWM mode - Forward Full-Bridge mode - Reverse Full-Bridge mode - Half-Bridge mode - Push-Pull mode • Selectable COG_clock clock source • Independently selectable rising event sources • Independently selectable falling event sources • Independently selectable edge or level event sensitivity • Independent output polarity selection • Phase delay with independent rising and falling delay times • Dead-band control with: - independent rising and falling event dead-band times - Synchronous and asynchronous timing • Blanking control with independent rising and falling event blanking times • Auto-shutdown control with: - Independently selectable shutdown sources - Auto-restart enable - Auto-shutdown pin override control (high, low, off, and High-Z) 2013-2015 Microchip Technology Inc. 18.1 18.1.1 Fundamental Operation STEERED PWM MODES In steered PWM mode, the PWM signal derived from the input event sources is output as a single phase PWM which can be steered to any combination of the four COG outputs. Outputs are selected by the GxSTRA through GxSTRD bits of the GxSTR register (Register 18-9). When the steering bits are cleared the output data is the static level determined by the GxDATA through GxSDATD bits of the GxSTR register. Output steering takes effect on the instruction cycle following the write to the GxSTR register. Synchronous steered PWM mode is identical to the steered PWM mode except that changes to the output steering take effect on the first rising event after the GxSTR register write. Static output data is not synchronized. Steering mode configurations are shown in Figure 18-2 and Figure 18-3. Steered PWM and synchronous steered PWM modes are selected by setting the GxMD bits of the COGxCON0 register (Register 18-1) to ‘000’ and ‘001’ respectively. 18.1.2 FULL-BRIDGE MODES In both Forward and Reverse Full-Bridge modes, two of the four COG outputs are active and the other two are inactive. Of the two active outputs, one is modulated by the PWM input signal and the other is on at 100% duty cycle. When the direction is changed, the dead-band time is inserted to delay the modulated output. This gives the unmodulated driver time to shut down, thereby, preventing shoot-through current in the series connected power devices. In Forward Full-Bridge mode, the PWM input modulates the COGxD output and drives the COGA output at 100%. In Reverse Full-Bridge mode, the PWM input modulates the COGxB output and drives the COGxC output at 100%. The full-bridge configuration is shown in Figure 18-4. Typical full-bridge waveforms are shown in Figure 18-12 and Figure 18-13. Full-Bridge Forward and Full-Bridge Reverse modes are selected by setting the GxMD bits of the COGxCON0 register to ‘010’ and ‘011’, respectively. DS40001729C-page 171 EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver QC QA FET Driver COGxA Load COGxB FET Driver COGxC FET Driver QD QB VCOGxD PIC16(L)F1705/9 DS40001729C-page 172 FIGURE 18-1: 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 18.1.3 HALF-BRIDGE MODE In Half-Bridge mode, the COG generates a two-output complementary PWM waveform from rising and falling event sources. In the simplest configuration, the rising and falling event sources are the same signal, which is a PWM signal with the desired period and duty cycle. The COG converts this single PWM input into a dual complementary PWM output. The frequency and duty cycle of the dual PWM output match those of the single input PWM signal. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time immediately after the PWM transition where neither output is driven. This is referred to as dead time and is covered in Section 18.5 “Dead-Band Control”. It may be necessary to guard against the possibility of circuit faults. In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as auto-shutdown and is covered in Section 18.8 “Auto-Shutdown Control”. The COG can be configured to operate in phase delayed conjunction with another PWM. The active drive cycle is delayed from the rising event by a phase delay timer. Phase delay is covered in more detail in Section 18.7 “Phase Delay”. A typical operating waveform, with phase delay and dead band, generated from a single CCP1 input is shown in Figure 18-10. A typical operating waveform, with dead-band, generated from a single CCP1 input is shown in Figure 18-9. The primary output can be steered to either or both COGxA and COGxC. The complementary output can be steered to either or both COGxB and COGxD. Half-Bridge mode is selected by setting the GxMD bits of the COGxCON0 register to ‘100’. 18.1.4 PUSH-PULL MODE In Push-Pull mode, the COG generates a single PWM output that alternates, every PWM period, between the two pairs of the COG outputs. COGxA has the same signal as COGxC. COGxB has the same signal as COGxD. The output drive activates with the rising input event and terminates with the falling event input. Each rising event starts a new period and causes the output to switch to the COG pair not used in the previous period. The push-pull configuration is shown in Figure 18-6. A typical push-pull waveform generated from a single CCP1 input is shown in Figure 18-11. Push-Pull mode is selected by setting the GxMD bits of the COGxCON0 register to ‘101’. 18.1.5 EVENT-DRIVEN PWM (ALL MODES) Besides generating PWM and complementary outputs from a single PWM input, the COG can also generate PWM waveforms from a periodic rising event and a separate falling event. In this case, the falling event is usually derived from analog feedback within the external PWM driver circuit. In this configuration, high power switching transients may trigger a false falling event that needs to be blanked out. The COG can be configured to blank falling (and rising) event inputs for a period of time immediately following the rising (and falling) event drive output. This is referred to as input blanking and is covered in Section 18.6 “Blanking Control”. 2013-2015 Microchip Technology Inc. DS40001729C-page 173 SIMPLIFIED COG BLOCK DIAGRAM (STEERED PWM MODE, GXMD = 0) GxASDAC<1:0> ‘1’ ‘0’ High-Z reserved HFINTOSC 11 10 Fosc Fosc/4 01 00 unimplemented PWM3OUT CCP2 CCP1 CLC1OUT C2OUT C1OUT COGINPPS COG_clock 1 0 src7 src6 src5 src4 src3 src2 src1 src0 src7 src6 src5 src4 src3 src2 src1 src0 GxSDATA 0 GxSTRA Rising Input Block GxASDBD<1:0> clock ‘1’ ‘0’ High-Z Reset Dominates rising_event S Q count_en GxPOLB GxSDATB COGxB 0 GxASDAC<1:0> GxSTRB ‘1’ ‘0’ High-Z clock 11 10 01 00 1 falling_event COGxC 1 count_en GxPOLC GxSDATC 0 0 GxASDBD<1:0> ‘1’ ‘0’ High-Z GxEN 2013-2015 Microchip Technology Inc. Write GxASE High 1 0 GxSTRC COGINPPS GxAS0E C1OUT GxAS1E C2OUT GxAS2E CLC2OUT GxAS3E 11 10 01 00 1 R Q Falling Input Block unimplemented PWM3OUT CCP2 CCP1 CLC1OUT C2OUT C1OUT COGINPPS COGxA 1 GxPOLA GxCS<1:0> 11 10 01 00 11 10 01 00 1 COGxD 1 GxPOLD Auto-shutdown source GxSDATD 0 0 GxSTRD GxASE S Q GxARSEN Write GxASE Low R Set Dominates S D Q PIC16(L)F1705/9 DS40001729C-page 174 FIGURE 18-2: 2013-2015 Microchip Technology Inc. FIGURE 18-3: SIMPLIFIED COG BLOCK DIAGRAM (SYNCHRONOUS STEERED PWM MODE, GXMD = 1) GxASDAC<1:0> ‘1’ ‘0’ High-Z reserved HFINTOSC 11 10 Fosc Fosc/4 01 00 GxCS<1:0> unimplemented PWM3OUT CCP2 CCP1 CLC1OUT C2OUT C1OUT COGINPPS COG_clock 1 0 GxPOLA GxSTRA Rising Input Block src7 src6 src5 src4 src3 src2 src1 src0 src7 src6 src5 src4 src3 src2 src1 src0 GxSDATA 0 D Q GxASDBD<1:0> clock ‘1’ ‘0’ High-Z Reset Dominates rising_event S Q count_en GxPOLB GxSTRB GxSDATB 1 COGxB 0 0 D Q GxASDAC<1:0> ‘1’ ‘0’ High-Z clock 11 10 01 00 1 falling_event COGxC 1 count_en GxPOLC GxSDATC 0 0 D Q GxASDBD<1:0> 11 10 01 00 1 COGxD 1 GxPOLD GxSTRD Auto-shutdown source GxSDATD 0 0 D Q DS40001729C-page 175 GxASE S Q GxARSEN Write GxASE Low R Set Dominates S D Q PIC16(L)F1705/9 ‘1’ ‘0’ High-Z GxEN Write GxASE High 11 10 01 00 1 R Q GxSTRC COGINPPS GxAS0E C1OUT GxAS1E C2OUT GxAS2E CLC2OUT GxAS3E COGxA 1 Falling Input Block unimplemented PWM3OUT CCP2 CCP1 CLC1OUT C2OUT C1OUT COGINPPS 11 10 01 00 SIMPLIFIED COG BLOCK DIAGRAM (FULL-BRIDGE MODES, FORWARD: GXMD = 2, REVERSE: GXMD = 3) GxASDAC<1:0> ‘1’ ‘0’ High-Z reserved HFINTOSC 11 10 Fosc Fosc/4 01 00 COG_clock 1 Rising Input Block src7 src6 src5 src4 src3 src2 src1 src0 clock clock Reset Dominates rising_event GxASDBD<1:0> GxPOLA signal_out signal_in ‘1’ ‘0’ High-Z S Q 11 10 01 00 R Q GxPOLB src7 src6 src5 src4 src3 src2 src1 src0 signal_out signal_in 11 10 01 00 1 falling_event COGxC 0 count_en GxMD0 GxEN 2013-2015 Microchip Technology Inc. Write GxASE High ‘1’ ‘0’ High-Z clock Forward/Reverse COGINPPS GxAS0E C1OUT GxAS1E C2OUT GxAS2E CLC2OUT GxAS3E COGxB GxASDAC<1:0> Falling Dead-Band Block clock 1 0 count_en Falling Input Block unimplemented PWM3OUT CCP2 CCP1 CLC1OUT C2OUT C1OUT COGINPPS COGxA 0 Rising Dead-Band Block GxCS<1:0> unimplemented PWM3OUT CCP2 CCP1 CLC1OUT C2OUT C1OUT COGINPPS 11 10 01 00 GxPOLC GxASDBD<1:0> ‘1’ ‘0’ High-Z D Q Q 11 10 01 00 1 COGxD 0 Auto-shutdown source GxPOLD GxASE S Q GxARSEN Write GxASE Low R Set Dominates S D Q PIC16(L)F1705/9 DS40001729C-page 176 FIGURE 18-4: 2013-2015 Microchip Technology Inc. FIGURE 18-5: SIMPLIFIED COG BLOCK DIAGRAM (HALF-BRIDGE MODE, GXMD = 4) GxASDAC<1:0> ‘1’ ‘0’ High-Z reserved HFINTOSC 11 10 Fosc Fosc/4 01 00 GxCS<1:0> unimplemented PWM3OUT CCP2 CCP1 CLC1OUT C2OUT C1OUT COGINPPS COG_clock 1 GxPOLA Rising Input Block src7 src6 src5 src4 src3 src2 src1 src0 src7 src6 src5 src4 src3 src2 src1 src0 GxASDBD<1:0> Rising Dead-Band Block clock Reset Dominates rising_event S Q ‘1’ ‘0’ High-Z clock signal_out signal_in 11 10 01 00 COGxB 0 count_en Falling Dead-Band Block GxASDAC<1:0> GxPOLB ‘1’ ‘0’ High-Z clock clock signal_out signal_in 11 10 01 00 1 falling_event COGxC 0 count_en GxASDBD<1:0> 11 10 01 00 1 COGxD 0 Auto-shutdown source GxPOLD DS40001729C-page 177 GxASE S Q GxARSEN Write GxASE Low R Set Dominates S D Q PIC16(L)F1705/9 ‘1’ ‘0’ High-Z GxEN Write GxASE High 1 R Q GxPOLC COGINPPS GxAS0E C1OUT GxAS1E C2OUT GxAS2E CLC2OUT GxAS3E COGxA 0 Falling Input Block unimplemented PWM3OUT CCP2 CCP1 CLC1OUT C2OUT C1OUT COGINPPS 11 10 01 00 SIMPLIFIED COG BLOCK DIAGRAM (PUSH-PULL MODE, GXMD = 5) GxASDAC<1:0> ‘1’ ‘0’ High-Z reserved HFINTOSC 11 10 Fosc Fosc/4 01 00 GxCS<1:0> unimplemented PWM3OUT CCP2 CCP1 CLC1OUT C2OUT C1OUT COGINPPS COG_clock 1 GxPOLA Rising Input Block src7 src6 src5 src4 src3 src2 src1 src0 src7 src6 src5 src4 src3 src2 src1 src0 GxASDBD<1:0> Push-Pull clock Reset Dominates rising_event S Q ‘1’ ‘0’ High-Z D Q R Q 11 10 01 00 R Q count_en COGxB GxASDAC<1:0> GxPOLB ‘1’ ‘0’ High-Z clock 11 10 01 00 1 falling_event COGxC 0 count_en GxASDBD<1:0> ‘1’ ‘0’ High-Z GxEN 2013-2015 Microchip Technology Inc. Write GxASE High 1 0 GxPOLC COGINPPS GxAS0E C1OUT GxAS1E C2OUT GxAS2E CLC2OUT GxAS3E COGxA 0 Falling Input Block unimplemented PWM3OUT CCP2 CCP1 CLC1OUT C2OUT C1OUT COGINPPS 11 10 01 00 11 10 01 00 1 COGxD 0 Auto-shutdown source GxPOLD GxASE S Q GxARSEN Write GxASE Low R Set Dominates S D Q PIC16(L)F1705/9 DS40001729C-page 178 FIGURE 18-6: 2013-2015 Microchip Technology Inc. FIGURE 18-7: COG (RISING/FALLING) INPUT BLOCK clock GxPH(R/F)<3:0> Blanking = Cnt/Clr count_en Phase Delay GxBLK(F/R)<3:0> src7 Gx(R/F)IS7 src6 Gx(R/F)SIM7 Gx(R/F)IS6 src5 Gx(R/F)SIM6 Gx(R/F)IS5 src4 Gx(R/F)SIM5 Gx(R/F)IS4 src3 Gx(R/F)SIM4 Gx(R/F)IS3 Gx(R/F)IS2 src1 Gx(R/F)SIM2 Gx(R/F)IS1 DS40001729C-page 179 src0 Gx(R/F)SIM1 Gx(R/F)IS0 Gx(R/F)SIM0 1 LE 0 D Q 1 LE 0 D Q 1 LE 0 D Q 1 LE 0 D Q 1 LE 0 D Q 1 LE 0 D Q 1 LE 0 D Q 1 LE 0 (rising/falling)_event PIC16(L)F1705/9 src2 Gx(R/F)SIM3 D Q PIC16(L)F1705/9 FIGURE 18-8: COG (RISING/FALLING) DEAD-BAND BLOCK Gx(R/F)DBTS Synchronous Delay = Cnt/Clr clock 0 0 1 GxDBR<3:0> 1 Asynchronous Delay Chain signal_in DS40001729C-page 180 signal_out 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 18-9: TYPICAL HALF-BRIDGE MODE COG OPERATION WITH CCP1 COG_clock Source CCP1 COGxA Rising_event Dead Band Falling_event Dead Band Falling_event Dead Band COGxB FIGURE 18-10: HALF-BRIDGE MODE COG OPERATION WITH CCP1 AND PHASE DELAY COG_clock Source CCP1 COGxA Falling_event Dead Band Phase Delay Rising_event Dead Band COGxB FIGURE 18-11: Falling_event Dead Band PUSH-PULL MODE COG OPERATION WITH CCP1 CCP1 COGxA COGxB 2013-2015 Microchip Technology Inc. DS40001729C-page 181 PIC16(L)F1705/9 FIGURE 18-12: FULL-BRIDGE FORWARD MODE COG OPERATION WITH CCP1 CCP1 COGxA COGxB COGxC COGxD FIGURE 18-13: FULL-BRIDGE MODE COG OPERATION WITH CCP1 AND DIRECTION CHANGE CCP1 COGxA Falling_event Dead Band COGxB COGxC COGxD CxMD0 DS40001729C-page 182 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 18.2 Clock Sources The COG_clock is used as the reference clock to the various timers in the peripheral. Timers that use the COG_clock include: • Rising and falling dead-band time • Rising and falling blanking time • Rising and falling event phase delay precluding an output change. The comparator output stays low and without a high-to-low transition to trigger the edge sense, the drive of the COG output will be stuck in a constant drive-on condition. See Figure 18-14. FIGURE 18-14: Rising (CCP1) Clock sources available for selection include: Falling (C1OUT) • 8 MHz HFINTOSC (active during Sleep) • Instruction clock (FOSC/4) • System clock (FOSC) COGOUT Edge Sensitive Selectable Event Sources Rising (CCP1) The COG uses any combination of independently selectable event sources to generate the complementary waveform. Sources fall into two categories: Falling (C1OUT) • Rising event sources • Falling event sources C1IN- The rising event sources are selected by setting bits in the COGxRIS register (Register 18-3). The falling event sources are selected by setting bits in the COGxFIS register (Register 18-5). All selected sources are ‘OR’d together to generate the corresponding event signal. Refer to Figure 18-7. COGOUT 18.3.1 hyst C1IN- The clock source is selected with the GxCS<1:0> bits of the COGxCON0 register (Register 18-1). 18.3 EDGE VS LEVEL SENSE EDGE VS. LEVEL SENSING Event input detection may be selected as level or edge sensitive. The detection mode is individually selectable for every source. Rising source detection modes are selected with the COGxRSIM register (Register 18-4). Falling source detection modes are selected with the COGxFSIM register (Register 18-6). A set bit enables edge detection for the corresponding event source. A cleared bit enables level detection. In general, events that are driven from a periodic source should be edge detected and events that are derived from voltage thresholds at the target circuit should be level sensitive. Consider the following two examples: hyst Level Sensitive 18.3.2 RISING EVENT The rising event starts the PWM output active duty cycle period. The rising event is the low-to-high transition of the rising_event output. When the rising event phase delay and dead-band time values are zero, the primary output starts immediately. Otherwise, the primary output is delayed. The rising event source causes all the following actions: • • • • • Start rising event phase delay counter (if enabled). Clear complementary output after phase delay. Start falling event input blanking (if enabled). Start dead-band delay (if enabled). Set primary output after dead-band delay expires. 18.3.3 FALLING EVENT 1. The first example is an application in which the period is determined by a 50% duty cycle clock and the COG output duty cycle is determined by a voltage level fed back through a comparator. If the clock input is level sensitive, duty cycles less than 50% will exhibit erratic operation. The falling event terminates the PWM output active duty cycle period. The falling event is the high-to-low transition of the falling_event output. When the falling event phase delay and dead-band time values are zero, the complementary output starts immediately. Otherwise, the complementary output is delayed. The falling event source causes all the following actions: 2. The second example is similar to the first except that the duty cycle is close to 100%. The feedback comparator high-to-low transition trips the COG drive off, but almost immediately the period source turns the drive back on. If the off cycle is short enough, the comparator input may not reach the low side of the hysteresis band • • • • • 2013-2015 Microchip Technology Inc. Start falling event phase delay counter (if enabled). Clear primary output. Start rising event input blanking (if enabled). Start falling event dead-band delay (if enabled). Set complementary output after dead-band delay expires. DS40001729C-page 183 PIC16(L)F1705/9 18.4 Output Control Upon disabling, or immediately after enabling the COG module, the primary COG outputs are inactive and complementary COG outputs are active. 18.4.1 OUTPUT ENABLES There are no output enable controls in the COG module. Instead, each device pin has an individual output selection control called the PPS register. All four COG outputs are available for selection in the PPS register of every pin. When a COG output is enabled by PPS selection, the output on the pin has several possibilities, which depend on the steering control, GxEN bit, and shutdown state as shown in Table 18-1 . TABLE 18-1: GxEN GxSTR Shutdown bit Output Inactive Static steering data 1 Active Shutdown override 1 Inactive Inactive state 1 Inactive Active PWM signal x 0 x 0 1 18.4.2 PIN OUTPUT STATES POLARITY CONTROL The polarity of each COG output can be selected independently. When the output polarity bit is set, the corresponding output is active-low. Clearing the output polarity bit configures the corresponding output as active-high. However, polarity affects the outputs in only one of the four shutdown override modes. See Section 18.8 “Auto-Shutdown Control” for more details. Output polarity is selected with the GxPOLA through GxPOLD bits of the COGxCON1 register (Register 18-2). 18.5 Dead-Band Control The dead-band control provides for non-overlapping PWM output signals to prevent shoot-through current in the external power switches. Dead time affects the output only in the Half-Bridge mode and when changing direction in the Full-Bridge mode. The COG contains two dead-band timers. One dead-band timer is used for rising event dead-band control. The other is used for falling event dead-band control. Timer modes are selectable as either: • Asynchronous delay chain • Synchronous counter The dead-band timer mode is selected for the rising_event and falling_event dead-band times with the respective GxRDBS and GxFDBS bits of the COGxCON1 register (Register 18-2). DS40001729C-page 184 In Half-Bridge mode, the rising_event dead-band time delays all selected primary outputs from going active for the selected dead time after the rising event. COGxA and COGxC are the primary outputs in Half-Bridge mode. In Half-Bridge mode, the falling_event dead-band time delays all selected complementary outputs from going active for the selected dead time after the falling event. COGxB and COGxD are the complementary outputs in Half-Bridge mode. In Full-Bridge mode, the dead-time delay occurs only during direction changes. The modulated output is delayed for the falling_event dead time after a direction change from forward to reverse. The modulated output is delayed for the rising_event dead time after a direction change from reverse to forward. 18.5.1 ASYNCHRONOUS DELAY CHAIN DEAD-BAND DELAY Asynchronous dead-band delay is determined by the time it takes the input to propagate through a series of delay elements. Each delay element is a nominal five nanoseconds. Set the COGxDBR register (Register 18-10) value to the desired number of delay elements in the rising_event dead-band time. Set the COGxDBF register (Register 18-11) value to the desired number of delay elements in the falling_event dead-band time. When the value is zero, dead-band delay is disabled. 18.5.2 SYNCHRONOUS COUNTER DEAD-BAND DELAY Synchronous counter dead band is timed by counting COG_clock periods from zero up to the value in the dead-band count register. Use Equation 18-1 to calculate dead-band times. Set the COGxDBR count register value to obtain the desired rising_event dead-band time. Set the COGxDBF count register value to obtain the desired falling_event dead-band time. When the value is zero, dead-band delay is disabled. 18.5.3 SYNCHRONOUS COUNTER DEAD-BAND TIME UNCERTAINTY When the rising and falling events that trigger the dead-band counters come from asynchronous inputs, it creates uncertainty in the synchronous counter dead-band time. The maximum uncertainty is equal to one COG_clock period. Refer to Example 18-1 for more detail. When event input sources are asynchronous with no phase delay, use the asynchronous delay chain dead-band mode to avoid the dead-band time uncertainty. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 18.5.4 RISING EVENT DEAD-BAND Rising event dead band delays the turn-on of the primary outputs from when complementary outputs are turned off. The rising event dead-band time starts when the rising_ event output goes true. See Section 18.5.1 “Asynchronous Delay Chain Dead-Band Delay” and Section 18.5.2 “Synchronous Counter Dead-Band Delay” for more information on setting the rising edge dead-band time. 18.5.5 FALLING EVENT DEAD-BAND Falling event dead band delays the turn-on of complementary outputs from when the primary outputs are turned off. The falling event dead-band time starts when the falling_ event output goes true. See Section 18.5.1 “Asynchronous Delay Chain Dead-Band Delay” and Section 18.5.2 “Synchronous Counter Dead-Band Delay” for more information on setting the rising edge dead-band time. 18.5.6 • Rising-to-falling • Falling-to-rising Rising-to-Falling Overlap In this case, the falling event occurs while the rising event dead-band counter is still counting. When this happens, the primary drives are suppressed and the dead-band extends by the falling event dead-band time. At the termination of the extended dead-band time, the complementary drive goes true. 18.5.6.2 Falling-to-Rising Overlap In this case, the rising event occurs while the falling event dead-band counter is still counting. When this happens, the complementary drive is suppressed and the dead-band extends by the rising event dead-band time. At the termination of the extended dead-band time, the primary drive goes true. 18.6 18.6.1 Blanking Control Input blanking is a function, whereby, the event inputs can be masked or blanked for a short period of time. This is to prevent electrical transients caused by the turn-on/off of power components from generating a false input event. The COG contains two blanking counters: one triggered by the rising event and the other triggered by the falling event. The counters are cross coupled with the events they are blanking. The falling event blanking counter is used to blank rising input events and the rising event blanking counter is used to blank falling input events. Once started, blanking extends for the time specified by the corresponding blanking counter. 2013-2015 Microchip Technology Inc. FALLING EVENT BLANKING OF RISING EVENT INPUTS The falling event blanking counter inhibits rising event inputs from triggering a rising event. The falling event blanking time starts when the rising event output drive goes false. The falling event blanking time is set by the value contained in the COGxBLKF register (Register 18-13). Blanking times are calculated using the formula shown in Equation 18-1. When the COGxBLKF value is zero, falling event blanking is disabled and the blanking counter output is true, thereby, allowing the event signal to pass straight through to the event trigger circuit. 18.6.2 DEAD-BAND OVERLAP There are two cases of dead-band overlap: 18.5.6.1 Blanking is timed by counting COG_clock periods from zero up to the value in the blanking count register. Use Equation 18-1 to calculate blanking times. RISING EVENT BLANKING OF FALLING EVENT INPUTS The rising event blanking counter inhibits falling event inputs from triggering a falling event. The rising event blanking time starts when the falling event output drive goes false. The rising event blanking time is set by the value contained in the COGxBLKR register (Register 18-12). When the COGxBLKR value is zero, rising event blanking is disabled and the blanking counter output is true, thereby, allowing the event signal to pass straight through to the event trigger circuit. 18.6.3 BLANKING TIME UNCERTAINTY When the rising and falling sources that trigger the blanking counters are asynchronous to the COG_clock, it creates uncertainty in the blanking time. The maximum uncertainty is equal to one COG_clock period. Refer to Equation 18-1 and Example 18-1 for more detail. 18.7 Phase Delay It is possible to delay the assertion of either or both the rising event and falling events. This is accomplished by placing a non-zero value in COGxPHR or COGxPHF phase-delay count register, respectively (Register 18-14 and Register 18-15). Refer to Figure 18-10 for COG operation with CCP1 and phase delay. The delay from the input rising event signal switching to the actual assertion of the events is calculated the same as the dead-band and blanking delays. Refer to Equation 18-1. When the phase-delay count value is zero, phase delay is disabled and the phase-delay counter output is true, thereby, allowing the event signal to pass straight through to the complementary output driver flop. DS40001729C-page 185 PIC16(L)F1705/9 18.7.1 CUMULATIVE UNCERTAINTY It is not possible to create more than one COG_clock of uncertainty by successive stages. Consider that the phase-delay stage comes after the blanking stage, the dead-band stage comes after either the blanking or phase-delay stages, and the blanking stage comes after the dead-band stage. When the preceding stage is enabled, the output of that stage is necessarily synchronous with the COG_clock, which removes any possibility of uncertainty in the succeeding stage. EQUATION 18-1: PHASE, DEAD-BAND AND BLANKING TIME CALCULATION T min = Count EXAMPLE 18-1: Given: Count = Ah = 10d F COG_Clock = 8MHz Therefore: 1 T uncertainty = -------------------------F COG_clock 1 = --------------- = 125ns 8MHz Proof: Count T min = -------------------------F COG_clock = 125ns 10d = 1.25s F COG_clock T max Count + 1 = -------------------------F COG_clock T uncertainty = T max – T min Count + 1 T max = -------------------------F COG_clock = 125ns 10d + 1 Also: 1 T uncertainty = -------------------------F COG_clock Where: TIMER UNCERTAINTY = 1.375s Therefore: T uncertainty = T max – T min T Count Rising Phase Delay COGxPHR Falling Phase Delay COGxPHF Rising Dead Band COGxDBR Falling Dead Band COGxDBF Rising Event Blanking COGxBLKR Falling Event Blanking COGxBLKF DS40001729C-page 186 = 1.375s – 1.25s = 125ns 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 18.8 Auto-Shutdown Control Auto-shutdown is a method to immediately override the COG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. In either case, the shutdown overrides remain in effect until the first rising event after the shutdown is cleared. 18.8.1 SHUTDOWN The shutdown state can be entered by either of the following two mechanisms: • Software generated • External Input 18.8.1.1 When auto-restart is disabled, the shutdown state will persist until the first rising event after the GxASE bit is cleared by software. When auto-restart is enabled, the GxASE bit will clear automatically and resume operation on the first rising event after the shutdown input clears. See Figure 18-15 and Section 18.8.3.2 “Auto-Restart”. External Shutdown Source External shutdown inputs provide the fastest way to safely suspend COG operation in the event of a Fault condition. When any of the selected shutdown inputs goes true, the output drive latches are reset and the COG outputs immediately go to the selected override levels without software delay. Any combination of the input sources can be selected to cause a shutdown condition. Shutdown occurs when the selected source is low. Shutdown input sources include: • • • • Any input pin selected with the COGxPPS control C2OUT C1OUT CLC2OUT PIN OVERRIDE LEVELS The levels driven to the output pins, while the shutdown is active, are controlled by the GxASDAC<1:0> and GxASDBC<1:0> bits of the COGxASD0 register (Register 18-7). GxASDAC<1:0> controls the COGxA and COGxC override levels and GxASDBC<1:0> controls the COGxB and COGxD override levels. There are four override options for each output pair: • • • • Forced low Forced high Tri-state PWM inactive state (same state as that caused by a falling event) Note: Software Generated Shutdown Setting the GxASE bit of the COGxASD0 register (Register 18-7) will force the COG into the shutdown state. 18.8.1.2 18.8.2 18.8.3 The polarity control does not apply to the forced low and high override levels but does apply to the PWM inactive state. AUTO-SHUTDOWN RESTART After an auto-shutdown event has occurred, there are two ways to resume operation: • Software controlled • Auto-restart The restart method is selected with the GxARSEN bit of the COGxASD0 register. Waveforms of a software controlled automatic restart are shown in Figure 18-15. 18.8.3.1 Software-Controlled Restart When the GxARSEN bit of the COGxASD0 register is cleared, software must clear the GxASE bit to restart COG operation after an auto-shutdown event. The COG will resume operation on the first rising event after the GxASE bit is cleared. Clearing the shutdown state requires all selected shutdown inputs to be false, otherwise, the GxASE bit will remain set. 18.8.3.2 Auto-Restart When the GxARSEN bit of the COGxASD0 register is set, the COG will restart from the auto-shutdown state automatically. The GxASE bit will clear automatically and the COG will resume operation on the first rising event after all selected shutdown inputs go false. Shutdown inputs are selected independently with bits of the COGxASD1 register (Register 18-8). Note: Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared as long as the shutdown input level persists, except by disabling auto-shutdown, 2013-2015 Microchip Technology Inc. DS40001729C-page 187 1 2 3 4 5 CCP1 GxARSEN Next rising event Shutdown input Next rising event GxASE Cleared in hardware Cleared in software GxASDAC 2b00 2b00 2b00 GxASDBD COGxA COGxB 2013-2015 Microchip Technology Inc. Operating State NORMAL OUTPUT SHUTDOWN NORMAL OUTPUT SOFTWARE CONTROLLED RESTART SHUTDOWN NORMAL OUTPUT AUTO-RESTART PIC16(L)F1705/9 DS40001729C-page 188 FIGURE 18-15: AUTO-SHUTDOWN WAVEFORM – CCP1 AS RISING AND FALLING EVENT INPUT SOURCE PIC16(L)F1705/9 18.9 Buffer Updates Changes to the phase, dead band, and blanking count registers need to occur simultaneously during COG operation to avoid unintended operation that may occur as a result of delays between each register write. This is accomplished with the GxLD bit of the COGxCON0 register and double buffering of the phase, blanking, and dead-band count registers. Before the COG module is enabled, writing the count registers loads the count buffers without need of the GxLD bit. However, when the COG is enabled, the count buffer updates are suspended after writing the count registers until after the GxLD bit is set. When the GxLD bit is set, the phase, dead-band, and blanking register values are transferred to the corresponding buffers synchronous with COG operation. The GxLD bit is cleared by hardware when the transfer is complete. 18.10 Input and Output Pin Selection The COG has one selection for an input from a device pin. That one input can be used as rising and falling event source or a fault source. The COG1PPS register is used to select the pin. Refer to Register 12-1 and Register 12-2. The pin PPS control registers are used to enable the COG outputs. Any combination of outputs to pins is possible including multiple pins for the same output. See the RxyPPS control register and Section 12.2 “PPS Outputs” for more details. 18.12 Configuring the COG The following steps illustrate how to properly configure the COG to ensure a synchronous start with the rising event input: 1. 2. 3. 4. 5. 6. 7. 8. 9. 18.11 Operation During Sleep The COG continues to operate in Sleep provided that the COG_clock, rising event, and falling event sources remain active. The HFINTSOC remains active during Sleep when the COG is enabled and the HFINTOSC is selected as the COG_clock source. 10. 11. 12. 13. 14. 15. 16. 17. 2013-2015 Microchip Technology Inc. If a pin is to be used for the COG fault or event input, use the COGxPPS register to configure the desired pin. Clear all ANSEL register bits associated with pins that are used for COG functions. Ensure that the TRIS control bits corresponding to the COG outputs to be used are cleared so that all are configured as outputs. The COG module will disable the output drivers as needed for shutdown. Clear the GxEN bit, if not already cleared. Set desired dead-band times with the COGxDBR and COGxDBF registers and select the source with the COGxRDBS and COGxFDBS bits of the COGxCON1 register. Set desired blanking times with the COGxBLKR and COGxBLKF registers. Set desired phase delay with the COGxPHR and COGxPHF registers. Select the desired shutdown sources with the COGxASD1 register. Setup the following controls in COGxASD0 auto-shutdown register: • Select both output override controls to the desired levels (this is necessary, even if not using auto-shutdown because start-up will be from a shutdown state). • Set the GxASE bit and clear the GxARSEN bit. Select the desired rising and falling event sources with the COGxRIS and COGxFIS registers. Select the desired rising and falling event modes with the COGxRSIM and COGxFSIM registers. Configure the following controls in the COGxCON1 register: • Select the desired clock source • Select the desired dead-band timing sources Configure the following controls in the COGxSTR register: • Set the steering bits of the outputs to be used. • Set the static levels. Set the polarity controls in the COGxCON1 register. Set the GxEN bit. Set the pin PPS controls to direct the COG outputs to the desired pins. If auto-restart is to be used, set the GxARSEN bit and the GxASE will be cleared automatically. Otherwise, clear the GxASE bit to start the COG. DS40001729C-page 189 PIC16(L)F1705/9 18.13 Register Definitions: COG Control REGISTER 18-1: COGxCON0: COG CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 GxEN GxLD — R/W-0/0 R/W-0/0 R/W-0/0 GxCS<1:0> R/W-0/0 R/W-0/0 GxMD<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxEN: COGx Enable bit 1 = Module is enabled 0 = Module is disabled bit 6 GxLD: COGx Load Buffers bit 1 = Phase, blanking, and dead-band buffers to be loaded with register values on next input events 0 = Register to buffer transfer is complete bit 5 Unimplemented: Read as ‘0’ bit 4-3 GxCS<1:0>: COGx Clock Selection bits 11 = Reserved. Do not use. 10 = COG_clock is HFINTOSC (stays active during Sleep) 01 = COG_clock is FOSC 00 = COG_clock is FOSC/4 bit 2-0 GxMD<2:0>: COGx Mode Selection bits 11x = Reserved. Do not use. 101 = COG outputs operate in Push-Pull mode 100 = COG outputs operate in Half-Bridge mode 011 = COG outputs operate in Reverse Full-Bridge mode 010 = COG outputs operate in Forward Full-Bridge mode 001 = COG outputs operate in synchronous steered PWM mode 000 = COG outputs operate in steered PWM mode DS40001729C-page 190 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 18-2: R/W-0/0 GxRDBS COGxCON1: COG CONTROL REGISTER 1 R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 GxFDBS — — GxPOLD GxPOLC GxPOLB GxPOLA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxRDBS: COGx Rising Event Dead-band Timing Source Select bit 1 = Delay chain and COGxDBR are used for dead-band timing generation 0 = COGx_clock and COGxDBR are used for dead-band timing generation bit 6 GxFDBS: COGx Falling Event Dead-band Timing Source select bit 1 = Delay chain and COGxDF are used for dead-band timing generation 0 = COGx_clock and COGxDBF are used for dead-band timing generation bit 5-4 Unimplemented: Read as ‘0’. bit 3 GxPOLD: COGxD Output Polarity Control bit 1 = Active level of COGxD output is low 0 = Active level of COGxD output is high bit 2 GxPOLC: COGxC Output Polarity Control bit 1 = Active level of COGxC output is low 0 = Active level of COGxC output is high bit 1 GxPOLB: COGxB Output Polarity Control bit 1 = Active level of COGxB output is low 0 = Active level of COGxB output is high bit 0 GxPOLA: COGxA Output Polarity Control bit 1 = Active level of COGxA output is low 0 = Active level of COGxA output is high 2013-2015 Microchip Technology Inc. DS40001729C-page 191 PIC16(L)F1705/9 REGISTER 18-3: COGxRIS: COG RISING EVENT INPUT SELECTION REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — GxRIS6 GxRIS5 GxRIS4 GxRIS3 GxRIS2 GxRIS1 GxRIS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as ‘0’ bit 6 GxRIS6: COGx Rising Event Input Source 6 Enable bit 1 = PWM3 output is enabled as a rising event input 0 = PWM3 has no effect on the rising event bit 5 GxRIS5: COGx Rising Event Input Source 5 Enable bit 1 = CCP2 output is enabled as a rising event input 0 = CCP2 output has no effect on the rising event bit 4 GxRIS4: COGx Rising Event Input Source 4 Enable bit 1 = CCP1 is enabled as a rising event input 0 = CCP1 has no effect on the rising event bit 3 GxRIS3: COGx Rising Event Input Source 3 Enable bit 1 = CLC1 output is enabled as a rising event input 0 = CLC1 output has no effect on the rising event bit 2 GxRIS2: COGx Rising Event Input Source 2 Enable bit 1 = Comparator 2 output is enabled as a rising event input 0 = Comparator 2 output has no effect on the rising event bit 1 GxRIS1: COGx Rising Event Input Source 1 Enable bit 1 = Comparator 1 output is enabled as a rising event input 0 = Comparator 1 output has no effect on the rising event bit 0 GxRIS0: COGx Rising Event Input Source 0 Enable bit 1 = Pin selected with COGxPPS control register is enabled as rising event input 0 = Pin selected with COGxPPS control has no effect on the rising event DS40001729C-page 192 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 18-4: COGxRSIM: COG RISING EVENT SOURCE INPUT MODE REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — GxRSIM6 GxRSIM5 GxRSIM4 GxRSIM3 GxRSIM2 GxRSIM1 GxRSIM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as ‘0’ bit 6 GxRSIM6: COGx Rising Event Input Source 6 Mode bit GxRIS6 = 1: 1 = PWM3 output low-to-high transition will cause a rising event after rising event phase delay 0 = PWM3 output high level will cause an immediate rising event GxRIS6 = 0: PWM3 output has no effect on rising event bit 5 GxRSIM5: COGx Rising Event Input Source 5 Mode bit GxRIS5 = 1: 1 = CCP2 output low-to-high transition will cause a rising event after rising event phase delay 0 = CCP2 output high level will cause an immediate rising event GxRIS5 = 0: CCP2 output has no effect on rising event bit 4 GxRSIM4: COGx Rising Event Input Source 4 Mode bit GxRIS4 = 1: 1 = CCP1 low-to-high transition will cause a rising event after rising event phase delay 0 = CCP1 high level will cause an immediate rising event GxRIS4 = 0: CCP1 has no effect on rising event bit 3 GxRSIM3: COGx Rising Event Input Source 3 Mode bit GxRIS3 = 1: 1 = CLC1 output low-to-high transition will cause a rising event after rising event phase delay 0 = CLC1 output high level will cause an immediate rising event GxRIS3 = 0: CLC1 output has no effect on rising event bit 2 GxRSIM2: COGx Rising Event Input Source 2 Mode bit GxRIS2 = 1: 1 = Comparator 2 low-to-high transition will cause a rising event after rising event phase delay 0 = Comparator 2 high level will cause an immediate rising event GxRIS2 = 0: Comparator 2 has no effect on rising event bit 1 GxRSIM1: COGx Rising Event Input Source 1 Mode bit GxRIS1 = 1: 1 = Comparator 1 low-to-high transition will cause a rising event after rising event phase delay 0 = Comparator 1 high level will cause an immediate rising event GxRIS1 = 0: Comparator 1 has no effect on rising event bit 0 GxRSIM0: COGx Rising Event Input Source 0 Mode bit GxRIS0 = 1: 1 = Pin selected with COGxPPS control low-to-high transition will cause a rising event after rising event phase delay 0 = Pin selected with COGxPPS control high level will cause an immediate rising event GxRIS0 = 0: Pin selected with COGxPPS control has no effect on rising event 2013-2015 Microchip Technology Inc. DS40001729C-page 193 PIC16(L)F1705/9 REGISTER 18-5: COGxFIS: COG FALLING EVENT INPUT SELECTION REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — GxFIS6 GxFIS5 GxFIS4 GxFIS3 GxFIS2 GxFIS1 GxFIS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as ‘0’ bit 6 GxFIS6: COGx Falling Event Input Source 6 Enable bit 1 = PWM3 output is enabled as a falling event input 0 = PWM3 has no effect on the falling event bit 5 GxFIS5: COGx Falling Event Input Source 5 Enable bit 1 = CCP2 output is enabled as a falling event input 0 = CCP2 output has no effect on the falling event bit 4 GxFIS4: COGx Falling Event Input Source 4 Enable bit 1 = CCP1 is enabled as a falling event input 0 = CCP1 has no effect on the falling event bit 3 GxFIS3: COGx Falling Event Input Source 3 Enable bit 1 = CLC1 output is enabled as a falling event input 0 = CLC1 output has no effect on the falling event bit 2 GxFIS2: COGx Falling Event Input Source 2 Enable bit 1 = Comparator 2 output is enabled as a falling event input 0 = Comparator 2 output has no effect on the falling event bit 1 GxFIS1: COGx Falling Event Input Source 1 Enable bit 1 = Comparator 1 output is enabled as a falling event input 0 = Comparator 1 output has no effect on the falling event bit 0 GxFIS0: COGx Falling Event Input Source 0 Enable bit 1 = Pin selected with COGxPPS control register is enabled as falling event input 0 = Pin selected with COGxPPS control has no effect on the falling event DS40001729C-page 194 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 18-6: COGxFSIM: COG FALLING EVENT SOURCE INPUT MODE REGISTER U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — GxFSIM6 GxFSIM5 GxFSIM4 GxFSIM3 GxFSIM2 GxFSIM1 GxFSIM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 Unimplemented: Read as ‘0’ bit 6 GxFSIM6: COGx Falling Event Input Source 6 Mode bit GxFIS6 = 1: 1 = PWM3 output high-to-low transition will cause a falling event after falling event phase delay 0 = PWM3 output low level will cause an immediate falling event GxFIS6 = 0: PWM3 output has no effect on falling event bit 5 GxFSIM5: COGx Falling Event Input Source 5 Mode bit GxFIS5 = 1: 1 = CCP2 output high-to-low transition will cause a falling event after falling event phase delay 0 = CCP2 output low level will cause an immediate falling event GxFIS5 = 0: CCP2 output has no effect on falling event bit 4 GxFSIM4: COGx Falling Event Input Source 4 Mode bit GxFIS4 = 1: 1 = CCP1 high-to-low transition will cause a falling event after falling event phase delay 0 = CCP1 low level will cause an immediate falling event GxFIS4 = 0: CCP1 has no effect on falling event bit 3 GxFSIM3: COGx Falling Event Input Source 3 Mode bit GxFIS3 = 1: 1 = CLC1 output high-to-low transition will cause a falling event after falling event phase delay 0 = CLC1 output low level will cause an immediate falling event GxFIS3 = 0: CLC1 output has no effect on falling event bit 2 GxFSIM2: COGx Falling Event Input Source 2 Mode bit GxFIS2 = 1: 1 = Comparator 2 high-to-low transition will cause a falling event after falling event phase delay 0 = Comparator 2 low level will cause an immediate falling event GxFIS2 = 0: Comparator 2 has no effect on falling event bit 1 GxFSIM1: COGx Falling Event Input Source 1 Mode bit GxFIS1 = 1: 1 = Comparator 1 high-to-low transition will cause a falling event after falling event phase delay 0 = Comparator 1 low level will cause an immediate falling event GxFIS1 = 0: Comparator 1 has no effect on falling event bit 0 GxFSIM0: COGx Falling Event Input Source 0 Mode bit GxFIS0 = 1: 1 = Pin selected with COGxPPS control high-to-low transition will cause a falling event after falling event phase delay 0 = Pin selected with COGxPPS control low level will cause an immediate falling event GxFIS0 = 0: Pin selected with COGxPPS control has no effect on falling event 2013-2015 Microchip Technology Inc. DS40001729C-page 195 PIC16(L)F1705/9 REGISTER 18-7: COGxASD0: COG AUTO-SHUTDOWN CONTROL REGISTER 0 R/W-0/0 R/W-0/0 GxASE GxARSEN R/W-0/0 R/W-0/0 GxASDBD<1:0> R/W-0/0 R/W-0/0 GxASDAC<1:0> U-0 U-0 — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxASE: Auto-Shutdown Event Status bit 1 = COG is in the shutdown state 0 = COG is either not in the shutdown state or will exit the shutdown state on the next rising event bit 6 GxARSEN: Auto-Restart Enable bit 1 = Auto-restart is enabled 0 = Auto-restart is disabled bit 5-4 GxASDBD<1:0>: COGxB and COGxD Auto-shutdown Override Level Select bits 11 = A logic ‘1’ is placed on COGxB and COGxD when shutdown is active 10 = A logic ‘0’ is placed on COGxB and COGxD when shutdown is active 01 = COGxB and COGxD are tri-stated when shutdown is active 00 = The inactive state of the pin, including polarity, is placed on COGxB and COGxD when shutdown is active bit 3-2 GxASDAC<1:0>: COGxA and COGxC Auto-shutdown Override Level Select bits 11 = A logic ‘1’ is placed on COGxA and COGxC when shutdown is active 10 = A logic ‘0’ is placed on COGxA and COGxC when shutdown is active 01 = COGxA and COGxC are tri-stated when shutdown is active 00 = The inactive state of the pin, including polarity, is placed on COGxA and COGxC when shutdown is active bit 1-0 Unimplemented: Read as ‘0’ DS40001729C-page 196 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 18-8: COGxASD1: COG AUTO-SHUTDOWN CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 — — — — GxAS3E GxAS2E GxAS1E GxAS0E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-4 Unimplemented: Read as ‘0’ bit 3 GxAS3E: COGx Auto-shutdown Source Enable bit 3 1 = COGx is shutdown when CLC2 output is low 0 = CLC2 output has no effect on shutdown bit 2 GxAS2E: COGx Auto-shutdown Source Enable bit 2 1 = COGx is shutdown when Comparator 2 output is low 0 = Comparator 2 output has no effect on shutdown bit 1 GxAS1E: COGx Auto-shutdown Source Enable bit 1 1 = COGx is shutdown when Comparator 1 output is low 0 = Comparator 1 output has no effect on shutdown bit 0 GxAS0E: COGx Auto-shutdown Source Enable bit 0 1 = COGx is shutdown when Pin selected with COGxPPS control is low 0 = Pin selected with COGxPPS control has no effect on shutdown 2013-2015 Microchip Technology Inc. DS40001729C-page 197 PIC16(L)F1705/9 REGISTER 18-9: COGxSTR: COG STEERING CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 GxSDATD GxSDATC GxSDATB GxSDATA GxSTRD GxSTRC GxSTRB GxSTRA bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 GxSDATD: COGxD Static Output Data bit 1 = COGxD static data is high 0 = COGxD static data is low bit 6 GxSDATC: COGxC Static Output Data bit 1 = COGxC static data is high 0 = COGxC static data is low bit 5 GxSDATB: COGxB Static Output Data bit 1 = COGxB static data is high 0 = COGxB static data is low bit 4 GxSDATA: COGxA Static Output Data bit 1 = COGxA static data is high 0 = COGxA static data is low bit 3 GxSTRD: COGxD Steering Control bit 1 = COGxD output has the COGxD waveform with polarity control from GxPOLD bit 0 = COGxD output is the static data level determined by the GxSDATD bit bit 2 GxSTRC: COGxC Steering Control bit 1 = COGxC output has the COGxC waveform with polarity control from GxPOLC bit 0 = COGxC output is the static data level determined by the GxSDATC bit bit 1 GxSTRB: COGxB Steering Control bit 1 = COGxB output has the COGxB waveform with polarity control from GxPOLB bit 0 = COGxB output is the static data level determined by the GxSDATB bit bit 0 GxSTRA: COGxA Steering Control bit 1 = COGxA output has the COGxA waveform with polarity control from GxPOLA bit 0 = COGxA output is the static data level determined by the GxSDATA bit DS40001729C-page 198 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 18-10: COGxDBR: COG RISING EVENT DEAD-BAND COUNT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u GxDBR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GxDBR<5:0>: Rising Event Dead-band Count Value bits GxRDBS = 0: = Number of COGx clock periods to delay primary output after rising event GxRDBS = 1: = Number of delay chain element periods to delay primary output after rising event REGISTER 18-11: COGxDBF: COG FALLING EVENT DEAD-BAND COUNT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u GxDBF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GxDBF<5:0>: Falling Event Dead-band Count Value bits GxFDBS = 0: = Number of COGx clock periods to delay complementary output after falling event input GxFDBS = 1: = Number of delay chain element periods to delay complementary output after falling event input 2013-2015 Microchip Technology Inc. DS40001729C-page 199 PIC16(L)F1705/9 REGISTER 18-12: COGxBLKR: COG RISING EVENT BLANKING COUNT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u GxBLKR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GxBLKR<5:0>: Rising Event Blanking Count Value bits = Number of COGx clock periods to inhibit falling event inputs REGISTER 18-13: COGxBLKF: COG FALLING EVENT BLANKING COUNT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u GxBLKF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GxBLKF<5:0>: Falling Event Blanking Count Value bits = Number of COGx clock periods to inhibit rising event inputs DS40001729C-page 200 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 18-14: COGxPHR: COG RISING EDGE PHASE DELAY COUNT REGISTER U-0 U-0 — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u GxPHR<5:0> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GxPHR<5:0>: Rising Edge Phase Delay Count Value bits = Number of COGx clock periods to delay rising edge event REGISTER 18-15: COGxPHF: COG FALLING EDGE PHASE DELAY COUNT REGISTER U-0 U-0 — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u GxPHF<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 GxPHF<5:0>: Falling Edge Phase Delay Count Value bits = Number of COGx clock periods to delay falling edge event 2013-2015 Microchip Technology Inc. DS40001729C-page 201 PIC16(L)F1705/9 TABLE 18-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH COG Bit 7 Bit 6 ANSELA — ANSELB(1) — Register on Page Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — ANSA4 — ANSA2 ANSA1 ANSA0 122 — ANSB5 ANSB4 — — — — 128 ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133 ANSC7(1) ANSC6(1) COG1PHR — — G1PHR<5:0> 201 COG1PHF — — G1PHF<5:0> 201 COG1BLKR — — G1BLKR<5:0> 200 COG1BLKF — — G1BLKF<5:0> 200 COG1DBR — — G1DBR<5:0> 199 COG1DBF — — G1DBF<5:0> COG1RIS — G1RIS6 G1RIS5 G1RIS4 G1RIS3 G1RIS2 G1RIS1 G1RIS0 192 COG1RSIM — G1RSIM6 G1RSIM5 G1RSIM4 G1RSIM3 G1RSIM2 G1RSIM1 G1RSIM0 193 COG1FIS — G1FIS6 G1FIS5 G1FIS4 G1FIS3 G1FIS2 G1FIS1 G1FIS0 194 COG1FSIM — G1FSIM6 G1FSIM5 G1FSIM4 G1FSIM3 G1FSIM2 G1FSIM1 G1FSIM0 COG1CON0 G1EN G1LD — COG1CON1 G1RDBS G1FDBS — COG1ASD0 G1ASE G1ARSEN ANSELC 199 G1CS<1:0> — G1ASDBD<1:0> G1MD<2:0> G1POLD G1POLC G1ASDAC<1:0> 195 190 G1POLB G1POLA 191 — — 196 COG1ASD1 — — — — G1AS3E G1AS2E G1AS1E G1AS0E 197 COG1STR G1SDATD G1SDATC G1SDATB G1SDATA G1STRD G1STRC G1STRB G1STRA 198 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF — — — PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 86 PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 89 — — — INTCON COG1PPS RxyPPS Legend: Note 1: 2: COG1PPS<4:0> 84 140 RxyPPS<4:0> 141 x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by COG. PIC16(L)F1709 only. PIC16(L)F1705 only. DS40001729C-page 202 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 19.0 CONFIGURABLE LOGIC CELL (CLC) The Configurable Logic Cell (CLCx) provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 32 input signals and, through the use of configurable gates, reduces the 32 inputs to four logic lines that drive one of eight selectable single-output logic functions. Input sources are a combination of the following: • • • • I/O pins Internal clocks Peripherals Register bits The output can be directed internally to peripherals and to an output pin. FIGURE 19-1: Refer to Figure 19-1 for a simplified diagram showing signal flow through the CLCx. Possible configurations include: • Combinatorial Logic - AND - NAND - AND-OR - AND-OR-INVERT - OR-XOR - OR-XNOR • Latches - S-R - Clocked D with Set and Reset - Transparent D with Set and Reset - Clocked J-K with Reset CLCx SIMPLIFIED BLOCK DIAGRAM D Q LCxOUT MLCxOUT Q1 . . . LCx_in[29] LCx_in[30] LCx_in[31] to Peripherals Input Data Selection Gates(1) LCx_in[0] LCx_in[1] LCx_in[2] LCxEN lcxg1 lcxg2 lcxg3 Logic Function LCx_out lcxq (2) PPS Module CLCx lcxg4 LCxPOL LCxMODE<2:0> Interrupt det LCXINTP LCXINTN set bit CLCxIF Interrupt det Note 1: 2: See Figure 19-2: Input Data Selection and Gating. See Figure 19-3: Programmable Logic Functions. 2013-2015 Microchip Technology Inc. DS40001729C-page 203 PIC16(L)F1705/9 19.1 CLCx Setup Programming the CLCx module is performed by configuring the four stages in the logic signal flow. The four stages are: • • • • Data selection Data gating Logic function selection Output polarity Each stage is setup at run time by writing to the corresponding CLCx Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 19.1.1 DATA SELECTION There are 32 signals available as inputs to the configurable logic. Four 32-input multiplexers are used to select the inputs to pass on to the next stage. TABLE 19-1: Data Input CLCx DATA INPUT SELECTION lcxdy DxS CLCx LCx_in[31] 11111 FOSC LCx_in[30] 11110 HFINTOSC LCx_in[29] 11101 LFINTOSC LCx_in[28] 11100 ADCRC LCx_in[27] 11011 IOCIF set signal (bit?) LCx_in[26] 11010 T2_match LCx_in[25] 11001 T1_overflow LCx_in[24] 11000 T0_overflow LCx_in[23] 10111 T6_match LCx_in[22] 10110 T4_match LCx_in[21] 10101 DT from EUSART LCx_in[20] 10100 TX/CK from EUSART Data selection is through four multiplexers as indicated on the left side of Figure 19-2. Data inputs in the figure are identified by a generic numbered input name. LCx_in[19] 10011 ZCDx_out from Zero-Cross Detect Table 19-1 correlates the generic input name to the actual signal for each CLC module. The column labeled lcxdy indicates the MUX selection code for the selected data input. DxS is an abbreviation for the MUX select input codes: LCxD1S<4:0> through LCxD4S<4:0>. LCx_in[16] 10000 SCK from MSSP Data inputs are selected with CLCxSEL0 through CLCxSEL3 registers (Register 19-3 through Register 19-6). LCx_in[12] 01100 CCP1 output Note: Data selections are undefined at power-up. DS40001729C-page 204 LCx_in[18] 10010 SDO from MSSP LCx_in[17] 10001 Reserved LCx_in[15] 01111 PWM4_out LCx_in[14] 01110 PWM3_out LCx_in[13] 01101 CCP2 output LCx_in[11] 01011 COG1B LCx_in[10] 01010 COG1A LCx_in[9] 01001 C2OUT LCx_in[8] 01000 C1OUT LCx_in[7] 00111 Reserved LCx_in[6] 00110 LC3_out from the CLC3 LCx_in[5] 00101 LC2_out from the CLC2 LCx_in[4] 00100 LC1_out from the CLC1 LCx_in[3] 00011 CLCIN3 pin input selected in CLCIN3PPS register LCx_in[2] 00010 CLCIN2 pin input selected in CLCIN2PPS register LCx_in[1] 00001 CLCIN1 pin input selected in CLCIN1PPS register LCx_in[0] 00000 CLCIN0 pin input selected in CLCIN0PPS register 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 19.1.2 DATA GATING Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. Note: Data gating is undefined at power-up. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ANDed together in each gate. The output of each gate can be inverted before going on to the logic function stage. The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the output is inverted, the gate is an OR of all enabled data inputs. When the inputs and output are not inverted, the gate is an AND or all enabled inputs. Table 19-2 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. TABLE 19-2: DATA GATING LOGIC CLCxGLS0 LCxG1POL Gate Logic 0x55 1 AND 0x55 0 NAND 0xAA 1 NOR 0xAA 0 OR 0x00 0 Logic 0 0x00 1 Logic 1 Data gating is indicated in the right side of Figure 19-2. Only one gate is shown in detail. The remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate. 19.1.3 LOGIC FUNCTION There are eight available logic functions including: • • • • • • • • AND-OR OR-XOR AND S-R Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in Figure 19-3. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the CLCx itself. 19.1.4 OUTPUT POLARITY The last stage in the configurable logic cell is the output polarity. Setting the LCxPOL bit of the CLCxCON register inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). If the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity bit to set the desired level. Data gating is configured with the logic gate select registers as follows: • • • • Gate 1: CLCxGLS0 (Register 19-7) Gate 2: CLCxGLS1 (Register 19-8) Gate 3: CLCxGLS2 (Register 19-9) Gate 4: CLCxGLS3 (Register 19-10) Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register. 2013-2015 Microchip Technology Inc. DS40001729C-page 205 PIC16(L)F1705/9 19.1.5 CLCx SETUP STEPS The following steps should be followed when setting up the CLCx: • Disable CLCx by clearing the LCxEN bit. • Select desired inputs using CLCxSEL0 through CLCxSEL3 registers (See Table 19-1). • Clear any associated ANSEL bits. • Set all TRIS bits associated with inputs. • Clear all TRIS bits associated with outputs. • Enable the chosen inputs through the four gates using CLCxGLS0, CLCxGLS1, CLCxGLS2, and CLCxGLS3 registers. • Select the gate output polarities with the LCxPOLy bits of the CLCxPOL register. • Select the desired logic function with the LCxMODE<2:0> bits of the CLCxCON register. • Select the desired polarity of the logic output with the LCxPOL bit of the CLCxPOL register. (This step may be combined with the previous gate output polarity step). • If driving a device pin, set the desired pin PPS control register and also clear the TRIS bit corresponding to that output. • If interrupts are desired, configure the following bits: - Set the LCxINTP bit in the CLCxCON register for rising event. - Set the LCxINTN bit in the CLCxCON register for falling event. - Set the CLCxIE bit of the associated PIE registers. - Set the GIE and PEIE bits of the INTCON register. • Enable the CLCx by setting the LCxEN bit of the CLCxCON register. 19.2 CLCx Interrupts An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. The CLCxIF bit of the associated PIR registers will be set when either edge detector is triggered and its associated enable bit is set. The LCxINTP enables rising edge interrupts and the LCxINTN bit enables falling edge interrupts. Both are located in the CLCxCON register. To fully enable the interrupt, set the following bits: • LCxON bit of the CLCxCON register • CLCxIE bit of the associated PIE registers • LCxINTP bit of the CLCxCON register (for a rising edge detection) • LCxINTN bit of the CLCxCON register (for a falling edge detection) • PEIE and GIE bits of the INTCON register The CLCxIF bit of the associated PIR registers, must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 19.3 Output Mirror Copies Mirror copies of all LCxCON output bits are contained in the CLCxDATA register. Reading this register reads the outputs of all CLCs simultaneously. This prevents any reading skew introduced by testing or reading the CLCxOUT bits in the individual CLCxCON registers. 19.4 Effects of a Reset The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values remain unchanged. 19.5 Operation During Sleep The CLC module operates independently from the system clock and will continue to run during Sleep, provided that the input sources selected remain active. The HFINTOSC remains active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an input source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and as a CLC input source, when the CLC is enabled, the CPU will go idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current. DS40001729C-page 206 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 19-2: LCx_in[0] INPUT DATA SELECTION AND GATING Data Selection 00000 Data GATE 1 LCx_in[31] lcxd1T LCxD1G1T lcxd1N LCxD1G1N 11111 LCxD2G1T LCxD1S<4:0> LCxD2G1N LCx_in[0] lcxg1 00000 LCxD3G1T lcxd2T LCxG1POL LCxD3G1N lcxd2N LCx_in[31] LCxD4G1T 11111 LCxD2S<4:0> LCx_in[0] LCxD4G1N 00000 Data GATE 2 lcxg2 lcxd3T (Same as Data GATE 1) lcxd3N LCx_in[31] Data GATE 3 11111 lcxg3 LCxD3S<4:0> LCx_in[0] (Same as Data GATE 1) Data GATE 4 00000 lcxg4 lcxd4T (Same as Data GATE 1) lcxd4N LCx_in[31] 11111 LCxD4S<4:0> Note: All controls are undefined at power-up. 2013-2015 Microchip Technology Inc. DS40001729C-page 207 PIC16(L)F1705/9 FIGURE 19-3: PROGRAMMABLE LOGIC FUNCTIONS AND - OR OR - XOR lcxg1 lcxg1 lcxg2 lcxq lcxg3 lcxg4 lcxg2 lcxq lcxg3 lcxg4 LCxMODE<2:0>= 000 LCxMODE<2:0>= 001 4-Input AND S-R Latch lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxg3 S lcxg3 lcxg4 R lcxg4 LCxMODE<2:0>= 010 lcxq Q LCxMODE<2:0>= 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D S lcxg4 Q lcxq D lcxg2 lcxg1 lcxg1 Q lcxq R R lcxg3 lcxg3 LCxMODE<2:0>= 100 LCxMODE<2:0>= 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R lcxg4 lcxg2 J Q lcxg1 lcxg4 K R lcxq lcxg2 D lcxg1 LE lcxg3 S Q lcxq R lcxg3 LCxMODE<2:0>= 110 DS40001729C-page 208 LCxMODE<2:0>= 111 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 19.6 Register Definitions: CLC Control REGISTER 19-1: CLCxCON: CONFIGURABLE LOGIC CELL CONTROL REGISTER R/W-0/0 U-0 R-0/0 R/W-0/0 R/W-0/0 LCxEN — LCxOUT LCxINTP LCxINTN R/W-0/0 R/W-0/0 R/W-0/0 LCxMODE<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxEN: Configurable Logic Cell Enable bit 1 = Configurable logic cell is enabled and mixing input signals 0 = Configurable logic cell is disabled and has logic zero output bit 6 Unimplemented: Read as ‘0’ bit 5 LCxOUT: Configurable Logic Cell Data Output bit Read-only: logic cell output data, after LCxPOL; sampled from lcx_out wire. bit 4 LCxINTP: Configurable Logic Cell Positive Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a rising edge occurs on lcx_out 0 = CLCxIF will not be set bit 3 LCxINTN: Configurable Logic Cell Negative Edge Going Interrupt Enable bit 1 = CLCxIF will be set when a falling edge occurs on lcx_out 0 = CLCxIF will not be set bit 2-0 LCxMODE<2:0>: Configurable Logic Cell Functional Mode bits 111 = Cell is 1-input transparent latch with S and R 110 = Cell is J-K flip-flop with R 101 = Cell is 2-input D flip-flop with R 100 = Cell is 1-input D flip-flop with S and R 011 = Cell is S-R latch 010 = Cell is 4-input AND 001 = Cell is OR-XOR 000 = Cell is AND-OR 2013-2015 Microchip Technology Inc. DS40001729C-page 209 PIC16(L)F1705/9 REGISTER 19-2: CLCxPOL: SIGNAL POLARITY CONTROL REGISTER R/W-0/0 U-0 U-0 U-0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxPOL — — — LCxG4POL LCxG3POL LCxG2POL LCxG1POL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxPOL: LCOUT Polarity Control bit 1 = The output of the logic cell is inverted 0 = The output of the logic cell is not inverted bit 6-4 Unimplemented: Read as ‘0’ bit 3 LCxG4POL: Gate 4 Output Polarity Control bit 1 = The output of gate 4 is inverted when applied to the logic cell 0 = The output of gate 4 is not inverted bit 2 LCxG3POL: Gate 3 Output Polarity Control bit 1 = The output of gate 3 is inverted when applied to the logic cell 0 = The output of gate 3 is not inverted bit 1 LCxG2POL: Gate 2 Output Polarity Control bit 1 = The output of gate 2 is inverted when applied to the logic cell 0 = The output of gate 2 is not inverted bit 0 LCxG1POL: Gate 1 Output Polarity Control bit 1 = The output of gate 1 is inverted when applied to the logic cell 0 = The output of gate 1 is not inverted DS40001729C-page 210 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 19-3: CLCxSEL0: GENERIC CLCx DATA 1 SELECT REGISTER U-0 U-0 U-0 — — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD1S<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 LCxD1S<4:0>: CLCx Data1 Input Selection bits See Table 19-1. REGISTER 19-4: CLCxSEL1: GENERIC CLCx DATA 2 SELECT REGISTER U-0 U-0 U-0 — — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD2S<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 LCxD2S<4:0>: CLCx Data 2 Input Selection bits See Table 19-1. REGISTER 19-5: CLCxSEL2: GENERIC CLCx DATA 3 SELECT REGISTER U-0 U-0 U-0 — — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD3S<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 LCxD3S<4:0>: CLCx Data 3 Input Selection bits See Table 19-1. 2013-2015 Microchip Technology Inc. DS40001729C-page 211 PIC16(L)F1705/9 REGISTER 19-6: CLCxSEL3: GENERIC CLCx DATA 4 SELECT REGISTER U-0 U-0 U-0 — — — R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxD4S<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 LCxD4S<4:0>: CLCx Data 4 Input Selection bits See Table 19-1. REGISTER 19-7: CLCxGLS0: GATE 1 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG1D4T LCxG1D4N LCxG1D3T LCxG1D3N LCxG1D2T LCxG1D2N LCxG1D1T LCxG1D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG1D4T: Gate 1 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg1 0 = lcxd4T is not gated into lcxg1 bit 6 LCxG1D4N: Gate 1 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg1 0 = lcxd4N is not gated into lcxg1 bit 5 LCxG1D3T: Gate 1 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg1 0 = lcxd3T is not gated into lcxg1 bit 4 LCxG1D3N: Gate 1 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg1 0 = lcxd3N is not gated into lcxg1 bit 3 LCxG1D2T: Gate 1 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg1 0 = lcxd2T is not gated into lcxg1 bit 2 LCxG1D2N: Gate 1 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg1 0 = lcxd2N is not gated into lcxg1 bit 1 LCxG1D1T: Gate 1 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg1 0 = lcxd1T is not gated into lcxg1 bit 0 LCxG1D1N: Gate 1 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg1 0 = lcxd1N is not gated into lcxg1 DS40001729C-page 212 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 19-8: CLCxGLS1: GATE 2 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG2D4T LCxG2D4N LCxG2D3T LCxG2D3N LCxG2D2T LCxG2D2N LCxG2D1T LCxG2D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG2D4T: Gate 2 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg2 0 = lcxd4T is not gated into lcxg2 bit 6 LCxG2D4N: Gate 2 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg2 0 = lcxd4N is not gated into lcxg2 bit 5 LCxG2D3T: Gate 2 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg2 0 = lcxd3T is not gated into lcxg2 bit 4 LCxG2D3N: Gate 2 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg2 0 = lcxd3N is not gated into lcxg2 bit 3 LCxG2D2T: Gate 2 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg2 0 = lcxd2T is not gated into lcxg2 bit 2 LCxG2D2N: Gate 2 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg2 0 = lcxd2N is not gated into lcxg2 bit 1 LCxG2D1T: Gate 2 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg2 0 = lcxd1T is not gated into lcxg2 bit 0 LCxG2D1N: Gate 2 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg2 0 = lcxd1N is not gated into lcxg2 2013-2015 Microchip Technology Inc. DS40001729C-page 213 PIC16(L)F1705/9 REGISTER 19-9: CLCxGLS2: GATE 3 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG3D4T LCxG3D4N LCxG3D3T LCxG3D3N LCxG3D2T LCxG3D2N LCxG3D1T LCxG3D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG3D4T: Gate 3 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg3 0 = lcxd4T is not gated into lcxg3 bit 6 LCxG3D4N: Gate 3 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg3 0 = lcxd4N is not gated into lcxg3 bit 5 LCxG3D3T: Gate 3 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg3 0 = lcxd3T is not gated into lcxg3 bit 4 LCxG3D3N: Gate 3 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg3 0 = lcxd3N is not gated into lcxg3 bit 3 LCxG3D2T: Gate 3 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg3 0 = lcxd2T is not gated into lcxg3 bit 2 LCxG3D2N: Gate 3 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg3 0 = lcxd2N is not gated into lcxg3 bit 1 LCxG3D1T: Gate 3 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg3 0 = lcxd1T is not gated into lcxg3 bit 0 LCxG3D1N: Gate 3 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg3 0 = lcxd1N is not gated into lcxg3 DS40001729C-page 214 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 19-10: CLCxGLS3: GATE 4 LOGIC SELECT REGISTER R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LCxG4D4T LCxG4D4N LCxG4D3T LCxG4D3N LCxG4D2T LCxG4D2N LCxG4D1T LCxG4D1N bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 LCxG4D4T: Gate 4 Data 4 True (non-inverted) bit 1 = lcxd4T is gated into lcxg4 0 = lcxd4T is not gated into lcxg4 bit 6 LCxG4D4N: Gate 4 Data 4 Negated (inverted) bit 1 = lcxd4N is gated into lcxg4 0 = lcxd4N is not gated into lcxg4 bit 5 LCxG4D3T: Gate 4 Data 3 True (non-inverted) bit 1 = lcxd3T is gated into lcxg4 0 = lcxd3T is not gated into lcxg4 bit 4 LCxG4D3N: Gate 4 Data 3 Negated (inverted) bit 1 = lcxd3N is gated into lcxg4 0 = lcxd3N is not gated into lcxg4 bit 3 LCxG4D2T: Gate 4 Data 2 True (non-inverted) bit 1 = lcxd2T is gated into lcxg4 0 = lcxd2T is not gated into lcxg4 bit 2 LCxG4D2N: Gate 4 Data 2 Negated (inverted) bit 1 = lcxd2N is gated into lcxg4 0 = lcxd2N is not gated into lcxg4 bit 1 LCxG4D1T: Gate 4 Data 1 True (non-inverted) bit 1 = lcxd1T is gated into lcxg4 0 = lcxd1T is not gated into lcxg4 bit 0 LCxG4D1N: Gate 4 Data 1 Negated (inverted) bit 1 = lcxd1N is gated into lcxg4 0 = lcxd1N is not gated into lcxg4 2013-2015 Microchip Technology Inc. DS40001729C-page 215 PIC16(L)F1705/9 REGISTER 19-11: CLCDATA: CLC DATA OUTPUT U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — MLC3OUT MLC2OUT MLC1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 MLC3OUT: Mirror copy of LC3OUT bit bit 1 MLC2OUT: Mirror copy of LC2OUT bit bit 0 MLC1OUT: Mirror copy of LC1OUT bit DS40001729C-page 216 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 19-3: Name ANSELA ANSELB(1) ANSELC SUMMARY OF REGISTERS ASSOCIATED WITH CLCx Bit7 Bit6 — — Bit4 BIt3 Bit2 Bit1 Bit0 Register on Page — ANSA4 — ANSA2 ANSA1 ANSA0 122 ANSB4 — — — — 128 ANSC2 ANSC1 ANSC0 133 Bit5 — — ANSB5 ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 CLC1CON LC1EN — LC1OUT LC1INTP LC1INTN LC1MODE<2:0> 209 CLC2CON LC2EN — LC2OUT LC2INTP LC2INTN LC2MODE<2:0> 209 CLC3CON LC3EN — LC3OUT LC3INTP LC3INTN CLCDATA — — — — — MLC3OUT MLC2OUT MLC1OUT 216 CLC1GLS0 LC1G1D4T LC1G1D4N LC1G1D3T LC1G1D3N LC1G1D2T LC1G1D2N LC1G1D1T LC1G1D1N 212 CLC1GLS1 LC1G2D4T LC1G2D4N LC1G2D3T LC1G2D3N LC1G2D2T LC1G2D2N LC1G2D1T LC1G2D1N 213 CLC1GLS2 LC1G3D4T LC1G3D4N LC1G3D3T LC1G3D3N LC1G3D2T LC1G3D2N LC1G3D1T LC1G3D1N 214 CLC1GLS3 LC1G4D4T LC1G4D4N LC1G4D3T LC1G4D3N LC1G4D2T LC1G4D2N LC1G4D1T LC1G4D1N 215 CLC1POL LC1POL — — — LC1G4POL LC1G3POL LC1G2POL LC1G1POL 210 LC3MODE<2:0> 209 CLC1SEL0 — — — LC1D1S<4:0> 211 CLC1SEL1 — — — LC1D2S<4:0> 211 CLC1SEL2 — — — LC1D3S<4:0> 211 CLC1SEL3 — — — LC1D4S<4:0> 212 CLC2GLS0 LC2G1D4T LC2G1D4N LC2G1D3T LC2G1D3N LC2G1D2T LC2G1D2N LC2G1D1T LC2G1D1N 212 CLC2GLS1 LC2G2D4T LC2G2D4N LC2G2D3T LC2G2D3N LC2G2D2T LC2G2D2N LC2G2D1T LC2G2D1N 213 CLC2GLS2 LC2G3D4T LC2G3D4N LC2G3D3T LC2G3D3N LC2G3D2T LC2G3D2N LC2G3D1T LC2G3D1N 214 CLC2GLS3 LC2G4D4T LC2G4D4N LC2G4D3T LC2G4D3N LC2G4D2T LC2G4D2N LC2G4D1T LC2G4D1N 215 CLC2POL LC2POL — — — LC2G4POL LC2G3POL LC2G2POL LC2G1POL 210 CLC2SEL0 — — — LC2D1S<4:0> 211 CLC2SEL1 — — — LC2D2S<4:0> 211 CLC2SEL2 — — — LC2D3S<4:0> 211 CLC2SEL3 — — — LC2D4S<4:0> 212 CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G1D1T LC3G1D1N 212 CLC3GLS1 LC3G2D4T LC3G2D4N LC3G2D3T LC3G2D3N LC3G2D2T LC3G2D2N LC3G2D1T LC3G2D1N 213 CLC3GLS2 LC3G3D4T LC3G3D4N LC3G3D3T LC3G3D3N LC3G3D2T LC3G3D2N LC3G3D1T LC3G3D1N 214 CLC3GLS3 LC3G4D4T LC3G4D4N LC3G4D3T LC3G4D3N LC3G4D2T LC3G4D2N LC3G4D1T LC3G4D1N 215 CLC3POL LC3POL — — — LC3G4POL LC3G3POL LC3G2POL LC3G1POL 210 CLC3SEL0 — — — LC3D1S<4:0> 211 CLC3SEL1 — — — LC3D2S<4:0> 211 CLC3SEL2 — — — LC3D3S<4:0> 211 CLC3SEL3 — — — LC3D4S<4:0> 212 CLCxPPS — — — CLCxPPS<4:0> 139, 140 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE3 INTCON — — COGIE ZCDIE — CLC3IE CLC2IE CLC1IE 87 PIR3 — — COGIF ZCDIF — CLC3IF CLC2IF CLC1IF RxyPPS — — — TRISA — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121 TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 TRISB(1) TRISC Legend: Note 1: 2: 3: RxyPPS<4:0> 90 141 — = unimplemented read as ‘0’. Shaded cells are not used for CLC module. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001729C-page 217 PIC16(L)F1705/9 20.0 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 20-1 shows the block diagram of the ADC. The ADC voltage reference is software selectable to be either internally generated or externally supplied. FIGURE 20-1: ADC BLOCK DIAGRAM VDD ADPREF = 00 VREF+ ADPREF = 11 FVR_Buffer1 ADPREF = 10 VREF- = VSS AN0 00000 VREF+/AN1 00001 AN2 00010 AN3 00011 AN4 00100 AN5 00101 AN6 00110 AN7 00111 ADCREF+ ADCREF- AN8 01000 ADC AN9 01001 AN10 01010 AN11 01011 ADNREF = 0 ADNREF = 1 10 GO/DONE ADFM 0 = Left Justify 1 = Right Justify 16 ADON Reserved 11100 Temp Indicator 11101 DAC_output 11110 FVR_Buffer1 11111 VSS ADRESH ADRESL CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. DS40001729C-page 218 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 20.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Result formatting 20.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 11.0 “I/O Ports” for more information. Note: 20.1.2 Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. CHANNEL SELECTION There are up to 17 channel selections available: • • • • • 20.1.4 CONVERSION CLOCK The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options: • • • • • • • FOSC/2 FOSC/4 FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (internal RC oscillator) The time to complete one bit conversion is defined as TAD. One full 10-bit conversion requires 11.5 TAD periods as shown in Figure 20-2. For correct conversion, the appropriate TAD specification must be met. Refer to Table : for more information. Table 20-1 gives examples of appropriate ADC clock selections. Note: Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. AN<13:8, 4:0> pins (PIC16(L)F1705 only) AN<21,13:0> pins (PIC16(L)F1709 only) Temperature Indicator DAC_output FVR_buffer1 The CHS bits of the ADCON0 register (Register 20-1) determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 20.2 “ADC Operation” for more information. 20.1.3 ADC VOLTAGE REFERENCE The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be: • • • • VREF+ pin VDD FVR 2.048V FVR 4.096V (Not available on LF devices) The ADNREF bit of the ADCON1 register provides control of the negative voltage reference. The negative voltage reference can be: • VREF- pin • VSS See Section 20.0 “Analog-to-Digital Converter (ADC) Module” for more details on the Fixed Voltage Reference. 2013-2015 Microchip Technology Inc. DS40001729C-page 219 PIC16(L)F1705/9 TABLE 20-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) Device Frequency (FOSC) ADC Clock Source ADCS<2:0> 32 MHz 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz FOSC/2 000 62.5ns(2) 100 ns(2) 125 ns(2) 250 ns(2) 500 ns(2) 2.0 s FOSC/4 100 125 ns (2) (2) (2) (2) FOSC/8 001 0.5 s(2) 400 ns(2) 0.5 s(2) FOSC/16 101 800 ns 800 ns 010 1.0 s FOSC/64 110 FRC x11 FOSC/32 Legend: Note 1: 2: 3: 4: 1.0 s 4.0 s 1.0 s 2.0 s 8.0 s(3) 1.0 s 2.0 s 4.0 s 16.0 s(3) 1.6 s 2.0 s 4.0 s 2.0 s 3.2 s 4.0 s 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 200 ns 250 ns 500 ns 8.0 s 32.0 s(2) (3) 8.0 s 16.0 s (3) 64.0 s(2) (2) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) 1.0-6.0 s(1,4) Shaded cells are outside of recommended range. See TAD parameter for FRC source typical TAD value. These values violate the required TAD time. Outside the recommended TAD time. The ADC clock period (TAD) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock FOSC. However, the FRC oscillator source must be used when conversions are to be performed with the device in Sleep mode. FIGURE 20-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 THCD Conversion Starts TACQ Holding capacitor disconnected from analog input (THCD). Set GO bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is reconnected to analog input. Enable ADC (ADON bit) and Select channel (ACS bits) DS40001729C-page 220 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 20.1.5 INTERRUPTS 20.1.6 The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. RESULT FORMATTING The 10-bit ADC conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format. Figure 20-3 shows the two output formats. Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. 2: The ADC operates during Sleep only when the FRC oscillator is selected. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the ADIE bit of the PIE1 register and the PEIE bit of the INTCON register must both be set and the GIE bit of the INTCON register must be cleared. If all three of these bits are set, the execution will switch to the Interrupt Service Routine. FIGURE 20-3: 10-BIT ADC CONVERSION RESULT FORMAT ADRESH (ADFM = 0) ADRESL MSB LSB bit 7 bit 0 bit 7 10-bit ADC Result (ADFM = 1) bit 0 Unimplemented: Read as ‘0’ MSB bit 7 Unimplemented: Read as ‘0’ 2013-2015 Microchip Technology Inc. LSB bit 0 bit 7 bit 0 10-bit ADC Result DS40001729C-page 221 PIC16(L)F1705/9 20.2 20.2.1 ADC Operation STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: 20.2.2 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 20.2.6 “ADC Conversion Procedure”. COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF Interrupt Flag bit • Update the ADRESH and ADRESL registers with new conversion result 20.2.3 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted. Note: A device Reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 20.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the FRC option. When the FRC oscillator source is selected, the ADC waits one additional instruction before starting the conversion. This allows the SLEEP instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set. When the ADC clock source is something other than FRC, a SLEEP instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set. 20.2.5 AUTO-CONVERSION TRIGGER The Auto-conversion Trigger allows periodic ADC measurements without software intervention. When a rising edge of the selected source occurs, the GO/DONE bit is set by hardware. The Auto-conversion Trigger source is selected with the TRIGSEL<3:0> bits of the ADCON2 register. Using the Auto-conversion Trigger does not assure proper ADC timing. It is the user’s responsibility to ensure that the ADC timing requirements are met. See Table 20-2 for auto-conversion sources. TABLE 20-2: AUTO-CONVERSION SOURCES Source Peripheral Signal Name CCP1 CCP2 DS40001729C-page 222 Timer0 T0_overflow Timer1 T1_overflow Timer2 T2_match Timer4 T4_match Timer6 T6_match Comparator C1 C1OUT_sync Comparator C2 C2OUT_sync CLC1 LC1_out CLC2 LC2_out CLC3 LC3_out 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 20.2.6 ADC CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: • Disable pin output driver (Refer to the TRIS register) • Configure pin as analog (Refer to the ANSEL register) Configure the ADC module: • Select ADC conversion clock • Configure voltage reference • Select ADC input channel • Turn on ADC module Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt(1) Wait the required acquisition time(2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). EXAMPLE 20-1: ADC CONVERSION ;This code block configures the ADC ;for polling, Vdd and Vss references, FRC ;oscillator and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSEL ADCON1 ; MOVLW B’11110000’ ;Right justify, FRC ;oscillator MOVWF ADCON1 ;Vdd and Vss Vref BANKSEL TRISA ; BSF TRISA,0 ;Set RA0 to input BANKSEL ANSEL ; BSF ANSEL,0 ;Set RA0 to analog BANKSEL ADCON0 ; MOVLW B’00000001’ ;Select channel AN0 MOVWF ADCON0 ;Turn ADC On CALL SampleTime ;Acquisiton delay BSF ADCON0,ADGO ;Start conversion BTFSC ADCON0,ADGO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRESH ; MOVF ADRESH,W ;Read upper 2 bits MOVWF RESULTHI ;store in GPR space BANKSEL ADRESL ; MOVF ADRESL,W ;Read lower 8 bits MOVWF RESULTLO ;Store in GPR space Note 1: The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution. 2: Refer to Section 20.4 “ADC Acquisition Requirements”. 2013-2015 Microchip Technology Inc. DS40001729C-page 223 PIC16(L)F1705/9 20.3 Register Definitions: ADC Control REGISTER 20-1: U-0 ADCON0: ADC CONTROL REGISTER 0 R/W-0/0 R/W-0/0 — R/W-0/0 R/W-0/0 CHS<4:0> R/W-0/0 R/W-0/0 R/W-0/0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS<4:0>: Analog Channel Select bits 11111 = FVR_buffer1 Output(2) 11110 = DAC_output(1) 11101 = Temperature Indicator(3) 11100 = Reserved 11011 = Reserved. No channel connected. • • • 01100 = Reserved. No channel connected. 01011 = AN11 01010 = AN10 01001 = AN9 01000 = AN8 00111 = AN7 00110 = AN6 00101 = AN5 00100 = AN4 00011 = AN3 00010 = AN2 00001 = AN1 00000 = AN0 bit 1 GO/DONE: ADC Conversion Status bit 1 = ADC conversion cycle in progress. Setting this bit starts an ADC conversion cycle. This bit is automatically cleared by hardware when the ADC conversion has completed. 0 = ADC conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Note 1: 2: 3: See Section 22.0 “8-Bit Digital-to-Analog Converter (DAC1) Module” for more information. See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. See Section 15.0 “Temperature Indicator Module” for more information. DS40001729C-page 224 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 20-2: R/W-0/0 ADCON1: ADC CONTROL REGISTER 1 R/W-0/0 ADFM R/W-0/0 R/W-0/0 ADCS<2:0> U-0 R/W-0/0 — ADNREF R/W-0/0 bit 7 R/W-0/0 ADPREF<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ADFM: ADC Result Format Select bit 1 = Right justified. Six Most Significant bits of ADRESH are set to ‘0’ when the conversion result is loaded. 0 = Left justified. Six Least Significant bits of ADRESL are set to ‘0’ when the conversion result is loaded. bit 6-4 ADCS<2:0>: ADC Conversion Clock Select bits 111 = FRC (clock supplied from an internal RC oscillator) 110 = FOSC/64 101 = FOSC/16 100 = FOSC/4 011 = FRC (clock supplied from an internal RC oscillator) 010 = FOSC/32 001 = FOSC/8 000 = FOSC/2 bit 3 Unimplemented: Read as ‘0’ bit 2 ADNREF: A/D Negative Voltage Reference Configuration 1 = VREF- is connected to external VREF 0 = VREF- is connected to VSS bit 1-0 ADPREF<1:0>: ADC Positive Voltage Reference Configuration bits 11 = VREF+ is connected to internal FVR_buffer1(1) 10 = VREF+ is connected to external VREF+ pin(1) 01 = Reserved 00 = VREF+ is connected to VDD Note 1: When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See Table : for details. 2013-2015 Microchip Technology Inc. DS40001729C-page 225 PIC16(L)F1705/9 REGISTER 20-3: R/W-0/0 ADCON2: ADC CONTROL REGISTER 2 R/W-0/0 R/W-0/0 TRIGSEL<3:0> R/W-0/0 (1) U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 bit 3-0 Note 1: 2: TRIGSEL<3:0>: Auto-Conversion Trigger Selection bits(1) 0000 = No auto-conversion trigger selected 0001 = CCP1 0010 = CCP2 0011 = Timer0 – T0_overflow(2) 0100 = Timer1 – T1_overflow(2) 0101 = Timer2 – T2_match 0110 = Comparator C1 – C1OUT_sync 0111 = Comparator C2 – C2OUT_sync 1000 = CLC1 – LC1_out 1001 = CLC2 – LC2_out 1010 = CLC3 – LC3_out 1011 = Reserved 1100 = Timer4 – T4_match 1101 = Timer6 – T6_match 1110 = Reserved 1111 = Reserved Unimplemented: Read as ‘0’ This is a rising edge sensitive input for all sources. Signal also sets its corresponding interrupt flag. DS40001729C-page 226 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 20-4: R/W-x/u ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<9:2>: ADC Result Register bits Upper eight bits of 10-bit conversion result REGISTER 20-5: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — ADRES<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower two bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2013-2015 Microchip Technology Inc. DS40001729C-page 227 PIC16(L)F1705/9 REGISTER 20-6: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u — — — — — — R/W-x/u R/W-x/u ADRES<9:8> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Reserved: Do not use. bit 1-0 ADRES<9:8>: ADC Result Register bits Upper two bits of 10-bit conversion result REGISTER 20-7: R/W-x/u ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 1 R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES<7:0>: ADC Result Register bits Lower eight bits of 10-bit conversion result DS40001729C-page 228 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 20.4 ADC Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 20-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 20-4. The maximum recommended impedance for analog sources is 10 k. As the EQUATION 20-1: Assumptions: source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an ADC acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 20-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Temperature = 50°C and external impedance of 10k 5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2µs + T C + Temperature - 25°C 0.05µs/°C The value for TC can be approximated with the following equations: 1 = V CHOLD V AP P LI ED 1 – -------------------------n+1 2 –1 ;[1] VCHOLD charged to within 1/2 lsb –TC ---------- RC V AP P LI ED 1 – e = V CHOLD ;[2] VCHOLD charge response to VAPPLIED – Tc --------- 1 RC ;combining [1] and [2] V AP P LI ED 1 – e = V A PP LIE D 1 – -------------------------n+1 2 –1 Note: Where n = number of bits of the ADC. Solving for TC: T C = – C HOLD R IC + R SS + R S ln(1/2047) = – 10pF 1k + 7k + 10k ln(0.0004885) = 1.37 µs Therefore: T A CQ = 2µs + 892ns + 50°C- 25°C 0.05 µs/°C = 4.62µs Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out. 2: The charge holding capacitor (CHOLD) is not discharged after each conversion. 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2013-2015 Microchip Technology Inc. DS40001729C-page 229 PIC16(L)F1705/9 FIGURE 20-4: ANALOG INPUT MODEL VDD Analog Input pin Rs VT 0.6V CPIN 5 pF VA RIC 1k Sampling Switch SS Rss I LEAKAGE(1) VT 0.6V CHOLD = 10 pF Ref- 6V 5V VDD 4V 3V 2V = Sample/Hold Capacitance = Input Capacitance Legend: CHOLD CPIN RSS I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC = Resistance of Sampling Switch RSS SS = Sampling Switch VT = Threshold Voltage Note 1: 5 6 7 8 9 10 11 Sampling Switch (k) Refer to Table 32-4: I/O Ports (parameter D060). FIGURE 20-5: ADC TRANSFER FUNCTION Full-Scale Range 3FFh 3FEh ADC Output Code 3FDh 3FCh 3FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB Ref- DS40001729C-page 230 Zero-Scale Transition 1.5 LSB Full-Scale Transition Ref+ 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 20-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 ADCON0 — ADCON1 ADFM ADCON2 Bit 6 Bit 5 Bit 4 Bit 2 — — ADPREF<1:0> 225 — — — 226 CHS<4:0> ADCS<2:0> TRIGSEL<3:0> ADRESH ADC Result Register High ADRESL ADC Result Register Low Bit 1 Bit 0 GO/DONE ADON Register on Page Bit 3 — 224 227, 228 227, 228 ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122 ANSELB(1) — — ANSB5 ANSB4 — — — — 128 ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121 TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 FVREN FVRRDY TSEN TSRNG CDAFVR<1:0> DAC1EN — DAC1OE1 DAC1OE2 DAC1PSS<1:0> TRISA TRISB(1) TRISC FVRCON DAC1CON0 Legend: Note 1: 2: 3: ADFVR<1:0> — DAC1NSS 153 238 x = unknown, u = unchanged, — = unimplemented read as ‘0’, q = value depends on condition. Shaded cells are not used for the ADC module. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001729C-page 231 PIC16(L)F1705/9 21.0 OPERATIONAL AMPLIFIER (OPA) MODULES The Operational Amplifier (OPA) is a standard three-terminal device requiring external feedback to operate. The OPA module has the following features: • External connections to I/O ports • Low leakage inputs • Factory Calibrated Input Offset Voltage FIGURE 21-1: OPAx MODULE BLOCK DIAGRAM OPAxIN+ 0x DAC_output 10 FVR Buffer 2 11 OPAXEN OPAXSP(1) OPAxIN- 0 OPAXOUT OPA 1 OPAxNCH<1:0> OPAXUG Note 1: The OPAxSP bit must be set. Low-Power mode is not supported. DS40001729C-page 232 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 21.1 OPA Module Performance Common AC and DC performance specifications for the OPA module: • • • • • Common Mode Voltage Range Leakage Current Input Offset Voltage Open Loop Gain Gain Bandwidth Product Common mode voltage range is the specified voltage range for the OPA+ and OPA- inputs, for which the OPA module will perform to within its specifications. The OPA module is designed to operate with input voltages between VSS and VDD. Behavior for Common mode voltages greater than VDD, or below VSS, are not guaranteed. Leakage current is a measure of the small source or sink currents on the OPA+ and OPA- inputs. To minimize the effect of leakage currents, the effective impedances connected to the OPA+ and OPA- inputs should be kept as small as possible and equal. Input offset voltage is a measure of the voltage difference between the OPA+ and OPA- inputs in a closed loop circuit with the OPA in its linear region. The offset voltage will appear as a DC offset in the output equal to the input offset voltage, multiplied by the gain of the circuit. The input offset voltage is also affected by the Common mode voltage. The OPA is factory calibrated to minimize the input offset voltage of the module. 21.1.1 OPA MODULE CONTROL The OPA module is enabled by setting the OPAxEN bit of the OPAxCON register. When enabled, the OPA forces the output driver of OPAxOUT pin into tri-state to prevent contention between the driver and the OPA output. Note: 21.1.2 When the OPA module is enabled, the OPAxOUT pin is driven by the op amp output, not by the PORT digital driver. Refer to Table : for the op amp output drive capability. UNITY GAIN MODE The OPAxUG bit of the OPAxCON register selects the Unity Gain mode. When unity gain is selected, the OPA output is connected to the inverting input and the OPAxIN pin is relinquished, releasing the pin for general purpose input and output. 21.2 Effects of Reset A device Reset forces all registers to their Reset state. This disables the OPA module. Open loop gain is the ratio of the output voltage to the differential input voltage, (OPA+) - (OPA-). The gain is greatest at DC and falls off with frequency. Gain Bandwidth Product or GBWP is the frequency at which the open loop gain falls off to 0 dB. 2013-2015 Microchip Technology Inc. DS40001729C-page 233 PIC16(L)F1705/9 21.3 Register Definitions: Op Amp Control REGISTER 21-1: OPAxCON: OPERATIONAL AMPLIFIERS (OPAx) CONTROL REGISTERS R/W-0/0 R/W-0/0 U-0 R/W-0/0 U-0 U-0 OPAxEN OPAxSP — OPAxUG — — R/W-0/0 R/W-0/0 OPAxCH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition bit 7 OPAxEN: Op Amp Enable bit 1 = Op amp is enabled 0 = Op amp is disabled and consumes no active power bit 6 OPAxSP: Op Amp Speed/Power Select bit 1 = Op amp operates in high GBWP mode 0 = Reserved. Do not use. bit 5 Unimplemented: Read as ‘0’ bit 4 OPAxUG: Op Amp Unity Gain Select bit 1 = OPA output is connected to inverting input. OPAxIN- pin is available for general purpose I/O. 0 = Inverting input is connected to the OPAxIN- pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 OPAxCH<1:0>: Non-inverting Channel Selection bits 11 = Non-inverting input connects to FVR_buffer2 output 10 = Non-inverting input connects to DAC_output 0x = Non-inverting input connects to OPAxIN+ pin TABLE 21-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH OP AMPS Bit 7 ANSELB(1) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSB5 ANSB4 — — — — 128 ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 128 DAC1CON0 DAC1EN — — DAC1NSS 238 DAC1OE1 DAC1OE2 DAC1CON1 FVRCON DAC1PSS<1:0> DAC1R<7:0> 238 FVREN FVRRDY TSEN TSRNG ADFVR<1:0> 153 OPA1CON OPA1EN OPA1SP — OPA1UG — — OPA1PCH<1:0> 234 OPA2CON OPA2EN OPA2SP — OPA2UG — — OPA2PCH<1:0> 234 TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 TRISB(1) TRISC Legend: Note 1: 2: 3: (1) TRISC7 (1) TRISC6 CDAFVR<1:0> — = unimplemented location, read as ‘0’. Shaded cells are not used by op amps. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. DS40001729C-page 234 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 22.0 8-BIT DIGITAL-TO-ANALOG CONVERTER (DAC1) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 256 selectable output levels. 22.1 Output Voltage Selection The DAC has 256 voltage level ranges. The 256 levels are set with the DAC1R<7:0> bits of the DAC1CON1 register. The DAC output voltage is determined by Equation 22-1: The input of the DAC can be connected to: • External VREF pins • VDD supply voltage • FVR (Fixed Voltage Reference) The output of the DAC can be configured to supply a reference voltage to the following: • • • • Comparator positive input ADC input channel DAC1OUT1 pin DAC1OUT2 pin The Digital-to-Analog Converter (DAC) is enabled by setting the DAC1EN bit of the DAC1CON0 register. EQUATION 22-1: DAC OUTPUT VOLTAGE IF DAC1EN = 1 DAC1R 7:0 VOUT = VSOURCE+ – VSOURCE- -------------------------------- + VSOURCE8 2 VSOURCE+ = VDD, VREF, or FVR BUFFER 2 VSOURCE- = VSS 22.2 Ratiometric Output Level The DAC output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. If the voltage of either input source fluctuates, a similar fluctuation will result in the DAC output value. The value of the individual resistors within the ladder can be found in Table : . 22.3 DAC Voltage Reference Output The DAC voltage can be output to the DAC1OUT1 and DAC1OUT2 pins by setting the respective DAC1OE1 and DAC1OE2 bits of the DAC1CON0 register. Selecting the DAC voltage for output on either DAC1OUTX pin automatically overrides the digital output buffer and digital input threshold detector functions of that pin. Reading the DAC1OUTX pin when it has been configured for DAC reference voltage output will always return a ‘0’. Due to the limited current drive capability, a buffer must be used on the DAC voltage output for external connections to either DAC1OUTx pin. Figure 22-2 shows an example buffering technique. 2013-2015 Microchip Technology Inc. DS40001729C-page 235 PIC16(L)F1705/9 FIGURE 22-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) FVR Buffer2 VSOURCE+ VDD 8 VREF+ DAC1R<7:0> R R DAC1PSS<1:0> 2 R DAC1EN R 256 Steps R 256-to-1 MUX R DAC1_Output R (To Comparator and ADC Modules) DAC1OUT1 R DAC1OE1 DAC1NSS DAC1OUT2 VREF- DAC1OE2 VSOURCE- VSS FIGURE 22-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS40001729C-page 236 DAC1OUTX + – Buffered DAC Output 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 22.4 Operation During Sleep The DAC continues to function during Sleep. When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the DAC1CON0 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 22.5 Effects of a Reset A device Reset affects the following: • DAC is disabled. • DAC output voltage is removed from the DAC1OUT pin. • The DAC1R<4:0> range select bits are cleared. 2013-2015 Microchip Technology Inc. DS40001729C-page 237 PIC16(L)F1705/9 22.6 Register Definitions: DAC Control REGISTER 22-1: DAC1CON0: VOLTAGE REFERENCE CONTROL REGISTER 0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 DAC1EN — DAC1OE1 DAC1OE2 R/W-0/0 R/W-0/0 U-0 R/W-0/0 — DAC1NSS DAC1PSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DAC1EN: DAC1 Enable bit 1 = DAC is enabled 0 = DAC is disabled bit 6 Unimplemented: Read as ‘0’ bit 5 DAC1OE1: DAC1 Voltage Output 1 Enable bit 1 = DAC voltage level is also an output on the DAC1OUT1 pin 0 = DAC voltage level is disconnected from the DAC1OUT1 pin bit 4 DAC1OE2: DAC1 Voltage Output 2 Enable bit 1 = DAC voltage level is also an output on the DAC1OUT2 pin 0 = DAC voltage level is disconnected from the DAC1OUT2 pin bit 3-2 DAC1PSS<1:0>: DAC1 Positive Source Select bits 11 = Reserved, do not use 10 = FVR Buffer2 output 01 = VREF+ pin 00 = VDD bit 1 Unimplemented: Read as ‘0’ bit 0 DAC1NSS: DAC1 Negative Source Select bits 1 = VREF- pin 0 = VSS REGISTER 22-2: R/W-0/0 DAC1CON1: VOLTAGE REFERENCE CONTROL REGISTER 1 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 DAC1R<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 DAC1R<7:0>: DAC1 Voltage Output Select bits TABLE 22-1: Name DAC1CON0 SUMMARY OF REGISTERS ASSOCIATED WITH THE DAC1 MODULE Bit 7 Bit 6 DAC1EN — DAC1CON1 Legend: Bit 5 Bit 4 DAC1OE1 DAC1OE2 Bit 3 Bit 2 DAC1PSS<1:0> Bit 1 Bit 0 Register on page — DAC1NSS 238 DAC1R<7:0> 238 — = Unimplemented location, read as ‘0’. Shaded cells are not used with the DAC module. DS40001729C-page 238 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 23.0 ZERO-CROSS DETECTION (ZCD) MODULE 23.1 The ZCD module detects when an A/C signal crosses through the ground potential. The actual zero-crossing threshold is the zero-crossing reference voltage, ZCPINV, which is typically 0.75V above ground. The connection to the signal to be detected is through a series current limiting resistor. The module applies a current source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby preventing the pin voltage from forward biasing the ESD protection diodes. When the applied voltage is greater than the reference voltage, the module sinks current. When the applied voltage is less than the reference voltage, the module sources current. The current source and sink action keeps the pin voltage constant over the full range of the applied voltage. The ZCD module is shown in the simplified block diagram Figure 23-2. The ZCD module requires a current limiting resistor in series with the external voltage source. The impedance and rating of this resistor depends on the external source peak voltage. Select a resistor value that will drop all of the peak voltage when the current through the resistor is nominally 300 µA (refer to Equation 23-1 and Figure 23-1). Make sure that the ZCD I/O pin internal weak pull-up is disabled so it does not interfere with the current source and sink. EQUATION 23-1: FIGURE 23-1: EXTERNAL VOLTAGE VMAXPEAK VMINPEAK VPEAK A/C period measurement Accurate long term time measurement Dimmer phase delayed drive Low EMI cycle switching FIGURE 23-2: EXTERNAL RESISTOR V PEAK R SERIES = ---------------–4 3 10 The ZCD module is useful when monitoring an A/C waveform for, but not limited to, the following purposes: • • • • External Resistor Selection ZCPINV SIMPLIFIED ZCD BLOCK DIAGRAM VPULLUP optional VDD RPULLUP External current limiting resistor ZCPINV + RSERIES ZCD pin RPULLDOWN optional External voltage source ZCDx_output D ZCDxPOL Q1 Q ZCDxOUT LE Interrupt det ZCDxINTP Sets ZCDIF flag ZCDxINTN Interrupt det 2013-2015 Microchip Technology Inc. DS40001729C-page 239 PIC16(L)F1705/9 23.2 ZCD Logic Output The ZCD module includes a Status bit, which can be read to determine whether the current source or sink is active. The ZCDxOUT bit of the ZCDxCON register is set when the current sink is active, and cleared when the current source is active. The ZCDxOUT bit is affected by the polarity bit. 23.3 ZCD Logic Polarity The ZCDxPOL bit of the ZCDxCON register inverts the ZCDxOUT bit relative to the current source and sink output. When the ZCDxPOL bit is set, a ZCDxOUT high indicates that the current source is active, and a low output indicates that the current sink is active. The ZCDxPOL bit affects the ZCD interrupts. See Section 23.4 “ZCD Interrupts”. 23.5 Correcting for ZCPINV offset The actual voltage at which the ZCD switches is the reference voltage at the non-inverting input of the ZCD op amp. For external voltage source waveforms, other than square waves, this voltage offset from zero causes the zero-cross event to occur either too early or too late. When the waveform is varying relative to VSS, then the zero cross is detected too early as the waveform falls and too late as the waveform rises. When the waveform is varying relative to VDD, then the zero cross is detected too late as the waveform rises and too early as the waveform falls. The actual offset time can be determined for sinusoidal waveforms with the corresponding equations shown in Equation 23-2. EQUATION 23-2: ZCD EVENT OFFSET When External Voltage Source is relative to Vss: 23.4 ZCD Interrupts An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in the ZCD for this purpose. The ZCDIF bit of the PIR3 register will be set when either edge detector is triggered and its associated enable bit is set. The ZCDxINTP enables rising edge interrupts and the ZCDxINTN bit enables falling edge interrupts. Both are located in the ZCDxCON register. To fully enable the interrupt, the following bits must be set: • ZCDIE bit of the PIE3 register • ZCDxINTP bit of the ZCDxCON register (for a rising edge detection) • ZCDxINTN bit of the ZCDxCON register (for a falling edge detection) • PEIE and GIE bits of the INTCON register Changing the ZCDxPOL bit will cause an interrupt, regardless of the level of the ZCDxEN bit. The ZCDIF bit of the PIR3 register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. T OFFSET Z CPINV asin ------------------ V PEAK = ----------------------------------2 Freq When External Voltage Source is relative to VDD: T OFFSET V DD – Z CPINV asin --------------------------------- V PEAK = ------------------------------------------------2 Freq This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin. A pull-up resistor is used when the external voltage source is varying relative to VSS. A pull-down resistor is used when the voltage is varying relative to VDD. The resistor adds a bias to the ZCD pin so that the target external voltage source must go to zero to pull the pin voltage to the ZCPINV switching voltage. The pull-up or pull-down value can be determined with the equations shown in Equation 23-3 or Equation 23-4. EQUATION 23-3: ZCD PULL-UP/DOWN When External Signal is relative to Vss: R SERIE S V PULLUP – Z CPINV R PULLUP = ------------------------------------------------------------------------- Z CPINV When External Signal is relative to VDD: R SERIES Z CPINV R PULLDOWN = -------------------------------------------- V DD – Z CPINV DS40001729C-page 240 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 The pull-up and pull-down resistor values are significantly affected by small variations of ZCPINV. Measuring ZCPINV can be difficult, especially when the waveform is relative to VDD. However, by combining Equations 23-2 and 23-3, the resistor value can be determined from the time difference between the ZCDx_output high and low periods. Note that the time difference, ∆T, is 4*TOFFSET. The equation for determining the pull-up and pull-down resistor values from the high and low ZCDx_output periods is shown in Equation 23-4. The ZCDx_output signal can be directly observed on a pin by routing the ZCDx_output signal through one of the CLCs. EQUATION 23-4: V BI A S R = R SERIES ---------------------------------------------------------------- – 1 T V PE AK sin Freq ---------- 2 R is pull-up or pull-down resistor. VBIAS is VPULLUP when R is pull-up or VDD when R is pull-down. ∆T is the ZCDOUT high and low period difference. 23.6 Handling VPEAK Variations If the peak amplitude of the external voltage is expected to vary, the series resistor must be selected to keep the ZCD current source and sink below the design maximum range of ± 600 A and above a reasonable minimum range. A general rule of thumb is that the maximum peak voltage can be no more than six times the minimum peak voltage. To ensure that the maximum current does not exceed ± 600 A and the minimum is at least ± 100 A, compute the series resistance as shown in Equation 23-5. The compensating pull-up for this series resistance can be determined with Equation 23-3 because the pull-up value is independent from the peak voltage. EQUATION 23-5: SERIES R FOR V RANGE V MAXPEAK + V MINPEAK R SERIES = --------------------------------------------------------–4 7 10 23.7 Operation During Sleep The ZCD current sources and interrupts are unaffected by Sleep. 23.8 Effects of a Reset The ZCD circuit can be configured to default to the active or inactive state on Power-On-Reset (POR). When the ZCDDIS Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCDDIS Configuration bit is set, the ZCDxEN bit of the ZCDxCON register must be set to enable the ZCD module. 2013-2015 Microchip Technology Inc. DS40001729C-page 241 PIC16(L)F1705/9 23.9 Register Definitions: ZCD Control REGISTER 23-1: ZCDxCON: ZERO-CROSS DETECTION CONTROL REGISTER R/W-0/0 U-0 R-x/x R/W-0/0 U-0 U-0 R/W-0/0 R/W-0/0 ZCDxEN — ZCDxOUT ZCDxPOL — — ZCDxINTP ZCDxINTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared q = value depends on configuration bits bit 7 ZCDxEN: Zero-Cross Detection Enable bit(1) 1 = Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current. 0 = Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls. bit 6 Unimplemented: Read as ‘0’ bit 5 ZCDxOUT: Zero-Cross Detection Logic Level bit ZCDxPOL bit = 0: 1 = ZCD pin is sinking current 0 = ZCD pin is sourcing current ZCDxPOL bit = 1: 1 = ZCD pin is sourcing current 0 = ZCD pin is sinking current bit 4 ZCDxPOL: Zero-Cross Detection Logic Output Polarity bit 1 = ZCD logic output is inverted 0 = ZCD logic output is not inverted bit 3-2 Unimplemented: Read as ‘0’ bit 1 ZCDxINTP: Zero-Cross Positive Edge Interrupt Enable bit 1 = ZCDIF bit is set on low-to-high ZCDx_output transition 0 = ZCDIF bit is unaffected by low-to-high ZCDx_output transition bit 0 ZCDxINTN: Zero-Cross Negative Edge Interrupt Enable bit 1 = ZCDIF bit is set on high-to-low ZCDx_output transition 0 = ZCDIF bit is unaffected by high-to-low ZCDx_output transition Note 1: The ZCDxEN bit has no effect when the ZCDDIS Configuration bit is cleared. TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH THE ZCD MODULE Name Bit 7 Bit 6 PIE3 — — PIR3 — — ZCD1EN — ZCD1OUT ZCD1CON Legend: CONFIG2 Legend: Bit 4 Bit 3 COGIE ZCDIE CWGIF ZCDIF ZCD1POL Bit 0 Register on page Bit 2 Bit 1 — — — — 87 — — — — 90 — — ZCD1INTP ZCD1INTN 242 — = unimplemented, read as ‘0’. Shaded cells are unused by the ZCD module. TABLE 23-2: Name Bit 5 SUMMARY OF CONFIGURATION WORD WITH THE ZCD MODULE Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register on Page 13:8 — — LVP DEBUG LPBOR BORV STVREN PLLEN 50 7:0 ZCDDIS — — — — — WRT<1:0> — = unimplemented location, read as ‘0’. Shaded cells are not used by the ZCD module. DS40001729C-page 242 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 24.0 24.1.2 TIMER0 MODULE 8-BIT COUNTER MODE The Timer0 module is an 8-bit timer/counter with the following features: In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin. • • • • • • 8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to ‘1’. 8-bit timer/counter register (TMR0) 8-bit prescaler (independent of Watchdog Timer) Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow TMR0 can be used to gate Timer1 The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION_REG register. Figure 24-1 is a block diagram of the Timer0 module. 24.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 24.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written. FIGURE 24-1: BLOCK DIAGRAM OF THE TIMER0 FOSC/4 Data Bus 0 8 T0CKI 1 Sync 2 TCY 1 TMR0 0 TMR0SE TMR0CS 8-bit Prescaler PSA Set Flag bit TMR0IF on Overflow Overflow to Timer1 8 PS<2:0> 2013-2015 Microchip Technology Inc. DS40001729C-page 243 PIC16(L)F1705/9 24.1.3 SOFTWARE PROGRAMMABLE PRESCALER A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register. Note: The Watchdog Timer (WDT) uses its own independent prescaler. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register. The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler. 24.1.4 TIMER0 INTERRUPT Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register. Note: 24.1.5 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. 8-BIT COUNTER MODE SYNCHRONIZATION When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in Table : . 24.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS40001729C-page 244 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 24.2 Register Definitions: Option Register REGISTER 24-1: OPTION_REG: OPTION REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 WPUEN INTEDG TMR0CS TMR0SE PSA R/W-1/1 R/W-1/1 R/W-1/1 PS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 WPUEN: Weak Pull-Up Enable bit 1 = All weak pull-ups are disabled (except MCLR, if it is enabled) 0 = Weak pull-ups are enabled by individual WPUx latch values bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 TMR0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (FOSC/4) bit 4 TMR0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is not assigned to the Timer0 module 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS<2:0>: Prescaler Rate Select bits TABLE 24-1: Name INTCON TRISA Timer0 Rate 000 001 010 011 100 101 110 111 1:2 1:4 1:8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 GIE OPTION_REG WPUEN TMR0 Bit Value Bit 6 PEIE INTEDG Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF TMR0CS TMR0SE PSA Bit 1 Bit 0 INTF IOCIF PS<2:0> — TRISA5 84 245 Timer0 Module Register — Register on Page 243* TRISA4 —(1) TRISA2 TRISA1 TRISA0 121 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. Note 1: Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001729C-page 245 PIC16(L)F1705/9 25.0 • • • • TIMER1 MODULE WITH GATE CONTROL The Timer1 module is a 16-bit timer/counter with the following features: Figure 25-1 is a block diagram of the Timer1 module. • • • • • • • • 16-bit timer/counter register pair (TMR1H:TMR1L) Programmable internal or external clock source 2-bit prescaler Dedicated 32 kHz oscillator circuit Optionally synchronized comparator out Multiple Timer1 gate (count enable) sources Interrupt on overflow Wake-up on overflow (external clock, Asynchronous mode only) • Time base for the Capture/Compare function • Auto-conversion Trigger (with CCP) • Selectable Gate Source Polarity FIGURE 25-1: Gate Toggle mode Gate Single-pulse mode Gate Value Status Gate Event Interrupt TIMER1 BLOCK DIAGRAM T1GSS<1:0> T1G T1GSPM 00 From Timer0 Overflow 01 sync_C1OUT 10 0 t1g_in T1GVAL 0 sync_C2OUT Single-Pulse D Q CK R Q 11 TMR1ON T1GPOL T1GTM 1 Acq. Control 1 Q1 Data Bus D Q RD T1GCON EN Interrupt T1GGO/DONE Set TMR1GIF det TMR1GE Set flag bit TMR1IF on Overflow To ADC Auto-Conversion TMR1ON To Comparator Module TMR1(2) TMR1H EN TMR1L Q D T1CLK Synchronized clock input 0 1 TMR1CS<1:0> SOSCO LFINTOSC SOSC SOSCI T1SYNC OUT 11 1 Synchronize(3) Prescaler 1, 2, 4, 8 det 10 EN 0 T1OSCEN (1) FOSC Internal Clock 01 FOSC/4 Internal Clock 00 2 T1CKPS<1:0> FOSC/2 Internal Clock Sleep input T1CKI To Clock Switching Modules Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. DS40001729C-page 246 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 25.1 Timer1 Operation 25.2 The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. Table 25-1 displays the Timer1 enable selections. TABLE 25-1: TIMER1 ENABLE SELECTIONS Clock Source Selection The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Table 25-2 displays the clock source selections. 25.2.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. The following asynchronous sources may be used: Timer1 Operation • Asynchronous event on the T1G pin to Timer1 gate • C1 or C2 comparator input to Timer1 gate TMR1ON TMR1GE 0 0 Off 0 1 Off 25.2.2 1 0 Always On 1 1 Count Enabled When the external clock source is selected, the Timer1 module may work as a timer or a counter. EXTERNAL CLOCK SOURCE When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI, which can be synchronized to the microcontroller system clock or can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • • • • TABLE 25-2: TMR1CS<1:0> Timer1 enabled after POR Write to TMR1H or TMR1L Timer1 is disabled Timer1 is disabled (TMR1ON = 0) when T1CKI is high then Timer1 is enabled (TMR1ON=1) when T1CKI is low. CLOCK SOURCE SELECTIONS T1OSCEN Clock Source 11 x LFINTOSC 10 0 External Clocking on T1CKI Pin 01 x System Clock (FOSC) 00 x Instruction Clock (FOSC/4) 2013-2015 Microchip Technology Inc. DS40001729C-page 247 PIC16(L)F1705/9 25.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. 25.4 Timer1 (Secondary) Oscillator 25.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair. The oscillator circuit is enabled by setting the T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep. 25.6 Note: 25.5 The oscillator requires a start-up and stabilization time before use. Thus, T1OSCEN should be set and a suitable delay observed prior to using Timer1. A suitable delay similar to the OST delay can be implemented in software by clearing the TMR1IF bit then presetting the TMR1H:TMR1L register pair to FC00h. The TMR1IF flag will be set when 1024 clock cycles have elapsed, thereby indicating that the oscillator is running and reasonably stable. Timer1 Operation in Asynchronous Counter Mode If the control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see Section 25.5.1 “Reading and Writing Timer1 in Asynchronous Counter Mode”). Note: When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. DS40001729C-page 248 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 Gate Enable. Timer1 gate can also be driven by multiple selectable sources. 25.6.1 TIMER1 GATE ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 25-3 for timing details. TABLE 25-3: TIMER1 GATE ENABLE SELECTIONS T1CLK T1GPOL T1G Timer1 Operation 0 0 Counts 0 1 Holds Count 1 0 Holds Count 1 1 Counts 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 25.6.2 TIMER1 GATE SOURCE SELECTION Timer1 gate source selections are shown in Table 25-4. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. TABLE 25-4: T1GSS TIMER1 GATE SOURCES Timer1 Gate Source 00 Timer1 Gate Pin 01 Overflow of Timer0 (TMR0 increments from FFh to 00h) 10 Comparator 1 Output sync_C1OUT (optionally Timer1 synchronized output) 11 Comparator 2 Output sync_C2OUT (optionally Timer1 synchronized output) 25.6.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 25.6.2.2 Timer0 Overflow Gate Operation When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. 25.6.2.3 Comparator C1 Gate Operation The output resulting from a Comparator 1 operation can be selected as a source for Timer1 gate control. The Comparator 1 output (sync_C1OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 16.4.1 “Comparator Output Synchronization”. 25.6.2.4 Comparator C2 Gate Operation The output resulting from a Comparator 2 operation can be selected as a source for Timer1 gate control. The Comparator 2 output (sync_C2OUT) can be synchronized to the Timer1 clock or left asynchronous. For more information see Section 16.4.1 “Comparator Output Synchronization”. 25.6.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Note: 25.6.4 Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. TIMER1 GATE SINGLE-PULSE MODE When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/DONE bit is once again set in software. See Figure 25-5 for timing details. If the Single-Pulse Gate mode is disabled by clearing the T1GSPM bit in the T1GCON register, the T1GGO/DONE bit should also be cleared. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 25-6 for timing details. 25.6.5 TIMER1 GATE VALUE STATUS When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). 25.6.6 TIMER1 GATE EVENT INTERRUPT When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 25-4 for timing details. 2013-2015 Microchip Technology Inc. DS40001729C-page 249 PIC16(L)F1705/9 25.7 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits: • • • • TMR1ON bit of the T1CON register TMR1IE bit of the PIE1 register PEIE bit of the INTCON register GIE bit of the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. Note: 25.8 Timer1 Operation During Sleep Timer1 can only operate during Sleep when setup in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • • • • • TMR1ON bit of the T1CON register must be set TMR1IE bit of the PIE1 register must be set PEIE bit of the INTCON register must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured • T1OSCEN bit of the T1CON register must be configured The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service Routine. 25.9 CCP Capture/Compare Time Base The CCP modules use the TMR1H:TMR1L register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. In Compare mode, an event is triggered when the value CCPR1H:CCPR1L register pair matches the value in the TMR1H:TMR1L register pair. This event can be an Auto-conversion Trigger. For more information, see “Capture/Compare/PWM Modules”. Section 27.0 25.10 CCP Auto-Conversion Trigger When any of the CCP’s are configured to trigger an auto-conversion, the trigger will clear the TMR1H:TMR1L register pair. This auto-conversion does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPR1H:CCPR1L register pair becomes the period register for Timer1. Timer1 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the Auto-conversion Trigger. Asynchronous operation of Timer1 can cause an Auto-conversion Trigger to be missed. In the event that a write to TMR1H or TMR1L coincides with an Auto-conversion Trigger from the CCP, the write will take precedence. For more information, see Section 27.2.4 “Auto-Conversion Trigger”. Secondary oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. FIGURE 25-2: TIMER1 INCREMENTING EDGE T1CKI = 1 when TMR1 Enabled T1CKI = 0 when TMR1 Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. DS40001729C-page 250 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 25-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N FIGURE 25-4: N+1 N+2 N+3 N+4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL Timer1 N 2013-2015 Microchip Technology Inc. N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 DS40001729C-page 251 PIC16(L)F1705/9 FIGURE 25-5: TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF DS40001729C-page 252 N Cleared by software N+1 N+2 Set by hardware on falling edge of T1GVAL Cleared by software 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 25-6: TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Cleared by hardware on falling edge of T1GVAL Set by software DONE Counting enabled on rising edge of T1G t1g_in T1CKI T1GVAL Timer1 TMR1GIF N Cleared by software 2013-2015 Microchip Technology Inc. N+1 N+2 N+3 N+4 Set by hardware on falling edge of T1GVAL Cleared by software DS40001729C-page 253 PIC16(L)F1705/9 25.11 Register Definitions: Timer1 Control REGISTER 25-1: R/W-0/u T1CON: TIMER1 CONTROL REGISTER R/W-0/u TMR1CS<1:0> R/W-0/u R/W-0/u T1CKPS<1:0> R/W-0/u R/W-0/u U-0 R/W-0/u T1OSCEN T1SYNC — TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TMR1CS<1:0>: Timer1 Clock Source Select bits 11 = LFINTOSC 10 = Timer1 clock source is pin or oscillator: If T1OSCEN = 0: External clock from T1CKI pin (on the rising edge) If T1OSCEN = 1: Crystal oscillator on SOSCI/SOSCO pins 01 = Timer1 clock source is system clock (FOSC) 00 = Timer1 clock source is instruction clock (FOSC/4) bit 5-4 T1CKPS<1:0>: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: LP Oscillator Enable Control bit 1 = Dedicated secondary oscillator circuit enabled 0 = Dedicated secondary oscillator circuit disabled bit 2 T1SYNC: Timer1 Synchronization Control bit 1 = Do not synchronize asynchronous clock input 0 = Synchronize asynchronous clock input with system clock (FOSC) bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 and clears Timer1 gate flip-flop DS40001729C-page 254 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 25-2: T1GCON: TIMER1 GATE CONTROL REGISTER R/W-0/u R/W-0/u R/W-0/u R/W-0/u R/W/HC-0/u R-x/x TMR1GE T1GPOL T1GTM T1GSPM T1GGO/ DONE T1GVAL R/W-0/u R/W-0/u T1GSS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Bit is cleared by hardware bit 7 TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of Timer1 gate function bit 6 T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) bit 5 T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. bit 4 T1GSPM: Timer1 Gate Single-Pulse Mode bit 1 = Timer1 Gate Single-Pulse mode is enabled and is controlling Timer1 gate 0 = Timer1 Gate Single-Pulse mode is disabled bit 3 T1GGO/DONE: Timer1 Gate Single-Pulse Acquisition Status bit 1 = Timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single-pulse acquisition has completed or has not been started bit 2 T1GVAL: Timer1 Gate Value Status bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L Unaffected by Timer1 Gate Enable (TMR1GE) bit 1-0 T1GSS<1:0>: Timer1 Gate Source Select bits 11 = Comparator 2 optionally synchronized output (sync_C2OUT) 10 = Comparator 1 optionally synchronized output (sync_C1OUT) 01 = Timer0 overflow output 00 = Timer1 gate pin 2013-2015 Microchip Technology Inc. DS40001729C-page 255 PIC16(L)F1705/9 TABLE 25-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122 CCP1CON — — DC1B<1:0> CCP1M<3:0> CCP2CON — — DC2B<1:0> CCP2M<3:0> GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF Name INTCON PIE1 PIR1 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register TRISA T1CON T1GCON Legend: * Note 1: — — TMR1CS<1:0> TMR1GE T1GPOL TRISA5 TRISA4 T1CKPS<1:0> T1GTM T1GSPM 269 269 88 246* 246* —(1) TRISA2 TRISA1 TRISA0 121 T1OSCEN T1SYNC — TMR1ON 254 T1GGO/ DONE T1GVAL T1GSS<1:0> 255 — = unimplemented location, read as ‘0’. Shaded cells are not used by the Timer1 module. Page provides register information. Unimplemented, read as ‘1’. DS40001729C-page 256 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 26.0 TIMER2/4/6 MODULE The Timer2/4/6 modules are 8-bit incorporate the following features: timers that • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16, and 1:64) • Software programmable postscaler (1:1 to 1:16) • Interrupt on TMR2 match with PR2, respectively • Optional use as the shift clock for the MSSP module See Figure 26-1 for a block diagram of Timer2. Three identical Timer2 modules are implemented on this device. To maintain consistency with earlier devices, the timers are named Timer2, Timer4, and Timer6. All references to Timer2 apply as well to Timer4 and Timer6. FIGURE 26-1: Fosc/4 TIMER2 BLOCK DIAGRAM Prescaler 1:1, 1:4, 1:16, 1:64 T2_match TMR2 R To Peripherals 2 T2CKPS<1:0> Comparator Postscaler 1:1 to 1:16 set bit TMR2IF 4 PR2 2013-2015 Microchip Technology Inc. T2OUTPS<3:0> DS40001729C-page 257 PIC16(L)F1705/9 26.1 Timer2 Operation The clock input to the Timer2 modules is the system instruction clock (FOSC/4). TMR2 increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, T2CKPS<1:0> of the T2CON register. The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section 26.2 “Timer2 Interrupt”). 26.3 Timer2 Output The unscaled output of TMR2 is available primarily to the CCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP module operating in SPI mode. Additional information is provided in Section 28.0 “Master Synchronous Serial Port (MSSP) Module” 26.4 Timer2 Operation During Sleep The Timer2 timers cannot be operated while the processor is in Sleep mode. The contents of the TMR2 and PR2 registers will remain unchanged while the processor is in Sleep mode. The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, whereas the PR2 register initializes to FFh. Both the prescaler and postscaler counters are cleared on the following events: • • • • • • • • • a write to the TMR2 register a write to the T2CON register Power-on Reset (POR) Brown-out Reset (BOR) MCLR Reset Watchdog Timer (WDT) Reset Stack Overflow Reset Stack Underflow Reset RESET Instruction Note: 26.2 TMR2 is not cleared when T2CON is written. Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE, of the PIE1 register. A range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS<3:0>, of the T2CON register. DS40001729C-page 258 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 26.5 Register Definitions: Timer2 Control REGISTER 26-1: U-0 T2CON: TIMER2 CONTROL REGISTER R/W-0/0 R/W-0/0 — R/W-0/0 R/W-0/0 T2OUTPS<3:0> R/W-0/0 R/W-0/0 TMR2ON bit 7 R/W-0/0 T2CKPS<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 T2OUTPS<3:0>: Timer2 Output Postscaler Select bits 1111 = 1:16 Postscaler 1110 = 1:15 Postscaler 1101 = 1:14 Postscaler 1100 = 1:13 Postscaler 1011 = 1:12 Postscaler 1010 = 1:11 Postscaler 1001 = 1:10 Postscaler 1000 = 1:9 Postscaler 0111 = 1:8 Postscaler 0110 = 1:7 Postscaler 0101 = 1:6 Postscaler 0100 = 1:5 Postscaler 0011 = 1:4 Postscaler 0010 = 1:3 Postscaler 0001 = 1:2 Postscaler 0000 = 1:1 Postscaler bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 11 = Prescaler is 64 10 = Prescaler is 16 01 = Prescaler is 4 00 = Prescaler is 1 2013-2015 Microchip Technology Inc. DS40001729C-page 259 PIC16(L)F1705/9 TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 CCP2CON — — GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 PR2 Timer2 Module Period Register INTCON PIE1 T2CON TMR2 — Bit 5 Bit 4 Bit 3 DC2B<1:0> T2OUTPS<3:0> Bit 2 Bit 1 Bit 0 Register on Page Name CCP2M<3:0> 269 257* TMR2ON T2CKPS<1:0> Holding Register for the 8-bit TMR2 Register 259 257* Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information. DS40001729C-page 260 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 26.6 CCP/PWM Clock Selection The PIC16(L)F1705/9 allow each individual CCP and PWM module to select the timer source that controls the module. Each module has an independent selection. As there are up to three 8-bit timers with auto-reload (Timer2, Timer4, and Timer6), PWM mode on the CCP and PWM modules can use any of these timers. The CCPTMRS register is used to select which timer is used. 26.7 Register Definitions: CCP/PWM Timers Control REGISTER 26-2: R/W-0/0 CCPTMRS: PWM TIMER SELECTION CONTROL REGISTER 0 R/W-0/0 R/W-0/0 P4TSEL<1:0> R/W-0/0 P3TSEL<1:0> R/W-0/0 R/W-0/0 R/W-0/0 C2TSEL<1:0> bit 7 R/W-0/0 C1TSEL<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 P4TSEL<1:0>: PWM4 Timer Selection bits 11 = Reserved 10 = PWM4 is based off Timer6 01 = PWM4 is based off Timer4 00 = PWM4 is based off Timer2 bit 5-4 P3TSEL<1:0>: PWM3 Timer Selection bits 11 = Reserved 10 = PWM3 is based off Timer6 01 = PWM3 is based off Timer4 00 = PWM3 is based off Timer2 bit 3-2 C2TSEL<1:0>: CCP2 (PWM2) Timer Selection bits 11 = Reserved 10 = CCP2 is based off Timer6 in PWM mode 01 = CCP2 is based off Timer4 in PWM mode 00 = CCP2 is based off Timer2 in PWM mode bit 1-0 C1TSEL<1:0>: CCP1 (PWM1) Timer Selection bits 11 = Reserved 10 = CCP1 is based off Timer6 in PWM mode 01 = CCP1 is based off Timer4 in PWM mode 00 = CCP1 is based off Timer2 in PWM mode 2013-2015 Microchip Technology Inc. DS40001729C-page 261 PIC16(L)F1705/9 27.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains two standard Capture/Compare/PWM modules (CCP1 and CCP2). The Capture and Compare functions are identical for all CCP modules. Note 1: In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2: Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required. 27.1 Capture Mode The Capture mode function described in this section is available and identical for all CCP modules. Capture mode makes use of the 16-bit Timer1 resource. When an event occurs on the CCPx pin, the 16-bit CCPRxH:CCPRxL register pair captures and stores the 16-bit value of the TMR1H:TMR1L register pair, respectively. An event is defined as one of the following and is configured by the CCPxM<3:0> bits of the CCPxCON register: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRxH, CCPRxL register pair is read, the old captured value is overwritten by the new captured value. Figure 27-1 shows a simplified diagram of the capture operation. 27.1.1 CCP PIN CONFIGURATION In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. Note: If the CCPx pin is configured as an output, a write to the port can cause a capture condition. FIGURE 27-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Prescaler 1, 4, 16 Set Flag bit CCPxIF (PIRx register) CCPx pin CCPRxH and Edge Detect CCPRxL Capture Enable TMR1H TMR1L CCPxM<3:0> System Clock (FOSC) DS40001729C-page 262 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 27.1.2 TIMER1 MODE RESOURCE 27.1.5 CAPTURE DURING SLEEP Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. See Section 25.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. 27.1.3 SOFTWARE INTERRUPT MODE When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. Note: 27.1.4 Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. CCP PRESCALER There are four prescaler settings specified by the CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. Example 27-1 demonstrates the code to perform this function. EXAMPLE 27-1: Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 27.2 Compare Mode The Compare mode function described in this section is available and identical for all CCP modules. Compare mode makes use of the 16-bit Timer1 resource. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMR1H:TMR1L register pair. When a match occurs, one of the following events can occur: • • • • • Toggle the CCPx output Set the CCPx output Clear the CCPx output Generate an Auto-conversion Trigger Generate a Software Interrupt The action on the pin is based on the value of the CCPxM<3:0> control bits of the CCPxCON register. At the same time, the interrupt flag CCPxIF bit is set. All Compare modes can generate an interrupt. Figure 27-2 shows a simplified diagram of the compare operation. FIGURE 27-2: COMPARE MODE OPERATION BLOCK DIAGRAM CHANGING BETWEEN CAPTURE PRESCALERS BANKSEL CCPxCON CLRF MOVLW MOVWF ;Set Bank bits to point ;to CCPxCON CCPxCON ;Turn CCP module off NEW_CAPT_PS ;Load the W reg with ;the new prescaler ;move value and CCP ON CCPxCON ;Load CCPxCON with this ;value CCPxM<3:0> Mode Select Set CCPxIF Interrupt Flag (PIRx) 4 CCPRxH CCPRxL CCPx Pin Q S R Output Logic Match Comparator TMR1H TRIS Output Enable TMR1L Auto-conversion Trigger 2013-2015 Microchip Technology Inc. DS40001729C-page 263 PIC16(L)F1705/9 27.2.1 CCPX PIN CONFIGURATION The user must configure the CCPx pin as an output by clearing the associated TRIS bit. Note: 27.2.2 Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. TIMER1 MODE RESOURCE In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section 25.0 “Timer1 Module with Gate Control” for more information on configuring Timer1. Note: 27.2.3 Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, TImer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. 27.2.4 AUTO-CONVERSION TRIGGER When Auto-conversion Trigger mode is chosen (CCPxM<3:0> = 1011), the CCPx module does the following: • Resets Timer1 • Starts an ADC conversion if ADC is enabled The CCPx module does not assert control of the CCPx pin in this mode. The Auto-conversion Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPRxH, CCPRxL register pair. The TMR1H, TMR1L register pair is not reset until the next rising edge of the Timer1 clock. The Auto-conversion Trigger output starts an ADC conversion (if the ADC module is enabled). This allows the CCPRxH, CCPRxL register pair to effectively provide a 16-bit programmable period register for Timer1. Refer to Section 20.2.5 “Auto-Conversion Trigger” for more information. Note 1: The Auto-conversion Trigger from the CCP module does not set interrupt flag bit TMR1IF of the PIR1 register. 2: Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Auto-conversion Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen (CCPxM<3:0> = 1010), the CCPx module does not assert control of the CCPx pin (see the CCPxCON register). 27.2.5 COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep. DS40001729C-page 264 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 27.3 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of on and off time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. FIGURE 27-3: Period Pulse Width 27.3.1 TMR2 = 0 FIGURE 27-4: The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to 10 bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • SIMPLIFIED PWM BLOCK DIAGRAM CCP1CON<5:4> Duty Cycle Registers CCPR1L CCPR1H(2) (Slave) CCP1 R Comparator (1) TMR2 Q S TRIS Comparator STANDARD PWM OPERATION The standard PWM function described in this section is available and identical for all CCP modules. TMR2 = PR2 TMR2 = CCPRxH:CCPxCON<5:4> The term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. Figure 27-3 shows a typical waveform of the PWM signal. CCP PWM OUTPUT SIGNAL PR2 Note 1: 2: Clear Timer, toggle CCP1 pin and latch duty cycle The 8-bit timer TMR2 register is concatenated with the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. In PWM mode, CCPR1H is a read-only register. PR2 registers T2CON registers CCPRxL registers CCPxCON registers Figure 27-4 shows a simplified block diagram of PWM operation. Note: The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 2013-2015 Microchip Technology Inc. DS40001729C-page 265 PIC16(L)F1705/9 27.3.2 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. 6. Use the desired output pin RxyPPS control to select CCPx as the source and disable the CCPx pin output driver by setting the associated TRIS bit. Load the PR2 register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRxL register and the DCxBx bits of the CCPxCON register, with the PWM duty cycle value. Configure and start Timer2: • Clear the TMR2IF interrupt flag bit of the PIRx register. See Note below. • Configure the T2CKPS bits of the T2CON register with the Timer prescale value. • Enable the Timer by setting the TMR2ON bit of the T2CON register. Enable PWM output pin: • Wait until the Timer overflows and the TMR2IF bit of the PIR1 register is set. See Note below. • Enable the CCPx pin output driver by clearing the associated TRIS bit. Note: 27.3.3 • TMR2 is cleared • The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) • The PWM duty cycle is latched from CCPRxL into CCPRxH. Note: 27.3.5 The Timer postscaler (see Section 26.1 “Timer2 Operation”) is not used in the determination of the PWM frequency. PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10-bit value to multiple registers: CCPRxL register and DCxB<1:0> bits of the CCPxCON register. The CCPRxL contains the eight MSbs and the DCxB<1:0> bits of the CCPxCON register contain the two LSbs. CCPRxL and DCxB<1:0> bits of the CCPxCON register can be written to at any time. The duty cycle value is not latched into CCPRxH until after the period completes (i.e., a match between PR2 and TMR2 registers occurs). While using the PWM, the CCPRxH register is read-only. Equation 27-2 is used to calculate the PWM pulse width. Equation 27-3 is used to calculate the PWM duty cycle ratio. In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. EQUATION 27-2: TIMER2 TIMER RESOURCE EQUATION 27-3: The PWM standard mode makes use of the 8-bit Timer2 timer resources to specify the PWM period. 27.3.4 When TMR2 is equal to PR2, the following three events occur on the next increment cycle: PULSE WIDTH Pulse Width = CCPRxL:CCPxCON<5:4> T OSC (TMR2 Prescale Value) DUTY CYCLE RATIO CCPRxL:CCPxCON<5:4> Duty Cycle Ratio = ----------------------------------------------------------------------4 PR2 + 1 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 27-1. EQUATION 27-1: PWM PERIOD PWM Period = PR2 + 1 4 T OSC (TMR2 Prescale Value) Note 1: TOSC = 1/FOSC DS40001729C-page 266 The CCPRxH register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer TMR2 register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPRxH and 2-bit latch, then the CCPx pin is cleared (see Figure 27-4). 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 27.3.6 PWM RESOLUTION EQUATION 27-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PR2 is 255. The resolution is a function of the PR2 register value as shown by Equation 27-4. TABLE 27-1: 1.22 kHz Timer Prescale PR2 Value Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged. 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Maximum Resolution (bits) EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 8 MHz) PWM Frequency 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Timer Prescale PR2 Value Maximum Resolution (bits) 27.3.7 log 4 PR2 + 1 Resolution = ------------------------------------------ bits log 2 EXAMPLE PWM FREQUENCIES AND RESOLUTIONS (FOSC = 20 MHz) PWM Frequency TABLE 27-2: PWM RESOLUTION OPERATION IN SLEEP MODE In Sleep mode, the TMR2 register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, TMR2 will continue from its previous state. 27.3.8 CHANGES IN SYSTEM CLOCK FREQUENCY The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See Section 6.0 “Oscillator Module (with Fail-Safe Clock Monitor)” for additional details. 27.3.9 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 2013-2015 Microchip Technology Inc. DS40001729C-page 267 PIC16(L)F1705/9 TABLE 27-3: Name CCP1CON CCPR1L CCPTMRS INTCON SUMMARY OF REGISTERS ASSOCIATED WITH STANDARD PWM Bit 7 Bit 6 — — Bit 5 Bit 4 Bit 3 DC1B<1:0> Bit 2 Bit 1 Bit 0 CCP1M<3:0> 269 Capture/Compare/PWM Register 1 (LSB) P4TSEL<1:0> Register on Page 266* P3TSEL<1:0> C2TSEL<1:0> GIE PEIE TMR0IE INTE IOCIE C1TSEL<1:0> TMR0IF INTF IOCIF 261 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 86 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF 89 PR2 Timer2 Period Register RxyPPS — T2CON — TMR2 — 257* — T2OUTPS<3:0> RxyPPS<4:0> TMR2ON 141 T2CKPS<1:0> Timer2 Module Register 259 257 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the PWM. * Page provides register information. DS40001729C-page 268 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 27.4 Register Definitions: CCP Control REGISTER 27-1: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 — — R/W-0/0 R/W-0/0 R/W-0/0 DCxB<1:0> R/W-0/0 R/W-0/0 R/W-0/0 CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: Unused Compare mode: Unused PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0 CCPxM<3:0>: CCPx Mode Select bits 11xx = PWM mode 1011 = Compare mode: Auto-conversion Trigger (sets CCPxIF bit), starts ADC conversion if TRIGSEL = CCPx (see Register 20-3) 1010 = Compare mode: generate software interrupt only 1001 = Compare mode: clear output on compare match (set CCPxIF) 1000 = Compare mode: set output on compare match (set CCPxIF) 0111 = 0110 = 0101 = 0100 = Capture mode: every 16th rising edge Capture mode: every 4th rising edge Capture mode: every rising edge Capture mode: every falling edge 0011 = 0010 = 0001 = 0000 = Reserved Compare mode: toggle output on match Reserved Capture/Compare/PWM off (resets CCPx module) 2013-2015 Microchip Technology Inc. DS40001729C-page 269 PIC16(L)F1705/9 28.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 28.1 MSSP Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) The SPI interface supports the following modes and features: • • • • • Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices Figure 28-1 is a block diagram of the SPI interface module. FIGURE 28-1: MSSP BLOCK DIAGRAM (SPI MODE) Data Bus Read Write SSPxBUF Reg SDI SSPSR Reg SDO bit 0 SS SS Control Enable Shift Clock 2 (CKP, CKE) Clock Select Edge Select SSPM<3:0> 4 SCK Edge Select TRIS bit DS40001729C-page 270 ( T2_match 2 ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD) 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 The I2C interface supports the following modes and features: • • • • • • • • • • • • • Master mode Slave mode Byte NACKing (Slave mode) Limited multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 28-2 is a block diagram of the I2C interface module in Master mode. Figure 28-3 is a diagram of the I2C interface module in Slave mode. MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal data bus Read [SSPM<3:0>] Write SSP1BUF Shift Clock SDA in Receive Enable (RCEN) SCL SCL in Bus Collision 2013-2015 Microchip Technology Inc. LSb Start bit, Stop bit, Acknowledge Generate (SSPCON2) Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Clock Cntl SSPSR MSb (Hold off clock source) SDA Baud Rate Generator (SSPxADD) Clock arbitrate/BCOL detect FIGURE 28-2: Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV Reset SEN, PEN (SSPCON2) Set SSP1IF, BCL1IF DS40001729C-page 271 PIC16(L)F1705/9 FIGURE 28-3: MSSP BLOCK DIAGRAM (I2C SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCL Shift Clock SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect DS40001729C-page 272 Set, Reset S, P bits (SSPxSTAT Reg) 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 28.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: • • • • Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) Figure 28-1 shows the block diagram of the MSSP module when operating in SPI mode. The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. Figure 28-4 shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDO pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its shift register. After eight bits have been shifted out, the master and slave have exchanged register values. If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: • Master sends useful data and slave sends dummy data. • Master sends useful data and slave sends useful data. • Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. Figure 28-5 shows a typical connection between two processors configured as master and slave devices. Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. 2013-2015 Microchip Technology Inc. DS40001729C-page 273 PIC16(L)F1705/9 FIGURE 28-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 28.2.1 SPI MODE REGISTERS 28.2.2 The MSSP module has five registers for SPI mode operation. These are: • • • • • • MSSP STATUS register, SSPxSTAT MSSP Control register 1, SSPxCON1 MSSP Control register 3 (SSPxCON3) MSSP Data Buffer register (SSPxBUF) MSSP Address register (SSPxADD) MSSP Shift register (SSPSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control STATUS registers in SPI mode operation. SSPxCON1 register is readable and writable. lower six bits of the SSPxSTAT are read-only. upper two bits of the SSPxSTAT are read/write. SPI MODE OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: • • • • and The The The In one SPI master mode, SSPxADD can be loaded with a value used in the Baud Rate Generator. More information on the Baud Rate Generator is available in Section 28.7 “Baud Rate Generator”. SSPSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPxBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR. Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCK) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) To enable the serial port, SSP Enable bit, SSPEN of the SSPxCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCONx registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: • SDI must have corresponding TRIS bit set • SDO must have corresponding TRIS bit cleared • SCK (Master mode) must have corresponding TRIS bit cleared • SCK (Slave mode) must have corresponding TRIS bit set • SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. DS40001729C-page 274 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPxBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF of the SSPxSTAT register, and the interrupt flag bit, SSPIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/reception of data will be ignored and the write collision detect bit WCOL of the SSPxCON1 register, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. FIGURE 28-5: When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF of the SSPxSTAT register, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various Status conditions. SPI MASTER/SLAVE CONNECTION SPI Master SSPM<3:0> = 00xx = 1010 SPI Slave SSPM<3:0> = 010x SDO SDI Serial Input Buffer (BUF) SDI Shift Register (SSPSR) MSb Serial Input Buffer (SSPxBUF) LSb SCK General I/O Processor 1 2013-2015 Microchip Technology Inc. SDO Serial Clock Slave Select (optional) Shift Register (SSPSR) MSb LSb SCK SS Processor 2 DS40001729C-page 275 PIC16(L)F1705/9 28.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 28-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit of the SSPxCON1 register and the CKE bit of the SSPxSTAT register. This then, would give waveforms for SPI communication as shown in Figure 28-6, Figure 28-8, Figure 28-9 and Figure 28-10, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • • • • • FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 FOSC/(4 * (SSPxADD + 1)) Figure 28-6 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. Note: DS40001729C-page 276 In Master mode the clock signal output to the SCK pin is also the clock signal input to the peripheral. The pin selected for output with the RxyPPS register must also be selected as the peripheral input with the SSPCLKPPS register. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 28-6: SPI MODE WAVEFORM (MASTER MODE) Write to SSPxBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPIF SSPSR to SSPxBUF 28.2.4 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPxCON1 register. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wake-up from Sleep. 2013-2015 Microchip Technology Inc. 28.2.4.1 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. Figure 28-7 shows the block diagram of a typical daisy-chain connection when operating in SPI mode. In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit of the SSPxCON3 register will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. DS40001729C-page 277 PIC16(L)F1705/9 28.2.5 SLAVE SELECT SYNCHRONIZATION When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPxCON1<3:0> = 0100). FIGURE 28-7: When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPxCON1<3:0> = 0100), the SPI module will reset if the SS pin is set to VDD. 2: When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. 3: While operated in SPI Slave mode the SMP bit of the SSPxSTAT register must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. SPI DAISY-CHAIN CONNECTION SPI Master SCK SCK SDO SDI SDI General I/O SDO SPI Slave #1 SS SCK SDI SDO SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS DS40001729C-page 278 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 28-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPSR and bit count are reset SSPxBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPxBUF 2013-2015 Microchip Technology Inc. DS40001729C-page 279 PIC16(L)F1705/9 FIGURE 28-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active FIGURE 28-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 7 bit 0 Input Sample SSPIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active DS40001729C-page 280 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 28.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP interrupts should be disabled. TABLE 28-1: Name In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page ANSELA — — — ANSA4 — ANSA2 ANSA1 ANSA0 122 ANSELC ANSC7(2) ANSC6(2) ANSC5(3) ANSC4(3) ANSC3 ANSC2 ANSC1 ANSC0 133 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 RxyPPS — — — RxyPPS<4:0> 141 SSPCLKPPS — — — SSPCLKPPS<4:0> 139, 140 SSPDATPPS — — — SSPDATPPS<4:0> 139, 140 SSPSSPPS — — — SSPSSPPS<4:0> 139, 140 SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 274* SSP1CON1 WCOL SSPOV SSPEN CKP SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 318 SSP1STAT SMP CKE D/A P S R/W UA BF 318 121 TRISA TRISB(2) TRISC Legend: * Note 1: 2: 3: SSPM<3:0> (1) — 319 — — TRISA5 TRISA4 TRISA2 TRISA1 TRISA0 TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC7(2) TRISC6(2) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. Page provides register information. Unimplemented, read as ‘1’. PIC16(L)F1709 only. PIC16(L)F1705 only. 2013-2015 Microchip Technology Inc. DS40001729C-page 281 PIC16(L)F1705/9 28.3 I2C MODE OVERVIEW The Inter-Integrated Circuit (I2C) bus is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. VDD SCL The I2C bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Figure 28-11 shows the block diagram of the MSSP module when operating in I2C mode. Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. Figure 28-11 shows a typical connection between two processors configured as master and slave devices. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: • Master Transmit mode (master is transmitting data to a slave) • Master Receive mode (master is receiving data from a slave) • Slave Transmit mode (slave is transmitting data to a master) • Slave Receive mode (slave is receiving data from the master) To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. DS40001729C-page 282 I2C MASTER/ SLAVE CONNECTION FIGURE 28-11: SCL VDD Master Slave SDA SDA The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols; • Single message where a master writes data to a slave. • Single message where a master reads data from a slave. • Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. 28.3.1 CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 28.3.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. 2013-2015 Microchip Technology Inc. DS40001729C-page 283 PIC16(L)F1705/9 28.4 I2C MODE OPERATION All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 28.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the eighth falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 28.4.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C specification. 28.4.3 SDA AND SCL PINS Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note 1: Data is tied to output zero when an I2C mode is enabled. 2: Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These functions are bidirectional. The SDA input is selected with the SSPDATPPS registers. The SCL input is selected with the SSPCLKPPS registers. Outputs are selected with the RxyPPS registers. It is the user’s responsibility to make the selections so that both the input and the output for each function is on the same pin. 28.4.4 TABLE 28-2: TERM I2C BUS TERMS Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Slave device that has received a Addressed Slave matching address and is actively being clocked by a master. Matching Address byte that is clocked into a Address slave that matches the value stored in SSPxADD. Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state. SDA HOLD TIME The hold time of the SDA pin is selected by the SDAHT bit of the SSPxCON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. DS40001729C-page 284 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 28.4.5 START CONDITION 28.4.7 I2C The specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 28-12 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. Figure 28-13 shows the wave form for a Restart condition. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. 28.4.6 RESTART CONDITION In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. STOP CONDITION A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. Note: At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained until a Stop condition, a high address with R/W clear, or high address match fails. 28.4.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits of the SSPxCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. Slave modes where interrupt on Start and Stop detect are already enabled, these bits will have no effect. FIGURE 28-12: I2C START AND STOP CONDITIONS SDA SCL S Start P Change of Change of Data Allowed Data Allowed Condition FIGURE 28-13: Stop Condition I2C RESTART CONDITION Sr Change of Change of Data Allowed Restart Data Allowed Condition 2013-2015 Microchip Technology Inc. DS40001729C-page 285 PIC16(L)F1705/9 28.4.9 ACKNOWLEDGE SEQUENCE The 9th SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit of the SSPCON2 register. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit of the SSPCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits of the SSPxCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit of the SSPxSTAT register or the SSPOV bit of the SSPxCON1 register are set when a byte is received. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit of the SSPxCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is enabled. 28.5 I2C SLAVE MODE OPERATION The MSSP Slave mode operates in one of four modes selected by the SSPM bits of SSPxCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operate the same as the other modes with SSPIF additionally getting set upon detection of a Start, Restart, or Stop condition. 28.5.1 SLAVE MODE ADDRESSES The SSPxADD register (Register 28-6) contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSP Mask register (Register 28-5) affects the address matching process. See Section 28.5.8 “SSP Mask Register” for more information. 28.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 28.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb’s of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPIF and UA are set, and SCL is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. DS40001729C-page 286 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 28.5.2 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPOV of the SSPxCON1 register is set. The BOEN bit of the SSPxCON3 register modifies this operation. For more information see Register 28-4. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPIF, must be cleared by software. When the SEN bit of the SSPCON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit of the SSPxCON1 register, except sometimes in 10-bit mode. See Section 28.5.6.2 “10-bit Addressing Mode” for more detail. 28.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit Addressing mode. Figure 28-14 and Figure 28-15 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSPIF bit. Software clears the SSPIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSPIF bit. Software clears SSPIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the master. Master sends Stop condition, setting P bit of SSPxSTAT, and the bus goes idle. 2013-2015 Microchip Technology Inc. 28.5.2.2 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that was not present on previous versions of this module. This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 28-16 displays a module using both address and data holding. Figure 28-17 includes the operation with the SEN bit of the SSPCON2 register set. 1. S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPIF is set and CKP cleared after the eighth falling edge of SCL. 3. Slave clears the SSPIF. 4. Slave can look at the ACKTIM bit of the SSPxCON3 register to determine if the SSPIF was after or before the ACK. 5. Slave reads the address value from SSPxBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPIF. Note: SSPIF is still set after the 9th falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSPIF not set 11. SSPIF set and CKP cleared after eighth falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit of SSPxCON3 to determine the source of the interrupt. 13. Slave reads the received data from SSPxBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit of the SSTSTAT register. DS40001729C-page 287 DS40001729C-page 288 SSPOV BF SSPIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 3 D5 Receiving Data From Slave to Master 8 D0 9 P SSPIF set on 9th falling edge of SCL ACK = 1 FIGURE 28-14: SCL SDA Receiving Address Bus Master sends Stop condition PIC16(L)F1705/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. CKP SSPOV BF SSPIF 1 SCL S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSPxBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 2 D6 CKP is written to ‘1’ in software, releasing SCL 1 D7 Receive Data 8 D0 9 ACK SCL is not held low because ACK= 1 SSPIF set on 9th falling edge of SCL P FIGURE 28-15: SDA Receive Address Bus Master sends Stop condition PIC16(L)F1705/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS40001729C-page 289 DS40001729C-page 290 P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPIF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL SSPIF is set on 9th falling edge of SCL, after ACK 1 8 ACK D7 D6 D5 D4 D3 D2 D1 D0 Received Data 1 2 4 5 6 ACKTIM set by hardware on 8th falling edge of SCL CKP set by software, SCL is released 8 Slave software sets ACKDT to not ACK 7 Cleared by software 3 D7 D6 D5 D4 D3 D2 D1 D0 Data is read from SSPxBUF 9 ACK 9 P No interrupt after not ACK from Slave ACK=1 Master sends Stop condition FIGURE 28-16: SCL SDA Master Releases SDA to slave for ACK sequence PIC16(L)F1705/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. P S ACKTIM CKP ACKDT BF SSPIF S Receiving Address 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPxBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCL 1 A7 A6 A5 A4 A3 A2 A1 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCL When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared Received data is available on SSPxBUF Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK Receive Data 1 3 4 5 6 7 8 Set by software, release SCL Slave sends not ACK SSPxBUF can be read any time before next byte is loaded 2 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK CKP is not cleared if not ACK No interrupt after if not ACK from Slave P Master sends Stop condition FIGURE 28-17: SCL SDA R/W = 0 Master releases SDA to slave for ACK sequence PIC16(L)F1705/9 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) DS40001729C-page 291 PIC16(L)F1705/9 28.5.3 SLAVE TRANSMISSION 28.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 28-18 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see Section 28.5.6 “Clock Stretching” for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSPxBUF register which also loads the SSPSR register. Then the SCL pin should be released by setting the CKP bit of the SSPxCON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit of the SSPCON2 register. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. 28.5.3.1 Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit of the SSPxCON3 register is set, the BCLIF bit of the PIR register is set. Once a bus collision is detected, the slave goes idle and waits to be addressed again. User software can use the BCLIF bit to handle a slave bus collision. DS40001729C-page 292 Master sends a Start condition on SDA and SCL. 2. S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSPIF bit. 4. Slave hardware generates an ACK and sets SSPIF. 5. SSPIF bit is cleared by user. 6. Software reads the received address from SSPxBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPxBUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSPIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than the falling. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. P S D/A R/W ACKSTAT CKP BF SSPIF S Receiving Address 1 2 5 6 7 8 Indicates an address has been received R/W is copied from the matching address byte 9 R/W = 1 Automatic ACK Received address is read from SSPxBUF 4 When R/W is set SCL is always held low after 9th SCL falling edge 3 A7 A6 A5 A4 A3 A2 A1 Transmitting Data Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPxBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters not ACK is copied to ACKSTAT BF is automatically cleared after 8th falling edge of SCL 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P FIGURE 28-18: SCL SDA Master sends Stop condition PIC16(L)F1705/9 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) DS40001729C-page 293 PIC16(L)F1705/9 28.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 28-19 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled. 1. 2. Bus starts Idle. Master sends Start condition; the S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. 3. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSPIF interrupt is generated. 4. Slave software clears SSPIF. 5. Slave software reads ACKTIM bit of SSPxCON3 register, and R/W and D/A of the SSPxSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the SSPCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPIF after the ACK if the R/W bit is set. 11. Slave software clears SSPIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Note: SSPxBUF cannot be loaded until after the ACK. 13. Slave sets the CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit of the SSPCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS40001729C-page 294 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address. 1 A7 A6 A5 A4 A3 A2 A1 3 4 5 6 Cleared by software 2 Set by software, releases SCL Data to transmit is loaded into SSPxBUF 1 7 8 9 Transmitting Data Automatic D7 D6 D5 D4 D3 D2 D1 D0 ACK ACKTIM is cleared on 9th rising edge of SCL Automatic Transmitting Data 1 3 4 5 6 7 after not ACK CKP not cleared Master’s ACK response is copied to SSPxSTAT BF is automatically cleared after 8th falling edge of SCL 2 8 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P Master sends Stop condition FIGURE 28-19: SCL SDA Master releases SDA to slave for ACK sequence PIC16(L)F1705/9 I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) DS40001729C-page 295 PIC16(L)F1705/9 28.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 28-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit of SSPxSTAT is set; SSPIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit of the SSPxSTAT register is set. Slave sends ACK and SSPIF is set. Software clears the SSPIF bit. Software reads received address from SSPxBUF clearing the BF flag. Slave loads low address into SSPxADD, releasing SCL. Master sends matching low address byte to the slave; UA bit is set. 28.5.5 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 28-21 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 28-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPIF is set. Note: If the low address does not match, SSPIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPIF. 11. Slave reads the received matching address from SSPxBUF clearing BF. 12. Slave loads high address into SSPxADD. 13. Master clocks a data byte to the slave and clocks out the slaves ACK on the 9th SCL pulse; SSPIF is set. 14. If SEN bit of SSPCON2 is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPIF. 16. Slave reads the received byte from SSPxBUF clearing BF. 17. If SEN is set the slave sets CKP to release the SCL. 18. Steps 13-17 repeat for each received byte. 19. Master sends Stop to end the transmission. DS40001729C-page 296 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. CKP UA BF SSPIF S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCL is held low 9 ACK If address matches SSPxADD it is loaded into SSPxBUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSPxADD and releases SCL 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPxBUF SCL is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte Receive address is read from SSPxBUF Cleared by software 2 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data P FIGURE 28-20: SCL SDA Master sends Stop condition PIC16(L)F1705/9 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) DS40001729C-page 297 DS40001729C-page 298 ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPxADD is not allowed until 9th falling edge of SCL SSPxBUF can be read anytime before the next received byte Cleared by software 1 A7 Receive Second Address Byte 8 A0 9 ACK UA 2 D6 3 D5 4 D4 6 D2 Set CKP with software releases SCL 7 D1 Update of SSPxADD, clears UA and releases SCL 5 D3 Receive Data Cleared by software 1 D7 8 9 2 Received data is read from SSPxBUF 1 D6 D5 Receive Data D0 ACK D7 FIGURE 28-21: SSPIF 1 SCL S 1 SDA Receive First Address Byte PIC16(L)F1705/9 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. D/A R/W ACKSTAT CKP UA BF SSPIF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPxADD must be updated SSPxBUF loaded with received address 2 8 9 1 SCL S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK 1 3 4 5 6 7 8 After SSPxADD is updated, UA is cleared and SCL is released Cleared by software 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receiving Second Address Byte 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the matching address byte When R/W = 1; CKP is cleared on 9th falling edge of SCL High address is loaded back into SSPxADD Received address is read from SSPxBUF Sr 1 1 1 1 0 A9 A8 Receive First Address Byte 9 ACK 2 3 4 5 6 7 8 Masters not ACK is copied Set by software releases SCL Data to transmit is loaded into SSPxBUF 1 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data Byte 9 P Master sends Stop condition ACK = 1 Master sends not ACK FIGURE 28-22: SDA Master sends Restart event PIC16(L)F1705/9 I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) DS40001729C-page 299 PIC16(L)F1705/9 28.5.6 CLOCK STRETCHING 28.5.6.2 10-bit Addressing Mode Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. In 10-bit Addressing mode, when the UA bit is set the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD. The CKP bit of the SSPxCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. When AHEN bit of SSPxCON3 is set; CKP is cleared by hardware after the eighth falling edge of SCL for a received matching address byte. When DHEN bit of SSPxCON3 is set; CKP is cleared after the eighth falling edge of SCL for received data. 28.5.6.1 Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. Normal Clock Stretching Following an ACK if the R/W bit of SSPxSTAT is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit of SSPCON2 is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Note 1: The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the 9th falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the 9th falling edge of SCL. It is now always cleared for read requests. FIGURE 28-23: Note: Previous versions of the module did not stretch the clock if the second address byte did not match. 28.5.6.3 28.5.6.4 Byte NACKing Clock Synchronization and the CKP Bit Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see Figure 28-23). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX ‚ – 1 DX SCL CKP Master device asserts clock Master device releases clock WR SSPxCON1 DS40001729C-page 300 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 28.5.7 GENERAL CALL ADDRESS SUPPORT software can read SSPxBUF Figure 28-24 shows a general sequence. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. respond. reception In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. If the AHEN bit of the SSPxCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the eighth falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit of the SSPCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave FIGURE 28-24: and call SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPIF BF (SSPxSTAT<0>) Cleared by software GCEN (SSPCON2<7>) SSPxBUF is read ’1’ 28.5.8 SSP MASK REGISTER An SSP Mask (SSPMSK) register (Register 28-5) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: • 7-bit Address mode: address compare of A<7:1>. • 10-bit Address mode: address compare of A<7:0> only. The SSP mask has no effect during the reception of the first (high) byte of the address. 2013-2015 Microchip Technology Inc. DS40001729C-page 301 PIC16(L)F1705/9 28.6 I2C Master Mode 28.6.1 I2C MASTER MODE OPERATION Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPxCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is Idle. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Firmware Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSPIF, to be set (SSP interrupt, if enabled): • • • • • Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See Section 28.7 “Baud Rate Generator” for more detail. 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. DS40001729C-page 302 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 28.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 28-25). FIGURE 28-25: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX ‚ – 1 DX SCL deasserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 28.6.3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle. Note: Because queuing of events is not allowed, writing to the lower five bits of SSPCON2 is disabled until the Start condition is complete. 2013-2015 Microchip Technology Inc. DS40001729C-page 303 PIC16(L)F1705/9 28.6.4 I2C MASTER MODE START CONDITION TIMING hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. To initiate a Start condition (Figure 28-26), the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit of the SSPxSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit of the SSPCON2 register will be automatically cleared by FIGURE 28-26: Note 1: If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2: The Philips I2C specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPxSTAT<3>) At completion of Start bit, hardware clears SEN bit and sets SSPIF bit SDA = 1, SCL = 1 TBRG TBRG Write to SSPxBUF occurs here SDA 2nd bit 1st bit TBRG SCL S DS40001729C-page 304 TBRG 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 28.6.5 I2C MASTER MODE REPEATED START CONDITION TIMING SSPCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit of the SSPxSTAT register will be set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. A Repeated Start condition (Figure 28-27) occurs when the RSEN bit of the SSPCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit of the FIGURE 28-27: Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low-to-high. • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. REPEATED START CONDITION WAVEFORM S bit set by hardware Write to SSPCON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears RSEN bit and sets SSPIF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPxBUF occurs here TBRG SCL Sr TBRG Repeated Start 2013-2015 Microchip Technology Inc. DS40001729C-page 305 PIC16(L)F1705/9 28.6.6 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCL low and SDA unchanged (Figure 28-28). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCL low and allowing SDA to float. 28.6.6.1 BF Status Flag 28.6.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit of the SSPCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 28.6.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Typical Transmit Sequence: The user generates a Start condition by setting the SEN bit of the SSPCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits of the SSPCON2 register. Interrupt is generated once the Stop/Restart condition is complete. In Transmit mode, the BF bit of the SSPxSTAT register is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted out. 28.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. DS40001729C-page 306 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. S R/W PEN SEN BF (SSPxSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPxBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPxBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxBUF is written by software Cleared by software service routine from SSP interrupt 2 D6 Transmitting Data or Second Half of 10-bit Address From slave, clear ACKSTAT bit SSPCON2<6> P Cleared by software 9 ACK ACKSTAT in SSPCON2 = 1 FIGURE 28-28: SEN = 0 Write SSPCON2<0> SEN = 1 Start condition begins PIC16(L)F1705/9 I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) DS40001729C-page 307 PIC16(L)F1705/9 28.6.7 I2C MASTER MODE RECEPTION Master mode reception (Figure 28-29) is enabled by programming the Receive Enable bit, RCEN bit of the SSP1CON2 register. Note: The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPxBUF, the BF flag bit is set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit of the SSPCON2 register. 28.6.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPSR. It is cleared when the SSPxBUF register is read. 28.6.7.2 SSPOV Status Flag 28.6.7.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 13. 14. 28.6.7.3 15. WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). DS40001729C-page 308 Typical Receive Sequence: The user generates a Start condition by setting the SEN bit of the SSPCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software. User writes SSPxBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit of the SSPCON2 register. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. User sets the RCEN bit of the SSPCON2 register and the master clocks in a byte from the slave. After the eighth falling edge of SCL, SSPIF and BF are set. Master clears SSPIF and reads the received byte from SSPUF, clears BF. Master sets ACK value sent to slave in ACKDT bit of the SSPCON2 register and initiates the ACK by setting the ACKEN bit. Master’s ACK is clocked out to the slave and SSPIF is set. User clears SSPIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. 2013-2015 Microchip Technology Inc. 2013-2015 Microchip Technology Inc. S RCEN ACKEN SSPOV BF (SSPxSTAT<0>) SDA = 0, SCL = 1 while CPU responds to SSPIF SSPIF SCL SDA 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDA = ACKDT = 0 Cleared in software Set SSPIF at end of receive 9 ACK is not sent ACK RCEN cleared automatically P Set SSPIF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPxSTAT<4>) and SSPIF PEN bit = 1 written here SSPOV is set because SSPxBUF is still full 8 D0 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 D7 D6 D5 D4 D3 D2 D1 Last bit is shifted into SSPSR and contents are unloaded into SSPxBUF Cleared by software Set SSPIF interrupt at end of receive 4 Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) A1 R/W RCEN = 1, start next receive ACK from Master SDA = ACKDT = 0 FIGURE 28-29: RCEN cleared automatically Master configured as a receiver by programming SSPCON2<3> (RCEN = 1) SEN = 0 Write to SSPxBUF occurs here, ACK from Slave start XMIT Write to SSPCON2<0> (SEN = 1), begin Start condition Write to SSPCON2<4> to start Acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 PIC16(L)F1705/9 I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) DS40001729C-page 309 PIC16(L)F1705/9 28.6.8 ACKNOWLEDGE SEQUENCE TIMING 28.6.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit of the SSPxSTAT register is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 28-31). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit, ACKEN bit of the SSPCON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 28-30). 28.6.8.1 28.6.9.1 WCOL Status Flag If the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 28-30: STOP CONDITION TIMING ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL 8 9 SSPIF SSPIF set at the end of receive Cleared in software Cleared in software SSPIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. FIGURE 28-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPCON2, set PEN PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. DS40001729C-page 310 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 28.6.10 SLEEP OPERATION 28.6.13 the I2C slave While in Sleep mode, module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 28.6.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 28.6.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit of the SSPxSTAT register is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLIF and reset the I2C port to its Idle state (Figure 28-32). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPxSTAT register, or the bus is Idle and the S and P bits are cleared. FIGURE 28-32: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF 2013-2015 Microchip Technology Inc. DS40001729C-page 311 PIC16(L)F1705/9 28.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 28-33). SCL is sampled low before SDA is asserted low (Figure 28-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 28-35). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: • the Start condition is aborted, • the BCLIF flag is set and • the MSSP module is reset to its Idle state (Figure 28-33). The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 28-33: The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSP module reset into Idle state. SEN BCLIF SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared by software S SSPIF SSPIF and BCLIF are cleared by software DS40001729C-page 312 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 28-34: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF. BCLIF Interrupt cleared by software S ’0’ ’0’ SSPIF ’0’ ’0’ FIGURE 28-35: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPIF TBRG SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time-out SEN BCLIF Set SEN, enable Start sequence if SDA = 1, SCL = 1 ’0’ S SSPIF SDA = 0, SCL = 1, set SSPIF 2013-2015 Microchip Technology Inc. Interrupts cleared by software DS40001729C-page 313 PIC16(L)F1705/9 28.6.13.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 28-36). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level (Case 1). SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’ (Case 2). If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition, see Figure 28-37. When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. FIGURE 28-36: If, at the end of the BRG time-out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared by software S ’0’ SSPIF ’0’ FIGURE 28-37: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLIF SCL goes low before SDA, set BCLIF. Release SDA and SCL. Interrupt cleared by software RSEN S ’0’ SSPIF DS40001729C-page 314 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 28.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 28-38). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 28-39). Bus collision occurs during a Stop condition if: a) b) After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out (Case 1). After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2). FIGURE 28-38: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG TBRG SDA SDA sampled low after TBRG, set BCLIF SDA asserted low SCL PEN BCLIF P ’0’ SSPIF ’0’ FIGURE 28-39: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG TBRG TBRG SDA Assert SDA SCL SCL goes low before SDA goes high, set BCLIF PEN BCLIF P ’0’ SSPIF ’0’ 2013-2015 Microchip Technology Inc. DS40001729C-page 315 PIC16(L)F1705/9 TABLE 28-3: Name SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION Bit 7 Bit 6 ANSELA — ANSELB(1) — ANSELC INTCON Reset Values on Page: Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — ANSA4 — ANSA2 ANSA1 ANSA0 122 — ANSB5 ANSB4 — — — — 128 ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIE2 OSFIE C2IE C1IE — BCL1IE TMR6IE TMR4IE CCP2IE 86 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 PIR2 OSFIF C2IF C1IF — BCL1IF TMR6IF TMR4IF CCP2IF RxyPPS — — — 89 RxyPPS<4:0> 141 SSPCLKPPS — — — SSPCLKPPS<4:0> 139, 140 SSPDATPPS — — — SSPDATPPS<4:0> 139, 140 SSPSSPPS — — — SSPSSPPS<4:0> 139, 140 SSP1ADD ADD<7:0> SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register SSP1CON1 322 274* WCOL SSPOV SSPEN CKP SSP1CON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 320 SSP1CON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 321 SMP CKE D/A P S R/W UA BF 318 — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121 TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 SSP1MSK SSP1STAT TRISA (1) Legend: * Note 1: 2: 3: SSPM<3:0> 319 MSK<7:0> 322 2 — = unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP module in I C mode. Page provides register information. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. DS40001729C-page 316 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 28.7 BAUD RATE GENERATOR The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 28-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Table 28-4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. EQUATION 28-1: FOSC FCLOCK = ------------------------------------------------ SSPxADD + 1 4 Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. An internal signal “Reload” in Figure 28-40 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. FIGURE 28-40: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM<3:0> SSPM<3:0> Reload SSPxADD<7:0> Reload Control SCL SSPCLK BRG Down Counter FOSC/2 Note: Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 28-4: Note: MSSP CLOCK RATE W/BRG FOSC FCY BRG Value FCLOCK (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Refer to the I/O port electrical specifications in Table 32-4 to ensure the system is designed to support IOL requirements. 2013-2015 Microchip Technology Inc. DS40001729C-page 317 PIC16(L)F1705/9 28.8 Register Definitions: MSSP Control REGISTER 28-1: SSP1STAT: SSP STATUS REGISTER R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 R-0/0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-Speed mode (400 kHz) bit 6 CKE: SPI Clock Edge Select bit (SPI mode only) In SPI Master or Slave mode: 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state In I2 C™ mode only: 1 = Enable input logic so that thresholds are compliant with SMBus specification 0 = Disable SMBus specific inputs bit 5 D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode. bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPxADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full Status bit Receive (SPI and I2 C modes): 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Transmit (I2 C mode only): 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPxBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPxBUF is empty DS40001729C-page 318 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 28-2: SSP1CON1: SSP CONTROL REGISTER 1 R/C/HS-0/0 R/C/HS-0/0 R/W-0/0 R/W-0/0 WCOL SSPOV(1) SSPEN CKP R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 SSPM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit(1) In SPI mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register (must be cleared in software). 0 = No overflow 2 In I C mode: 1 = A byte is received while the SSPxBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software). 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins(2) 0 = Disables serial port and configures these pins as I/O port pins In I2C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins(3) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2C Master mode: Unused in this mode bit 3-0 SSPM<3:0>: Synchronous Serial Port Mode Select bits 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1101 = Reserved 1100 = Reserved 1011 = I2C firmware controlled Master mode (slave idle) 1010 = SPI Master mode, clock = FOSC/(4 * (SSPxADD+1))(5) 1001 = Reserved 1000 = I2C Master mode, clock = FOSC / (4 * (SSPxADD+1))(4) 0111 = I2C Slave mode, 10-bit address 0110 = I2C Slave mode, 7-bit address 0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin 0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled 0011 = SPI Master mode, clock = T2_match/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 0000 = SPI Master mode, clock = FOSC/4 Note 1: 2: 3: 4: 5: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, these pins must be properly configured as input or output. Use SSPSSPPS, SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins. When enabled, the SDA and SCL pins must be configured as inputs. Use SSPCLKPPS, SSPDATPPS, and RxyPPS to select the pins. SSPxADD values of 0, 1 or 2 are not supported for I2C mode. SSPxADD value of ‘0’ is not supported. Use SSPM = 0000 instead. 2013-2015 Microchip Technology Inc. DS40001729C-page 319 PIC16(L)F1705/9 SSP1CON2: SSP CONTROL REGISTER 2(1) REGISTER 28-3: R/W-0/0 R-0/0 R/W-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/S/HS-0/0 R/W/HS-0/0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCKMSSP Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Stop condition Idle bit 1 RSEN: Repeated Start Condition Enable bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated Start condition Idle bit 0 SEN: Start Condition Enable/Stretch Enable bit In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Start condition Idle In Slave mode: 1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = Clock stretching is disabled Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the Idle mode, this bit may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). DS40001729C-page 320 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 28-4: SSP1CON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM(3) PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on eighth falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled(2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled(2) bit 4 BOEN: Buffer Overwrite Enable bit In SPI Slave mode:(1) 1 = SSPxBUF updates every time that a new data byte is shifted in ignoring the BF bit 0 = If new byte is received with BF bit of the SSPxSTAT register already set, SSPOV bit of the SSPxCON1 register is set, and the buffer is not updated In I2C Master mode and SPI Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPxBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPxBUF is only updated when SSPOV is clear bit 3 SDAHT: SDA Hold Time Selection bit (I2C mode only) 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If, on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCL1IF bit of the PIR2 register is set, and bus goes idle 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a matching received address byte; CKP bit of the SSPxCON1 register will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the eighth falling edge of SCL for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCL is held low. 0 = Data holding is disabled Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set. 2013-2015 Microchip Technology Inc. DS40001729C-page 321 PIC16(L)F1705/9 REGISTER 28-5: R/W-1/1 SSP1MSK: SSP MASK REGISTER R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1 MSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPxADD<n> to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK<0>: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM<3:0> = 0111 or 1111): 1 = The received address bit 0 is compared to SSPxADD<0> to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 28-6: R/W-0/0 SSP1ADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode – Most Significant Address Byte: bit 7-3 Not used: Unused for Most Significant Address Byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 ADD<2:1>: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. 10-Bit Slave mode – Least Significant Address Byte: bit 7-0 ADD<7:0>: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD<7:1>: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”. DS40001729C-page 322 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 29.0 • • • • • • • • • Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in synchronous modes • Sleep operation ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: • Automatic detection and calibration of the baud rate • Wake-up on Break reception • 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 29-1 and Figure 29-2. The EUSART transmit output (TX_out) is available to the TX/CK pin and internally to the following peripherals: The EUSART module includes the following capabilities: • Configurable Logic Cell (CLC) • Full-duplex asynchronous transmit and receive FIGURE 29-1: EUSART TRANSMIT BLOCK DIAGRAM Data Bus TXIE Interrupt TXIF TXREG Register 8 MSb LSb (8) 0 • • • TX/CK pin Pin Buffer and Control Transmit Shift Register (TSR) TX_out TXEN TRMT Baud Rate Generator FOSC ÷n +1 SPBRGH TX9 n BRG16 SPBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 2013-2015 Microchip Technology Inc. TX9D DS40001729C-page 323 PIC16(L)F1705/9 FIGURE 29-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 SPBRGH SPBRGL Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR (8) ••• 7 1 LSb 0 Start RX9 ÷n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) • Baud Rate Control (BAUDCON) These registers are detailed in Register 29-1, Register 29-2 and Register 29-3, respectively. The RX and CK input pins are selected with the RXPPS and CKPPS registers, respectively. TX, CK, and DT output pins are selected with each pin’s RxyPPS register. Since the RX input is coupled with the DT output in Synchronous mode, it is the user’s responsibility to select the same pin for both of these functions when operating in Synchronous mode. The EUSART control logic will control the data direction drivers automatically. DS40001729C-page 324 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 29.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a ‘1’ data bit, and a VOL Space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 29-5 for examples of baud rate configurations. 29.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXREG until the Stop bit of the previous character has been transmitted. The pending character in the TXREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXREG. 29.1.1.3 Transmit Data Polarity The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. The polarity of the transmit data can be controlled with the SCKP bit of the BAUDCON register. The default state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the SCKP bit to ‘1’ will invert the transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous mode only. In Synchronous mode, the SCKP bit has a different function. See Section 29.5.1.2 “Clock Polarity”. 29.1.1 29.1.1.4 EUSART ASYNCHRONOUS TRANSMITTER The EUSART transmitter block diagram is shown in Figure 29-1. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXREG register. 29.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: • TXEN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the TXEN bit of the TXSTA register enables the transmitter circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART and automatically configures the TX/CK I/O pin as an output. If the TX/CK pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Note: Transmit Interrupt Flag The TXIF interrupt flag bit of the PIR1 register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXREG. In other words, the TXIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXREG. The TXIF flag bit is not cleared immediately upon writing TXREG. TXIF becomes valid in the second instruction cycle following the write execution. Polling TXIF immediately following the TXREG write will return invalid results. The TXIF bit is read-only, it cannot be set or cleared by software. The TXIF interrupt can be enabled by setting the TXIE interrupt enable bit of the PIE1 register. However, the TXIF flag bit will be set whenever the TXREG is empty, regardless of the state of TXIE enable bit. To use interrupts when transmitting data, set the TXIE bit only when there is more data to send. Clear the TXIE interrupt enable bit upon writing the last character of the transmission to the TXREG. The TXIF Transmitter Interrupt flag is set when the TXEN enable bit is set. 2013-2015 Microchip Technology Inc. DS40001729C-page 325 PIC16(L)F1705/9 29.1.1.5 TSR Status 29.1.1.7 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user has to poll this bit to determine the TSR status. Note: 29.1.1.6 1. 2. 3. The TSR register is not mapped in data memory, so it is not available to the user. Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXSTA register is set, the EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXSTA register is the ninth, and Most Significant data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXREG is written. A special 9-bit Address mode is available for use with multiple receivers. See Section 29.1.2.7 “Address Detection” for more information on the Address mode. FIGURE 29-3: Write to TXREG BRG Output (Shift Clock) TX/CK pin TXIF bit (Transmit Buffer Reg. Empty Flag) TRMT bit (Transmit Shift Reg. Empty Flag) DS40001729C-page 326 4. 5. 6. 7. 8. Asynchronous Transmission Set-up: Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 29.4 “EUSART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. Set SCKP bit if inverted transmit is desired. Enable the transmission by setting the TXEN control bit. This will cause the TXIF interrupt bit to be set. If interrupts are desired, set the TXIE interrupt enable bit of the PIE1 register. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. Load 8-bit data into the TXREG register. This will start the transmission. ASYNCHRONOUS TRANSMISSION Word 1 Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY Word 1 Transmit Shift Reg. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 29-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 2 Word 1 BRG Output (Shift Clock) TX/CK pin Start bit bit 0 bit 1 Word 1 1 TCY TXIF bit (Transmit Buffer Reg. Empty Flag) bit 7/8 Stop bit Start bit Word 2 bit 0 1 TCY Word 1 Transmit Shift Reg. TRMT bit (Transmit Shift Reg. Empty Flag) Word 2 Transmit Shift Reg. This timing diagram shows two consecutive transmissions. Note: TABLE 29-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSA4 — ANSA2 ANSA1 ANSA0 122 — ANSB5 ANSB4 — — — — 128 ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 335 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 334 RxyPPS — — — Name Bit 7 Bit 6 ANSELA — ANSELB(1) — ANSELC BAUD1CON INTCON RxyPPS<4:0> 141 SP1BRGL BRG<7:0> 336* SP1BRGH BRG<15:8> 336* — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 SYNC SENDB BRGH TRMT TX9D TRISA (2) TX1REG TX1STA Legend: * Note 1: 2: 3: EUSART Transmit Data Register CSRC TX9 TXEN 121 325* 333 — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous transmission. Page provides register information. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001729C-page 327 PIC16(L)F1705/9 29.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode is typically used in RS-232 systems. The receiver block diagram is shown in Figure 29-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. 29.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: • CREN = 1 • SYNC = 0 • SPEN = 1 All other EUSART control bits are assumed to be in their default state. Setting the CREN bit of the RCSTA register enables the receiver circuitry of the EUSART. Clearing the SYNC bit of the TXSTA register configures the EUSART for asynchronous operation. Setting the SPEN bit of the RCSTA register enables the EUSART. The programmer must set the corresponding TRIS bit to configure the RX/DT I/O pin as an input. Note: If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. 29.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘1’. If the data recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See Section 29.1.2.4 “Receive Framing Error” for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCIF interrupt flag bit of the PIR1 register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCREG register. Note: 29.1.2.3 If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See Section 29.1.2.5 “Receive Overrun Error” for more information on overrun errors. Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCIF interrupts are enabled by setting all of the following bits: • RCIE, Interrupt Enable bit of the PIE1 register • PEIE, Peripheral Interrupt Enable bit of the INTCON register • GIE, Global Interrupt Enable bit of the INTCON register The RCIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. DS40001729C-page 328 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 29.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCSTA register which resets the EUSART. Clearing the CREN bit of the RCSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Note: 29.1.2.5 29.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. If all receive characters in the receive FIFO have framing errors, repeated reads of the RCREG will not clear the FERR bit. Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register. 29.1.2.6 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG. 2013-2015 Microchip Technology Inc. DS40001729C-page 329 PIC16(L)F1705/9 29.1.2.8 Asynchronous Reception Set-up 29.1.2.9 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 29.4 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. If 9-bit reception is desired, set the RX9 bit. 6. Enable reception by setting the CREN bit. 7. The RCIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 8. Read the RCSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. 10. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. FIGURE 29-5: Rcv Shift Reg Rcv Buffer Reg. RCIDL This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 29.4 “EUSART Baud Rate Generator (BRG)”). 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 4. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 5. Enable 9-bit reception by setting the RX9 bit. 6. Enable address detection by setting the ADDEN bit. 7. Enable reception by setting the CREN bit. 8. The RCIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCIE interrupt enable bit was also set. 9. Read the RCSTA register to get the error flags. The ninth data bit will always be set. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCREG register. Software determines if this is the device’s address. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 12. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. ASYNCHRONOUS RECEPTION Start bit bit 0 RX/DT pin 9-bit Address Detection Mode Set-up bit 1 bit 7/8 Stop bit Start bit Word 1 RCREG bit 0 bit 7/8 Stop bit Start bit bit 7/8 Stop bit Word 2 RCREG Read Rcv Buffer Reg. RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS40001729C-page 330 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 29-2: Name SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 ANSELA — ANSELB(1) — ANSELC BAUD1CON Register on Page Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — ANSA4 — ANSA2 ANSA1 ANSA0 122 — ANSB5 ANSB4 — — — — 128 ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 335 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 RC1STA SPEN RX9 SREN OERR RX9D RxyPPS — — — INTCON RC1REG EUSART Receive Data Register SP1BRGL TRISB(1) TRISC TX1STA Legend: * Note 1: 2: 3: ADDEN 328* FERR RxyPPS<4:0> 334 141 BRG<7:0> SP1BRGH TRISA CREN 336 BRG<15:8> 336 — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121 TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 TXEN SYNC SENDB BRGH TRMT TX9D 333 (1) TRISC7 CSRC (1) TRISC6 TX9 — = unimplemented location, read as ‘0’. Shaded cells are not used for asynchronous reception. Page provides register information. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001729C-page 331 PIC16(L)F1705/9 29.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. See Section 6.2.2.3 “Internal Oscillator Frequency Adjustment” for more information. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see Section 29.4.1 “Auto-Baud Detect”). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. DS40001729C-page 332 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 29.3 Register Definitions: EUSART Control REGISTER 29-1: R/W-/0 TX1STA: TRANSMIT STATUS AND CONTROL REGISTER R/W-0/0 CSRC TX9 R/W-0/0 TXEN (1) R/W-0/0 R/W-0/0 R/W-0/0 R-1/1 R/W-0/0 SYNC SENDB BRGH TRMT TX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CSRC: Clock Source Select bit Asynchronous mode: Don’t care Synchronous mode: 1 = Master mode (clock generated internally from BRG) 0 = Slave mode (clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN: Transmit Enable bit(1) 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: EUSART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 SENDB: Send Break Character bit Asynchronous mode: 1 = Send Sync Break on next transmission (cleared by hardware upon completion) 0 = Sync Break transmission completed Synchronous mode: Don’t care bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Sync mode. 2013-2015 Microchip Technology Inc. DS40001729C-page 333 PIC16(L)F1705/9 REGISTER 29-2: RC1STA: RECEIVE STATUS AND CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R-0/0 R-0/0 R-0/0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled 0 = Serial port disabled (held in Reset) bit 6 RX9: 9-Bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode – Master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode – Slave Don’t care bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables receiver 0 = Disables receiver Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1): 1 = Enables address detection, enable interrupt and load the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received and ninth bit can be used as parity bit Asynchronous mode 8-bit (RX9 = 0): Don’t care bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: Ninth bit of Received Data This can be address/data bit or a parity bit and must be calculated by user firmware. DS40001729C-page 334 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 REGISTER 29-3: BAUD1CON: BAUD RATE CONTROL REGISTER R-0/0 R-1/1 U-0 R/W-0/0 R/W-0/0 U-0 R/W-0/0 R/W-0/0 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 RCIDL: Receive Idle Flag bit Asynchronous mode: 1 = Receiver is Idle 0 = Start bit has been received and the receiver is receiving Synchronous mode: Don’t care bit 5 Unimplemented: Read as ‘0’ bit 4 SCKP: Synchronous Clock Polarity Select bit Asynchronous mode: 1 = Transmit inverted data to the TX/CK pin 0 = Transmit non-inverted data to the TX/CK pin Synchronous mode: 1 = Data is clocked on rising edge of the clock 0 = Data is clocked on falling edge of the clock bit 3 BRG16: 16-bit Baud Rate Generator bit 1 = 16-bit Baud Rate Generator is used 0 = 8-bit Baud Rate Generator is used bit 2 Unimplemented: Read as ‘0’ bit 1 WUE: Wake-up Enable bit Asynchronous mode: 1 = Receiver is waiting for a falling edge. No character will be received, byte RCIF will be set. WUE will automatically clear after RCIF is set. 0 = Receiver is operating normally Synchronous mode: Don’t care bit 0 ABDEN: Auto-Baud Detect Enable bit Asynchronous mode: 1 = Auto-Baud Detect mode is enabled (clears when auto-baud is complete) 0 = Auto-Baud Detect mode is disabled Synchronous mode: Don’t care 2013-2015 Microchip Technology Inc. DS40001729C-page 335 PIC16(L)F1705/9 29.4 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. The SPBRGH, SPBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXSTA register and the BRG16 bit of the BAUDCON register. In Synchronous mode, the BRGH bit is ignored. Table 29-3 contains the formulas for determining the baud rate. Example 29-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in Table 29-5. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. EXAMPLE 29-1: CALCULATING BAUD RATE ERROR For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: F OS C Desired Baud Rate = -----------------------------------------------------------------------64 [SPBRGH:SPBRGL] + 1 Solving for SPBRGH:SPBRGL: FOSC --------------------------------------------Desired Baud Rate X = --------------------------------------------- – 1 64 16000000 -----------------------9600 = ------------------------ – 1 64 = 25.042 = 25 16000000 Calculated Baud Rate = --------------------------64 25 + 1 = 9615 Calc. Baud Rate – Desired Baud Rate Error = -------------------------------------------------------------------------------------------Desired Baud Rate 9615 – 9600 = ---------------------------------- = 0.16% 9600 Writing a new value to the SPBRGH, SPBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock. DS40001729C-page 336 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 29-3: BAUD RATE FORMULAS Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 1 Legend: FOSC/[16 (n+1)] FOSC/[4 (n+1)] x = Don’t care, n = value of SPBRGH, SPBRGL register pair. TABLE 29-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH THE BAUD RATE GENERATOR Bit 7 BAUD1CON ABDOVF RC1STA SPEN Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page RCIDL — SCKP BRG16 — WUE ABDEN 335 RX9 SREN CREN ADDEN FERR OERR RX9D 334 SP1BRGL BRG<7:0> 336 SP1BRGH BRG<15:8> 336 TX1STA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 333 Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for the Baud Rate Generator. * Page provides register information. 2013-2015 Microchip Technology Inc. DS40001729C-page 337 PIC16(L)F1705/9 TABLE 29-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 1.000 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — 10417 10417 0.00 11 10417 0.00 5 — — — — — — 19.2k — — — — — — 19.20k 0.00 2 — — — 57.6k — — — — — — 57.60k 0.00 0 — — — 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 32.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 20.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 DS40001729C-page 338 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 29-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 — 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz Actual Rate FOSC = 20.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 18.432 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 11.0592 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — — — 115.2k 0.00 1 — — — 2013-2015 Microchip Technology Inc. DS40001729C-page 339 PIC16(L)F1705/9 TABLE 29-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 1200 300.0 1200 0.00 0.00 26666 6666 300.0 1200 0.00 -0.01 16665 4166 300.0 1200 0.00 0.00 15359 3839 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz Actual Rate FOSC = 4.000 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 3.6864 MHz % Error SPBRG value (decimal) Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 832 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — — DS40001729C-page 340 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 29.4.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. and SPBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note 1: If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see Section 29.4.3 “Auto-Wake-up on Break”). In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDCON register starts the auto-baud calibration sequence. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPBRG begins counting up using the BRG counter clock as shown in Figure 29-6. The fifth rising edge will occur on the RX pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPBRGH, SPBRGL register pair, the ABDEN bit is automatically cleared and the RCIF interrupt flag is set. The value in the RCREG needs to be read to clear the RCIF interrupt. RCREG content should be discarded. When calibrating for modes that do not use the SPBRGH register the user can verify that the SPBRGL register did not overflow by checking for 00h in the SPBRGH register. 2: It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. 3: During the auto-baud process, the auto-baud counter starts counting at one. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPBRGH:SPBRGL register pair. TABLE 29-6: The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 29-6. During ABD, both the SPBRGH and SPBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPBRGH FIGURE 29-6: BRG16 BRGH BRG Base Clock BRG ABD Clock 0 0 FOSC/64 FOSC/512 0 1 FOSC/16 FOSC/128 1 0 FOSC/16 FOSC/128 1 1 FOSC/4 FOSC/32 Note: During the ABD sequence, SPBRGL and SPBRGH registers are both used as a 16-bit counter, independent of the BRG16 setting. AUTOMATIC BAUD RATE CALIBRATION XXXXh BRG Value BRG COUNTER CLOCK RATES 0000h RX pin 001Ch Start Edge #1 bit 1 bit 0 Edge #2 bit 3 bit 2 Edge #3 bit 5 bit 4 Edge #4 bit 7 bit 6 Edge #5 Stop bit BRG Clock Auto Cleared Set by User ABDEN bit RCIDL RCIF bit (Interrupt) Read RCREG SPBRGL XXh 1Ch SPBRGH XXh 00h Note 1: The ABD sequence requires the EUSART module to be configured in Asynchronous mode. 2013-2015 Microchip Technology Inc. DS40001729C-page 341 PIC16(L)F1705/9 29.4.2 AUTO-BAUD OVERFLOW 29.4.3.1 Special Considerations During the course of auto-baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. The Overflow condition will set the RCIF flag. The counter continues to count until the fifth rising edge is detected on the RX pin. The RCIDL bit will remain false (‘0’) until the fifth rising edge at which time the RCIDL bit will be set. If the RCREG is read after the overflow occurs but before the fifth rising edge, then the fifth rising edge will set the RCIF again. Break Character Terminating the auto-baud process early to clear an Overflow condition will prevent proper detection of the Sync character fifth rising edge. If any falling edges of the Sync character have not yet occurred when the ABDEN bit is cleared, then those will be falsely detected as Start bits. The following steps are recommended to clear the Overflow condition: Therefore, the initial character in the transmission must be all ‘0’s. This must be ten or more bit times, 13-bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. 1. 2. 3. Read RCREG to clear RCIF. If RCIDL is zero, then wait for RCIF and repeat step 1. Clear the ABDOVF bit. 29.4.3 AUTO-WAKE-UP ON BREAK During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. The EUSART module generates an RCIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes (Figure 29-7), and asynchronously if the device is in Sleep mode (Figure 29-8). The interrupt condition is cleared by reading the RCREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. DS40001729C-page 342 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 29-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set. FIGURE 29-8: AUTO-WAKE-UP BIT (WUE) TIMINGS DURING SLEEP Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 OSC1 Auto Cleared Bit Set by User WUE bit RX/DT Line Note 1 RCIF Sleep Command Executed Note 1: 2: Sleep Ends Cleared due to User Read of RCREG If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal is still active. This sequence should not depend on the presence of Q clocks. The EUSART remains in Idle while the WUE bit is set. 2013-2015 Microchip Technology Inc. DS40001729C-page 343 PIC16(L)F1705/9 29.4.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXSTA register indicates when the transmit operation is active or idle, just as it does during normal transmission. See Figure 29-9 for the timing of the Break character sequence. 29.4.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. 4. 5. 29.4.5 RECEIVING A BREAK CHARACTER The Enhanced EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCSTA register and the received data as indicated by RCREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when; • RCIF bit is set • FERR bit is set • RCREG = 00h The second method uses the Auto-Wake-up feature described in Section 29.4.3 “Auto-Wake-up on Break”. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDCON register before placing the EUSART in Sleep mode. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXREG with a dummy character to initiate transmission (the value is ignored). Write ‘55h’ to TXREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXREG becomes empty, as indicated by the TXIF, the next data byte can be written to TXREG. FIGURE 29-9: Write to TXREG SEND BREAK CHARACTER SEQUENCE Dummy Write BRG Output (Shift Clock) TX (pin) Start bit bit 0 bit 1 bit 11 Stop bit Break TXIF bit (Transmit Interrupt Flag) TRMT bit (Transmit Shift Empty Flag) SENDB (send Break control bit) DS40001729C-page 344 SENDB Sampled Here Auto Cleared 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 29.5 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 29.5.1 SYNCHRONOUS MASTER MODE Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 29.5.1.3 Data is transferred out of the device on the RX/DT pin. The RX/DT and TX/CK pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note: The TSR register is not mapped in data memory, so it is not available to the user. 29.5.1.4 Synchronous Master Transmission Set-up: The following bits are used to configure the EUSART for synchronous master operation: • • • • • SYNC = 1 CSRC = 1 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Setting the CSRC bit of the TXSTA register configures the device as a master. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 29.5.1.1 29.5.1.2 1. 2. 3. 4. 5. 6. Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TX/CK pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. Synchronous Master Transmission 7. 8. Initialize the SPBRGH, SPBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 29.4 “EUSART Baud Rate Generator (BRG)”). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit. If 9-bit transmission is desired, set the TX9 bit. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. Start transmission by loading data to the TXREG register. Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. 2013-2015 Microchip Technology Inc. DS40001729C-page 345 PIC16(L)F1705/9 FIGURE 29-10: SYNCHRONOUS TRANSMISSION RX/DT pin bit 0 bit 1 Word 1 bit 2 bit 7 bit 0 bit 1 Word 2 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to TXREG Reg Write Word 1 Write Word 2 TXIF bit (Interrupt Flag) TRMT bit TXEN bit Note: ‘1’ ‘1’ Sync Master mode, SPBRGL = 0, continuous transmission of two 8-bit words. FIGURE 29-11: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RX/DT pin bit 0 bit 1 bit 2 bit 6 bit 7 TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit DS40001729C-page 346 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 29-7: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 ANSELA — ANSELB(1) — ANSELC BAUD1CON Register on Page Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — ANSA4 — ANSA2 ANSA1 ANSA0 122 — ANSB5 ANSB4 — — — — 128 ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 335 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 334 RxyPPS — — — INTCON RxyPPS<4:0> SP1BRGL BRG<7:0> SP1BRGH BRG<15:8> TRISA TRISB(1) TRISC — — Legend: * Note 1: 2: 3: TRISA4 336 336 —(3) TRISA2 TRISA1 TRISA0 121 TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 TRMT TX9D TX1REG TX1STA TRISA5 141 EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB 325* BRGH 333 — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master transmission. Page provides register information. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001729C-page 347 PIC16(L)F1705/9 29.5.1.5 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RX/DT pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCREG. The RCIF bit remains set as long as there are unread characters in the receive FIFO. Note: 29.5.1.6 If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TX/CK pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Note: If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared. DS40001729C-page 348 29.5.1.7 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCREG is read to access the FIFO. When this happens the OERR bit of the RCSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. 29.5.1.8 Receiving 9-bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCREG. 29.5.1.9 Synchronous Master Reception Set-up: 1. Initialize the SPBRGH, SPBRGL register pair for the appropriate baud rate. Set or clear the BRGH and BRG16 bits, as required, to achieve the desired baud rate. 2. Clear the ANSEL bit for the RX pin (if applicable). 3. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 4. Ensure bits CREN and SREN are clear. 5. If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set bit RX9. 7. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 8. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 9. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. Read the 8-bit received data by reading the RCREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 29-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TX/CK pin (SCKP = 0) TX/CK pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RCREG Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0. Note: TABLE 29-8: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 Bit 6 ANSELA — ANSELB(1) — ANSELC BAUD1CON Register on Page Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — ANSA4 — ANSA2 ANSA1 ANSA0 122 — ANSB5 ANSB4 — — — — 128 ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133 SCKP BRG16 — WUE ABDEN 335 ABDOVF RCIDL — CKPPS — — — INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 RC1STA SPEN RX9 SREN OERR RX9D RXPPS — — — RXPPS<4:0> 139, 140 RxyPPS — — — RxyPPS<4:0> 141 RC1REG CKPPS<4:0> EUSART Receive Data Register CREN ADDEN SP1BRGL BRG<7:0> SP1BRGH BRG<15:8> TRISA (1) 139, 140 — — TRISA5 TRISA4 328* FERR 334 336* 336* —(3) TRISA2 TRISA1 TRISA0 121 TRISB TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 333 TX1STA Legend: * Note 1: 2: 3: — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous master reception. Page provides register information. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001729C-page 349 PIC16(L)F1705/9 29.5.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave. Clearing the SREN and CREN bits of the RCSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. Setting the SPEN bit of the RCSTA register enables the EUSART. 29.5.2.1 29.5.2.2 1. 2. 3. 4. 5. 6. 7. 8. Synchronous Slave Transmission Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for the CK pin (if applicable). Clear the CREN and SREN bits. If interrupts are desired, set the TXIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit transmission is desired, set the TX9 bit. Enable transmission by setting the TXEN bit. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. Start transmission by writing the Least Significant eight bits to the TXREG register. EUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave modes are identical (see Section 29.5.1.3 “Synchronous Master Transmission”), except in the case of the Sleep mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. 4. 5. The first character will immediately transfer to the TSR register and transmit. The second word will remain in the TXREG register. The TXIF bit will not be set. After the first character has been shifted out of TSR, the TXREG register will transfer the second character to the TSR and the TXIF bit will now be set. If the PEIE and TXIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. DS40001729C-page 350 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 29-9: Name SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Bit 7 Bit 6 ANSELA — ANSELB(1) — ANSELC BAUD1CON CKPPS INTCON Register on Page Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — ANSA4 — ANSA2 ANSA1 ANSA0 122 — ANSB5 ANSB4 — — — — 128 ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133 ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN — — — CKPPS<4:0> 335 139, 140 GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 88 RC1STA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 334 RXPPS — — — RXPPS<4:0> 139, 140 RxyPPS — — — RxyPPS<4:0> 141 TRISA TRISB(1) TRISC — — TRISA5 TRISA4 —(3) TRISA2 TRISA1 TRISA0 121 TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 TX1REG TX1STA Legend: * Note 1: 2: 3: EUSART Transmit Data Register CSRC TX9 TXEN SYNC SENDB 325* BRGH TRMT TX9D 333 — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave transmission. Page provides register information. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. 2013-2015 Microchip Technology Inc. DS40001729C-page 351 PIC16(L)F1705/9 29.5.2.3 EUSART Synchronous Slave Reception 29.5.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 29.5.1.5 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never idle • SREN bit, which is a “don’t care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCREG register. If the RCIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 4. 5. 6. 7. 8. 9. Synchronous Slave Reception Set-up: Set the SYNC and SPEN bits and clear the CSRC bit. Clear the ANSEL bit for both the CK and DT pins (if applicable). If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCIF bit will be set when reception is complete. An interrupt will be generated if the RCIE bit was set. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCSTA register. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCSTA register or by clearing the SPEN bit which resets the EUSART. TABLE 29-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name ANSELA (1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — — ANSA4 — ANSA2 ANSA1 ANSA0 122 ANSELB — — ANSB5 ANSB4 — — — — 128 ANSELC ANSC7(1) ANSC6(1) ANSC5(2) ANSC4(2) ANSC3 ANSC2 ANSC1 ANSC0 133 BAUD1CON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 335 CKPPS — — — INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 84 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 85 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF RC1REG CKPPS<4:0> EUSART Receive Data Register RC1STA SPEN RX9 SREN RXPPS — — — TRISA — — TRISA5 TRISB(1) TRISC TX1STA Legend: * Note 1: 2: 3: 139, 140 CREN ADDEN FERR OERR RX9D RXPPS<4:0> TRISA4 —(3) 88 328* TRISA2 334 139, 140 TRISA1 TRISA0 121 TRISB7 TRISB6 TRISB5 TRISB4 — — — — 127 TRISC7(1) TRISC6(1) TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 132 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 333 — = unimplemented location, read as ‘0’. Shaded cells are not used for synchronous slave reception. Page provides register information. PIC16(L)F1709 only. PIC16(L)F1705 only. Unimplemented, read as ‘1’. DS40001729C-page 352 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 29.6 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 29.6.1 SYNCHRONOUS RECEIVE DURING SLEEP To receive during Sleep, all the following conditions must be met before entering Sleep mode: • RCSTA and TXSTA Control registers must be configured for Synchronous Slave Reception (see Section 29.5.2.4 “Synchronous Slave Reception Set-up:”). • If interrupts are desired, set the RCIE bit of the PIE1 register and the GIE and PEIE bits of the INTCON register. • The RCIF interrupt flag must be cleared by reading RCREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RX/DT and TX/CK pins, respectively. When the data word has been completely clocked in by the external device, the RCIF interrupt flag bit of the PIR1 register will be set. Thereby, waking the processor from Sleep. 29.6.2 SYNCHRONOUS TRANSMIT DURING SLEEP To transmit during Sleep, all the following conditions must be met before entering Sleep mode: • The RCSTA and TXSTA Control registers must be configured for synchronous slave transmission (see Section 29.5.2.2 “Synchronous Slave Transmission Set-up:”). • The TXIF interrupt flag must be cleared by writing the output data to the TXREG, thereby filling the TSR and transmit buffer. • If interrupts are desired, set the TXIE bit of the PIE1 register and the PEIE bit of the INTCON register. • Interrupt enable bits TXIE of the PIE1 register and PEIE of the INTCON register must set. Upon entering Sleep mode, the device will be ready to accept clocks on TX/CK pin and transmit data on the RX/DT pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXREG will transfer to the TSR and the TXIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXREG is available to accept another character for transmission, which will clear the TXIF flag. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. 2013-2015 Microchip Technology Inc. DS40001729C-page 353 PIC16(L)F1705/9 30.0 IN-CIRCUIT SERIAL PROGRAMMING™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • ICSPCLK • ICSPDAT • MCLR/VPP • VDD • VSS In Program/Verify mode the program memory, user IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “PIC16(L)F170X Memory Programming Specification” (DS40001683). 30.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 30.2 Low-Voltage Programming Entry Mode The Low-Voltage Programming Entry mode allows the PIC® Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. 30.3 Common Programming Interfaces Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 30-1. FIGURE 30-1: VDD ICD RJ-11 STYLE CONNECTOR INTERFACE ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VPP/MCLR VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 30-2. For additional interface recommendations, refer to your specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 30-3 for more information. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See Section 5.5 “MCLR” for more information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. DS40001729C-page 354 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 30-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE Pin 1 Indicator Pin Description* 1 = VPP/MCLR 1 2 3 4 5 6 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect * FIGURE 30-3: The 6-pin header (0.100" spacing) accepts 0.025" square pins. TYPICAL CONNECTION FOR ICSP™ PROGRAMMING External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). 2013-2015 Microchip Technology Inc. DS40001729C-page 355 PIC16(L)F1705/9 31.0 INSTRUCTION SET SUMMARY 31.1 Read-Modify-Write Operations • Byte Oriented • Bit Oriented • Literal and Control Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. The literal and control category contains the most varied instruction word format. TABLE 31-1: Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories. Table 31-3 lists the instructions recognized by the MPASMTM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: • Subroutine takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) • Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) • One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of four oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. OPCODE FIELD DESCRIPTIONS Field f Description Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. n FSR or INDF number. (0-1) mm Pre-post increment-decrement mode selection TABLE 31-2: ABBREVIATION DESCRIPTIONS Field Program Counter TO Time-Out bit C DC Z PD DS40001729C-page 356 Description PC Carry bit Digit Carry bit Zero bit Power-Down bit 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 31-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) 0 d = 0 for destination W d = 1 for destination f f = 7-bit file register address Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) 0 b = 3-bit bit address f = 7-bit file register address Literal and control operations General 13 OPCODE 8 7 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 10 OPCODE 0 k (literal) k = 11-bit immediate value MOVLP instruction only 13 OPCODE 7 6 0 k (literal) k = 7-bit immediate value MOVLB instruction only 13 OPCODE 5 4 0 k (literal) k = 5-bit immediate value BRA instruction only 13 OPCODE 9 8 0 k (literal) k = 9-bit immediate value FSR Offset instructions 13 OPCODE 7 6 n 5 0 k (literal) n = appropriate FSR k = 6-bit immediate value FSR Increment instructions 13 OPCODE 3 2 1 0 n m (mode) n = appropriate FSR m = 2-bit mode value OPCODE only 13 0 OPCODE 2013-2015 Microchip Technology Inc. DS40001729C-page 357 PIC16(L)F1705/9 TABLE 31-3: PIC16(L)F1705/9 INSTRUCTION SET 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ADDWFC ANDWF ASRF LSLF LSRF CLRF CLRW COMF DECF INCF IORWF MOVF MOVWF RLF RRF SUBWF SUBWFB SWAPF XORWF f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d Add W and f Add with Carry W and f AND W with f Arithmetic Right Shift Logical Left Shift Logical Right Shift Clear f Clear W Complement f Decrement f Increment f Inclusive OR W with f Move f Move W to f Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Subtract with Borrow W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z C, DC, Z Z C, Z C, Z C, Z Z Z Z Z Z Z Z C C C, DC, Z C, DC, Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ f, d f, d Decrement f, Skip if 0 Increment f, Skip if 0 BCF BSF f, b f, b Bit Clear f Bit Set f 1(2) 1(2) 00 00 1, 2 1, 2 1011 dfff ffff 1111 dfff ffff BIT-ORIENTED FILE REGISTER OPERATIONS 1 1 01 01 00bb bfff ffff 01bb bfff ffff 2 2 1, 2 1, 2 BIT-ORIENTED SKIP OPERATIONS BTFSC BTFSS f, b f, b Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 (2) 1 (2) 01 01 10bb bfff ffff 11bb bfff ffff 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 LITERAL OPERATIONS ADDLW ANDLW IORLW MOVLB MOVLP MOVLW SUBLW XORLW k k k k k k k k Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. 2: Add literal and W AND literal with W Inclusive OR literal with W Move literal to BSR Move literal to PCLATH Move literal to W Subtract W from literal Exclusive OR literal with W DS40001729C-page 358 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk C, DC, Z Z Z C, DC, Z Z 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 31-3: PIC16(L)F1705/9 INSTRUCTION SET (CONTINUED) 14-Bit Opcode Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes CONTROL OPERATIONS BRA BRW CALL CALLW GOTO RETFIE RETLW RETURN k – k – k k k – Relative Branch Relative Branch with W Call Subroutine Call Subroutine with W Go to address Return from interrupt Return with literal in W Return from Subroutine 2 2 2 2 2 2 2 2 CLRWDT NOP OPTION RESET SLEEP TRIS – – – – – f Clear Watchdog Timer No Operation Load OPTION_REG register with W Software device Reset Go into Standby mode Load TRIS register with W ADDFSR MOVIW n, k n mm MOVWI k[n] n mm Add Literal k to FSRn Move Indirect FSRn to W with pre/post inc/dec modifier, mm Move INDFn to W, Indexed Indirect. Move W to Indirect FSRn with pre/post inc/dec modifier, mm Move W to INDFn, Indexed Indirect. 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 TO, PD 0000 0010 0001 0011 TO, PD 0fff INHERENT OPERATIONS 1 1 1 1 1 1 C-COMPILER OPTIMIZED k[n] Note 1: 2: 3: 1 1 11 00 0001 0nkk kkkk 0000 0001 0nmm Z 2, 3 1 1 11 00 1111 0nkk kkkk Z 0000 0001 1nmm 2 2, 3 1 11 1111 1nkk kkkk 2 If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. See Table in the MOVIW and MOVWI instruction descriptions. 2013-2015 Microchip Technology Inc. DS40001729C-page 359 PIC16(L)F1705/9 31.2 Instruction Descriptions ADDFSR Add Literal to FSRn ANDLW AND literal with W Syntax: [ label ] ADDFSR FSRn, k Syntax: [ label ] ANDLW Operands: -32 k 31 n [ 0, 1] Operands: 0 k 255 Operation: FSR(n) + k FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. k Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are AND’ed with the 8-bit literal ‘k’. The result is placed in the W register. ANDWF AND W with f FSRn is limited to the range 0000h-FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0 k 255 Operation: Status Affected: Syntax: [ label ] ANDWF Operands: 0 f 127 d 0,1 (W) + k (W) Operation: (W) .AND. (f) (destination) C, DC, Z Status Affected: Z Description: The contents of the W register are added to the 8-bit literal ‘k’ and the result is placed in the W register. Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ASRF Arithmetic Right Shift ADDWF Add W and f Syntax: [ label ] ADDWF Operands: 0 f 127 d 0,1 Operation: (W) + (f) (destination) Status Affected: C, DC, Z Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ADDWFC k f,d ADD W and CARRY bit to f Syntax: [ label ] ADDWFC Operands: 0 f 127 d [0,1] Operation: (W) + (f) + (C) dest Syntax: [ label ] ASRF Operands: 0 f 127 d [0,1] f {,d} Operation: (f<7>) dest<7> (f<7:1>) dest<6:0>, (f<0>) C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. register f C f {,d} Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. DS40001729C-page 360 f,d 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 BCF Bit Clear f Syntax: [ label ] BCF BTFSC f,b Bit Test f, Skip if Clear Syntax: [ label ] BTFSC f,b 0 f 127 0b7 Operands: 0 f 127 0b7 Operands: Operation: 0 (f<b>) Operation: skip if (f<b>) = 0 Status Affected: None Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BRA Relative Branch BTFSS Bit Test f, Skip if Set Syntax: [ label ] BRA label [ label ] BRA $+k Syntax: [ label ] BTFSS f,b Operands: 0 f 127 0b<7 Operands: -256 label - PC + 1 255 -256 k 255 Operation: skip if (f<b>) = 1 Operation: (PC) + 1 + k PC Status Affected: None Status Affected: None Description: Description: Add the signed 9-bit literal ‘k’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a 2-cycle instruction. This branch has a limited range. If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a 2-cycle instruction. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W) PC Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a 2-cycle instruction. BSF Bit Set f Syntax: [ label ] BSF Operands: 0 f 127 0b7 f,b Operation: 1 (f<b>) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. 2013-2015 Microchip Technology Inc. DS40001729C-page 361 PIC16(L)F1705/9 CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 k 2047 Operands: None Operation: (PC)+ 1 TOS, k PC<10:0>, (PCLATH<6:3>) PC<14:11> Operation: Status Affected: None 00h WDT 0 WDT prescaler, 1 TO 1 PD Description: Call Subroutine. First, return address (PC + 1) is pushed onto the stack. The 11-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH. CALL is a 2-cycle instruction. Status Affected: TO, PD Description: CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set. CALLW Subroutine Call With W COMF Complement f Syntax: [ label ] CALLW Syntax: [ label ] COMF Operands: None Operands: Operation: (PC) +1 TOS, (W) PC<7:0>, (PCLATH<6:0>) PC<14:8> 0 f 127 d [0,1] Operation: (f) (destination) Status Affected: Z Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DECF Decrement f Syntax: [ label ] DECF f,d Status Affected: None Description: Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC<7:0>, and the contents of PCLATH into PC<14:8>. CALLW is a 2-cycle instruction. CLRF Clear f Syntax: [ label ] CLRF f f,d Operands: 0 f 127 Operands: Operation: 00h (f) 1Z 0 f 127 d [0,1] Operation: (f) - 1 (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are cleared and the Z bit is set. Description: Decrement register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h (W) 1Z Status Affected: Z Description: W register is cleared. Zero bit (Z) is set. DS40001729C-page 362 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, then a NOP is executed instead, making it a 2-cycle instruction. Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. If the result is ‘1’, the next instruction is executed. If the result is ‘0’, a NOP is executed instead, making it a 2-cycle instruction. GOTO Unconditional Branch IORLW Inclusive OR literal with W Syntax: [ label ] Syntax: [ label ] GOTO k INCFSZ f,d IORLW k Operands: 0 k 2047 Operands: 0 k 255 Operation: k PC<10:0> PCLATH<6:3> PC<14:11> Operation: (W) .OR. k (W) Status Affected: Z Status Affected: None Description: Description: GOTO is an unconditional branch. The 11-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. GOTO is a 2-cycle instruction. The contents of the W register are OR’ed with the 8-bit literal ‘k’. The result is placed in the W register. INCF Increment f IORWF Inclusive OR W with f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] INCF f,d Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination) Operation: (W) .OR. (f) (destination) Status Affected: Z Status Affected: Z Description: The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. Description: Inclusive OR the W register with register ‘f’. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. 2013-2015 Microchip Technology Inc. IORWF f,d DS40001729C-page 363 PIC16(L)F1705/9 LSLF Logical Left Shift MOVF f {,d} Move f Syntax: [ label ] LSLF Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 f 127 d [0,1] Operation: (f<7>) C (f<6:0>) dest<7:1> 0 dest<0> Operation: (f) (dest) Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the left through the Carry flag. A ‘0’ is shifted into the LSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. C register f 0 Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status of d. If d = 0, destination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register since status flag Z is affected. Words: 1 Cycles: 1 Example: Logical Right Shift Syntax: [ label ] LSRF Operands: 0 f 127 d [0,1] Operation: 0 dest<7> (f<7:1>) dest<6:0>, (f<0>) C, Status Affected: C, Z Description: The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘0’ is shifted into the MSb. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. DS40001729C-page 364 f {,d} register f MOVF FSR, 0 After Instruction W = value in FSR register Z = 1 LSRF 0 MOVF f,d C 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 MOVIW Move INDFn to W Syntax: [ label ] MOVIW ++FSRn [ label ] MOVIW --FSRn [ label ] MOVIW FSRn++ [ label ] MOVIW FSRn-[ label ] MOVIW k[FSRn] Operands: n [0,1] mm [00,01, 10, 11] -32 k 31 Operation: INDFn W Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) • Unchanged Status Affected: MOVLP Syntax: [ label ] MOVLP k Operands: 0 k 127 Operation: k PCLATH Status Affected: None Description: The 7-bit literal ‘k’ is loaded into the PCLATH register. MOVLW Move literal to W Syntax: [ label ] 0 k 255 Operation: k (W) Status Affected: None Description: The 8-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as ‘0’s. Words: 1 1 Mode Syntax mm Cycles: Preincrement ++FSRn 00 Example: --FSRn 01 Postincrement FSRn++ 10 Postdecrement FSRn-- 11 Description: This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. MOVLB Move literal to BSR Syntax: [ label ] MOVLB k Operands: 0 k 31 Operation: k BSR Status Affected: None Description: The 5-bit literal ‘k’ is loaded into the Bank Select Register (BSR). 2013-2015 Microchip Technology Inc. MOVLW k Operands: Z Predecrement Move literal to PCLATH MOVLW 0x5A After Instruction W = MOVWF Move W to f Syntax: [ label ] MOVWF Operands: 0 f 127 Operation: (W) (f) 0x5A f Status Affected: None Description: Move data from W register to register ‘f’. Words: 1 Cycles: 1 Example: MOVWF OPTION_REG Before Instruction OPTION_REG = 0xFF W = 0x4F After Instruction OPTION_REG = 0x4F W = 0x4F DS40001729C-page 365 PIC16(L)F1705/9 MOVWI Move W to INDFn Syntax: [ label ] MOVWI ++FSRn [ label ] MOVWI --FSRn [ label ] MOVWI FSRn++ [ label ] MOVWI FSRn-[ label ] MOVWI k[FSRn] Operands: Operation: Status Affected: n [0,1] mm [00,01, 10, 11] -32 k 31 W INDFn Effective address is determined by • FSR + 1 (preincrement) • FSR - 1 (predecrement) • FSR + k (relative offset) After the Move, the FSR value will be either: • FSR + 1 (all increments) • FSR - 1 (all decrements) Unchanged None No Operation Syntax: [ label ] Operands: None Operation: No operation Status Affected: None Description: No operation. Words: 1 Cycles: 1 Example: OPTION Load OPTION_REG Register with W Syntax: [ label ] OPTION Operands: None Operation: (W) OPTION_REG Status Affected: None Description: Move data from W register to OPTION_REG register. 1 Syntax Preincrement ++FSRn 00 Predecrement --FSRn 01 Postincrement FSRn++ 10 Words: Postdecrement FSRn-- 11 Cycles: 1 Example: OPTION Before Instruction OPTION_REG = 0xFF W = 0x4F After Instruction OPTION_REG = 0x4F W = 0x4F This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it. Note: The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn. FSRn is limited to the range 0000h-FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around. The increment/decrement operation on FSRn WILL NOT affect any Status bits. DS40001729C-page 366 NOP NOP Mode Description: mm NOP RESET Software Reset Syntax: [ label ] RESET Operands: None Operation: Execute a device Reset. Resets the RI flag of the PCON register. Status Affected: None Description: This instruction provides a way to execute a hardware Reset by software. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 RETFIE Return from Interrupt RETURN Return from Subroutine Syntax: [ label ] Syntax: [ label ] None RETFIE k RETURN Operands: None Operands: Operation: TOS PC, 1 GIE Operation: TOS PC Status Affected: None Status Affected: None Description: Description: Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a 2-cycle instruction. Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = GIE = TOS 1 RETLW Return with literal in W Syntax: [ label ] Operands: 0 k 255 Operation: k (W); TOS PC Status Affected: None Description: The W register is loaded with the 8-bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a 2-cycle instruction. Words: 1 Cycles: 2 Example: TABLE RETLW k RLF Rotate Left f through Carry Syntax: [ label ] Operands: 0 f 127 d [ 0, 1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. RLF C CALL TABLE;W contains table ;offset value • ;W now has table value • • ADDWF PC ;W = offset RETLW k1 ;Begin table RETLW k2 ; • • • RETLW kn ; End of table Before Instruction W = After Instruction W = 2013-2015 Microchip Technology Inc. Words: 1 Cycles: 1 Example: RLF f,d Register f REG1,0 Before Instruction REG1 C After Instruction REG1 W C = = 1110 0110 0 = = = 1110 0110 1100 1100 1 0x07 value of k8 DS40001729C-page 367 PIC16(L)F1705/9 SUBLW Subtract W from literal Syntax: [ label ] RRF Rotate Right f through Carry Syntax: [ label ] Operands: 0 f 127 d [0,1] Operands: 0 k 255 Operation: k - (W) W) Operation: See description below Status Affected: C, DC, Z Status Affected: C Description: Description: The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. The W register is subtracted (2’s complement method) from the 8-bit literal ‘k’. The result is placed in the W register. RRF f,d C Register f SUBLW k C=0 Wk C=1 Wk DC = 0 W<3:0> k<3:0> DC = 1 W<3:0> k<3:0> SLEEP Enter Sleep mode SUBWF Subtract W from f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: (f) - (W) destination) Status Affected: C, DC, Z Description: Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f. SLEEP Operands: None Operation: 00h WDT, 0 WDT prescaler, 1 TO, 0 PD Status Affected: TO, PD Description: The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared. The processor is put into Sleep mode with the oscillator stopped. DS40001729C-page 368 SUBWF f,d C=0 Wf C=1 Wf DC = 0 W<3:0> f<3:0> DC = 1 W<3:0> f<3:0> SUBWFB Subtract W from f with Borrow Syntax: SUBWFB Operands: 0 f 127 d [0,1] Operation: (f) – (W) – (B) dest f {,d} Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 SWAPF Swap Nibbles in f XORLW Exclusive OR literal with W Syntax: [ label ] Syntax: [ label ] Operands: 0 f 127 d [0,1] Operation: SWAPF f,d (f<3:0>) (destination<7:4>), (f<7:4>) (destination<3:0>) Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register are XOR’ed with the 8-bit literal ‘k’. The result is placed in the W register. XORWF TRIS Load TRIS Register with W XORLW k Exclusive OR W with f Syntax: [ label ] Operands: 0 f 127 d [0,1] XORWF f,d (W) .XOR. (f) destination) Syntax: [ label ] TRIS f Operands: 5f7 Operation: Operation: (W) TRIS register ‘f’ Status Affected: Z Status Affected: None Description: Description: Move data from W register to TRIS register. When ‘f’ = 5, TRISA is loaded. When ‘f’ = 6, TRISB is loaded. When ‘f’ = 7, TRISC is loaded. Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 2013-2015 Microchip Technology Inc. DS40001729C-page 369 PIC16(L)F1705/9 32.0 ELECTRICAL SPECIFICATIONS 32.1 Absolute Maximum Ratings(†) Ambient temperature under bias ...................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on pins with respect to VSS on VDD pin PIC16F1705/9 ........................................................................................................... -0.3V to +6.5V PIC16LF1705/9 ......................................................................................................... -0.3V to +4.0V on MCLR pin ........................................................................................................................... -0.3V to +9.0V on all other pins ............................................................................................................ -0.3V to (VDD + 0.3V) Maximum current(1) on VSS pin -40°C TA +85°C, Industrial ............................................................................................. 250 mA +85°C TA +125°C, Extended ............................................................................................ 85 mA on VDD pin -40°C TA +85°C,Industrial .............................................................................................. 250 mA +85°C TA +125°C, Extended ............................................................................................ 85 mA Maximum output current sunk by any I/O pin ................................................................................................................................ 50 mA sourced by any I/O pin .......................................................................................................................... 50 mA sourced by any op amp output pin ...................................................................................................... 100 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) ................................................................................................... 20 mA Total power dissipation(2) ...............................................................................................................................800 mW Note 1: 2: Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Table 32-3 to calculate device specifications. Power dissipation is calculated as follows: PDIS = VDD x {IDD – ΣIOH} + Σ{VDD – VOH) x IOH} + Σ(VOL x IOI). † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. DS40001729C-page 370 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 32.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC16LF1705/9 VDDMIN (Fosc 16 MHz) ......................................................................................................... +1.8V VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.5V VDDMAX .................................................................................................................................... +3.6V PIC16F1705/9 VDDMIN (Fosc 16 MHz) ......................................................................................................... +2.3V VDDMIN (16 MHz) .................................................................................................................. +2.5V VDDMAX .................................................................................................................................... +5.5V TA — Operating Ambient Temperature Range Industrial Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................... +85°C Extended Temperature TA_MIN ...................................................................................................................................... -40°C TA_MAX .................................................................................................................................. +125°C Note 1: See Parameter D001, DS Characteristics: Supply Voltage. 2013-2015 Microchip Technology Inc. DS40001729C-page 371 PIC16(L)F1705/9 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16F1705/9 ONLY FIGURE 32-1: VDD (V) 5.5 2.5 2.3 0 10 4 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 32-7 for each Oscillator mode’s supported frequencies. VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C, PIC16LF1705/9 ONLY VDD (V) FIGURE 32-2: 3.6 2.5 1.8 0 4 10 16 32 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 32-7 for each Oscillator mode’s supported frequencies. DS40001729C-page 372 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 32.3 DC Characteristics TABLE 32-1: SUPPLY VOLTAGE PIC16LF1705/9 Standard Operating Conditions (unless otherwise stated) PIC16F1705/9 Standard Operating Conditions (unless otherwise stated) Param. No. D001 Sym. VDD Characteristic Min. Typ.† Max. Units PIC16LF1705/9 1.8 2.5 — — 3.6 3.6 V V FOSC 16 MHz FOSC 32 MHz (Note 2) PIC16F1705/9 2.3 2.5 — — 5.5 5.5 V V FOSC 16 MHz: FOSC 32 MHz (Note 2) Supply Voltage D001 D002* VDR RAM Data Retention Voltage(1) PIC16LF1705/9 1.5 — — V Device in Sleep mode PIC16F1705/9 1.7 — — V Device in Sleep mode PIC16LF1705/9 — 1.6 — V Device in Sleep mode PIC16F1705/9 — 1.6 — V Device in Sleep mode PIC16LF1705/9 — 0.8 — V PIC16F1705/9 — 1.5 — V 1x gain, 1.024 -4 — +4 % VDD 2.5V, -40°C to +85°C 2x gain, 2.048 -4 — +4 % VDD 2.5V, -40°C to +85°C -5 — +5 % VDD 4.75V, -40°C to +85°C 0.05 — — V/ms D002* D002A* VPOR Conditions Power-on Reset Release Voltage(3) D002A* D002B* VPORR* Power-on Reset Rearm Voltage(3) D002B* D003 VFVR Fixed Voltage Reference Voltage(4) 4x gain, 4.096 D004* SVDD * † Note 1: 2: 3: 4: VDD Rise Rate to ensure internal Power-on Reset signal(2) See Section 5.1 “Power-On Reset (POR)” for details. These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. PLL required for 32 MHz operation. See Figure 32-3: POR and POR Rearm with Slow Rising VDD. Industrial temperature range only. 2013-2015 Microchip Technology Inc. DS40001729C-page 373 PIC16(L)F1705/9 FIGURE 32-3: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(2) Note 1: 2: 3: DS40001729C-page 374 TPOR(3) When NPOR is low, the device is held in Reset. TVLOW 1 s typical. TPOR 2.7 s typical. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 32-2: SUPPLY CURRENT (IDD)(1,2) PIC16LF1705/9 Standard Operating Conditions (unless otherwise stated) PIC16F1705/9 Standard Operating Conditions (unless otherwise stated) Param. No. Device Characteristics LDO Regulator Conditions Min. Typ.† Max. Units Note VDD — 75 — A — High Power mode, normal operation — 15 — A — Sleep, VREGCON<1> = 0 — 0.3 — A — Sleep, VREGCON<1> = 1 D010 — 5.0 12 A 1.8 — 8.0 18 A 3.0 FOSC = 32 kHz, LP Oscillator mode (Note 4), -40°C TA +85°C D010 — 16 26 A 2.3 — 18 32 A 3.0 — 22 35 A 5.0 D009 D012 D012 D014 D014 D015 D015 D017 D017 D019 D019 † Note 1: 2: 3: 4: 5: — 160 240 A 1.8 — 280 380 A 3.0 — 250 320 A 2.3 — 320 420 A 3.0 — 400 500 A 5.0 — 140 180 A 1.8 — 240 300 A 3.0 — 210 280 A 2.3 — 280 350 A 3.0 — 360 420 A 5.0 — 1.9 2.6 mA 3.0 — 2.4 3.0 mA 3.6 — 2 2.6 mA 3.0 — 2.2 2.8 mA 5.0 — 115 170 A 1.8 — 135 200 A 3.0 — 150 200 A 2.3 — 170 220 A 3.0 — 215 280 A 5.0 — 0.7 1.1 mA 1.8 — 1.2 1.8 mA 3.0 — 0.9 1.5 mA 2.3 — 1.3 1.8 mA 3.0 — 1.4 2.0 mA 5.0 FOSC = 32 kHz, LP Oscillator mode (Note 4, Note 5), -40°C TA +85°C FOSC = 4 MHz, XT Oscillator mode FOSC = 4 MHz, XT Oscillator mode (Note 5) FOSC = 4 MHz, External Clock (ECM), Medium-Power mode (Note 3) FOSC = 4 MHz, External Clock (ECM), Medium-Power mode (Note 3) FOSC = 32 MHz, External Clock (ECH), High-Power mode (Note 3, Note 5) FOSC = 32 MHz, External Clock (ECH), High-Power mode (Note 3, Note 5) FOSC = 500 kHz, MFINTOSC mode FOSC = 500 kHz, MFINTOSC mode FOSC = 16 MHz, HFINTOSC mode FOSC = 16 MHz, HFINTOSC mode Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k FVR and BOR are disabled. 8 MHz clock with 4x PLL enabled. 2013-2015 Microchip Technology Inc. DS40001729C-page 375 PIC16(L)F1705/9 TABLE 32-2: SUPPLY CURRENT (IDD)(1,2) (CONTINUED) PIC16LF1705/9 Standard Operating Conditions (unless otherwise stated) PIC16F1705/9 Standard Operating Conditions (unless otherwise stated) Param. No. Device Characteristics D020 D020 D022 D022 † Note 1: 2: 3: 4: 5: Conditions Min. Typ.† Max. Units VDD — 2.3 3.0 mA 3.0 — 2.8 3.5 mA 3.6 — 2.4 3.1 mA 3.0 — 2.6 3.4 mA 5.0 — 2 3.0 mA 3.0 — 2.6 3.5 mA 3.6 — 2.1 3.0 mA 3.0 — 3 3.5 mA 5.0 Note FOSC = 32 MHz, HFINTOSC mode (Note 5) FOSC = 32 MHz, HFINTOSC mode (Note 5) FOSC = 32 MHz, HS Oscillator mode (Note 5) FOSC = 32 MHz, HS Oscillator mode (Note 5) Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. For RC oscillator configurations, current through REXT is not included. The current through the resistor can be extended by the formula IR = VDD/2REXT (mA) with REXT in k FVR and BOR are disabled. 8 MHz clock with 4x PLL enabled. DS40001729C-page 376 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 32-3: POWER-DOWN CURRENTS (IPD)(1,2) PIC16LF1705/9 Standard Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1705/9 Low-Power Sleep Mode, VREGPM = 1 Param. No. Device Characteristics D023 Base IPD D023 Base IPD D023A Base IPD D024 D024 D025 D025 Conditions Min. Typ.† Max. +85°C Max. +125°C Units — 0.05 1.0 8.0 A 1.8 — 0.08 2.0 9.0 A 3.0 — 0.3 3.0 10 A 2.3 — 0.4 4.0 12 A 3.0 — 0.5 6.0 15 A 5.0 — 9.8 16 18 A 2.3 — 10.3 18 20 A 3.0 — 11.5 21 26 A 5.0 WDT, BOR, FVR and SOSC disabled, all Peripherals inactive, Normal-Power Sleep mode VREGPM = 0 — 0.5 6 14 A 1.8 WDT Current — 0.8 7 17 A 3.0 — 0.8 6 15 A 2.3 — 0.9 7 20 A 3.0 — 1.0 8 22 A 5.0 — 15 28 30 A 1.8 — 18 30 33 A 3.0 — 18 33 35 A 2.3 — 19 35 37 A 3.0 Note VDD WDT, BOR, FVR, and SOSC disabled, all Peripherals Inactive WDT, BOR, FVR, and SOSC disabled, all Peripherals Inactive, Low-Power Sleep mode WDT Current FVR Current FVR Current — 20 37 39 A 5.0 D026 — 7.5 25 28 A 3.0 BOR Current D026 — 10 25 28 A 3.0 BOR Current — 12 28 31 A 5.0 D027 — 0.5 4 10 A 3.0 LPBOR Current D027 — 0.8 6 14 A 3.0 LPBOR Current — 1 8 17 A 5.0 — 0.5 5 9 A 1.8 — 0.8 8.5 12 A 3.0 — 1.1 6 10 A 2.3 — 1.3 8.5 20 A 3.0 — 1.4 10 25 A 5.0 — 0.05 2 9 A 1.8 — 0.08 3 10 A 3.0 — 0.3 4 12 A 2.3 — 0.4 5 13 A 3.0 — 0.5 7 16 A 5.0 D028 D028 D029 D029 * † Note 1: 2: 3: SOSC Current SOSC Current ADC Current (Note 3), no conversion in progress ADC Current (Note 3), no conversion in progress These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. ADC oscillator source is FRC. 2013-2015 Microchip Technology Inc. DS40001729C-page 377 PIC16(L)F1705/9 TABLE 32-3: POWER-DOWN CURRENTS (IPD)(1,2) (CONTINUED) PIC16LF1705/9 Standard Operating Conditions: (unless otherwise stated) Low-Power Sleep Mode PIC16F1705/9 Low-Power Sleep Mode, VREGPM = 1 Param. No. Device Characteristics D030 D030 Min. Typ.† Conditions Max. +85°C Max. +125°C Units VDD — 250 — — A 1.8 — 250 — — A 3.0 — 280 — — A 2.3 — 280 — — A 3.0 Note ADC Current (Note 3), conversion in progress ADC Current (Note 3), conversion in progress — 280 — — A 5.0 D031 — 250 650 — A 3.0 Op Amp (High-power) D031 — 250 650 — A 3.0 Op Amp (High-power) — 350 850 — A 5.0 D032 D032 * † Note 1: 2: 3: — 250 600 — A 1.8 — 300 650 — A 3.0 — 280 600 — A 2.3 — 300 650 — A 3.0 — 310 650 — A 5.0 Comparator, CxSP = 1 Comparator, CxSP = 1 VREGPM = 0 These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this peripheral is enabled. The peripheral current can be determined by subtracting the base IDD or IPD current from this limit. Max values should be used when calculating total current consumption. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to VSS. ADC oscillator source is FRC. DS40001729C-page 378 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 32-4: I/O PORTS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. VIL Characteristic Min. Typ.† Max. Units — — — Conditions — 0.8 V 4.5V VDD 5.5V — 0.15 VDD V 1.8V VDD 4.5V — 0.2 VDD V 2.0V VDD 5.5V Input Low Voltage I/O PORT: D034 with TTL buffer D034A D035 with Schmitt Trigger buffer 2 with I C levels — — 0.3 VDD V with SMBus levels — — 0.8 V 2.7V VDD 5.5V D036 MCLR, OSC1 (RC mode) — — 0.2 VDD V (Note 1) D036A OSC1 (HS mode) — — 0.3 VDD V VIH Input High Voltage I/O ports: D040 2.0 — — V 4.5V VDD 5.5V 0.25 VDD + 0.8 — — V 1.8V VDD 4.5V with Schmitt Trigger buffer 0.8 VDD — — V 2.0V VDD 5.5V with I2C levels 0.7 VDD — — V with TTL buffer D040A D041 with SMBus levels 2.7V VDD 5.5V 2.1 — — V D042 MCLR 0.8 VDD — — V D043A OSC1 (HS mode) 0.7 VDD — — V D043B OSC1 (RC oscillator) 0.9 VDD — — V VDD 2.0V (Note 1) — ±5 ± 125 nA VSS VPIN VDD, Pin at high-impedance, 85°C — ±5 ± 1000 nA VSS VPIN VDD, Pin at high-impedance, 125°C — ±5 ± 200 nA VSS VPIN VDD, Pin at high-impedance, 85°C 25 100 200 A VDD = 3.3V, VPIN = VSS — — 0.6 V IOL = 8 mA, VDD = 5V IOL = 6 mA, VDD = 3.3V IOL = 1.8 mA, VDD = 1.8V VDD – 0.7 — — V IOH = -3.5 mA, VDD = 5V IOH = -3 mA, VDD = 3.3V IOH = -1 mA, VDD = 1.8V IIL D060 Input Leakage Current I/O Ports MCLR(3) D061 IPUR Weak Pull-up Current D070* VOL D080 (2) Output Low Voltage (4) I/O ports VOH D090 Output High Voltage(4) I/O ports * † Note 1: 2: 3: 4: These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. 2013-2015 Microchip Technology Inc. DS40001729C-page 379 PIC16(L)F1705/9 TABLE 32-4: I/O PORTS (CONTINUED) Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units — — 15 pF — — 50 pF Conditions Capacitive Loading Specs on Output Pins D101* COSC2 OSC2 pin D101A* CIO * † Note 1: 2: 3: 4: All I/O pins In XT, HS and LP modes when external clock is used to drive OSC1 These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use an external clock in RC mode. Negative current is defined as current sourced by the pin. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Including OSC2 in CLKOUT mode. DS40001729C-page 380 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 32-5: MEMORY PROGRAMMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions Program Memory Programming Specifications D110 VIHH Voltage on MCLR/VPP pin 8.0 — 9.0 V D111 IDDP Supply Current during Programming — — 10 mA D112 VBE VDD for Bulk Erase D113 VPEW VDD for Write or Row Erase D114 IPPGM Current on MCLR/VPP during Erase/Write D115 IDDPGM Current on VDD during Erase/Write D121 EP Cell Endurance D122 VPR VDD for Read D123 TIW Self-timed Write Cycle Time D124 TRETD Characteristic Retention D125 EHEFC High-Endurance Flash Cell (Note 1, Note 2) 2.7 — VDDMAX V VDDMIN — VDDMAX V — — 1.0 mA — — 5.0 mA 10K — — E/W VDDMIN — VDDMAX V — 2 2.5 ms — 40 — Year Provided no other specifications are violated 100K — — E/W 0C TA +60°C, Lower byte last 128 addresses Program Flash Memory -40C TA +85C (Note 3) † Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Required only if single-supply programming is disabled. 2: The MPLAB ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed between the ICD2 and target system when programming or debugging with the ICD2. 3: Self-write and Block Erase. 2013-2015 Microchip Technology Inc. DS40001729C-page 381 PIC16(L)F1705/9 TABLE 32-6: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. TH01 TH02 TH03 TH04 TH05 Sym. Characteristic Typ. Units JA Thermal Resistance Junction to Ambient 70.0 C/W 14-pin PDIP package JC TJMAX PD Thermal Resistance Junction to Case Maximum Junction Temperature Power Dissipation PINTERNAL Internal Power Dissipation Conditions 95.3 C/W 14-pin SOIC package 100.0 C/W 14-pin TSSOP package 51.5 C/W 16-pin QFN 3x3mm package 62.2 C/W 20-pin PDIP package 87.3 C/W 20-pin SSOP package 77.7 C/W 20-pin SOIC package 43.0 C/W 20-pin QFN 4x4mm package 32.75 C/W 14-pin PDIP package 31.0 C/W 14-pin SOIC package 24.4 C/W 14-pin TSSOP package 5.4 C/W 16-pin QFN 4x4mm package 27.5 C/W 20-pin PDIP package 31.1 C/W 20-pin SSOP package 23.1 C/W 20-pin SOIC package 5.3 C/W 20-pin QFN 4x4mm package 150 C — W PD = PINTERNAL + PI/O — W PINTERNAL = IDD x VDD(1) TH06 PI/O I/O Power Dissipation — W PI/O = (IOL * VOL) + (IOH * (VDD - VOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ - TA)/JA(2) Note 1: IDD is current to run the chip alone without driving any load on the output pins. 2: TA = Ambient Temperature, TJ = Junction Temperature DS40001729C-page 382 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 32.4 AC Characteristics Timing Parameter Symbology has been created with one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O PORT mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low FIGURE 32-4: T Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z Period Rise Valid High-impedance LOAD CONDITIONS Load Condition Pin CL VSS Legend: CL = 50 pF for all pins 2013-2015 Microchip Technology Inc. DS40001729C-page 383 PIC16(L)F1705/9 FIGURE 32-5: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS12 OS02 OS11 OS03 CLKOUT (CLKOUT Mode) Note 1: See Table 32-7. TABLE 32-7: CLOCK OSCILLATOR TIMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param No. Sym. OS01 FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency OS02 TOSC (1) External CLKIN Period(1) Oscillator Period(1) Instruction Cycle Time(1) OS03 TCY OS04* TosH, External CLKIN High, TosL External CLKIN Low OS05* TosR, External CLKIN Rise, TosF External CLKIN Fall Min. Typ† Max. Units Conditions DC — 0.5 MHz EC Oscillator mode (low) DC — 4 MHz EC Oscillator mode (medium) DC — 20 MHz EC Oscillator mode (high) — 32.768 — kHz LP Oscillator mode 0.1 — 4 MHz XT Oscillator mode 1 — 4 MHz HS Oscillator mode 1 — 20 MHz HS Oscillator mode, VDD > 2.7V DC — 4 MHz RC Oscillator mode, VDD > 2.0V 27 — s 250 — ns XT Oscillator mode 50 — ns HS Oscillator mode EC Oscillator mode LP Oscillator mode 50 — ns — 30.5 — s LP Oscillator mode 250 — 10,000 ns XT Oscillator mode 50 — 1,000 ns HS Oscillator mode 50 — — ns RC Oscillator mode 125 TCY DC ns TCY = 4/FOSC 2 — — s LP Oscillator mode 100 — — ns XT Oscillator mode 20 — — ns HS Oscillator mode 0 — — ns LP Oscillator mode 0 — — ns XT Oscillator mode 0 — — ns HS Oscillator mode * † These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. DS40001729C-page 384 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 32-8: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Freq. Tolerance Min. Typ.† Max. Units Conditions OS08 HFOSC Internal Calibrated HFINTOSC Frequency(1) ±2% — 16.0 — MHz 3.2V, TA = 25°C OS08A MFOSC Internal Calibrated MFINTOSC Frequency(1) ±2% — 500 — kHz 3.2V, TA = 25°C OS09 LFOSC Internal LFINTOSC Frequency — — 31 — kHz -40°C TA +125°C OS10* TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time — — 3.2 8 s MFINTOSC Wake-up from Sleep Start-up Time — — 24 35 s * † These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min" values with an external clock applied to the OSC1 pin. When an external clock input is used, the "max" cycle time limit is "DC" (no clock) for all devices. 2: To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 F and 0.01 F values in parallel are recommended. FIGURE 32-6: HFINTOSC AND MFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% 85 Temperature (°C) ± 3% 60 ± 2% 25 0 -20 -40 1.8 ± 5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2013-2015 Microchip Technology Inc. DS40001729C-page 385 PIC16(L)F1705/9 TABLE 32-9: PLL CLOCK TIMING SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. Sym. No. Min. Typ.† Max. Units FOSC Oscillator Frequency Range 4 — 8 MHz F11 FSYS On-Chip VCO System Frequency 16 — 32 MHz F12 TRC PLL Start-up Time (Lock Time) — — 2 ms CLK CLKOUT Stability (Jitter) -0.25% — +0.25% % F10 F13* Characteristic Conditions * These parameters are characterized but not tested. † Data in “Typ.” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 32-7: CLKOUT AND I/O TIMING Cycle Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS16 OS13 OS18 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 DS40001729C-page 386 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 32-10: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions TOSH2CKL FOSC to CLKOUT (1) — — 70 ns 3.3V VDD 5.0V OS12* TOSH2CKH FOSC to CLKOUT — — 72 ns 3.3V VDD 5.0V OS13* TCKL2IOV CLKOUT to Port out valid(1) — — 20 ns OS14* TIOV2CKH Port input valid before CLKOUT(1) TOSC + 200 ns — — ns OS15* TOSH2IOV Fosc (Q1 cycle) to Port out valid — 50 70* ns 3.3V VDD 5.0V OS16* TOSH2IOI Fosc (Q2 cycle) to Port input invalid (I/O in hold time) 50 — — ns 3.3V VDD 5.0V OS17* TIOV2OSH Port input valid to Fosc(Q2 cycle) (I/O in setup time) 20 — — ns OS18* TIOR Port output rise time(2) — — 40 15 72 32 ns VDD = 1.8V 3.3V VDD 5.0V OS19* TIOF Port output fall time(2) — — 28 15 55 30 ns VDD = 1.8V 3.3V VDD 5.0V OS20* TINP INT pin input high or low time 25 — — ns OS21* TIOC Interrupt-on-change new input level time 25 — — ns OS11* (1) * These parameters are characterized but not tested. † Data in “Typ.” column is at 3.0V, 25C unless otherwise stated. Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC. 2: Slew rate limited. FIGURE 32-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR PWRT Time-out 33 32 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) 34 31 34 I/O pins Note 1: Asserted low. 2013-2015 Microchip Technology Inc. DS40001729C-page 387 PIC16(L)F1705/9 TABLE 32-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions 2 — — s 10 16 27 ms Oscillator Start-up Timer Period(1) — 1024 — TOSC TPWRT Power-up Timer Period, PWRTE = 0 40 65 140 ms 34* TIOZ I/O high-impedance from MCLR Low or Watchdog Timer Reset — — 2.0 s 35 VBOR Brown-out Reset Voltage(2) 2.55 2.70 2.85 V BORV = 0 2.30 1.80 2.45 1.90 2.60 2.10 V V BORV = 1 (PIC16F1705/9) BORV = 1 (PIC16LF1705/9) 1.80 2.1 2.5 V LPBOR = 1 0 25 75 mV -40°C TA +85°C 1 3 35 s VDD VBOR 30 TMCL 31 TWDTLP Low-Power Watchdog Timer Time-out Period 32 TOST 33* MCLR Pulse Width (low) 35A VLPBOR Low-Power Brown-out(2) 36* VHYST 37* TBORDC Brown-out Reset DC Response Time Brown-out Reset Hysteresis(2) 3.3V VDD 5.0V 1:16 Prescaler used * † These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. DS40001729C-page 388 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 32-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 FIGURE 32-10: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) 37 Reset (due to BOR) 2013-2015 Microchip Technology Inc. 33(1) DS40001729C-page 389 PIC16(L)F1705/9 TABLE 32-12: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. 40* Sym. TT0H Characteristic T0CKI High Pulse Width No Prescaler With Prescaler 41* TT0L T0CKI Low Pulse Width No Prescaler With Prescaler Min. Typ.† Max. Units 0.5 TCY + 20 — — ns 10 — — ns 0.5 TCY + 20 — — ns 10 — — ns — — ns 42* TT0P T0CKI Period Greater of: 20 or (TCY + 40)*N 45* TT1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler 0.5 TCY + 20 — — ns 15 — — ns Asynchronous 46* TT1L 47* TT1P T1CKI Low Time 30 — — ns Synchronous, No Prescaler 0.5 TCY + 20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Greater of: 30 or (TCY + 40)*N — — ns 60 — — ns 32.4 32.76 8 33.1 kHz 2 TOSC — 7 TOSC — T1CKI Input Synchronous Period Asynchronous 48 FT1 49* TCKEZTMR1 Delay from External Clock Edge to Timer Increment * † Timer1 Oscillator Input Frequency Range (oscillator enabled by setting bit T1OSCEN) Conditions N = prescale value (2, 4, ..., 256) Timers in Sync mode These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001729C-page 390 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 32-11: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 32-4 for load conditions. TABLE 32-13: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Param. Sym. No. CC01* TccL Characteristic CCPx Input Low Time No Prescaler With Prescaler CC02* TccH CCPx Input High Time No Prescaler With Prescaler CC03* * † TccP CCPx Input Period Min. Typ.† Max. Units 0.5 TCY + 20 — — ns 20 — — ns 0.5 TCY + 20 — — ns 20 — — ns (3TCY + 40)*N — — ns Conditions N = prescale value (1, 4 or 16) These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2013-2015 Microchip Technology Inc. DS40001729C-page 391 PIC16(L)F1705/9 FIGURE 32-12: CLC PROPAGATION TIMING CLCxINn CLC Input time CLCxINn CLC Input time LCx_in[n](1) LCx_in[n](1) CLC01 Note 1: CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC02 CLC03 See Figure 19-1 to identify specific CLC signals. TABLE 32-14: CONFIGURATION LOGIC CELL (CLC) CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions CLC01* TCLCIN CLC input pin (CLCxIN[n]) to CLC module input select (LCx_in[n]) propagation time — 7 OS17 ns (Note 1) CLC02* TCLC CLC module input to output progagation time — — 24 12 — — ns ns VDD = 1.8V VDD > 3.6V Rise Time — OS18 — — (Note 2) Fall Time — OS19 — — (Note 2) — 45 — MHz CLC03* TCLCOUT CLC output time CLC04* FCLCMAX CLC maximum switching frequency * † These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: I/O setup delay. 2: See Table for OS17, OS18 and OS19 rise and fall times. DS40001729C-page 392 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 32-15: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1) Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C, Single-ended, 2 s TAD, VREF+ = 3V, VREF- = VSS Param. Sym. No. Characteristic Min. Typ.† Max. Units Conditions AD01 NR Resolution — — 10 bit AD02 EIL Integral Error — — ±1.7 LSb VREF = 3.0V AD03 EDL Differential Error — — ±1 LSb No missing codes, VREF = 3.0V AD04 EOFF Offset Error AD05 EGN AD06 VREF Reference Voltage(2) AD07 VAIN Full-Scale Range AD08 ZAIN Recommended Impedance of Analog Voltage Source Gain Error — — ±2.5 LSb VREF = 3.0V — — ±2.0 LSb VREF = 3.0V 1.8 — VDD V VSS — VREF V — — 10 k VREF = (VREF+ minus VREF-) Can go higher if external 0.01 F capacitor is present on input pin. * † These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. 2: VREF = (VREF+ – VREF-); ADCREF+ may be VDD, VREF+ pin or FVR1_buffer. The ADCREF- may be VSS or VREF- pin. If selecting the FVR1_buffer, the buffers output voltage must be 2.048V or 4.096V. TABLE 32-16: ADC CONVERSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. Sym. No. AD130* TAD AD131 TCNV Characteristic Min. Typ.† Max. Units ADC Clock Period (TADC) 1.0 FRC Oscillator Period (TFRC) 1.0 Conversion Time (not including Acquisition Time)(1) — Conditions — 9.0 s 2 6.0 s ADCS<1:0> = 11 (ADC FRC mode) 11 — TAD Set GO/DONE bit to conversion complete s FOSC-based AD132* TACQ Acquisition Time — 5.0 — AD133* THCD Holding Capacitor Disconnect Time — 0.5 TAD — ADCS<2:0> x11 (FOSC based) — 1/2 TAD + 1 TCY — ADCS<2:0> = x11 (FRC based) * † These parameters are characterized but not tested. Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: The ADRES register may be read on the following TCY cycle. 2013-2015 Microchip Technology Inc. DS40001729C-page 393 PIC16(L)F1705/9 FIGURE 32-13: ADC CONVERSION TIMING (ADC CLOCK FOSC-BASED) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD132 FIGURE 32-14: ADC CONVERSION TIMING (ADC CLOCK FROM FRC) BSF ADCON0, GO AD133 1 TCY AD131 Q4 AD130 ADC_clk 9 ADC Data 8 7 6 OLD_DATA ADRES 2 1 0 NEW_DATA 1 TCY ADIF GO Sample 3 DONE AD132 Sampling Stopped Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. DS40001729C-page 394 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 TABLE 32-17: OPERATIONAL AMPLIFIER (OPA) Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C, OPAxSP = 1 (High GBWP mode) Param. Symbol No. Parameters Min. Typ. Max. Units MHz OPA01* GBWP Gain Bandwidth Product — 3.5 — OPA02* TON Turn on Time — 10 — s OPA03* PM Phase Margin — 40 — degrees OPA04* SR Slew Rate — 3 — V/s OPA05 OFF Offset — ±3 ±9 mV OPA06 CMRR Common Mode Rejection Ratio 52 70 — dB OPA07* AOL Open Loop Gain — 90 — dB OPA08 Common Mode Input Voltage 0 — VDD V Power Supply Rejection Ratio — 80 — dB VICM OPA09* PSRR * Conditions VDD > 2.5V These parameters are characterized but not tested. TABLE 32-18: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C See Section 33.0 “DC and AC Characteristics Graphs and Charts” for operating characterization. Param. No. Sym. Characteristics Min. Typ. Max. Units — ±2.5 ±5 mV Comments CM01 VIOFF Input Offset Voltage CM02 VICM Input Common Mode Voltage 0 — VDD V CM03 CMRR Common Mode Rejection Ratio 40 50 — dB Response Time Rising Edge — 60 125 ns Normal-Power mode measured at VDD/2 (Note 1) Response Time Falling Edge — 60 110 ns Normal-Power mode measured at VDD/2 (Note 1) Response Time Rising Edge — 85 — ns Low-Power mode measured at VDD/2 (Note 1) Response Time Falling Edge — 85 — ns Low-Power mode measured at VDD/2 (Note 1) CM04A CM04B CM04C RESP(1) T CM04D Normal-Power mode measured at VDD/2 CM05* TMC2OV Comparator Mode Change to Output Valid* — — 10 s CM06 CHYSTER Comparator Hysteresis 20 45 75 mV * Note 1: These parameters are characterized but not tested. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. Comparator hysteresis is available when the CxHYS bit of the CMxCON0 register is enabled. 2: 2013-2015 Microchip Technology Inc. Hysteresis ON High-Power mode measured at VDD/2 (Note 2) DS40001729C-page 395 PIC16(L)F1705/9 TABLE 32-19: DIGITAL-TO-ANALOG CONVERTER (DAC) SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C See Section 33.0 “DC and AC Characteristics Graphs and Charts” for operating characterization. Param. No. Sym. Characteristics Min. Typ. Max. Units — VREF/256 — V LSb DAC01* CLSB Step Size DAC02* CACC Absolute Accuracy — — 1.5 DAC03* CR Unit Resistor Value (R) — 600 — DAC04* CST Settling Time(1) — — 10 s * Note 1: Comments These parameters are characterized but not tested. Settling time measured while DACR<7:0> transitions from ‘0x00’ to ‘0xFF’. TABLE 32-20: ZERO CROSS PIN SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param. No. ZC01 Sym. Characteristics ZCPINV Voltage on Zero-Cross Pin ZC02 ZCSRC Source current ZC03 ZCSNK Sink current ZC04* ZCISW ZC05* ZCOUT * Min. Typ. Max. Units — 0.75 — V — — -600 A ZCPINV = VSS 600 — — A ZCPINV = VDD Response Time Rising Edge — 1 — s Response Time Falling Edge — 1 — s Response Time Rising Edge — 1 — s Response Time Falling Edge — 1 — s Comments These parameters are characterized but not tested. DS40001729C-page 396 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 32-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 32-4 for load conditions. TABLE 32-21: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol US120* TCKH2DTV US121* TCKRF US122* TDTRF * Characteristic Min. Max. Units Conditions SYNC XMIT (Master and Slave) Clock high to data-out valid — 80 ns 3.0V VDD 5.5V — 100 ns 1.8V VDD 5.5V Clock out rise time and fall time (Master mode) — 45 ns 3.0V VDD 5.5V — 50 ns 1.8V VDD 5.5V Data-out rise time and fall time — 45 ns 3.0V VDD 5.5V — 50 ns 1.8V VDD 5.5V These parameters are characterized but not tested. FIGURE 32-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING CK US125 DT US126 Note: Refer to Figure 32-4 for load conditions. TABLE 32-22: USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic US125* TDTV2CKL SYNC RCV (Master and Slave) Data-setup before CK (DT hold time) US126* TCKL2DTL * Data-hold after CK (DT hold time) Min. Max. Units 10 — ns 15 — ns Conditions These parameters are characterized but not tested. 2013-2015 Microchip Technology Inc. DS40001729C-page 397 PIC16(L)F1705/9 FIGURE 32-17: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 32-4 for load conditions. FIGURE 32-18: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 SP78 LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 32-4 for load conditions. DS40001729C-page 398 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 32-19: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 32-4 for load conditions. FIGURE 32-20: SS SPI SLAVE MODE TIMING (CKE = 1) SP82 SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note: Refer to Figure 32-4 for load conditions. 2013-2015 Microchip Technology Inc. DS40001729C-page 399 PIC16(L)F1705/9 TABLE 32-23: SPI MODE REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Typ.† Max. Unit s SP70* TSSL2SCH, TSSL2SCL SS to SCK or SCK input 2.25 TCY — — ns SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SCK input low time (Slave mode) TCY + 20 — — ns SP72* TSCL Conditions SP73* TDIV2SCH, TDIV2SCL Setup time of SDI data input to SCK edge 100 — — ns SP74* TSCH2DIL, TSCL2DIL Hold time of SDI data input to SCK edge 100 — — ns SP75* TDOR SDO data output rise time — 10 25 ns 3.0V VDD 5.5V — 25 50 ns 1.8V VDD 5.5V SP76* TDOF SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time (Master mode) — 10 25 ns 3.0V VDD 5.5V — 25 50 ns 1.8V VDD 5.5V SP79* TSCF SCK output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, TSCL2DOV SDO data output valid after SCK edge — — 50 ns 3.0V VDD 5.5V 1.8V VDD 5.5V SP81* TDOV2SCH, SDO data output setup to SCK TDOV2SCL edge SP82* TSSL2DOV SDO data output valid after SS edge SP83* TSCH2SSH, TSCL2SSH SS after SCK edge — — 145 ns TCY — — ns — — 50 ns 1.5 TCY + 40 — — ns * These parameters are characterized but not tested. † Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS40001729C-page 400 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 FIGURE 32-21: I2C BUS START/STOP BITS TIMING SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note: Refer to Figure 32-4 for load conditions. TABLE 32-24: I2C BUS START/STOP BITS REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol SP90* TSU:STA SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition Characteristic Start condition 100 kHz mode 4700 Typ. Max. Units — — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time Hold time * Min. 400 kHz mode 600 — — 100 kHz mode 4000 — — 400 kHz mode 600 — — Conditions ns Only relevant for repeated Start condition ns After this period, the first clock pulse is generated ns ns These parameters are characterized but not tested. FIGURE 32-22: I2C BUS DATA TIMING SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note: Refer to Figure 32-4 for load conditions. 2013-2015 Microchip Technology Inc. DS40001729C-page 401 PIC16(L)F1705/9 TABLE 32-25: I2C BUS DATA REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5 TCY — — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.5 TCY — — SSP module SP101* TLOW Clock low time SSP module SP102* SP103* TR TF SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1CB 300 ns SDA and SCL fall time 100 kHz mode — 250 ns 400 kHz mode 20 + 0.1CB 250 ns 0 — ns SP106* THD:DAT Data input hold time 100 kHz mode 400 kHz mode 0 0.9 s SP107* TSU:DAT Data input setup time 100 kHz mode 250 — ns 400 kHz mode 100 — ns SP109* TAA Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns SP110* TBUF Bus free time 100 kHz mode 4.7 — s 400 kHz mode 1.3 — s — 400 pF SP111 * Note 1: 2: CB Bus capacitive loading CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start These parameters are characterized but not tested. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. DS40001729C-page 402 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 33.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the F and LF devices. Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. “Typical” represents the mean of the distribution at 25C. “Maximum”, “Max.”, “Minimum” or “Min.” represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each temperature range. Microchip Technology Inc. DS40001729C-page 403 PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 28 10 Max: 85°C + 3ı Typical: 25°C 9 Max. 24 Max. 8 Typical 22 Typical IDD (μA) 7 IDD (μA) Max: 85°C + 3ı Typical: 25°C 26 6 20 18 5 16 4 14 3 12 2 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 VDD (V) FIGURE 33-1: IDD, LP Oscillator Mode, Fosc = 32 kHz, PIC16LF1705/9 Only. 4.5 5.0 5.5 6.0 FIGURE 33-2: IDD, LP Oscillator Mode, Fosc = 32 kHz, PIC16F1705/9 Only. 400 400 Typical: 25°C 350 4 MHz XT 4 MHz XT Max: 85°C + 3ı 350 300 300 250 250 IDD (μA) IDD (μA) 4.0 VDD (V) 200 150 200 150 1 MHz XT 1 MHz XT 100 100 50 50 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 VDD (V) 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 33-3: IDD Typical, XT and EXTRC Oscillator, PIC16LF1705/9 Only. FIGURE 33-4: IDD Maximum, XT and EXTRC Oscillator, PIC16LF1705/9 Only. 500 450 4 MHz XT 4 MHz XT Max: 85°C + 3ı 450 Typical: 25°C 400 400 350 350 300 IDD (μA) IDD (μA) 300 250 1 MHz XT 200 150 1 MHz XT 250 200 150 100 100 50 50 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-5: IDD Typical, XT and EXTRC Oscillator, PIC16F1705/9 Only. DS40001729C-page 404 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-6: IDD Maximum, XT and EXTRC Oscillator, PIC16F1705/9 Only. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 12 24 Max: 85°C + 3ı Typical: 25°C 10 Max. Max: 85°C + 3ı Typical: 25°C 22 Max. 20 Typical IDD (μA) IDD (μA) 8 Typical 6 18 16 4 14 2 12 10 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 33-7: IDD, EC Oscillator LP Mode, Fosc = 32 MHz, PIC16LF1705/9 Only. FIGURE 33-8: IDD, EC Oscillator LP Mode, Fosc = 32 MHz, PIC16F1705/9 Only. 50 60 45 Max. 40 50 35 45 Max. Max: 85°C + 3ı Typical: 25°C 55 Max: 85°C + 3ı Typical: 25°C IDD (μA) IDD (μA) Typical Typical 30 40 25 35 20 30 15 25 20 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 4.0 4.5 FIGURE 33-9: IDD, EC Oscillator LP Mode, Fosc = 500 kHz, PIC16LF1705/9 Only. 5.5 6.0 FIGURE 33-10: IDD, EC Oscillator LP Mode, Fosc = 500 kHz, PIC16F1705/9 Only. 350 350 Typical: 25°C 300 4 MHz Max: 85°C + 3ı 300 4 MHz 250 250 200 IDD (μA) IDD (μA) 5.0 VDD (V) VDD (V) 150 200 150 100 1 MHz 1 MHz 100 50 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) FIGURE 33-11: IDD Typical, EC Oscillator MP Mode, PIC16LF1705/9 Only. Microchip Technology Inc. 3.8 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 33-12: IDD Maximum, EC Oscillator MP Mode, PIC16LF1705/9 Only. DS40001729C-page 405 PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 450 400 350 400 Typical: 25°C Max: 85°C + 3ı 4 MHz 350 300 4 MHz 250 IDD (μA) IDD (μA) 300 200 1 MHz 250 200 1 MHz 150 150 100 100 50 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 6.0 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-13: IDD Typical, EC Oscillator MP Mode, PIC16F1705/9 Only. FIGURE 33-14: IDD Maximum, EC Oscillator MP Mode, PIC16F1705/9 Only. 2.5 3.0 32 MHz Typical: 25°C Max: 85°C + 3ı 2.5 2.0 32 MHz IDD (mA) IDD (mA) 2.0 1.5 16 MHz 1.5 1.0 16 MHz 1.0 8 MHz 0.5 8 MHz 0.5 0.0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 1.6 1.8 2.0 2.2 2.4 VDD (V) 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD ((V)) FIGURE 33-15: IDD Typical, EC Oscillator HP Mode, PIC16LF1705/9 Only. FIGURE 33-16: IDD Maximum, EC Oscillator HP Mode, PIC16LF1705/9 Only. 2.5 2.5 32 MHz Max: 85°C + 3ı Typical: 25°C 2.0 32 MHz 2.0 IDD (mA) IDD (mA) 1.5 16 MHz 1.0 1.5 16 MHz 1.0 8 MHz 8 MHz 0.5 0.5 0.0 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 33-17: IDD Typical, EC Oscillator HP Mode, PIC16F1705/9 Only. DS40001729C-page 406 6.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-18: IDD Maximum, EC Oscillator HP Mode, PIC16F1705/9 Only. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 9 24 Max. 8 Max. Max: 85°C + 3ı Typical: 25°C 22 7 IDD (μA) IDD (μA) 20 Typical 6 5 4 Typical 18 16 3 14 2 12 1 0 Max: 85°C + 3ı Typical: 25°C 10 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-19: IDD, LFINTOSC Mode, Fosc = 31 kHz, PIC16LF1705/9 Only. FIGURE 33-20: IDD, LFINTOSC Mode, Fosc = 31 kHz, PIC16F1705/9 Only. 260 180 Max. Max: 85°C + 3ı Typical: 25°C 170 Typical 220 Max. 160 200 IDD (μA) 150 IDD (μA) Max: 85°C + 3ı Typical: 25°C 240 Typical 140 180 130 160 120 140 110 120 100 100 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 FIGURE 33-21: IDD, MFINTOSC Mode, Fosc = 500 kHz, PIC16LF1705/9 Only. 4.5 5.0 5.5 6.0 FIGURE 33-22: IDD, MFINTOSC Mode, Fosc = 500 kHz, PIC16F1705/9 Only. 1.6 1.6 16 MHz 16 MHz Typical: 25°C 1.4 Max: 85°C + 3ı 1.4 1.2 1.0 IDD (mA) 1.2 IDD (mA) 4.0 VDD (V) VDD (V) 8 MHz 8 MHz 1.0 0.8 0.8 4 MHz 4 MHz 0.6 0.6 2 MHz 0.4 2 MHz 0.4 1 MHz 1 MHz 0.2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 VDD (V) FIGURE 33-23: IDD Typical, HFINTOSC Mode, PIC16LF1705/9 Only. Microchip Technology Inc. 3.8 0.2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 33-24: IDD Maximum, HFINTOSC Mode, PIC16LF1705/9 Only. DS40001729C-page 407 PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 1.6 1.6 16 MHz 16 MHz Typical: 25°C 1.4 1.2 1.2 1.0 8 MHz 0.8 IDD (mA) IDD (mA) Max: 85°C + 3ı 1.4 4 MHz 2 MHz 0.6 0.8 4 MHz 2 MHz 0.6 1 MHz 0.4 8 MHz 1.0 1 MHz 0.4 0.2 0.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-25: IDD Typical, HFINTOSC Mode, PIC16F1705/9 Only. FIGURE 33-26: IDD Maximum, HFINTOSC Mode, PIC16F1705/9 Only. 2.0 2.0 Max: 85°C + 3ı 1.8 Typical: 25°C 1.8 20 MHz 1.6 1.6 20 MHz 1.4 1.4 16 MHz IDD (mA) IDD (mA) 1.2 16 MHz 1.2 1.0 0.8 0.8 8 MHz 0.6 8 MHz 0.6 1.0 0.4 0.4 4 MHz 4 MHz 0.2 0.2 0.0 0.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.4 3.8 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 33-27: IDD Typical, HS Oscillator, 25°C, PIC16LF1705/9 Only. FIGURE 33-28: IDD Maximum, HS Oscillator, PIC16LF1705/9 Only. 2.0 2.2 Typical: 25°C 1.8 20 MHz Max: 85°C + 3ı 2.0 20 MHz 1.6 1.8 16 MHz 1.4 1.6 1.2 1.4 IDD (mA) IDD (mA) 16 MHz 1.0 8 MHz 0.8 0.6 1.2 1.0 8 MHz 0.8 4 MHz 0.4 0.6 0.2 0.4 0.0 0.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-29: IDD Typical, HS Oscillator, 25°C, PIC16F1705/9 Only. DS40001729C-page 408 4 MHz 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-30: IDD Maximum, HS Oscillator, PIC16F1705/9 Only. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 3.0 3.5 Max. 2.5 3.0 Max. Typical 2.5 IDD (mA) IDD (mA) 2.0 1.5 1.0 Typical 2.0 1.5 Typical: 25°C Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı 0.5 1.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-31: IDD, HS Oscillator, 32 MHz (8 MHz + 4x PLL), PIC16LF1705/9 Only. FIGURE 33-32: IDD, HS Oscillator, 32 MHz (8 MHz + 4x PLL), PIC16F1705/9 Only. 450 1.2 Max. 400 Max. 1.0 350 0.8 IPD (μA) IDD (nA) 300 250 Max: 85°C + 3ı Typical: 25°C 200 150 Max: 85°C + 3ı T i l 25°C Typical: 0.6 0.4 Typical 00 100 0.2 50 Typical 0 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 FIGURE 33-33: IPD Base, LP Sleep Mode, PIC16LF1705/9 Only. 4.5 5.0 5.5 6.0 FIGURE 33-34: IPD Base, LP Sleep Mode (VREGPM = 1), PIC16F1705/9 Only. 3.0 2.5 Max: 85°C + 3ı Typical: 25°C Max: 85°C + 3ı Typical: 25°C 2.5 2.0 Max. Max. IPD (μA) 2.0 IPD (μA) μA) 4.0 VDD (V) VDD (V) 1.5 15 1.5 1.0 1.0 Typical Typical 0.5 0.5 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 0.0 1.5 VDD (V) FIGURE 33-35: IPD, Watchdog Timer (WDT), PIC16LF1705/9 Only. Microchip Technology Inc. 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-36: IPD, Watchdog Timer (WDT), PIC16F1705/9 Only. DS40001729C-page 409 PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 35 35 Max: 85°C + 3 M 3ı Typical: 25°C 30 Max. 30 Max. IDD (nA) IDD (nA) 25 20 25 Typical 20 Typical 15 15 Max: 85°C + 3ı Typical: 25°C 10 10 5 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 1.5 3.6 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-37: IPD, Fixed Voltage Reference (FVR), PIC16LF1705/9 Only. FIGURE 33-38: IPD, Fixed Voltage Reference (FVR), PIC16F1705/9 Only. 11 13 Max: 85°C + 3 M 3ı Typical: 25°C 10 Max: 85°C + 3ı Typical: 25°C 12 Max. Max. 11 9 Typical IDD (nA) nA) IDD (nA) 10 8 7 9 Typical 8 7 6 6 5 5 4 4 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 2.8 3.0 3.2 3.4 3.6 3.8 4.0 VDD (V) FIGURE 33-39: IPD, Brown-Out Reset (BOR), BORV = 1, PIC16LF1705/9 Only. 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.4 5.6 FIGURE 33-40: IPD, Brown-Out Reset (BOR), BORV = 1, PIC16F1705/9 Only. 1.8 1.8 Max. 1.6 Max: 85°C + 3ı Typical: 25°C 1.6 1.4 Max. 1.4 1.2 1.2 Max: 85°C + 3ı Typical: 25°C 1.0 IDD (μA) IDD (nA) 4.2 VDD (V) 0.8 0.6 1.0 0.8 0.6 Typical 0.4 0.4 0.2 02 0.2 0.0 Typical 0.0 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VDD (V) FIGURE 33-41: IPD, LP Brown-Out Reset (LPBOR = 0), PIC16LF1705/9 Only. DS40001729C-page 410 3.7 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 VDD (V) FIGURE 33-42: IPD, LP Brown-Out Reset (LPBOR = 0), PIC16F1705/9 Only. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 7 12 Max: 85°C + 3 M 3ı Typical: 25°C Max: 85°C + 3ı Typical: 25°C 6 10 Max. 5 Max. IDD (μA) μA) IDD (μA) 8 4 3 Typical 6 Typical 4 2 2 1 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 0 3.8 1.5 2.0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-43: IPD, Timer1 Oscillator, FOSC = 32 kHz, PIC16LF1705/9 Only. FIGURE 33-44: IPD, Timer1 Oscillator, FOSC = 32 kHz, PIC16F1705/9 Only. 900 700 Max: 85°C + 3ı Typical: 25°C 600 Max: 8 M 85°C °C + 3 3ı Typical: 25°C 800 Max. 700 Max. 500 IDD (μA) IDD (μA) μA) 600 400 Typical 300 500 Typical 400 300 200 200 100 100 0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 1.5 3.8 2.0 2.5 3.0 FIGURE 33-45: IPD, Op Amp, High GBWP Mode (OPAxSP = 1), PIC16LF1705/9 Only. 4.0 4.5 5.0 5.5 6.0 FIGURE 33-46: IPD, Op Amp, High GBWP Mode (OPAxSP = 1), PIC16F1705/9 Only. 1.4 500 Max: 85°C + 3ı Typical: 25°C 450 Max: 85°C + 3ı Typical: 25°C 1.2 Max. 400 Max. 1.0 350 IDD (μA) μA) 300 IDD (μA) μA) 3.5 VDD (V) VDD (V) 250 200 150 0.8 0.6 0.4 Typical 100 0.2 50 Typical 0.0 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 33-47: IPD, ADC Non-Converting, PIC16LF1705/9 Only. Microchip Technology Inc. 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-48: IPD, ADC Non-Converting, PIC16F1705/9 Only. DS40001729C-page 411 PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 800 800 Max: -40°C + 3ı Typical: 25°C Max: -40°C + 3ı Typical: 25°C 700 Max. 600 600 Typical IDD (μA) IDD D (μA) Max. 700 500 Typical 500 400 400 300 300 200 200 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 2.0 2.5 3.0 3.5 VDD (V) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-49: IPD, Comparator, NP Mode (CxSP = 1), PIC16LF1705/9 Only. FIGURE 33-50: IPD, Comparator, NP Mode (CxSP = 1), PIC16F1705/9 Only. 6 5 Graph represents 3ı Limits Graph represents 3ı Limits 5 4 3 -40°C VOL (V) VOH (V) 4 3 125°C 2 -40°C 2 Typical Typical 125°C 1 1 0 -30 -25 -20 -15 -10 -5 0 0 0 10 20 30 IOH (mA) FIGURE 33-51: VOH vs. IOH Over Temperature, VDD = 5.0V, PIC16F1705/9 Only. 40 IOL (mA) 50 60 70 80 FIGURE 33-52: VOL vs. IOL Over Temperature, VDD = 5.0V, PIC16F1705/9 Only. 3.0 3.5 Graph represents 3ı Limits Graph represents 3ı Limits 3.0 2.5 2.5 VOL (V) VOH (V) 2.0 2.0 1.5 -40°C Typical 1.5 125°C 125°C 1.0 Typical 1.0 -40°C 0.5 0.5 0.0 0.0 -14 -12 -10 -8 -6 -4 IOH (mA) FIGURE 33-53: VOH vs. IOH Over Temperature, VDD = 3.0V. DS40001729C-page 412 -2 0 0 5 10 15 20 25 30 IOL (mA) FIGURE 33-54: VOL vs. IOL Over Temperature, VDD = 3.0V. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 2.0 1.8 Graph represents 3ı Limits Graph represents 3ı Limits 1.8 1.6 1.6 1.4 1.4 Vol (V) VOH (V) 1.2 1.2 125°C 1.0 0.8 1.0 125°C Typical 0.8 -40°C Typical 0.6 -40°C 0.6 0.4 0.4 0.2 0.2 0.0 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.0 0 1 2 3 4 FIGURE 33-55: VOH vs. IOH Over Temperature, VDD = 1.8V, PIC16LF1705/9 Only. 7 8 9 10 40,000 38,000 38,000 Max. Max. 36,000 36,000 34,000 34,000 Frequency (Hz) Typical Frequency (Hz) 6 FIGURE 33-56: VOL vs. IOL Over Temperature, VDD = 1.8V, PIC16LF1705/9 Only. 40,000 32,000 30,000 Min. 28,000 Typical 32,000 30,000 Min. 28,000 26,000 26,000 24,000 24,000 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 22,000 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 22,000 20,000 20,000 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 2.0 3.8 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 33-57: LFINTOSC Frequency, PIC16LF1705/9 Only. FIGURE 33-58: LFINTOSC Frequency, PIC16F1705/9 Only. 24 24 22 22 Max. Max. 20 20 18 Time (ms) Time (ms) 5 IOL (mA) IOH (mA) Typical 16 18 Typical 16 Min. Min. 14 14 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 12 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 12 10 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.6 1.8 2.0 2.2 2.4 2.6 VDD (V) 2.8 3.0 3.2 3.4 3.6 3.8 VDD (V) FIGURE 33-59: WDT Time-Out Period, PIC16F1705/9 Only. Microchip Technology Inc. FIGURE 33-60: WDT Time-Out Period, PIC16LF1705/9 Only. DS40001729C-page 413 PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 70 2.00 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 60 Max. 1.95 Max. 50 Voltage (mV) Voltage (V) Typical 1.90 Min. 40 30 Typical 20 1.85 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı Min. 10 0 1.80 -60 -40 -20 0 20 40 60 80 100 120 -60 140 -40 -20 0 Temperature (°C) ( C) 20 40 60 80 100 120 140 Temperature (°C) FIGURE 33-61: Brown-Out Reset Voltage, Low Trip Point (BORV = 1), PIC16LF1705/9 Only. FIGURE 33-62: Brown-Out Reset Hysteresis, Low Trip Point (BORV = 1), PIC16LF1705/9 Only. 2.60 70.0 2.55 60.0 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı Max. Max. Typical 50.0 Voltage (mV) Voltage (V) 2.50 Min. 2.45 40.0 Typical 30.0 2.40 20.0 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 2.35 Min. 10.0 2.30 -60 -40 -20 0 20 40 60 80 100 120 0.0 140 -60 -40 -20 0 Temperature (°C) 40 60 80 100 120 140 Temperature (°C) FIGURE 33-63: Brown-Out Reset Voltage, High Trip Point (BORV = 1), PIC16F1705/9 Only. FIGURE 33-64: Brown-Out Reset Hysteresis, Low Trip Point (BORV = 1), PIC16F1705/9 Only. 80 2.85 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 2.80 Max. 60 Voltage (mV) 2.75 Typical Min. 2.70 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 70 Max. Voltage (V) 20 50 Typical 40 30 20 Min. 2.65 10 0 2.60 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) FIGURE 33-65: Brown-Out Reset Voltage, High Trip Point (BORV = 0). DS40001729C-page 414 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C) ( C) FIGURE 33-66: Brown-Out Reset Hysteresis, High Trip Point (BORV = 0). 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 2.7 50 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 2.6 2.5 Max. 40 2.4 35 2.3 Voltage (mV) Voltage (V) Max: Typical + 3ı Typical: statistical mean 45 Max. 2.2 Typical 2.1 30 25 20 Typical 2.0 15 1.9 10 Min. 1.8 5 1.7 -60 -40 -20 0 20 40 60 80 100 120 0 140 -60 -40 -20 0 20 Temperature (°C) FIGURE 33-67: 40 LPBOR Reset Voltage. FIGURE 33-68: Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 90 100 120 140 LPBOR Reset Hysteresis. Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 90 Max. Max. 80 Time (ms) 80 Time (ms) 80 100 100 Typical 70 Min. Typical 70 60 60 50 50 Min. 40 40 2 2.5 3 3.5 4 4.5 5 5.5 1.6 6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 VDD (V) VDD (V) FIGURE 33-69: PWRT Period, PIC16F1705/9 Only. FIGURE 33-70: PWRT Period, PIC16LF1705/9 Only. 1.58 1.58 1.70 Max: Typical + 3ı Typical: 25°C Min: Typical - 3ı 1.56 1.56 1.68 Max. Voltage Voltage (V) (V) Max. 1.66 1.64 Typical Voltage (V) 60 Temperature (°C) 1.62 1.60 Min. 1.58 1.54 1.54 Typical 1.52 1.52 1.5 1.50 Min. 1.48 1.48 1.56 1.54 1.46 Max: Typical + 3ı 0 1.46 -40 Typical:-20 statistical mean Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 1.52 20 40 60 80 100 120 75 100 125 150 Temperature (°C) Min: Typical - 3ı 1.44 1.50 -50 -25 0 25 50 75 100 125 150 Temperature (°C) FIGURE 33-71: devices. POR Release Voltage. All Microchip Technology Inc. -50 -25 0 25 50 Temperature (°C) FIGURE 33-72: POR Rearm Voltage, NP Mode (VREGPM 1 = 0), PIC16F1705/9 Only. DS40001729C-page 415 PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 12 1.4 1.3 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 10 Max. 1.2 Time (μs) Voltage (V) 8 1.1 Typical 1.0 Max. 6 Typical 0.9 4 Min. 0.8 2 Max: Typical + 3ı Typical: statistical mean Min: Typical - 3ı 0.7 0 0.6 -50 -25 0 25 50 75 100 125 1.5 150 2.0 2.5 3.0 3.5 Temperature (°C) 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-73: POR Rearm Voltage, NP Mode, PIC16LF1705/9 Only. FIGURE 33-74: VREGPM = 0. Wake From Sleep, 40 50 Max: Typical + 3ı Typical: statistical mean @ 25°C 45 35 40 Max. Max. 30 Time (μs) Time (μs) 35 30 Typical 25 Typical 25 20 20 15 10 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 5 Note: The FVR Stabiliztion Period applies when coming out of RESET or exiting sleep mode. 15 10 0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.6 6.0 1.8 2.0 2.2 2.4 Wake From Sleep, 2.8 3.0 3.2 3.4 3.6 3.8 FIGURE 33-76: FVR Stabilization Period. PIC16LF1705/9 Only. 1.0 1.0 0.5 0.5 DNL(LSb) DNL(LSb) FIGURE 33-75: VREGPM = 1. 2.6 VDD (V) VDD (V) 0.0 0.0 Ͳ0.5 Ͳ0.5 Ͳ1.0 Ͳ1.0 0 128 256 384 512 640 768 896 1024 OutputCode FIGURE 33-77: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1 S, 25°C. DS40001729C-page 416 0 128 256 384 512 640 768 896 1024 OutputCode FIGURE 33-78: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 4 S, 25°C. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 2.0 1.0 1.0 1.5 1.0 INL(LSb) DNL(LSb) INL(LSb) 0.5 0.0 0.5 0.5 0.0 Ͳ0.5 0.0 Ͳ1.0 Ͳ1.5 Ͳ0.5 Ͳ0.5 Ͳ2.0 0 512 1024 1536 2048 2560 3072 3584 4096 640 768 896 1024 OutputCode Ͳ1.0 0 128 256 384 512 640 768 896 Ͳ1.0 1024 0 128 256 384 OutputCode 512 OutputCode FIGURE 33-79: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1 S, 25°C. FIGURE 33-80: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 4 S, 25°C. , , , , 1.5 1.5 MaxͲ40°C MinͲ40°C 1.0 1.0 Min25°C 0.5 DNL(LSb) Min125°C 0.0 Min125°C INL(LSb) 0.5 Min25°C Ͳ0.5 Max25°C Max125°C 0.0 Ͳ0.5 Min25°C Min125°C MinͲ40°C MinͲ40°C Ͳ1.0 Ͳ1.0 Ͳ1.5 Ͳ1.5 5.00EͲ07 1.00EͲ06 2.00EͲ06 4.00EͲ06 5.00EͲ07 8.00EͲ06 1.00EͲ06 FIGURE 33-81: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, VREF = 3.0V. 4.00EͲ06 8.00EͲ06 FIGURE 33-82: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, VREF = 3.0V. 1.5 1.5 1.0 MaxͲ40°C 1.0 MaxͲ40°C 0.5 Max25°C Max25°C Max125°C 0.0 INL(LSb) DNL(LSb) 2.00EͲ06 TADs TADs 0.5 Max125°C 0.0 Min125°C Ͳ0.5 Min125°C Min25°C MinͲ40°C Ͳ1.0 MinͲ40°C Ͳ0.5 Min25°C Ͳ1.0 Ͳ1.5 1.8 2.3 3 VREF FIGURE 33-83: ADC 10-Bit Mode, Single-Ended DNL, VDD = 3.0V, TAD = 1 S. Microchip Technology Inc. 1.8 2.3 3 VREF FIGURE 33-84: ADC 10-Bit Mode, Single-Ended INL, VDD = 3.0V, TAD = 1 S. DS40001729C-page 417 PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 900 800 ADC VREF+ SET TO VDD ADC VREF- SET TO GND ADC VREF+ SET TO VDD ADC VREF- SET TO GND 700 Max. Max. 800 Typical 600 Min. 700 ADC Output Codes ADC Output Codes Typical 500 Min. 400 300 200 500 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı 400 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı 100 600 300 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.0 6.0 2.5 3.0 FIGURE 33-85: Temperature Indicator Initial Offset, High Range, Temp. = 20°C, PIC16F1705/9 Only. 4.0 4.5 5.0 5.5 6.0 FIGURE 33-86: Temperature Indicator Initial Offset, Low Range, Temp. = 20°C, PIC16F1705/9 Only. 150 800 ADC VREF+ SET TO VDD ADC VREF- SET TO GND 100 Typical 600 Max. Typical ADC VREF+ SET TO VDD ADC VREF- SET TO GND 125 Max. 700 Min. Min. 75 ADC Output Codes ADC Output Codes 3.5 VDD (V) VDD (V) 500 400 300 50 25 0 -25 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı 200 100 1.5 1.8 2.1 2.4 2.7 3.0 3.3 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -50 3.6 -75 3.9 -50 -25 0 25 50 75 100 125 150 Temperature (°C) ( C) VDD (V) FIGURE 33-87: Temperature Indicator Initial Offset, Low Range, Temp. = 20°C, PIC16F1705/9 Only. FIGURE 33-88: Temperature Indicator Slope Normalized to 20°C, High Range, VDD = 5.5V, PIC16LF1705/9 Only. 250 150 ADC VREF+ SET TO VDD ADC VREF- SET TO GND 200 Max. 150 Max. ADC VREF+ SET TO VDD ADC VREF- SET TO GND 125 Typical Typical 100 Min. Min. ADC Output Codes ADC Output Codes 75 100 50 0 -50 50 25 0 -25 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -100 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -50 -150 -75 -50 -25 0 25 50 75 100 125 150 Temperature (°C) ( C) FIGURE 33-89: Temperature Indicator Slope Normalized to 20°C, High Range, VDD = 3V, PIC16F1705/9 Only. DS40001729C-page 418 -50 -25 0 25 50 75 100 125 150 Temperature (°C) ( C) FIGURE 33-90: Temperature Indicator Slope Normalized to 20°C, Low Range, VDD = 3.0V, PIC16F1705/9 Only. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 150 250 200 ADC VREF+ SET TO VDD ADC VREF- SET TO GND Max. ADC VREF+ SET TO VDD ADC VREF- SET TO GND Max. Typical Typical 100 Min. 150 Min. ADC Output Codes ADC Output Codes 100 50 0 50 0 -50 -50 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -100 -100 -150 -50 -25 0 25 50 75 100 125 -50 150 -25 0 25 50 75 100 125 FIGURE 33-91: Temperature Indicator Slope Normalized to 20°C, Low Range, VDD = 1.8V, PIC16LF1705/9 Only. FIGURE 33-92: Temperature Indicator Slope Normalized to 20°C, Low Range, VDD = 3.0V, PIC16LF1705/9 Only. 250 80 ADC VREF+ SET TO VDD ADC VREF- SET TO GND 200 Max. 75 Typical Max. 70 Min. CMRR (dB) ADC Output Codes 150 100 50 65 Typical 60 0 55 -50 50 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -100 -50 -25 0 25 50 75 100 125 Min. Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı 45 -150 40 150 -50 -25 0 25 50 Temperature (°C) Temperature (°C) FIGURE 33-93: Temperature Indicator Slope Normalized to 20°C, High Range, VDD = 3.6V, PIC16LF1705/9 Only. 75 100 125 150 FIGURE 33-94: Op Amp, Common Mode Rejection Ratio (CMRR), VDD = 3.0V. 35% 80 -40°C Sample Size = 3,200 75 25°C 30% Max. 85°C 70 125°C 25% 65 Percent of Units CMRR (dB) 150 Temperature (°C) ( C) Temperature (°C) ( C) Typical 60 55 Min. 20% 15% 10% 50 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı 45 5% 40 -50 -25 0 25 50 Temperature (°C) 75 100 125 FIGURE 33-95: Op Amp, Common Mode Rejection Ratio (CMRR), VDD = 3.0V. Microchip Technology Inc. 150 0% -7 -5 -4 -3 -2 -1 0 1 2 Offset Voltage (mV) 3 4 5 6 7 FIGURE 33-96: Op Amp, Offset Voltage Histogram, VDD = 3.0V, VCM = VDD/2. DS40001729C-page 419 PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 3.8 8 Max. VDD = 3.6V 3.7 6 3.6 Slew Rate (V/μs) Offset Voltage (V) 4 Typical 2 0 -2 VDD = 5.5V 3.5 3.4 VDD = 2.3V 3.3 VDD = 3V 3.2 -4 Min. Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı -6 3.1 3.0 -8 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 -60 5.5 -40 -20 0 FIGURE 33-97: Op Amp, Offset over Common Mode Voltage, VDD = 5.0V, Temp = 25°C PIC16F1705/9 Only. 40 60 80 100 120 140 FIGURE 33-98: Op Amp, Output Slew Rate, Rising Edge, PIC16F1705/9 Only. 5.4 45 5.2 43 -40°C 41 5.0 VDD = 2.3V Hysteresis (mV) Slew Rate (V/μs) 20 Temperature (°C) Common Mode Voltage (V) 4.8 4.6 4.4 VDD = 3.6V 4.2 VDD = 5.5V 39 25°C 37 85°C 35 125°C 33 31 4.0 29 3.8 27 VDD = 3V 25 3.6 -60 -40 -20 0 20 40 60 80 100 120 0.0 140 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Common Mode Voltage (V) Temperature (°C) FIGURE 33-99: Op Amp, Output Slew Rate, Falling Edge, PIC16F1705/9 Only. FIGURE 33-100: Comparator Hysteresis, Normal-Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values. 30 30 25 25 Max. 20 20 15 Offset Voltage (mV) Offset Voltage (mV) Max. 10 5 0 Min. 15 10 5 0 Min. -5 -5 -10 -10 -15 -15 -20 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Common Mode Voltage (V) FIGURE 33-101: Comparator Offset, Normal-Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values at 25°C. DS40001729C-page 420 3.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Common Mode Voltage (V) FIGURE 33-102: Comparator Offset, Normal-Power Mode (CxSP = 1), VDD = 3.0V, Typical Measured Values from -40°C to 125°C. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 30 50 25 45 Hysteresis (mV) Hysteresis (mV) 40 25°C 85°C 35 Max. 20 -40°C 125°C 30 15 10 5 0 Min. -5 -10 25 -15 -20 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 6.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Common Mode Voltage (V) Common Mode Voltage (V) FIGURE 33-103: Comparator Hysteresis, Normal-Power Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values, PIC16F1705/9. FIGURE 33-104: Comparator Offset, Normal-Power Mode (CxSP = 1), VDD = 5.0V, Typical Measured Values at 25°C, PIC16F1705/9 Only. 140 40 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 120 30 Max. Time (ns) Offset Voltage (mV) 100 20 10 80 60 Max. 0 Typical 40 Min. Min. -10 20 -20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 5.5 1.5 2.0 2.5 Common Mode Voltage (V) 3.0 3.5 4.0 VDD (V) FIGURE 33-105: Comparator Offset, Normal-Power Mode (CxSP = 1), VDD = 5.5V, Typical Measured Values from -40°C to 125°C, PIC16F1705/9 Only. FIGURE 33-106: Comparator Response Time over Voltage, Normal-Power Mode (CxSP = 1), Typical Measured Values, PIC16LF1705/9 Only. TYPICAL MEASURED VALUES 90 1,400 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 80 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 1,200 70 1,000 Time (ns) Time (ns) 60 50 Max. 40 Typical 800 600 30 Min. 400 Max. 20 Typical 200 10 Min. 0 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-107: Comparator Response Time over Voltage, Normal-Power Mode (CxSP = 1), Typical Measured Values, PIC16F1705/9 Only. Microchip Technology Inc. 1.5 2.0 2.5 3.0 3.5 4.0 VDD (V) FIGURE 33-108: Comparator Output Filter Delay Time over Temperature, Normal-Power Mode, Typical Measured Values, PIC16LF1705/9 Only. DS40001729C-page 421 PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. TYPICAL MEASURED VALUES 0.025 800 -40°C 0.020 Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 700 25°C 85°C 0.015 125°C 600 500 DNL (LSb) Time (ns) 0.010 400 300 0.005 0.000 -0.005 Max. 200 -0.010 Typical 100 -0.015 Min. 0 -0.020 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 16 32 48 64 80 96 VDD (V) FIGURE 33-109: Comparator Output Filter Delay Time over Temperature, Normal-Power Mode, Typical Measured Values, PIC16F1705/9 Only. 112 128 144 160 176 192 208 224 240 Output Code FIGURE 33-110: Typical DAC DNL Error, VDD = 3.0V, VREF = External 3V. 0.00 0.020 -0.05 0.015 -40°C 25°C 85°C -0.10 125°C 0.010 DNL (LSb) INL (LSb) -0.15 -0.20 -0.25 -0.30 0.000 -0.005 -40°C -0.35 0.005 25°C -0.010 85°C -0.40 125°C -0.015 -0.45 0 16 32 48 64 80 96 0 112 128 144 160 176 192 208 224 240 Output Code FIGURE 33-111: Typical DAC INL Error, VDD = 3.0V, VREF = External 3V. 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code FIGURE 33-112: Typical DAC INL Error, VDD = 5.0V, VREF = External 5V, PIC16F1705/9 Only. 0.00 24 -0.05 Max. 22 -0.10 20 DNL (LSb) INL (LSb) -0.15 -0.20 -0.25 18 Typical 16 -0.30 14 -40°C -0.35 Min. 25°C Max: Typical + 3ı (-40°C to +125°C) Typical; statistical mean @ 25°C Min: Typical - 3ı (-40°C to +125°C) 12 85°C -0.40 125°C 10 -0.45 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 Output Code FIGURE 33-113: Typical DAC INL Error, VDD = 5.0V, VREF = External 5V, PIC16F1705/9 Only. DS40001729C-page 422 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 Output Code FIGURE 33-114: DAC INL Error, VDD = 3.0V, PIC16LF1705/9 Only. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 0.4 0.45 Vref = Int. Vdd Vref = Ext. 1.8V 0.2 Vref = Ext. 2.0V 0.15 0.2 Vref = Ext. 3.0V 0.1 0.05 0 50 Temperature (°C) 100 Absolute Absolute INL (LSb) INL (LSb) VREF = EXT. 3.0V 0.25 -50 -40 -20 0 20 40 60 Temperature (°C) ( C) 80 VREF = EXT. 2.0V -2.5 VREF = EXT. 3.0V 0.86 -2.7 -40 25 -2.9 0.84 -3.1 85 125 -3.3 0.82 -3.5 0.0 0.80 150 0.0 -60 VREF = EXT. 1.8V -2.3 0.88 VREF = EXT. 2.0V 0.3 0.3 0.10 VREF = INT. VDD VREF = EXT. 1.8V 0.35 Absolute Absolute DNL (LSb) DNL (LSb) 0.90 -2.1 VREF = INT. VDD 0.4 100 120 2.0 3.0 Temperature (°C) 4.0 5.0 0.78 140 FIGURE 33-115: Absolute Value of DAC DNL Error, VDD = 3.0V, VREF = VDD. 1.0 -60 -40 -20 0 20 40 60 Temperature (°C) ( C) 80 100 120 140 FIGURE 33-116: Absolute Value of DAC INL Error, VDD = 3.0V, VREF = VDD. 0.30 0.3 0.85 VREF = INT. VDD 0.25 0.80 VREF = EXT. 2.0V -40°C VREF = EXT. 3.0V 0.15 0.22 -40 VREF = EXT. 5.0V 25 85 0.1 125 0.18 0.05 ZCD Pin Voltage (V) Absolute Absolute DNL (LSb) DNL (LSb) VREF = EXT. 1.8V 0.26 0.2 0 0.14 0.0 1.0 2.0 3.0 4.0 Temperature (°C) 5.0 0.75 25°C 0.70 85°C 125°C 0.65 6.0 0.60 2.0 0.10 -60 -40 -20 0 20 40 60 Temperature (°C) ( C) 80 100 120 2.5 3.0 3.5 140 FIGURE 33-117: Absolute Value of DAC DNL Error, VDD = 5.0V, VREF = VDD, PIC16F1705/9 Only. 4.0 4.5 5.0 5.5 6.0 VDD (V) FIGURE 33-118: Measured Values. ZCD Pin Voltage. Typical 8.0 1.4 5.5V 1.2 Fall-3.0V Fall-5.5V Time (μs) 1.0 0.8 0.6 0.4 Rise-2.3V Rise-3.0V Rise-5.5V 0.2 0.0 -50 -25 0 25 50 75 Temperature (°C) 100 125 150 FIGURE 33-119: ZCD Response Time over Voltage, Typical Measured Values. Microchip Technology Inc. ZCD Source/Sink Current (mA) Fall-2.3V 3.0V 6.0 2.3V 4.0 1.8V 2.0 0.0 -2.0 -4.0 -0.20 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 2.20 ZCD Pin Voltage (V) FIGURE 33-120: ZCD Pin Current over ZCD Pin Voltage, Typical Measured Values from -40°C to 125°C. DS40001729C-page 423 PIC16(L)F1705/9 Note: Unless otherwise noted, VIN = 5V, FOSC = 500 kHz, CIN = 0.1 µF, TA = 25°C. 0.28 1.00 0.26 0.90 0.80 Time (μs) 0.24 Time (μs) 0.70 0.60 0.22 0.20 0.50 0.18 0.40 0.30 1.8V 0.20 3.0V 125°C 85°C 25°C -40°C 0.16 2.3V 0.14 5.5V 1.5 0.10 0 100 200 300 400 2.0 2.5 3.0 500 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) ZCD Source/Sink Current (uA) FIGURE 33-122: COG Dead-Band Delay, DBR/DBF = 32, Typical Measured Values. 9.0 0.45 8.5 0.40 8.0 0.35 7.5 0.30 7.0 0.25 Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı Max. Typical Min. Time (μs) Time (ns) FIGURE 33-121: ZCD Pin Response Time Over Current, Typical Measured Values from -40°C to 125°C. 6.5 6.0 0.20 0.15 5.5 0.10 125°C 85°C 25°C -40°C 5.0 0.05 4.5 0.00 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 10 20 30 40 50 60 70 DBR/DBF Value VDD (V) FIGURE 33-123: COG Dead-Band DBR/DBF Delay Per Step, Typical Measured Values. FIGURE 33-124: COG Dead-Band Delay per Step, Typical Measured Values. 0.07 Max. Max: Typical + 3ı Typical; statistical mean Min: Typical - 3ı 0.06 Typical 0.05 Min. Time (μs) 0.04 0.03 0.02 0.01 0.00 0 1 2 3 4 5 6 7 8 9 10 11 DBR/DBF Value FIGURE 33-125: COG Dead-Band Delay per Step, Zoomed to First 10 Codes, Typical Measured Values. DS40001729C-page 424 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 34.0 DEVELOPMENT SUPPORT The PIC® microcontrollers (MCU) and dsPIC® digital signal controllers (DSC) are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® X IDE Software • Compilers/Assemblers/Linkers - MPLAB XC Compiler - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB X SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers/Programmers - MPLAB ICD 3 - PICkit™ 3 • Device Programmers - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits • Third-party development tools 34.1 MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and hardware development tool that runs on Windows®, Linux and Mac OS® X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: • Color syntax highlighting • Smart code completion makes suggestions and provides hints as you type • Automatic code formatting based on user-defined rules • Live parsing User-Friendly, Customizable Interface: • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. • Call graph window Project-Based Workspaces: • • • • Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: • Local file history feature • Built-in support for Bugzilla issue tracker 2013-2015 Microchip Technology Inc. DS40001729C-page 425 PIC16(L)F1705/9 34.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility 34.3 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: 34.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 34.5 MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility • Integration into MPLAB X IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multipurpose source files • Directives that allow complete control over the assembly process DS40001729C-page 426 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 34.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 34.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradeable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 2013-2015 Microchip Technology Inc. 34.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 34.9 PICkit 3 In-Circuit Debugger/ Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer’s PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial Programming™ (ICSP™). 34.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. DS40001729C-page 427 PIC16(L)F1705/9 34.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. 34.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. • Device Programmers and Gang Programmers from companies, such as SoftLog and CCS • Software Tools from companies, such as Gimpel and Trace Systems • Protocol Analyzers from companies, such as Saleae and Total Phase • Demonstration Boards from companies, such as MikroElektronika, Digilent® and Olimex • Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika® The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. DS40001729C-page 428 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 35.0 PACKAGING INFORMATION 35.1 Package Marking Information 14-Lead PDIP (300 mil) Example PIC16F1705 -I/P e3 1304017 28-Lead SOIC (7.50 mm) 14-Lead SOIC (3.90 mm) Example Example PIC16F1705 -I/SL e3 1304017 14-Lead TSSOP (4.4 mm) Example XXXXXXXX YYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: F1705IST 1304 017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC® designator e( 3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2013-2015 Microchip Technology Inc. DS40001729C-page 429 PIC16(L)F1705/9 Package Marking Information (Continued) 16-Lead QFN (4x4x0.9 mm) PIN 1 Example PIN 1 PIC16 F1705 ML 130417 e3 20-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SSOP (5.30 mm) Example PIC16F1709 E/P e3 130417 Example PIC16F1709 SS e3 130417 Legend: XX...X Y YY WW NNN e3 * Note: DS40001729C-page 430 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC® designator e( 3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Package Marking Information (Continued) 20-Lead SOIC (7.50 mm) Example PIC16F1709 SO e3 130417 20-Lead QFN (4x4x0.9 mm) PIN 1 Example PIN 1 PIC16 F1709 ML 130417 e3 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC® designator e( 3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 2013-2015 Microchip Technology Inc. DS40001729C-page 431 PIC16(L)F1705/9 35.2 Package Details The following sections give the technical details of the packages. 3 %& %!%4") ' % 4$% %"% %%255)))& &54 N NOTE 1 E1 1 3 2 D E A2 A L A1 c b1 b e eB 6% & 9&% 7!&( $ 7+8- 7 7 7: ; % % % < < ""44 0 , 0 1 % % 0 < < !"% !"="% - , ,0 ""4="% - 0 > :9% ,0 0 0 % % 9 0 , 0 9"4 > 0 ( 0 ? ( > 1 < < 69"="% 9 )9"="% : )* 1+ , !"#$%!&'(!%&! %( %")%%%" *$%+% % , & "-" %!"& "$ %! "$ %! %#". " & "% -/0 1+21 & %#%! ))% !%% ) +01 DS40001729C-page 432 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc. DS40001729C-page 433 PIC16(L)F1705/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001729C-page 434 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 3 %& %!%4") ' % 4$% %"% %%255)))& &54 2013-2015 Microchip Technology Inc. DS40001729C-page 435 PIC16(L)F1705/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001729C-page 436 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc. DS40001729C-page 437 PIC16(L)F1705/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001729C-page 438 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 16-Lead Plastic Quad Flat, No Lead Package (ML) - 4x4x0.9mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A B N NOTE 1 1 2 E (DATUM B) (DATUM A) 2X 0.15 C 2X TOP VIEW 0.15 C 0.10 C C A1 A SEATING PLANE 16X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 0.10 C A B E2 2 e 2 1 NOTE 1 K N 0.40 16X b 0.10 e C A B BOTTOM VIEW Microchip Technology Drawing C04-127D Sheet 1 of 2 2013-2015 Microchip Technology Inc. DS40001729C-page 439 PIC16(L)F1705/9 16-Lead Plastic Quad Flat, No Lead Package (ML) - 4x4x0.9mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits N Number of Pins e Pitch A Overall Height A1 Standoff A3 Contact Thickness E Overall Width E2 Exposed Pad Width D Overall Length D2 Exposed Pad Length b Contact Width Contact Length L Contact-to-Exposed Pad K MIN 0.80 0.00 2.50 2.50 0.25 0.30 0.20 MILLIMETERS NOM 16 0.65 BSC 0.90 0.02 0.20 REF 4.00 BSC 2.65 4.00 BSC 2.65 0.30 0.40 - MAX 1.00 0.05 2.80 2.80 0.35 0.50 - Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-127D Sheet 2 of 2 DS40001729C-page 440 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc. DS40001729C-page 441 PIC16(L)F1705/9 ! 3 %& %!%4") ' % 4$% %"% %%255)))& &54 N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e 6% & 9&% 7!&( $ 7+8- 7 7 7: ; % % % < < ""44 0 , 0 1 % % 0 < < !"% !"="% - , , ,0 ""4="% - 0 > :9% > , ? % % 9 0 , 0 9"4 > 0 ( 0 ? ( > 1 < < 69"="% 9 )9"="% : )* 1+ , !"#$%!&'(!%&! %( %")%%%" *$%+% % , & "-" %!"& "$ %! "$ %! %#". " & "% -/0 1+2 1 & %#%! ))% !%% ) +1 DS40001729C-page 442 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 ! "#$%"&""'(""& 3 %& %!%4") ' % 4$% %"% %%255)))& &54 D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 6% & 9&% 7!&( $ L 99-- 7 7 7: ; % :8% < ?01+ < ""44 ?0 0 >0 %" $$ 0 < < :="% - > > ""4="% - 0 0, 0? :9% ? 0 3 %9% 9 00 0 0 3 %% 9 0-3 9"4 < 3 % V V 0 >V 9"="% ( < ,> !"#$%!&'(!%&! %( %")%%%" & "-" %!"& "$ %! "$ %! %#"&& " , & "% -/0 1+2 1 & %#%! ))% !%% -32 $& '! !)% !%% '$ $ &% ! ) +1 2013-2015 Microchip Technology Inc. DS40001729C-page 443 PIC16(L)F1705/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001729C-page 444 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc. DS40001729C-page 445 PIC16(L)F1705/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001729C-page 446 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2013-2015 Microchip Technology Inc. DS40001729C-page 447 PIC16(L)F1705/9 ! )*+ %,-..(/)* 3 %& %!%4") ' % 4$% %"% %%255)))& &54 D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 6% & 9&% 7!&( $ 99-- 7 7 7: ; % :8% > %" $$ 0 + %%4 , :="% - -# ""="% - :9% -# ""9% 01+ -3 1+ ? > 1+ ? > + %%="% ( > 0 , + %%9% 9 , 0 + %%% -# "" W < < !"#$%!&'(!%&! %( %")%%%" 4 ) !%" , & "% -/0 1+2 1 & %#%! ))% !%% -32 $& '! !)% !%% '$ $ &% ! ) +?1 DS40001729C-page 448 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 3 %& %!%4") ' % 4$% %"% %%255)))& &54 2013-2015 Microchip Technology Inc. DS40001729C-page 449 PIC16(L)F1705/9 APPENDIX A: DATA SHEET REVISION HISTORY Revision A (12/2013) Initial release of this document. Revision B (04/2015) Updated Sections 8.2.2, 20.1.2, 20.1.3, 21.1, 21.1.1, 22.3, 28.2.1, 29.4.2, 32.0 (“Electrical Specifications”) and 33.0 (“DC and AC Characteristics Graphs and Charts”); Updated introductory paragraph of Section 21.0; Added Sections 3.2 (“High-Endurance Flash”) and 6.5.5 (“Clock Switch Before Sleep”); Updated Tables 1, 2, 1-2, 3-1, 3-3, 3-4, 3-5, 6-1; Updated note references, bit 2 and values on POR, BOR and all other Resets for the ADCON1 register in Table 3-10; Updated Figures 3-1, 6-7, 18-2 through 18-6, 20-1, 22-1 and 25-1; Added note to Figure 21-1; Updated Registers 20-1, 20-2 and 21-1; Other minor corrections. Revision C (12/2015) Updated graphs in Section 33.0. Added High Endurance Flash Data Memory (HEF) bullet on front page. Updated PIC16(L)F170x Family Types Table. Removed Section 18.1.1 Steering (All Modes). Updated new Section 18.1.1 Steered PWM Modes. Updated Figures 32-1, 32-2, and 32-5; Register 25-1; Sections 18.2, 32.1, and 35.1; Tables 32-1, 32-2, 32-7, 32-9, 32-10, 32-11, 32-13, 32-14, 32-15, 32-19, 32-21, and 32-22. DS40001729C-page 450 2013-2015 Microchip Technology Inc. PIC16(L)F1705/9 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://www.microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. 2013-2015 Microchip Technology Inc. DS40001729C-page 451 PIC16(L)F1705/9 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X](1) PART NO. Device - X Tape and Reel Temperature Option Range /XX XXX Package Pattern Examples: a) b) Device: PIC16F1705, PIC16LF1705, PIC16F1709, PIC16LF1709 Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C = -40C to +125C Package:(2) ML P SP ST SL SO SS = = = = = = = Pattern: (Industrial) (Extended) QFN PDIP SPDIP TSSOP SOIC SOIC SSOP QTP, SQTP, Code or Special Requirements (blank otherwise) DS40001729C-page 452 PIC16LF1705- I/P Industrial temperature PDIP package PIC16F1709- E/SS Extended temperature, SSOP package Note 1: 2: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Small form-factor packaging options may be available. Please check www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office. 2013-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2013-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0070-7 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2013-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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