IRS2153(1)D and IR2153(1)/IR2153(1)D Comparison

Application Note AN-1085revC
IRS2153(1)D and IR2153(1)/IR2153(1)D Comparison
Table of Contents
Page
Introduction...................................................................................................................................... 1
Block Diagrams............................................................................................................................. 2
IR2153(1)/IR2153(1)D vs. IRS2153(1)D Electrical Characteristics Differences.................... 4
Conclusions..................................................................................................................................... 7
1. INTRODUCTION
The new IRS2153(1)D replaces the existing IR2153(1)/IR2153(1)D HVICs advantageously by saving the need for an
external bootstrap diode. It is based on the same core design and is pin-to-pin compatible, allowing minimum changes
to the previous design. This application note describes the differences between the existing IR2153(1)/IR2153(1)D IC
family and the new IRS2153(1)D.
2. BLOCK DIAGRAMS
The IR2153(1)/IR2153(1)D is not a single IC, but consists of a family of ICs (Table I).
P/N
IR2153PbF
IR2153SPbF
IR21531PbF
IR21531SPbF
IR2153DPbF
IR2153DSPbF
IR21531DPbF
IR21531DSPbF
Deadtime (typ.)
1.2 μs
1.2 μs
0.6 μs
0.6 μs
1.2 μs
1.2 μs
0.6 μs
0.6 μs
Internal Bootstrap Diode
No
No
No
No
Yes
Yes
Yes
Yes
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Package Type
DIP8
SO8
DIP8
SO8
DIP8
SO8
DIP8
SO8
1
The functional block diagrams of each IC (Figs. 1 and 2) are exactly the same except the internal bootstrap diode.
Figure 1: IR2153(1) Functional Block Diagram
Figure 2: IR2153(1)D Functional Block Diagram
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In the new IRS2153(1)D IC (Fig. 3), an internal FET now replaces the internal bootstrap diode, which was previously a
separate die. IRS2153(1)D has the same functionality as IR2153(1)D and the need for an additional diode has been
eliminated.
Figure 3: IRS2153(1)D Functional Block Diagram
Consequently: a customer using IR2153(1)/IR2153(1)D should take particular care of the bootstrap circuitry
when switching to IRS2153(1)D.
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3. IR2153(1)/IR2153(1)D vs. IRS2153(1)D ELECTRICAL CHARACTERISTICS DIFFERENCES
The following tables and comments highlight the differences between the IR2153(1)/IR2153(1)D and the new IRS2153(1)D:
Absolute Maximum Ratings
Parameter
Symbol
IR2153(1)/IR2153(1)D
Definition
IRS2153(1)D
Units
min
max
min
max
-0.3
625
-0.3
625
V
VB
High side floating supply voltage
VS
High side floating supply offset voltage
VB - 25
VB + 0.3
VB - 25
VB + 0.3
VHO
High side floating output voltage
VS - 0.3
VB + 0.3
VS - 0.3
VB + 0.3
V
V
V
VLO
Low side output voltage
-0.3
VCC + 0.3
-0.3
VCC + 0.3
V
IRT
RT pin current
-5
5
-5
5
mA
VRT
RT pin voltage
-0.3
VCC + 0.3
-0.3
VCC + 0.3
VCT
CT pin voltage
-0.3
VCC + 0.3
-0.3
VCC + 0.3
V
V
V
ICC
Supply current (Note 1)
---
25
---
20
IOMAX
Maximum allowable current at LO and HO due to
external power transistor Miller effect
-500
500
mA
mA
mA
dVS/dt
Allowable offset voltage slew rate
-50
50
-50
50
V/ns
PD
Max. power dissipation @ TA ≤ +25 ºC, 8-Pin DIP
---
1.0
---
1.0
PD
Max. power dissipation @ TA ≤ +25 ºC, 8-Pin SOIC
---
0.625
---
0.625
W
W
W
RthJA
Thermal resistance, junction to ambient, 8-Pin DIP
---
125
---
85
ºC/W
oC/W
RthJA
Thermal resistance, junction to ambient, 8-Pin SOIC
---
200
---
128
ºC/W
TJ
Junction temperature
-55
150
-55
150
TS
Storage temperature
-55
150
-55
150
TL
Lead temperature (soldering, 10 seconds)
---
300
---
300
ºC
Comments: All absolute maximum ratings are exactly the same except for the maximum supply current limit and the
thermal resistance. The maximum supply current is rated at 20 mA for the new IRS2153(1)D versus 25 mA for the
IR2153(1)/IR2153(1)D and is due to the internal zener clamp. A 20 mA maximum versus 25 mA should be a negligible
amount for most applications. A lower thermal resistance will give lower temperatures on the package surface.
Recommended Operating Conditions
Parameter
Symbol
VBS
IR2153(1)/IR2153(1)D
Definition
High side floating supply voltage
VS
Steady state high side floating supply offset voltage
VCC
Supply voltage
ICC
Supply current
TJ
Junction temperature
IRS2153(1)D
Units
min
max
min
max
VCC - 0.7
VCLAMP
VCC - 0.7
VCLAMP
V
-3.0
600
-3.0
600
V
V
10
VCLAMP
VCCUV+ + 0.1V
VCLAMP
V
5
mA
125
ºC
5
-40
125
-40
Comments: All parameters are mostly the same.
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Recommended Component Values
Parameter
Symbol
Definition
RT
CT
IR2153(1)/IR2153(1)D
IRS2153(1)D
Units
min
max
min
max
Timing resistor value
1
---
1
---
kΩ
CT pin capacitor value
330
---
330
---
pF
Comments: All parameters are exactly the same.
Electrical Characteristics
Bootstrap FET/Diode Characteristics
Symbol
VF
Definition
Bootstrap diode forward voltage (IR2153(1)D)
IR2153(1)/IR2153(1)D
Min
Typ
Max
0.5
---
1.0
IRS2153(1)D
Min
Typ
Max
VB_ON
VB when the bootstrap FET is on
---
13.7
---
IB_CAP
VB source current when bootstrap FET is on
40
55
---
IB_10V
VB source current when bootstrap FET is on
10
12
Units
Test
Conditions
V
IF = 250 mA
V
V
mA
CBS=0.1 µF
mA
VB=10 V
mA
Comments: The IRS2153(1)D contains an integrated bootstrap MOSFET that eliminates the need for an external highvoltage bootstrap diode. The integrated bootstrap MOSFET is turned on only during the time when LO is ‘high’, and has
a limited source current due to RDSon. The VBS voltage will determined each cycle by on the on-time of LO, the size of
the external MOSFETs and the value of the CBS capacitor. At start-up, several cycles of LO will occur first until VBS
increases above VBSUV+ (see Floating Supply Characteristics) and then HO will start to oscillate. The maximum operating frequency will be determined by the MOSFET driven by IRS2153(1)D and the value of the CBS capacitor since the
bootstrap MOSFET needs to maintain VBS above VBSUV- each cycle. If the frequency is too high, VBS will fall below
VBSUV- and the HO output will turn off. To avoid this problem, an external high-voltage bootstrap diode can be added in
parallel to maintain VBS above VBSUV- during high-frequency applications.
Low Voltage Supply Characteristics
Symbol
Definition
IR2153(1)/IR2153(1)D
IRS2153(1)D
Min
Typ
Max
Min
Typ
M ax
Units
Test
Conditions
VCCUV+
Rising VCC undervoltage lockout threshold
8.1
9.0
8.1
10.0
11.0
12.0
VCCUV-
Falling VCC undervoltage lockout
threshold
t threshold
7.2
8.0
7.2
8.0
9.0
10.0
VCC undervoltage lockout hysteresis
0.5
1.0
0.5
1.6
2.0
2.4
Micropower startup VCC supply current
---
75
150
---
130
170
IQCC
Quiescent VCC supply current
---
500
950
---
800
1000
ICC
VCC supply current
---
1.8
---
mA
R T =36.9 kΩ
14.4
15.4
16.8
V
ICC = 5 mA
VCCUVHYS
IQCCUV
VCLAMP
VCC zener clamp voltage
14.4
15.6
16.8
V
µA
V CC ≤ V CCUV-
Comments: No major changes other than VCCUV+ and VCCUV- being higher, as well as the hysteresis. The higher UVLO
thresholds should not impact the application since typically VCC is regulated against its internal 15.4 V clamp voltage.
The increased hysteresis should make the application more robust and prevent the IC from turning off momentarily
should transient dips in the VCC voltage occur.
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Floating Supply Characteristics
Symbol
IQBS
VBSUV+
Definition
Quiescent VBS supply current
IR2153(1)/IR2153(1)D
IRS2153(1)D
Min
Typ
Max
Min
Typ
Max
---
30
50
---
60
80
8.0
9.0
9.5
VBS supply undervoltage positive going
threshold
Test
Conditions
Units
µA
V
VBSUV-
VBS supply undervoltage negative going
threshold
IQBSUV-
Micropower startup VBS supply current
---
0
10
µA
VCC ≤ VCCUV-,
VCC = VBS
VBSMIN
Minimum required VBS voltage for proper
functionality from RT to HO
---
4.0
5.0
V
VCC = VCCUV- + 0.1 V
Offset supply leakage current
---
---
50
µA
VB = VS = 600 V
ILK
7.0
---
8.0
---
9.0
50
Comments: The new IRS2153(1)D contains an under-voltage lockout circuit. This is necessary because of the
additional integrated bootstrap MOSFET. The UVLO circuit will guarantee that VBS is high enough before turning on HO
and will protect the external MOSFET from being driven in the linear region should VBS decrease too much.
Oscillator I/O Characteristics
Symbol
f OSC
Definition
Oscillator frequency
IR2153(1)/IR2153(1)D
IRS2153(1)D
Min
Typ
Max
Min
Typ
Max
19.4
20
20.6
18.4
19.0
19.6
94
100
106
88
93
100
Units
kHz
d
RT pin duty cycle
48
50
52
---
50
---
%
ICT
CT pin current
---
0.001
1.0
---
0.02
1.0
µA
mA
Test Conditions
RT= 36.9/36.5 kΩ
RT= 7.43/7.15 kΩ
fo < 100 kHz
ICTUV
UV-mode CT pin pulldown current
0.30
0.70
1.2
0.2
0.3
0.6
VCT+
Upper CT ramp voltage threshold
---
8.0
---
---
9.32
---
VCT-
Lower CT ramp voltage threshold
---
4.0
---
---
4.66
---
CT voltage shutdown threshold
1.8
2.1
2.4
2.2
2.3
2.4
---
10
50
---
10
50
IRT = -100 µA
---
100
300
---
100
300
IRT = -1 mA
---
10
50
---
10
50
IRT = 100 µA
---
100
300
---
100
300
IRT = 1 mA
---
0
100
---
0
100
---
10
50
---
10
50
---
100
300
---
100
300
VCTSD
VRT+
High-level RT output voltage, VCC - VRT
VRT-
Low-level RT output voltage
VRTUV
UV-mode RT output voltage
VRTSD
SD-mode RT output voltage, VCC - VRT
VCC = 7 V
V
mV
VCC ≤ VCCUVIRT = -100 µA,
VCT = 0 V
IRT = -1 mA,
VCT = 0 V
Comments: The new IRS2153(1)D should fit into an existing design and maintain existing performance without any
changes to the design with the exception of RT/CT value.
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IR2153(1)/IR2153(1)D
Gate Driver Output Characteristics
Symbol
Definition
IRS2153(1)D
Min
Typ
Max
Min
Typ
Max
VOH
High level output voltage
---
0
100
---
VCC
---
VOL
Low level output voltage, VO
---
0
100
---
COM
---
VOL_UV
UV-mode output voltage, VO
---
0
100
---
COM
---
tr
Output rise time
---
80
150
---
120
220
tf
Output fall time
---
45
100
---
50
80
tsd
Shutdown propagation delay
td
Output deadtime
(HO or LO)
---
660
---
---
350
---
0.75
0.35
1.20
0.6
1.65
0.85
0.65
0.35
1.10
0.6
1.75
0.85
I O+
Output source current
---
180
---
I O+
Output sink current
---
260
---
2153D
21531D
Units
Test
Conditions
IO = 0 A
mV
IO = 0 A
IO = 0 A ,
VCC ≤ VCCUV-
ns
µs
mA
Comments: Output rise and fall times are slightly longer due to a slight decrease in the output source and sink
currents Deadtime tolerances had to be slightly downgraded, but should not impact most applications.
3. Conclusions
In most cases, any member for the IR2153(1)/IR2153(1)D family will be easily and advantageously replaced by the new
leadfree IRS2153(1)D. The application will benefit a monolithic solution integrating a bootstrap FET, an increased UVLO
hysteresis, a possibility of non-latch IC shutdown, better thermal behavior and ROHS compatibility while keeping a 3%
tolerance on the frequency.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 7/242006
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