Product Information High Voltage SLA6820M and SMA6820MP Series Driver ICs for 3-Phase DC Motor Applications Introduction The SLA6820M and SMA6820MP Series power packages incorporate all of the necessary power control components to configure the main circuit of an inverter power module (IPM). These products are especially suitable for driving the inverters of low-capacity motors, such as those used in 100 to 200 V fans for air conditioners. Leadform 2452 (SMA) Features and benefits include the following: ▪ Built-in pre-driver ICs and three bootstrap diodes as a high-side drive power supply ▪ CMOS-compatible input (5 V) ▪ High-side gate driver using bootstrap circuit or floating power supply ▪ One pin for 7.5 V regulator output ▪ Built-in protection circuit for controlling power supply voltage drop (UVLO) ▪ Built-in overtemperature detection circuit (TD) ▪ Fault signal output during operation of protection circuit ▪ Output current up to 2.5 A continuous ▪ Small SIP (SLA and SMA, 24 pins) Leadform 2451 (SMA) Functional Description The functional block diagram is shown in figure 2. High voltage power and 15 VDC are input between VBB and LS1/LS2, between VCC1 and COM1, and between VCC2 and COM2. The on/off signals of the power MOSFETs are operated by six signals: HIN1, HIN2, HIN3, LIN1, LIN2, and LIN3. These input signals are positive logic (the MOSFET turns on at VxINx = high). The boot capacitors are connected between VB1 and U, VB2 and V, and VB3 and W1, as the high voltage power source. Leadform 2171 (SLA) Leadform 2175 (SLA) Figure 1. SLA6820M and SMA6820MP Series packages are fully molded SIPs, offering compact configurations both horizontal mount (leadforms 2451 and 2175) and vertical mount (leadforms 2452 and 2171). The SLA packages feature an aluminum heatsink pad for mounting external heatsinks. Product Lineup MOSFET Rating Input Voltage (VAC) Heatsink Pad SLA6826M 250 V / 2 A 120 Yes SLA6827M 500 V / 1.5 A 230 Yes SLA6828M 500 V / 2.5 A 230 Yes SMA6821MP 250 V / 2 A 120 No SMA6822MP 500 V / 1.5 A 230 No SMA6823MP 500 V / 2.5 A 230 No Type SLASMA6820Mx-AN, Rev. 2 Contents Introduction Functional Description Protection Functions Application Circuit Recommendations Electrical Characteristics Data 1 1 7 10 10 VB1 VB2 VB3 VD VBB 1 VCC1 VBB 2 UVLO HIN1 HIN2 HIN3 Input Logic UVLO UVLO UVLO High-Side Level Shift Driver COM1 VCC 2 7.5V Reg. VREG UVLO Overtemperature Detect Input Logic Low-Side Driver LIN1 LIN2 LIN3 COM 2 U V W1 W2 LS2 LS1 FO Heatsink Tab (SLA only) Figure 2. SLA6820M and SMA6820MP Series Functional Block Diagram. These devices support high-side and low-side three-phase MOSFET output drivers. Terminal List Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Tab Name VB1 VB2 VD VB3 VCC1 COM1 HIN3 HIN2 HIN1 VBB1 VBB2 W1 V W2 LS2 VREG LS1 LIN3 LIN2 LIN1 COM2 FO VCC2 U – Function High-side bootstrap terminal (U phase) High-side bootstrap terminal (V phase) Bootstrap diodes anode terminal High-side bootstrap terminal (W phase) High-side logic supply voltage High-side logic GND terminal High-side input terminal (W phase) High-side input terminal (V phase) High-side input terminal (U phase) Main supply voltage 1 (connect to VBB2 externally) Main supply voltage 2 (connect to VBB1 externally) Output of W phase (connect to W2 externally) Output of V phase Output of W phase (connect to W1 externally) Low-side emitter terminal (connect to LS1 externally) Internal regulator output terminal Low-side emitter terminal (connect to LS2 externally) Low-side input terminal (W phase) Low-side input terminal (V phase) Low-side input terminal (U phase) Low-side GND terminal Overtemperature and low-side UVLO fault-signal output Low-side logic supply voltage Output of U phase (SLA only) Electrically isolated heatsink/external heatsink mounting tab Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 The protection functions, including overtemperature detection (at abnormal ambient temperature, overload, and so forth), and undervoltage of low control power supply voltage (at instantaneous fall, and so forth) are built-in and when any of these functions is operated, it can be monitored at the fault output terminal, FO. Structural Description The external configurations of the device packages are shown in figure 1. The device cases are molded epoxy resin. The surface of each package has branding that includes the part number and lot number. As shown in figure 3, the backside of SLA6820M series provides an aluminum heatsink tab. It is electrically isolated from the leadframe. It can be attached to external heatsinks by means of one or two M3 screws. The devices each have 11 embedded die, including six power MOSFETs, two pre-driver ICs, and three bootstrap diodes. These die are mounted on a copper leadframe and connected with gold wire between die and from die to leadframe (figure 3). Terminal Descriptions A summary description of the function of the various terminals is given in the Terminal List table. Pin 1 for the package appears in figure 5. This section provides detailed functional descriptions of the individual pins. U, V, W1, and W2 These are the output terminals that are connected to the motor. W1 and W2 must be tied together externally on the printed circuit board (PCB) with a trace of minimum length. VD, VB1, VB2, and VB3 Power supply terminals for driving the high-side MOSFETs. As shown in figure 4, a bootstrap capacitor, CBOOTx, must be connected between VB1 and U, VB2 and V, and VB3 and W. A bootstrap capacitor circuit is required on each high-side bridge, because they operate independently of each other. The bootstrap capacitors, CBOOTx, must be charged at startup. Before charging CBOOT, the corresponding low-side MOSFET must be turned on. The IC has a built-in 22 Ω ±20% serial resistor and a bootstrap diode (600 V / 1 A). In applications in which 22 Ω is not sufficient, an external resistor can be added between VCC and the VD pin. The following factors should be considered when determining the parameters of the bootstrap circuit. First, the optimal value for the bootstrap capacitor, CBOOT, varies according to the driving method (modulation method and output frequency), the switching frequency (carrier frequency), the modulation ratio (duty cycle), and the gate input capacity of the driving MOSFETs. The following table provides an example for three-phase modulation with 90% duty cycle: VBB VD Epoxy resin case Gold wire VBx VBB CBOOT charge current Die Copper leadframe High Side Drive Circuit Resin isolation layer VCC CBOOT U,V,W Aluminum heatsink To Motor Low Side Drive Circuit LS Figure 3. SLA Package Cross-section View Figure 4. Connection of Bootstrap Capacitor. There is a separate CBOOT capacitor for each of the three phases. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Gate protrusion 31.3 ±0.2 4 ±0.2 31 ±0.2 (A) 2X Gate protrusion 1.2 ±0.1 BSC 10.2 ±0.2 3 ±0.5 BSC 2X Exposed tie bar 2.2 ±0.7 BSC R1 REF 4.4 REF 1 +0.15 C 0.7 – 0.05 Gate protrusion 1.27 ±0.1 A 1.27 ±0.6 B 0.6 +0.15 – 0.05 2.2 ±0.7 BSC 0.55 +0.2 – 0.1 31.3 ±0.2 4 ±0.2 31 ±0.2 (B) 2X Gate protrusion 1.2 ±0.1 BSC 10.2 ±0.2 2X Exposed tie bar R1 REF 5 ±0.5 9.5 +0.7 – 0.5 0.5 +0.15 – 0.05 4.5 REF 1 1.27 ±0.5 A 4.5 ±0.5 0.6 +0.15 – 0.05 Figure 5. Package Outline Drawings. (A) LF2451, L-bend horizontal mount, (B) LF2452, vertical mount. 31.3 ±0.1 31 ±0.2 24.4 ±0.2 16.4 ±0.2 Gate protrusion (A) 4.8 ±0.2 0.6 Exposed heatsink pad 1.7 ±0.1 Ø3.2 ±0.15 Ø3.2 ±0.15 2X Gate protrusion 2.45 ±0.1 BSC 16 ±0.2 B 12.9 ±0.2 3 ±0.3 BSC 9.9 ±0.1 Branding Area 2X Exposed tie bar 2.2 ±0.6 BSC R1 REF 4.4 REF 0.6 +0.2 – 0.1 2.2 ±0.6 BSC 1.27 ±0.2 A 0.5 ±0.1 31.3 ±0.2 31 ±0.2 24.4 ±0.2 16.4 ±0.2 Gate protrusion (B) 4.8 ±0.2 0.6 Exposed heatsink pad 1.7 ±0.1 Ø3.2 ±0.15 Ø3.2 ±0.15 2X Gate protrusion 16 ±0.2 B 2.45 ±0.2 BSC 12.9 ±0.2 9.9 ±0.2 Branding Area 2X Exposed tie bar 5 ±0.5 9.5 +0.7 – 0.5 0.6 +0.15 – 0.05 1.27 ±0.7 A R1 REF +0.15 0.5 – 0.05 4.5 REF 4.5 ±0.7 Figure 6. Package Outline Drawings. (A) LF2175, L-bend horizontal mount, (B) LF2171, vertical mount. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 SW Frequency (kHz) Recommended Capacitor Value (μF) 3 2.2 5 1 10 0.47 20 0.22 the built-in pre-driver IC. COM1 and COM2 must be connected together externally on the application PCB. Varying electric potential may become a cause of improper operation, so careful attention is required to the design of connection points and minimizing the length of the PCB traces. For two-phase modulation, or 120°C current-carrying topology, several tens of times the values above would be required due to the longer on-time. Please select capacitors considering the conditions used. When starting-up the IC, the low-side must be turned on first, and the boot capacitor needs to be charged sufficiently. The adequacy of the values shown above needs to be validated by testing in the actual application. Because the VB1, VB2, and VB3 pins connect to UVLO circuits, these terminal voltages must be set such that the UVLO protection does not operate. VCC1 and VCC2 These are the IC logic supply terminals for the built-in pre-driver IC. VCC1 and VCC2 must be connected together externally on the application PCB. To avoid improper operation because of supply ripples or other factors, a ceramic capacitor of approximately 0.1 μF must be installed near the pins. Also, there is the possibility of permanent damage to the IC if a voltage greater than 20 V is applied to the IC. To protect against this, adding a Zener diode (VZ = 20 to 23 V) is recommended. VCC1 and VCC2 have a built-in UVLO circuit, so these terminal voltages need to be regulated within the rated range, so that the UVLO protection does not operate. COM1 and COM2 These are the logic ground terminals for HIN1, HIN2, HIN3, LIN1, LIN2, and LIN3 These are the input terminals for controlling driver output to the motor. The IC uses a 5 V, CMOS Schmitt trigger circuit configuration. The input logic is active high, and internal pull-down resistors are provided. The value for the pull-down resistors is 100 kΩ on both the HIN side and the LIN side, as shown in figure 7, but an additional input filter (RC filter) or pull-down resistor should be considered in case the application has excessive noise or the input voltage is unstable. VBB1 and VBB2 These are the main power supply terminals. The VBB1 and VBB2 terminals are connected internally, but it is recommended to also tie them together externally by a short-circuit connection on the PCB, in order to decrease wiring impedance. A snubber capacitor (0.01 μF) should be placed near each of VBB1 and VBB2, connecting to the corresponding COM terminal, for suppressing surge voltages. LS1 and LS2 These are source terminals for the low-side MOSFETs. LS1 and LS2 must be connected together externally on the PCB. When connecting a shunt resistor to these terminals, such as for overcurrent sensing, the length of the trace between the IC terminals and the shunt resistor must be as short as practicable. Greater length increase the susceptibility to improper operation due to noise. VREG This is the terminal for the 7.5 V / 35 mA output to an external current regulator. Using an external regulation function is an important consideration for stabilizing the supply voltage. 5V HIN 2 kΩ 2 kΩ LIN COM 100 kΩ Figure 7. HINx and LINx Terminals Internal Equivalent Circuit Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 This could include placing an electrolytic capacitor between VREG and COM for avoiding supply ripple, and placing a ceramic capacitor for noise protection. If an external regulator is not required, VREG can be left open. FO This is the fault signal output terminal used to indicate abnormal operation. Its internal circuit is shown in figure 8. The output logic is shown in the following table Overtemperature Detection (TD) Logic Supply Undervoltage Detection (UVLO VCC2 to COM2) FO Output Yes Yes IC Shutdown No Yes It outputs a 5 V signal at overtemperature detection (TD) or a UVLO condition between VCC2 and COM2. When a UVLO condition is in effect, the IC shuts down output on the low side, at the same time FO output occurs. When a TD condition occurs, the FO output occurs, but there is no shutdown of the low-side output. The response to a TD condition must be handled by the application system logic. For example, the FO signal could be input into the application microprocessor, which could then turn off the gate control inputs to the IC. 5V 100 Ω 200 kΩ FO COM Figure 8. FO Terminal Internal Equivalent Circuit Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 Undervoltage Lockout (UVLO) of Control Power Supply When the gate-driving voltages on the output MOSFETs become too low, the losses of the power MOSFETs increase, and in the worst case the circuits may be damaged. In order to prevent this, undervoltage protection circuits are built into the control power supply. The high-side driver IC monitors the voltage between VCC1 and COM1, the voltage between VB1 and U, VB2 and V, and VB3 and W. The low-side driver IC monitors the voltage between VCC2 and COM2. As shown in the timing charts (figure 10), the UVLO functions monitor VB voltage, and if it falls below theVUVHL voltage level, the high-side MOSFETs will be shut down. Similarly, if the VCC1 to COM1 voltage falls below the VUVHL voltage level, the high-side MOSFETs will be shut down. Subsequently, when the supply voltage rises and exceeds VUVHH, the IC resets automatically and resumes outputs according to the input command signal (HIN). On the low side, if the VCC2 to COM2 voltage falls below the VUVLL voltage, the low-side MOSFETs will be shut down and the FO output goes high. When the supply voltage rises and exceeds the VUVLH voltage level, the low-side MOSFETs will be released from shut down, and the FO output goes low. Subsequently, the low side operates according to the input command signal (LIN). Overtemperature Detect Function The devices have a builtin overheating detection (TD) circuit. If the device overheats abnormally (exceeds TDH), it outputs 5 V to the FO terminal. The IC does not, however, shut down the output MOSFETs automatically. Instead, the application system logic should respond to the FO output and transmit shutdown commands on the control signals (HIN1, HIN2, and HIN3 and LIN1, LIN2, and LIN3). When the device temperature falls below the TDL level, the TD shutdown is released. The TD function parameters are as follows: Min (°C) Typ (°C) Max (°C) TDH 135 150 185 TDL 105 120 135 TDhys 25 30 35 This TD function is not intended to completely protect the internal MOSFETs or driver logic ICs. The application logic should monitor temperature conditions, and be designed to minimize the delay to response, particularly in the case of a rapid current increase. External Regulator Function The devices have a built-in external regulator (7.5 V / 35 mA) output. The fundamental characteristics of the regulator are shown in figure 9. 8 6 25°C VREG (V) This section describes in detail the various device protection features provided in these devices. TDhys (Overtemperature Detect Hysteresis) is the difference between TDH and TDL . 125°C 4 IO = 35 mA 25°C ≤ TJ ≤ 125°C 2 0 0 5 10 15 20 VCC (V) (A) 10 8 VREG (V) Protection Functions 6 4 VCC = 15 V 25°C ≤ TJ ≤ 125°C 2 0 0 10 20 IO (mA) 30 40 (B) Figure 9. External Regulator Characteristics: (A) line regulation, and (B) load regulation Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 HIN VUVHH VUVHL VB - HS UVLO Release (High-Side) HO (A) LIN VUVLH VCC VUVLL UVLO Release (Low-Side) LO FO TDH TJ TDL (B) Figure 10. UVLO Protection Circuit Timing (A) high-side, (B) low-side Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 1 2 4 11 10 3 5 VB1 VB2VB3 VCC1 HO1 HS1 24 High-side Logic Circuit ZD HO2 9 8 7 6 HS2 HIN 1 HIN 2 HIN 3 HO3 COM1 HS3 13 M 12 14 23 VCC 2 ZD LO 1 System Logic Low-side Logic Circuit 20 19 18 16 22 21 LIN 1 LO 2 17 LIN 2 LIN 3 LO 3 VREG 15 FO COM2 15V Figure 11. Typical Application Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 Application Circuit Recommendations When designing application circuits using these devices, the following should be taken into consideration: Supply Sequence The load power supply does not have to be provided in any particular sequence. However, commands should not be transmitted on the sequencing signal input terminals, HIN and LIN, until after the logic control power supply, VCC, has reached steady state. Short Circuit Protection There is no built-in protection circuit against short circuits through the outputs to ground. The application circuit logic should be designed to monitor outputs to detect a short circuit condition. Pin to Pin Distance The device packages have 24 pins, and a 1.27 mm pin pitch. At operating voltage levels, there may be insufficient creepage and clearance distance, and conformal coating or encapsulation of the application printed board assembly is recommended. Surge Protection Each terminal should be protected against power surges by isolation using an external component such as a ceramic capacitor or Zener diode. Power surges that impinge on the device may cause critical damage to the IC as well as faulty operation. Input Blanking Time In order to avoid a high-side to low-side short-circuit, the HIN and LIN signals must never be in phase. The blanking time, tBLANK, or dead-time, is the delay between rising edges on the HIN and LIN signals. It must be controlled externally by the application system logic, as it is not set internally. A tBLANK of more than 1.5 μs is recommended. Electrical Characteristics Data The following pages contain characteristic performance data. The information shown applies to all models of the SLA6820M/ SMA6820MP series, unless otherwise specified. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 All SLA6820M and SMA6820MP Series Devices Bootstrap Current versus Bootstrap Voltage Supply Current versus Supply Voltage 400 6 125°C 4 IBOOT (μA) ICC (mA) 5 25°C 3 2 300 125°C 200 100 25°C 1 0 0 12 13 14 15 16 VCC (V) 17 18 19 20 10 14 16 VBOOT (V) 18 20 UVLO Voltage versus Case Temperature IIN Current versus Case Temperature 100 15 VCC = 15 V VCC = 15 V VIN = 5 V VUVLO (V) 80 IIN (μA) 12 60 40 UVHH 10 UVHL 5 20 0 -25 0 25 50 TC (°C) 75 100 0 -25 125 25 50 TC (°C) 75 100 125 Boot Diode Forward Current versus Forward Voltage FO Voltage versus Case Temperature Includes series resistance 200 6 5 TC = 25°C 150 4 IF (mA) VFO (V) 0 3 2 100 TC = 125°C 50 1 0 0 -25 0 25 50 TC (°C) 75 100 125 0 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 1 2 VF (V) 3 4 5 11 SLA6826M/SMA6821MP MOSFET Characteristics RDS(on) versus ID 4 VSD = 15 V 3 1.5 ISD (A) 125°C 75°C 2 25°C 1 TC = 125°C 1 TC = 75°C 0.5 TC = 25°C 0 0 0.5 1 ID (A) 1.5 0 0.0 2 0.2 0.4 0.6 0.8 1.0 VSD (V) Typical Switching Loss versus Drain Current 50 Switching Loss (μJ) RDS (on) (Ω) SD Voltage versus SD Current 2 VGS = 15 V TJ = 125°C VCC = 15 V VBB = 120 V Inductive load 40 30 Eon 20 Eoff 10 0 0.0 0.5 1.0 ID (A) 1.5 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2.0 12 SLA6827M/SMA6822MP MOSFET Characteristics RDS(on) versus ID 8 VGS = 15 V 7 VSD = 0 V 6 5 ISD (A) 125°C 75°C 4 25°C 3 TC = 125°C 1 TC = 75°C 0.5 2 TC = 25°C 1 0 0.0 0 0.0 0.5 ID (A) 1.0 1.5 0.2 0.4 0.6 0.8 VSD (V) 1.0 1.2 1.4 Typical Switching Loss versus Drain Current 100 Switching Loss (μJ) RDS (on) (Ω) SD Voltage versus SD Current 1.5 80 TJ = 125°C VCC = 15 V VBB = 280 V Inductive load Eon 60 40 Eoff 20 0 0.0 0.5 ID (A) 1.0 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 1.5 13 SLA6828M/SMA6823MP MOSFET Characteristics RDS(on) versus ID 5 VGS = 15 V VSD = 0 V 125°C 4 2 75°C 25°C 2 TC = 125°C 1.5 ISD (A) 3 TC = 75°C 1 0.5 1 0 0.5 1 ID (A) 1.5 2 TC = 25°C 0 0.0 0 2.5 0.5 VSD (V) 1.0 1.5 Typical Switching Loss versus Drain Current 160 Switching Loss (μJ) RDS (on) (Ω) SD Voltage versus SD Current 2.5 140 120 100 TJ = 125°C VCC = 15 V VBB = 280 V Inductive load Eon 80 Eoff 60 40 20 0 0.0 0.5 1.0 ID (A) 1.5 2.0 Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2.5 14 All performance characteristics given are typical values for circuit or system baseline design only and are at the nominal operating voltage and an ambient temperature of 25°C, unless otherwise stated. The products described herein are manufactured in Japan by Sanken Electric Co., Ltd. for sale by Allegro MicroSystems, Inc. Sanken and Allegro reserve the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Therefore, the user is cautioned to verify that the information in this publication is current before placing any order. When using the products described herein, the applicability and suitability of such products for the intended purpose should be reviewed at the users responsibility. Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products at a certain rate is inevitable. Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems against any possible injury, death, fires or damages to society due to device failure or malfunction. Sanken products listed in this publication are designed and intended for use as components in general-purpose electronic equipment or apparatus (home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Their use in any application requiring radiation hardness assurance (e.g., aerospace equipment) is not supported. When considering the use of Sanken products in applications where higher reliability is required (transportation equipment and its control systems or equipment, fire- or burglar-alarm systems, various safety devices, etc.), contact a company sales representative to discuss and obtain written confirmation of your specifications. The use of Sanken products without the written consent of Sanken in applications where extremely high reliability is required (aerospace equipment, nuclear power-control stations, life-support systems, etc.) is strictly prohibited. The information included herein is believed to be accurate and reliable. Application and operation examples described in this publication are given for reference only and Sanken and Allegro assume no responsibility for any infringement of industrial property rights, intellectual property rights, or any other rights of Sanken or Allegro or any third party that may result from its use. Anti radioactive ray design is not considered for the products listed herein. Copyright © 2008 Allegro MicroSystems, Inc. Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 15