High Voltage SMA6850M Series Driver ICs for 3-Phase DC Motor Applications

Product Information
High Voltage SMA6850M Series
Driver ICs for 3-Phase DC Motor Applications
Introduction
The SMA6850M Series power packages incorporate all
of the necessary power control components to configure
the main circuit of an inverter power module (IPM). These
products are especially suitable for driving the inverters of
low-capacity motors, such as those used in 100 to 200 V
fans for air conditioners.
Leadform 2452
Features and benefits include the following:
▪ Built-in pre-driver ICs and three bootstrap diodes as a
high-side drive power supply
▪ CMOS-compatible input (3.3 and 5 V)
▪ High-side gate driver using bootstrap circuit or floating
power supply
▪ One pin for 7.5 V regulator output
▪ Built-in protection circuit for controlling power supply
voltage drop (UVLO)
▪ Built-in overtemperature detection circuit (TD)
▪ Fault signal output during operation of protection circuit
▪ Overcurrent detection enabled via three shunt resistors
▪ Output current up to 2.5 A continuous
▪ Small SIP (SMA, 24 pins)
Functional Description
The functional block diagram is shown in figure 2. High
voltage power and 15 VDC are input between VBB and
LS1/LS2, between VCC1 and COM1, and between VCC2
and COM2. The on/off signals of the power MOSFETs
are operated by six signals: HIN1, HIN2, HIN3, LIN1,
LIN2, and LIN3. These input signals are positive logic (the
MOSFET turns on at VxINx = high). The boot capacitors are
connected between VB1 and U, VB2 and V, and VB3 and
W1, as the high voltage power source.
Product Lineup
MOSFET Rating
SMA6851M
250 V / 2 A
120
SMA6852M
500 V / 1.5 A
230
SMA6853M
500 V / 2.5 A
230
28610.22, Rev. 1
Figure 1. SMA6850M Series packages are fully molded SIPs,
offering compact configurations both horizontal mount (leadform
2451) and vertical mount (leadform 2452).
The protection functions, including overtemperature
detection (at abnormal ambient temperature, overload, and
so forth), and undervoltage of low control power supply
voltage (at instantaneous fall, and so forth) are built-in and
when any of these functions is operated, it can be monitored
at the fault output terminal, FO.
Structural Description
The external configurations of the device packages are
shown in figure 1. The device cases are molded epoxy resin.
The surface of each package has branding that includes the
part number and lot number.
Contents
Input Voltage
(VAC)
Type
Leadform 2451
Introduction
Functional Description
Protection Functions
Application Circuit Recommendations
Electrical Characteristics Data
1
1
6
9
9
VB1
VB2
VB3
VCC1
VBB 1
UVLO
HIN1
HIN2
HIN3
UVLO
Input
Logic
UVLO
VBB 2
UVLO
High-Side
Level Shift Driver
COM1
U
V
W1
W2
VCC 2
7.5V
Reg.
VREG
UVLO
LIN1
LIN2
LIN3
Input
Logic
Low-Side
Driver
LS3
LS2
LS1
COM 2
Thermal
Detect
FO
Figure 2. SMA6850M Series Functional Block Diagram. These devices support
high-side and low-side three-phase MOSFET output drivers.
Leadform 2451
1
3
2
5
4
7
9
6
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
Leadform 2452
24
1
3
2
5
4
7
6
9
8
11
10
13
12
15
14
17
16
19
18
21
20
23
22
24
Chamfer Side
Chamfer on Opposite Side
Terminal List
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
VB1
VB2
VB3
VCC1
COM1
HIN3
HIN2
HIN1
VBB1
VBB2
W1
V
LS2
W2
LS3
VREG
LS1
LIN3
LIN2
LIN1
COM2
FO
VCC2
U
Function
High-side bootstrap terminal (U phase)
High-side bootstrap terminal (V phase)
High-side bootstrap terminal (W phase)
High-side logic supply voltage
High-side logic GND terminal
High-side input terminal (W phase)
High-side input terminal (V phase)
High-side input terminal (U phase)
Main supply voltage 1 (connect to VBB2 externally)
Main supply voltage 2 (connect to VBB1 externally)
Output of W phase (connect to W2 externally)
Output of V phase
Low-side source terminal (V phase)
Output of W phase (connect to W1 externally)
Low-side source terminal (W phase)
Internal regulator output terminal
Low-side source terminal (U phase)
Low-side input terminal (W phase)
Low-side input terminal (V phase)
Low-side input terminal (U phase)
Low-side GND terminal
Overtemperature detect/UVLO fault signal output
Low-side logic supply voltage
Output of U phase
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
The devices each have 11 embedded die, including six power
MOSFETs, two pre-driver ICs, and three bootstrap diodes. These
die are mounted on a copper leadframe and connected with gold
wire between die and from die to leadframe (figure 3).
Terminal Descriptions
A summary description of the function of the various terminals is
given in the Terminal List table. Pin 1 for the package appears in
figure 5. This section provides detailed functional descriptions of
the individual pins.
The following factors should be considered when determining the
parameters of the bootstrap circuit. First, the optimal value for
the bootstrap capacitor, CBOOT, varies according to the driving
method (modulation method and output frequency), the switching
frequency (carrier frequency), the modulation ratio (duty cycle),
and the gate input capacity of the driving MOSFETs.
The following table provides an example for three-phase modulation with 90% duty cycle:
U, V, W1, and W2 These are the output terminals that are connected to the motor. W1 and W2 must be tied together externally
on the printed circuit board (PCB) with a trace of minimum
length.
SW Frequency
(kHz)
Recommended
Capacitor Value
(μF)
3
2.2
5
1
10
0.47
20
0.22
VB1, VB2, and VB3 Power supply terminals for driving the
high-side MOSFETs.
As shown in figure 4, a bootstrap capacitor, CBOOTx, must be
connected between VB1 and U, VB2 and V, and VB3 and W. A
bootstrap capacitor circuit is required on each high-side bridge,
because they operate independently of each other.
The bootstrap capacitors, CBOOTx, must be charged at startup.
Before charging CBOOT, the corresponding low-side MOSFET
must be turned on. The IC has a built-in 22 Ω ±20% serial resistor and a bootstrap diode (600 V / 1 A). In applications in which
22 Ω is not sufficient, an external resistor can be added between
VCC and the VD pin.
For two-phase modulation, or 120°C current-carrying topology,
several tens of times the values above would be required due to
the longer on-time.
Please select capacitors considering the conditions used. When
starting-up the IC, the low-side must be turned on first, and the
boot capacitor needs to be charged sufficiently. The adequacy of
the values shown above needs to be validated by testing in the
actual application. Because the VB1, VB2, and VB3 pins connect
to UVLO circuits, these terminal voltages must be set such that
the UVLO protection does not operate.
VBB
VBx
Gold wire
VCC1
Copper leadframe
Epoxy resin case
VBB
CBOOT
charge current
Die
High Side
Drive Circuit
VCC
CBOOT
U,V,W
To Motor
VCC2
Low Side
Drive Circuit
LSx
Figure 3. SLA Package Cross-section View
Figure 4. Connection of Bootstrap Capacitor. There is a separate CBOOT
capacitor for each of the three phases.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
VCC1 and VCC2 These are the IC logic supply terminals for
the built-in pre-driver IC. VCC1 and VCC2 must be connected
together externally on the application PCB. To avoid improper
operation because of supply ripples or other factors, a ceramic
capacitor of approximately 0.1 μF must be installed near the pins.
Also, there is the possibility of permanent damage to the IC if a
voltage greater than 20 V is applied to the IC. To protect against
this, adding a Zener diode (VZ = 20 to 23 V) is recommended.
VCC1 and VCC2 have a built-in UVLO circuit, so these terminal
voltages need to be regulated within the rated range, so that the
UVLO protection does not operate.
COM1 and COM2 These are the logic ground terminals for
the built-in pre-driver IC. COM1 and COM2 must be connected
together externally on the application PCB. Varying electric
potential may become a cause of improper operation, so careful
attention is required to the design of connection points and minimizing the length of the PCB traces.
Gate protrusion
HIN1, HIN2, HIN3, LIN1, LIN2, and LIN3 These are the input
terminals for controlling driver output to the motor. The IC uses a
5 V, CMOS Schmitt trigger circuit configuration. The input logic
is active high, and internal pull-down resistors are provided. The
value for the pull-down resistors is 100 kΩ on both the HIN side
and the LIN side, as shown in figure 7, but an additional input
filter (RC filter) or pull-down resistor should be considered in
case the application has excessive noise or the input voltage is
unstable.
VBB1 and VBB2 These are the main power supply terminals. The VBB1 and VBB2 terminals are connected internally,
but it is recommended to also tie them together externally by a
short-circuit connection on the PCB, in order to decrease wiring
impedance. A snubber capacitor (0.01 μF) should be placed near
each of VBB1 and VBB2, connecting to the corresponding COM
terminal, for suppressing surge voltages.
31.3 ±0.2
4 ±0.2
31 ±0.2
2X Gate protrusion
1.2 ±0.1
BSC
10.2 ±0.2
3 ±0.5
BSC
(A)
2X Exposed
tie bar
2.2 ±0.7
BSC
R1
REF
4.4
REF
1
Gate protrusion
+0.15
– 0.05
C 0.7
0.6 +0.15
– 0.05
1.27 ±0.1 A
1.27 ±0.6 B
2.2 ±0.7
BSC
0.55 +0.2
– 0.1
31.3 ±0.2
4 ±0.2
31 ±0.2
2X Gate protrusion
1.2 ±0.1
BSC
10.2 ±0.2
(B)
2X Exposed
tie bar
5 ±0.5
9.5 +0.7
– 0.5
R1
REF
0.5 +0.15
– 0.05
4.5
REF
1
1.27 ±0.5 A
0.6 +0.15
– 0.05
4.5 ±0.5
Figure 5. Package Outline Drawings. (A) LF2451, L-bend horizontal mount, (B) LF2452, vertical mount.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
LS1, LS2, and LS3 These are source terminals for the low-side
MOSFETs. LS1, LS2, and LS3 must each be connected to the
COM terminal, externally on the PCB via shunt resistors. When
connecting a shunt resistor to these terminals, such as for overcurrent sensing, the length of the trace between the IC terminals
and the shunt resistor must be as short as practicable. Greater
length increases the susceptibility to improper operation due to
noise.
logic is shown in the following table
VREG This is the terminal for the 7.5 V / 35 mA output to an
external current regulator. Using an external regulation function
is an important consideration for stabilizing the supply voltage.
This could include placing an electrolytic capacitor between
VREG and COM for avoiding supply ripple, and placing a
ceramic capacitor for noise protection. If an external regulator is
not required, VREG can be left open.
It outputs a 5 V signal at overtemperature detection (TD) or a
UVLO condition between VCC2 and COM2. When a UVLO
condition is in effect, the IC shuts down output on the low side,
at the same time FO output occurs. When a TD condition occurs,
the FO output occurs, but there is no shutdown of the low-side
output. The response to a TD condition must be handled by the
application system logic. For example, the FO signal could be
input into the application microprocessor, which could then turn
off the gate control inputs to the IC.
FO This is the fault signal output terminal used to indicate abnormal operation. Its internal circuit is shown in figure 8. The output
5V
HIN
2 kΩ
Overtemperature
Detection (TD)
Logic Supply
Undervoltage
Detection (UVLO
VCC2 to COM2)
FO Output
Yes
Yes
IC Shutdown
No
Yes
5V
2 kΩ
100 Ω
LIN
200 kΩ
COM
FO
COM
100 kΩ
Figure 7. HINx and LINx Terminals Internal Equivalent Circuit
Figure 8. FO Terminal Internal Equivalent Circuit
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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Undervoltage Lockout (UVLO) of Control Power Supply
When the gate-driving voltages on the output MOSFETs become
too low, the losses of the power MOSFETs increase, and in the
worst case the circuits may be damaged. In order to prevent this,
undervoltage protection circuits are built into the control power
supply.
The high-side driver IC monitors the voltage between VCC1 and
COM1, the voltage between VB1 and U, VB2 and V, and VB3
and W. The low-side driver IC monitors the voltage between
VCC2 and COM2.
As shown in the timing charts (figure 10), the UVLO functions
monitor VB voltage, and if it falls below theVUVHL voltage level,
the high-side MOSFETs will be shut down. Similarly, if the
VCC1 to COM1 voltage falls below the VUVHL voltage level, the
high-side MOSFETs will be shut down. Subsequently, when the
supply voltage rises and exceeds VUVHH, the IC resets automatically and resumes outputs according to the input command signal
(HIN).
On the low side, if the VCC2 to COM2 voltage falls below the
VUVLL voltage, the low-side MOSFETs will be shut down and the
FO output goes high. When the supply voltage rises and exceeds
the VUVLH voltage level, the low-side MOSFETs will be released
from shut down, and the FO output goes low. Subsequently, the
low side operates according to the input command signal (LIN).
Overtemperature Detect Function The devices have a builtin overheating detection (TD) circuit. If the device overheats
abnormally (exceeds TDH), it outputs 5 V to the FO terminal. The
IC does not, however, shut down the output MOSFETs automatically. Instead, the application system logic should respond to
the FO output and transmit shutdown commands on the control
signals (HIN1, HIN2, and HIN3 and LIN1, LIN2, and LIN3).
When the device temperature falls below the TDL level, the TD
shutdown is released. The TD function parameters are as follows:
Min (°C)
Typ (°C)
Max (°C)
TDH
135
150
185
TDL
105
120
135
TDhys
25
30
35
This TD function is not intended to completely protect the internal MOSFETs or driver logic ICs. The application logic should
monitor temperature conditions, and be designed to minimize
the delay to response, particularly in the case of a rapid current
increase.
External Regulator Function The devices have a built-in
external regulator (7.5 V / 35 mA) output. The fundamental characteristics of the regulator are shown in figure 9.
8
6
25°C
VREG (V)
This section describes in detail the various device protection
features provided in these devices.
TDhys (Overtemperature Detect Hysteresis) is the difference
between TDH and TDL .
125°C
4
IO = 35 mA
25°C ≤ TJ ≤ 125°C
2
0
0
5
10
15
20
VCC (V)
(A)
10
8
VREG (V)
Protection Functions
6
4
VCC = 15 V
25°C ≤ TJ ≤ 125°C
2
0
0
10
20
IO (mA)
30
40
(B)
Figure 9. External Regulator Characteristics: (A) line regulation, and
(B) load regulation
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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Figure 10. UVLO Protection Circuit Timing (A) high-side, (B) low-side
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
1
2
3
9
10
VB1 VB2 VB3
4
HO 1
VCC1
HS1
HVIC
8
7
6
5
24
HO 2
HS2
12
M
HIN 1
HIN 2
HIN 3
HO 3
COM1
HS3
11
14
23
VCC 2
LO 1
17
MC U
20
19
18
LVIC
LIN1
LIN2
LO 2
13
LIN3
LO 3
16
22
21
VREG
15
FO
COM 2
15 V
Figure 11. Typical Application
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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Application Circuit Recommendations
When designing application circuits using these devices, the following should be taken into consideration:
Supply Sequence The load power supply does not have to be
provided in any particular sequence. However, commands should
not be transmitted on the sequencing signal input terminals, HIN
and LIN, until after the logic control power supply, VCC, has
reached steady state.
Short Circuit Protection There is no built-in protection circuit
against short circuits through the outputs to ground. The application circuit logic should be designed to monitor outputs to detect
a short circuit condition.
Pin to Pin Distance The device packages have 24 pins, and
a 1.27 mm pin pitch. At operating voltage levels, there may be
insufficient creepage and clearance distance, and conformal coating or encapsulation of the application printed board assembly is
recommended.
Surge Protection Each terminal should be protected against
power surges by isolation using an external component such as a
ceramic capacitor or Zener diode. Power surges that impinge on
the device may cause critical damage to the IC as well as faulty
operation.
Input Blanking Time In order to avoid a high-side to low-side
short-circuit, the HIN and LIN signals must never be in phase.
The blanking time, tBLANK, or dead-time, is the delay between
rising edges on the HIN and LIN signals. It must be controlled
externally by the application system logic, as it is not set internally. A tBLANK of more than 1.5 μs is recommended.
Electrical Characteristics Data
The following pages contain characteristic performance data.
The information shown applies to all models of the SMA6850M
series, unless otherwise specified.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
SMA6850M Series Common Device Characteristics
Typical Supply Current versus Supply Voltage
Supply Current versus Junction Temperature
7
6
5
VCC = 15 V
Input Off
Max
ICC (mA)
ICC (mA)
5
4
Typ
3
2
Min
0
25
50
75
TJ (°C)
3
TJ = 25°C
2
100
125
0
12
150
13
Bootstrap Current versus Junction Temperature
350
IBOOT (μA)
300
VB = 15 V
Input Off
350
300
250
Max
200
Typ
150
14
100
16
17
VCC (V)
18
19
20
VB = 15 V
Input On
250
Max
200
Typ
150
100
Min
50
0
–25
0
25
50
75
Min
50
100
125
0
–25
150
0
25
TJ (°C)
50
75
100
125
150
TJ (°C)
Typical Bootstrap Current versus Voltage
Input Current versus Junction Temperature
160
250
Input Off
140
200
150
100
TJ = 25°C
Max
100
80
Typ
60
40
50
Min
20
0
12
VIN = 5 V
120
TJ = 125°C
IIN (μA)
IBOOT (μA)
15
Bootstrap Current versus Junction Temperature
400
IBOOT (μA)
400
TJ = 125°C
1
1
0
–25
Input Off
4
13
14
15
16
VB (V)
17
18
19
20
0
–25
0
25
50
75
100
125
150
TJ (°C)
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
SMA6850M Series Common Device Characteristics (continued)
Output Voltage for Regulator versus Junction Temperature
8.0
VREG Load Regulation
IREG = 35 mA
Max
7.6
VREG (V)
VREG (V)
7.8
Typ
7.4
Min
7.2
7.0
–25
0
25
50
75
TJ (°C)
100
125
9
8
7
6
5
4
3
2
1
0
150
VCC = 15 V, Typical
TJ = 125°C
TJ = 25°C
0
Input Voltage (High) versus Junction Temperature
Typ
2.0
Min
1.5
150
175
200
1.0
1.0
0.5
0.5
0
25
50
75
100
125
0
–25
150
Max
1.5
Typ
0
25
TJ (°C)
TOFF (ns)
Min
25
50
75
75
100
125
150
Off-Time (High Side) versus Junction Temperature
Max
Typ
0
50
Min
TJ (°C)
On-Time (High Side) versus Junction Temperature
TON (ns)
100
125
IREG (mA)
2.5
VIL (V)
2.0
500
450
400
350
300
250
200
150
100
50
0
–25
75
3.0
Max
2.5
VIH (V)
50
Input Voltage (Low) versus Junction Temperature
3.0
0
–25
25
100
125
150
500
450
400
350
300
250
200
150
100
50
0
–25
TJ (°C)
Max
Typ
Min
0
25
50
75
100
125
150
TJ (°C)
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115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
SMA6850M Series Common Device Characteristics (continued)
Off-Time (Low Side) versus Junction Temperature
Max
Typ
TOFF (ns)
TON (ns)
On-Time (Low Side) versus Junction Temperature
500
450
400
350
300
250
200
150
100
50
0
–25
Min
0
25
50
75
100
125
150
500
450
400
350
300
250
200
150
100
50
0
–25
Max
Typ
Min
0
25
TJ (°C)
125
150
160
140
140
Max
120
120
Typ
100
tdL(on) (ns)
tdH(on) (ns)
100
Minimum Switch-on Time (Low Side) versus Junction Temperature
Minimum Switch-on Time (High Side) versus Junction Temperature
80
60
100
80
40
20
20
0
25
50
75
100
125
Max
60
40
0
–25
Typ
0
–25
150
0
25
TJ (°C)
5.2
VFO (V)
Low Side
300
High Side
200
5.0
Typ
Min
4.8
100
150
Max
5.1
4.9
100
0
125
5.3
500
400
100
5.4
TJ = 25°C
VCC = 15 V
600
75
FO Terminal Outout Voltage versus Junction Temperature
Typical Output Pulse Width versus Input Pulse Width
700
50
TJ (°C)
800
tw(out) (ns)
75
TJ (°C)
160
0
50
200
300
400
500
600
700
800
4.7
–25
tw(in) (ns)
0
25
50
75
100
125
150
TJ (°C)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
SMA6850M Series Common Device Characteristics (continued)
VCC1 Pin UVLO (Low Side) versus Junction Temperature
High Threshold
VCC1 Pin UVLO (Low Side) versus Junction Temperature
Low Threshold
11.6
Max
12.0
Max
11.4
11.8
VUVLH (V)
11.8
Typ
11.6
VUVLL (V)
12.2
11.4
Min
11.2
11.2
Typ
11.0
10.8
Min
10.6
11.0
10.4
10.8
–25
0
25
50
75
100
125
10.2
–25
150
0
25
TJ (°C)
12.2
11.8
11.6
Max
11.4
Typ
VUVLL (V)
VUVLH (V)
125
150
VCC2 Pin UVLO (Low Side) versus Junction Temperature
Low Threshold
11.4
11.8
11.2
11.2
Max
11.0
Typ
10.8
10.6
11.0
Min
0
25
50
75
Min
10.4
100
125
10.2
–25
150
0
25
TJ (°C)
50
75
100
125
150
TJ (°C)
VB Pin UVLO (High Side) versus Junction Temperature
High Threshold
10.8
VB Pin UVLO (High Side) versus Junction Temperature
Low Threshold
10.6
Max
Max
10.4
VUVHL (V)
VUVHH (V)
100
11.6
12.0
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
9.8
–25
75
TJ (°C)
VCC2 Pin UVLO (Low Side) versus Junction Temperature
High Threshold
10.8
–25
50
Typ
Min
Typ
10.2
10.0
Min
9.8
9.6
9.4
0
25
50
75
100
125
150
9.2
–25
TJ (°C)
0
25
50
75
100
125
150
TJ (°C)
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13
SMA6850M Series Common Device Characteristics (continued)
VCC UVLO Filter (Low Side) versus Junction Temperature
VB UVLO Filter (High Side) versus Junction Temperature
16
14
6
tUVFILTER (μs)
8
Max
4
2
0
–25
0
25
50
12
10
Max
8
6
Typ
4
Typ
Min
2
Min
75
100
125
0
–25
150
0
25
TJ (°C)
50
75
100
125
150
TJ (°C)
200
Bootstrap Diode Forward Voltage versus Forward Current
Includes series resistance
150
If (mA)
tUVFILTER (μs)
10
TC = 25°C
TC = 125°C
100
50
0
0
1
2
3
4
5
Vf (V)
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SMA6851M MOSFET Characteristics
RDS(on) versus ID
4
VSD = 15 V
3
1.5
125°C
ISD (A)
RDS (on) (Ω)
SD Voltage versus SD Current
2
VGS = 15 V
75°C
2
25°C
1
TC = 125°C
1
TC = 75°C
0.5
TC = 25°C
0
0
0.5
1
ID (A)
1.5
0
0.0
2
0.8
1.0
100
TJ = 25°C
VCC = 15 V
VBB = 150 V
50
Switching Loss (μJ)
Switching Loss (μJ)
0.6
Typical Switching Loss versus Drain Current
100
Low Side On
25
Low Side Off
High Side On
High Side Off
75
TJ = 125°C
VCC = 15 V
VBB = 150 V
Low Side On
50
High Side On
25
High Side Off
Low Side Off
0
0
0.0
0.5
1.0
ID (A)
1.5
0.0
2.0
TJ = 25°C
VCC = 15 V
VBB = 150 V
10
Low Side
5
0
0.0
1.0
ID (A)
1.5
2.0
20
Recovery Loss (μJ)
15
0.5
Typical Recovery Loss versus Drain Current
Typical Recovery Loss versus Drain Current
20
Recovery Loss (μJ)
0.4
VSD (V)
Typical Switching Loss versus Drain Current
75
0.2
High Side
0.5
1.0
ID (A)
1.5
2.0
15
10
TJ = 125°C
VCC = 15 V
VBB = 150 V
Low Side
High Side
5
0
0.0
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0.5
1.0
ID (A)
1.5
2.0
15
SMA6852M MOSFET Characteristics
RDS(on) versus ID
8
VGS = 15 V
7
VSD = 0 V
125°C
6
5
ISD (A)
RDS (on) (Ω)
SD Voltage versus SD Current
1.5
75°C
4
25°C
3
TC = 125°C
1
TC = 75°C
0.5
2
TC = 25°C
1
0
0.0
0
0.0
0.5
1.0
ID (A)
1.5
Typical Switching Loss versus Drain Current
TJ = 25°C
VCC = 15 V
VBB = 300 V
100
Switching Loss (μJ)
Switching Loss (μJ)
0.6
0.8
VSD (V)
1.0
1.2
1.4
Typical Switching Loss versus Drain Current
Low Side On
50
Low Side Off
High Side On
High Side Off
150
TJ = 125°C
VCC = 15 V
VBB = 300 V
Low Side On
100
High Side On
50
High Side Off
Low Side Off
0
0
0.0
0.5
ID (A)
1.0
1.5
0.0
Typical Recovery Loss versus Drain Current
30
TJ = 25°C
VCC = 15 V
VBB = 300 V
25
20
15
High Side
Low Side
10
5
0
0.0
ID (A)
1.0
1.5
40
Recovery Loss (μJ)
35
0.5
Typical Recovery Loss versus Drain Current
40
Recovery Loss (μJ)
0.4
200
200
150
0.2
35
30
25
20
15
TJ = 125°C
VCC = 15 V
VBB = 300 V
High Side
Low Side
10
5
0.5
ID (A)
1.0
1.5
0
0.0
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0.5
ID (A)
1.0
1.5
16
SMA6853M MOSFET Characteristics
RDS(on) versus ID
5
VGS = 15 V
VSD = 0 V
125°C
4
2
75°C
3
25°C
2
TC = 75°C
1
0.5
1
0
0.5
1
ID (A)
1.5
2
2.5
Typical Switching Loss versus Drain Current
250
200
300
TJ = 25°C
VCC = 15 V
VBB = 300 V
Low Side On
150
100
High Side On
High Side Off
50
0.5
1.0
VSD (V)
1.5
Typical Switching Loss versus Drain Current
Switching Loss (μJ)
Switching Loss (μJ)
300
TC = 25°C
0
0.0
0
Low Side Off
0
250
200
TJ = 125°C
VCC = 15 V
VBB = 300 V
Low Side On
150
High Side On
100
High Side Off
50
Low Side Off
0
0.0
0.5
1.0
ID (A)
1.5
2.0
2.5
0.0
Typical Recovery Loss versus Drain Current
40
TJ = 25°C
VCC = 15 V
VBB = 300 V
30
Low Side
20
0.5
1.0
1.5
ID (A)
2.0
2.5
Typical Recovery Loss versus Drain Current
50
Recovery Loss (μJ)
50
Recovery Loss (μJ)
TC = 125°C
1.5
ISD (A)
RDS (on) (Ω)
SD Voltage versus SD Current
2.5
High Side
10
0
TJ = 125°C
VCC = 15 V
VBB = 300 V
40
30
Low Side
High Side
20
10
0
0.0
0.5
1.0
ID (A)
1.5
2.0
2.5
0.0
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0.5
1.0
1.5
ID (A)
2.0
2.5
17
All performance characteristics given are typical values for
circuit or system baseline design only and are at the nominal
operating voltage and an ambient temperature of 25°C,
unless otherwise stated.
The products described herein are manufactured in Japan by Sanken Electric Co., Ltd. for sale by Allegro MicroSystems, Inc.
Sanken and Allegro reserve the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Therefore, the user is cautioned to verify that the information in this
publication is current before placing any order.
When using the products described herein, the applicability and suitability of such products for the intended purpose should be reviewed at the
users responsibility.
Although Sanken undertakes to enhance the quality and reliability of its products, the occurrence of failure and defect of semiconductor products
at a certain rate is inevitable.
Users of Sanken products are requested to take, at their own risk, preventative measures including safety design of the equipment or systems
against any possible injury, death, fires or damages to society due to device failure or malfunction.
Sanken products listed in this publication are designed and intended for use as components in general-purpose electronic equipment or apparatus
(home appliances, office equipment, telecommunication equipment, measuring equipment, etc.). Their use in any application requiring radiation
hardness assurance (e.g., aerospace equipment) is not supported.
When considering the use of Sanken products in applications where higher reliability is required (transportation equipment and its control systems
or equipment, fire- or burglar-alarm systems, various safety devices, etc.), contact a company sales representative to discuss and obtain written
confirmation of your specifications.
The use of Sanken products without the written consent of Sanken in applications where extremely high reliability is required (aerospace equipment, nuclear power-control stations, life-support systems, etc.) is strictly prohibited.
The information included herein is believed to be accurate and reliable. Application and operation examples described in this publication are
given for reference only and Sanken and Allegro assume no responsibility for any infringement of industrial property rights, intellectual property
rights, or any other rights of Sanken or Allegro or any third party that may result from its use.
Anti radioactive ray design is not considered for the products listed herein.
Copyright © 2008 Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
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18