INTERSIL HIP4086

HIP4086
Data Sheet
May 1999
File Number
4220.4
80V, 0.5A Three Phase Driver
Features
The HIP4086 is a Three Phase Bridge N-Channel MOSFET
driver IC. The HIP4086 is specifically targeted for PWM
motor control. It makes bridge based designs simple and
flexible. Like the HIP4081, the HIP4086 has a flexible input
protocol for driving every possible switch combination. Unlike
the HIP4081, the user can override the shoot-through
protection for switched reluctance applications. The HIP4086
has reduced drive current compared to the HIP4081 (0.5A
vs 2.5A) and a much wider range of programmable dead
times (0.25µs to 4.5µs) - like the HIP4082. The HIP4086 is
suitable for applications requiring DC to 100kHz. Unlike the
previous family members, the HIP4086 has a programmable
undervoltage set point.
• Independently Drives 6 N-Channel MOSFETs in Three
Phase Bridge Configuration
Also refer to the HIP4083, three phase upper only MOSFET
driver, for a lower current solution optimized for smaller
motors.
Ordering Information
• Bias Supply Operation from 7V to 15V
• 1.25A Peak Turn-Off Current
• User-Programmable Dead Time (0.25µs to 4.5µs)
• Charge-Pump and Bootstrap Maintain Upper Bias
Supplies
• Programmable Bootstrap Refresh Time
• Drives 1000pF Load with Typical Rise Time of 20ns and
Fall Time of 10ns
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with 5V to 15V Logic
Levels
• Dead Time Disable Capability
TEMP.
RANGE (oC)
PART NUMBER
• Bootstrap Supply Max Voltage to 95VDC
PACKAGE
PKG.
NO.
• Programmable Undervoltage Set Point
HIP4086AB
-40 to 125
24 Ld SOIC
M24.3
Applications
HIP4086AP
-40 to 125
24 Ld PDIP
E24.3
• Brushless Motors
• AC Motor Drives
Pinout
• Switched Reluctance Motor Drives
HIP4086
(PDIP, SOIC)
TOP VIEW
• Battery Powered Vehicles
Application Block Diagram
BHB 1
24 BHO
BHI 2
23 BHS
BLI
3
22 BLO
ALI
4
21 ALO
AHI 5
20 VDD
VSS
6
19 CLO
RDEL 7
18 AHS
8
17 AHO
RFSH 9
16 AHB
DIS 10
15 CHS
CLI 11
14 CHO
CHI 12
13 CHB
UVLO
80V
12V
HIP4086
GND
GND
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HIP4086
Functional Block Diagram (1/3 of HIP4086 )
CHARGE
PUMP
16 AHB
AHI
DRIVER
5
TURN-ON
DELAY
LEVEL
SHIFTER
17 AHO
DIS 10
VDD 20
UVLO
8
RFSH
9
UNDERVOLTAGE
DETECTOR
10ns
DELAY
18 AHS
UV
DEAD TIME
DISABLE
UV
20 VDD
RFSH
PULSE
DRIVER
TURN-ON
DELAY
ALI
RDEL
21 ALO
4
6
DEAD TIME
CURRENT
MIRRORS
7
VSS
DEAD TIME
DISABLE
2µs
DELAY
+
100mV +VSS
TRUTH TABLE
INPUT
ALI, BLI, CLI
AHI, BHI, CHI
UV
X
X
X
X
1
OUTPUT
DIS
RDEL
ALO, BLO, CLO
AHO, BHO, CHO
X
1
X
0
0
1
X
X
0
0
X
0
0
>100mV
1
0
0
0
0
0
X
0
1
0
1
0
0
X
0
0
1
0
0
0
<100mV
1
1
NOTE: X signifies that input can be either a “1” or “0”.
Typical Application (PWM Mode Switching)
+12V
80V
+12V
RDEL
PWM
INPUTS
RUV
(OPTIONAL)
CRFSH
(OPTIONAL)
FROM
OPTIONAL
OVERCURRENT
LATCH
2
1 BHB
BHO 24
2 BHI
BHS 23
3 BLI
BLO 22
4 ALI
ALO 21
5 AHI
VDD 20
6 VSS
CLO 19
7 RDEL
AHS 18
8 UVLO
AHO 17
9 RFSH
AHB 16
10 DIS
CHS 15
11 CLI
CHO 14
12 CHI
CHB 13
RDIS
GND
3-PHASE
LOAD
HIP4086
Pin Descriptions
PIN
NUMBER
NOTE:
SYMBOL
DESCRIPTION
16
1
13
AHB
BHB
CHB
(xHB)
High-Side Bootstrap supplies. One external bootstrap diode and one capacitor are required for each. Connect
cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB pin.
5
2
12
AHI
BHI
CHI
(xHI)
High-Side Logic Level Inputs. Logic at these three pins controls the three high side output drivers, AHO (Pin
17), BHO (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI is high, xHO is low. Unless the
dead time is disabled by connecting RDEL (Pin 7) to ground, the low side input of each phase will override the
corresponding high side input on that phase - see Truth Table on previous page. If RDEL is tied to ground,
dead time is disabled and the outputs follow the inputs. Care must be taken to avoid shoot-through in this application. DIS (Pin 10) also overrides the high side inputs. xHI can be driven by signal levels of 0V to 15V (no
greater than VDD). An internal 100µA pull-up to VDD will hold each xHI high if the pins are not driven.
4
3
11
ALI
BLI
CLI
(xLI)
Low-Side Logic Level Inputs. Logic at these three pins controls the three low side output drivers ALO (Pin 21),
BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the lower inputs control both xLO and
xHO drivers, with the dead time set by the resistor at RDEL (Pin 7). DIS (Pin 10) high level input overrides xLI,
forcing all outputs low. xLI can be driven by signal levels of 0V to 15V (no greater than VDD). An internal 100µA
pull-up to VDD will hold xLI high if these pins are not driven.
6
VSS
Ground. Connect the sources of the Low-Side power MOSFETs to this pin.
7
RDEL
Dead Time Setting. Connect a resistor from this pin to VDD to set timing current that defines the dead time
between drivers - see Figure 15. All drivers turn-off with no adjustable delay, so the RDEL resistor guarantees
no shoot-through by delaying the turn-on of all drivers. When RDEL is tied to VSS, both upper and lowers can
be commanded on simultaneously. While not necessary in most applications, a decoupling capacitor of 0.1µF
or smaller may be connected between RDEL and VSS.
8
UVLO
Undervoltage Setting. A resistor can be connected between this pin and VSS to program the undervoltage set
point, see Figure 16. With this pin not connected, the undervoltage disable is typically 6.6V. When this pin is
tied to VDD, the undervoltage disable is typically 6.2V.
9
RFSH
Refresh Pulse Setting. An external capacitor can be connected from this pin to V SS to increase the length of
the start up refresh pulse - see Figure 14. If this pin is not connected, the refresh pulse is typically 1.5µs.
10
DIS
Disable Input. Logic level input that when taken high sets all six outputs low. DIS high overrides all other inputs.
With DIS low, the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to 15V
(no greater than VDD). An internal 100µA pull-up to VDD will hold DIS high if this pin is not driven.
17
24
14
AHO
BHO
CHO
(xHO)
High-Side Outputs. Connect to the gates of the High-Side power MOSFETs in each phase.
15
23
15
AHS
BHS
CHS
(xHS)
High-Side Source Connection. Connect the sources of the High-Side power MOSFETs to these pins. The negative side of the bootstrap capacitors should also be connected to these pins.
20
VDD
Positive Supply. Decouple this pin to VSS (Pin 6).
21
22
19
ALO
BLO
CLO
(xLO)
Low-Side Outputs. Connect the gates of the Low-Side power MOSFETs to these pins.
x = A, B and C.
3
HIP4086
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on xHS . . . . . . . . . -6V (Transient) to 85V (-40oC to 150oC)
Voltage on xHB . . . . . . . . . . . . . . . . . . . . VxHS -0.3V to VxHS +VDD
Voltage on xLO . . . . . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V
Voltage on xHO . . . . . . . . . . . . . . . . . . . . VxHS -0.3V to VxHB +0.3V
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V to +15V
Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS + VDD
Voltage on xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . -40oC to 125oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . -40oC to 150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. All voltages are relative to VSS unless otherwise specified.
3. x = A, B and C. For example, xHS refers to AHS, BHS and CHS.
VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 20K, RUV = ∞, Gate Capacitance (CGATE) = 1000pF
Electrical Specifications
TJ = -40oC TO
150oC
TJ = 25oC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
MIN
MAX
UNITS
SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION
VDD Quiescent Current
xHI = 5V, xLI = 5V
2.7
3.4
4.2
2.1
4.3
mA
VDD Operating Current
f = 20kHz, 50% Duty Cycle
6.3
8.25
10.5
5
11
mA
xHB On Quiescent Current
xHI = 0V
-
40
80
-
100
µA
xHB Off Quiescent Current
xHI = VDD
0.6
0.8
1.3
0.5
1.4
mA
xHB Operating Current
f = 20kHz, 50% Duty Cycle
0.7
0.9
1.3
-
2.0
mA
Qpump Output Voltage
No Load
11.5
12.5
14
10.5
14.5
V
Qpump Output Current
VxHS = 12V, VxHB = 22V
50
100
130
-
140
µA
xHB, xHS Leakage Current
VxHS = 80V, VxHB = 93V
7
24
45
-
50
µA
VDD Rising Undervoltage Threshold
RUV open
6.2
7.1
8.0
6.1
8.1
V
VDD Falling Undervoltage Threshold
RUV open
5.75
6.6
7.5
5.6
7.6
V
Minimum Undervoltage Threshold
RUV = VDD
5
6.2
6.8
4.9
6.9
V
Low Level Input Voltage
-
-
1.0
-
0.8
V
High Level Input Voltage
2.5
-
-
2.7
-
V
Input Voltage Hysteresis
-
35
-
-
-
mV
INPUT PINS: ALI, BLI, CLI, AHI, BHI, CHI, AND DIS
Low Level Input Current
VIN = 0V
60
100
135
55
140
µA
High Level Input Current
VIN = 5V
-1
-
+1
-10
+10
µA
-
100
-
-
200
mV
GATE DRIVER OUTPUT PINS: ALO, BLO, CLO, AHO, BHO, AND CHO
Low Level Output Voltage (VOUT - VSS)
ISINKING = 30mA
Peak Turn-On Current
VOUT = 0V
0.3
0.5
0.7
-
1.0
A
Peak Turn-Off Current
VOUT = 12V
0.7
1.1
1.5
0.5
1.7
A
4
HIP4086
Switching Specifications
VDD = VxHB = 12V, VSS = VxHS = 0V, CGATE = 1000pF, RDEL = 10k
TJ = -40oC TO
150oC
TJ = 25oC
MIN
TYP
MAX
MIN
MAX
UNITS
RDEL = 100K
3.8
4.5
6
3
7
µs
RDEL = 10K
0.38
0.5
0.65
0.3
0.7
µs
Dead Time Channel Matching
RDEL = 10K
-
7
15
-
20
%
Lower Turn-Off Propagation Delay
(xLI-xLO)
No Load
-
30
45
-
65
ns
Upper Turn-Off Propagation Delay
(xHI-xHO)
No Load
-
75
90
-
100
ns
Lower Turn-On Propagation Delay
(xLI-xLO)
No Load
-
45
75
-
90
ns
Upper Turn-On Propagation Delay (xHI-xHO)
No Load
-
65
90
-
100
ns
Rise Time
CGATE = 1000pF
-
20
40
-
50
ns
Fall Time
CGATE = 1000pF
-
10
20
-
25
ns
Disable Turn-Off Propagation Delay
(DIS - Lower Outputs)
-
55
80
-
90
ns
Disable Turn-Off Propagation Delay
(DIS - Upper Outputs)
-
80
90
-
100
ns
Disable to Lower Turn-On Propagation Delay
(DIS - xLO)
-
55
80
-
100
ns
PARAMETER
TEST CONDITIONS
TURN-ON DELAY AND PROPAGATION DELAY
Dead Time
Disable to Upper Enable (DIS - xHO)
RDEL = 10K, CRFSH Open
-
2.0
-
-
-
µs
Refresh Pulse Width (xLO)
CRFSH Open
-
1.5
-
-
-
µs
5
HIP4086
Timing Diagrams
LOWER
TURN-OFF
LOWER
TURN-ON
XLI
XHI
XLO
XHO
DEAD TIME
DEAD TIME
XLO (RDEL = VSS)
XHO (RDEL = VSS)
UPPER
TURN-ON
UPPER
TURN-OFF
FIGURE 1.
DISABLE TO LOWER
TURN-ON PROP DELAY
DIS OR UV
DISABLE TURN-OFF
PROP DELAY (UPPERS)
REFRESH
PULSE WIDTH
XHI, XLI
XLO
XHO
DISABLE TO UPPER
ENABLE
FIGURE 2. DISABLE FUNCTION
NOTES:
4. X means any “A”, “B”, or “C” phase.
5. With RDEL resistor tied to VDD, lowers and uppers cannot be turned on at the same time. Low side logic overrides high side logic unless RDEL
< 100mV.
6
HIP4086
Typical Performance Curves
30
6
VDD SUPPLY CURRENT (mA)
VDD SUPPLY CURRENT (mA)
5
VDD = 15V
VDD = 12V
4
VDD = 10V
3
CGATE = 1000pF
ALL GATE CONTROL INPUTS = 5V
VDD = 16V
VDD = 8V
200kHz
25
100kHz
20
50kHz
20kHz
10kHz
15
VDD = 7V
2
-60
-40
-20
0
20
40
60
80 100
JUNCTION TEMPERATURE (oC)
120
140
10
-60
160
FIGURE 3. VDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE
120
140
160
VDD = 15V
1.6
3000
BIAS CURRENT (mA)
FLOATING BIAS CURRENT (µA)
0
20
40
60
80 100
JUNCTION TEMPERATURE (oC)
1.8
TJ = 25oC
CGATE = 1000pF
2000
1000
CGATE = NO LOAD
0
20
40
60
80
100 120 140 160
SWITCHING FREQUENCY (kHz)
1.4
1.2
VDD = 10V
VDD = 8V
VDD = 7V
1.0
VDD = 12V
0.8
180
0.6
-60
200
-40
-20
0
20
40
60
80 100
JUNCTION TEMPERATURE (oC)
120
140
160
140
160
FIGURE 6. OFF-STATE IXHB BIAS CURRENT
FIGURE 5. FLOATING IXHB BIAS CURRENT
14
CHARGE PUMP OUTPUT VOLTAGE (V)
200
VxHB - VxHS = 10V
OUTPUT CURRENT (µA)
-20
FIGURE 4. VDD SUPPLY CURRENT vs SWITCHING
FREQUENCY
4000
0
-40
150
100
50
0
-60
-40
-20
0
20
40
60
80
100 120 140 160
JUNCTION TEMPERATURE (oC)
FIGURE 7. CHARGE PUMP OUTPUT CURRENT
7
VDD = 15V
13
12
VDD = 12V
VDD = 10V
11
10
VDD = 8V
9
8
VDD = 7V
7
6
-60
-40
-20
0
20
40
60
80
100
120
JUNCTION TEMPERATURE (oC)
FIGURE 8. CHARGE PUMP OUTPUT VOLTAGE
HIP4086
Typical Performance Curves
(Continued)
1
2
AVERAGE TURN-OFF CURRENT (A)
AVERAGE TURN-ON CURRENT (A)
CGATE = 1000pF
0.8
VDD = 15V
0.6
VDD = 12V
VDD = 10V
0.4 V
DD = 8V
VDD = 7V
0.2
0
-60
-40
-20
0
20
40
60
80 100
JUNCTION TEMPERATURE (oC)
120
140
1.6
VDD = 12V
1.2 VDD = 10V
VDD = 8V
0.8
VDD = 7V
0.4
0
-60
160
CGATE = 1000pF
VDD = 15V
-40
-20
0
20
40
60
80 100
JUNCTION TEMPERATURE (oC)
120
140
160
FIGURE 9. AVERAGE TURN-ON CURRENT (0 TO 5V)
FIGURE 10. AVERAGE TURN-OFF CURRENT (VDD TO 4V)
40
100
PROPAGATION DELAY (ns)
RISE AND FALL TIMES (ns)
VDD = XHB-XHS = 12V, CGATE = 1000pF
30
RISE
20
FALL
10
0
-60
-40
-20
0
20
40
60
80 100
JUNCTION TEMPERATURE (oC)
120
140
80
xHI to xHO
60
40
xLI to xLO
20
-60
160
-40
0
20
40
60
80
100
120
140
160
450
500
JUNCTION TEMPERATURE (oC)
FIGURE 11. RISE AND FALL TIMES (10-90%)
FIGURE 12. PROPAGATION DELAY
80
100
TJ = 25oC
REFRESH TIME (µs)
UPPER DISABLE TURN-OFF
PROPAGATION DELAY (ns)
-20
LOWER DISABLE TURN-OFF
LOWER ENABLE TURN-ON
10
-60
-40
-20
0
20
40
60
80 100
JUNCTION TEMPERATURE (oC)
120
140
FIGURE 13. DISABLE PIN PROPAGATION DELAY
8
160
60
40
20
0
0
50
100
150
200 250 300
CRFSH (pF)
350
FIGURE 14. REFRESH TIME
400
HIP4086
Typical Performance Curves
(Continued)
11
6
10.5
UNDERVOLTAGE SHUTDOWN/
ENABLE VOLTAGE
DEAD TIME (µs)
RDEL = 100kΩ
4
2
RDEL = 10kΩ
10
ENABLE (50K, UVLO TO GND)
9.5
9
8.5
TRIP (50K, UVLO TO GND)
8
7.5
TRIP/ENABLE (0K, UVLO TO VDD)
7
ENABLE (UVLO OPEN)
TRIP (UVLO OPEN)
6.5
0
-60
-40
-20
0
20
40
60
80 100
JUNCTION TEMPERATURE (oC)
120
140
160
FIGURE 15. DEAD TIME
6
-60
-40
-20
0
20
40
60
80 100 120 140 160
JUNCTION TEMPERATURE (oC)
FIGURE 16. UNDERVOLTAGE THRESHOLD
LEAKAGE CURRENT (µA)
25
VxHS = 80V
20
15
10
-60
-40
-20
0
20
40
60
80 100
JUNCTION TEMPERATURE (oC)
120
140
160
FIGURE 17. IxHS LEAKAGE CURRENT
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