INTERSIL HS1

HS-26C32RH
TM
Data Sheet
August 2000
Radiation Hardened Quad Differential Line
Receiver
The Intersil HS-26C32RH is a differential line receiver
designed for digital data transmission over balanced lines
and meets the requirements of EIA Standard RS-422.
Radiation hardened CMOS processing assures low power
consumption, high speed, and reliable operation in the most
severe radiation environments.
File Number
3402.3
Features
• Electrically Screened to SMD # 5962-95689
• QML Qualified per MIL-PRF-38535 Requirements
• 1.2 Micron Radiation Hardened CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . . 300 krad(Si) (Max)
• Latchup Free
• EIA RS-422 Compatible Inputs
The HS-26C32RH has an input sensitivity typically of 200mV
over the common mode input voltage range of ±7V. The
receivers are also equipped with input fail safe circuitry,
which causes the outputs to go to a logic “1” when the inputs
are open. Enable and Disable functions are common to all
four receivers.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95689. A “hot-link” is provided
on our homepage for downloading.
www.intersil.com/spacedefense/space.asp
• CMOS Compatible Outputs
• Input Fail Safe Circuitry
• High Impedance Inputs when Disabled or Powered Down
• Low Power Dissipation 138mW Standby (Max)
• Single 5V Supply
• Full -55oC to 125oC Military Temperature Range
Pinouts
HS1-26C32RH 16 LEAD CERAMIC SIDEBRAZE DIP
MIL-STD-1835: CDIP2-T16
TOP VIEW
Ordering Information
ORDERING NO.
AOUT 3
14 BIN
HS1-26C32RH-8
-55 to 125
COUT 5
CIN 6
11 DOUT
CIN 7
10 DIN
GND 8
9 DIN
HS9-26C32RH-8
-55 to 125
5962F9568901V9A
HS0-26C32RH-Q
25
5962F9568901VEC
HS1-26C32RH-Q
-55 to 125
5962F9568901VXC
HS9-26C32RH-Q
-55 to 125
HS1-26C32RH/PROTO HS1-26C32RH/PROTO
-55 to 125
HS9-26C32RH/PROTO HS9-26C32RH/PROTO
-55 to 125
ENABLE DIN DIN
-
CIN CIN
+
-
COUT
1
BIN BIN
+
-
BOUT
AIN AIN
+
13 BOUT
ENABLE 4
12 ENABLE
HS9-26C32RH 16 LEAD FLATPACK
MIL-STD-1835: CDFP4-F16
TOP VIEW
Logic Diagram
DOUT
15 BIN
TEMP. RANGE
(oC)
5962F9568901QXC
+
16 VDD
AIN 2
INTERNAL MKT. NO.
5962F9568901QEC
ENABLE
AIN 1
-
AIN
1
16
VDD
AIN
2
15
BIN
AOUT
3
14
BIN
ENABLE
4
13
BOUT
COUT
5
12
ENABLE
CIN
6
11
DOUT
CIN
7
10
DIN
GND
8
9
DIN
AOUT
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HS-26C32RH
Propagation Delay Timing Diagram
Propagation Delay Load Circuit
TEST
POINT
DUT
-VIN
+2.5V
INPUT
0V
+VIN = 0V
CL
-2.5V
RL
tPHL
tPLH
VOH
VS = 50%
CL = 50pF
OUTPUT
RL = 1000Ω
VOL
Three-State Low Timing Diagram
Three-State High Timing Diagrams
VIH
VIH
INPUT
VS
INPUT
VS
VSS
VSS
TPZL
tPZH
TPLZ
VOZ
tPHZ
VOH
VT
VW
OUTPUT
VOL
VT
VW
OUTPUT
VOZ
THREE-STATE LOW VOLTAGE LEVELS
PARAMETER
THREE-STATE HIGH VOLTAGE LEVELS
HS-26C32RH
UNITS
VDD
4.50
V
VIH
4.50
VS
HS-26C32RH
UNITS
VDD
4.50
V
V
VIH
4.50
V
2.25
V
VS
2.25
V
VT
50
%
VT
50
%
VW
VOL + 0.5
V
VW
VOH - 0.5
V
0
V
GND
0
V
GND
Three-State Low Load Circuit
PARAMETER
Three-State High Load Circuit
VDD
TEST
POINT
DUT
RL
TEST
POINT
DUT
CL
CL
CL = 50pF
CL = 50pF
RL = 1000Ω
RL = 1000Ω
2
RL
HS-26C32RH
Die Characteristics
DIE DIMENSIONS:
Top Metallization:
84 mils x 130 mils
(2140µm x 3290µm)
M1: Mo/Tiw
Thickness: 5800Å
M2: Al/Si/Cu
Thickness: 5800Å
INTERFACE MATERIALS:
Glassivation:
Worst Case Current Density:
Type: SiO2
Thickness: 10kÅ ± 1kÅ
<2.0 x 105A/cm2
Bond Pad Size:
110µm x 100µm
Metallization Mask Layout
HS-26C32RH
AIN
(1)
VDD
(16)
BIN
(15)
(14) BIN
AIN (2)
(13) BOUT
AOUT (3)
ENAB (4)
(12) ENAB
COUT (5)
(11) DOUT
(10) DIN
CIN (6)
(7)
CIN
3
(8)
GND
(9)
DIN
HS-26C32RH
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
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4
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