HS-26CT32RH ® Data Sheet August 7, 2008 Radiation Hardened Quad Differential Line Receiver The Intersil HS-26CT32RH is a differential line receiver designed for digital data transmission over balanced lines and meets the requirements of EIA standard RS-422. Radiation hardened CMOS processing assures low power consumption, high speed, and reliable operation in the most severe radiation environments. FN2930.4 Features • Electrically Screened to SMD # 5962-95631 • QML Qualified per MIL-PRF-38535 Requirements • 1.2 Micron Radiation Hardened CMOS - Total Dose . . . . . . . . . . . . . . . . . . . .Up to 300kRAD(Si) • Latch-up Free • EIA RS-422 Compatible Outputs The HS-26CT32RH has an input sensitivity typically of 200mV over the common mode input voltage range of ±7V. The receivers are also equipped with input fail safe circuitry, which causes the outputs to go to a logic “1” when the inputs are open. Enable and Disable functions are common to all four receivers. • Operation with TTL Based on VIH = VDD/2 • Input Fail Safe Circuitry • High Impedance Inputs when Disabled or Powered Down • Low Power Dissipation Standby (Max). . . . . . . . . .138mW Specifications for Rad Hard QML devices are controlled by the Defense Supply Center in Columbus (DSCC). The SMD numbers listed in the “Ordering Information” must be used when ordering. • Single 5V Supply Detailed Electrical Specifications for these devices are contained in SMD 5962-95631. A “hot-link” is provided on our homepage for downloading. http://www.intersil.com/military/ • Line Receiver for MIL-STD-1553 Serial Data Bus • Full Military Temperature Range . . . . . . -55°C to +125°C Applications • Line Receiver for RS422 Logic Diagram ENABLE ENABLE DIN DIN + - DOUT CIN CIN BIN BIN AIN AIN + + + - COUT - BOUT - AOUT Ordering Information ORDERING NUMBER INTERNAL MKT. NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # 5962F9563101QEC HS1-26CT32RH-8 Q 5962F95 63101QEC -55 to +125 16 Ld SBDIP 5962F9563101QXC HS9-26CT32RH-8 Q 5962F95 63101QXC -55 to +125 16 Ld FLATPACK K16.A 5962F9563101V9A HS0-26CT32RH-Q 5962F9563101VEC HS1-26CT32RH-Q Q 5962F95 63101VEC -55 to +125 16 Ld SBDIP 5962F9563101VXC HS9-26CT32RH-Q Q 5962F95 63101VXC -55 to +125 16 Ld FLATPACK K16.A HS1-26CT32RH/PROTO HS1-26CT32RH/PROTO HS1- 26CT32RH /PROTO -55 to +125 16 Ld SBDIP HS9-26CT32RH/PROTO HS9-26CT32RH/PROTO HS9- 26CT32RH /PROTO -55 to +125 16 Ld FLATPACK K16.A 1 D16.3 -55 to +125 D16.3 D16.3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. HS-26CT32RH Pinouts HS9-26CT32RH (16 LD FLATPACK, CDFP4-F16) TOP VIEW HS1-26CT32RH (16 LD SBDIP, CDIP2-T16) TOP VIEW AIN 1 16 VDD AIN 1 16 VDD AIN 2 15 BIN AIN 2 15 BIN 14 BIN AOUT 3 14 BIN ENABLE 4 13 BOUT COUT 5 12 ENABLE CIN 6 11 DOUT CIN 7 10 DIN GND 8 9 DIN AOUT 3 13 BOUT ENABLE 4 COUT 5 12 ENABLE CIN 6 11 DOUT CIN 7 10 DIN GND 8 9 DIN All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 2 FN2930.4 August 7, 2008 HS-26CT32RH Die Characteristics DIE DIMENSIONS: Backside Finish: 84 mils x 130 mils (2140µm x 3290µm) Silicon ASSEMBLY RELATED INFORMATION: INTERFACE MATERIALS: Substrate Potential: Glassivation: VDD (When Powered Up) Type: PSG (Phosphorus Silicon Glass) Thickness: 10kÅ ±1kÅ ADDITIONAL INFORMATION: Worst Case Current Density: Top Metallization: <2.0 x 105A/cm2 M1: Mo/Tiw Thickness: 5800Å M2: Al/Si/Cu Thickness: 10kÅ ±1kÅ Transistor Count: 240 Bond Pad Size: Substrate: 110µm x 100µm AVLSI1RA Metallization Mask Layout HS-26CT32RH AIN (1) VDD (16) BIN (15) (14) BIN AIN (2) (13) BOUT AOUT (3) ENAB (4) (12) ENAB COUT (5) (11) DOUT (10) DIN CIN (6) (7) CIN 3 (8) GND (9) DIN FN2930.4 August 7, 2008