KMB001EVAL vdd2_anlg anlg_1.8V vdd3_anlg_sense vdd3_anlg anlg_3.3V Anlg_5V clk_out clk_outn dig_out8 dig_outn8 dig_out7 dig_outn7 DNP dig_outn8 dig_out7 R79 DNP dig_outn7 dig_out6 R81 DNP dig_outn6 dig_out5 R86 DNP dig_outn5 dig_out4 R24 DNP dig_outn4 dig_out3 R25 DNP dig_outn3 dig_out2 R30 DNP dig_outn2 dig_out0 R87 2.5V VCCO U7B dig_out2 dig_outn2 dig_out1 dig_outn1 dig_out0 dig_outn0 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 SD0 SC0 SD2 SC2 PORn/ExtResetn PD2 PD4 PD5 PD7 FPGA_spare_1 DGND GND dig_outn9 dig_out8 dig_outn8 RAM_A2 clk_out clk_outn dig_out7 dig_outn7 1.2V VCCINT VCCO 1 8 14 25 30 41 47 53 59 66 75 82 91 99 105 112 118 129 134 145 151 157 163 170 179 186 195 202 dig_out3 dig_outn3 VCCO DNP dig_outn0 dig_out5 dig_outn5 dig_out4 dig_outn4 dig_out12 dig_outn12 RAM_A0 dig_out11 dig_outn11 dig_out10 dig_outn10 RAM_A1 dig_out9 DNP dig_outn1 dig_out1 R31 dig_out6 dig_outn6 dig_out13 dig_outn13 VCCO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX RAM_A3 dig_out6 dig_outn6 dig_out5 dig_outn5 RAM_A4 dig_out4 dig_outn4 RAM_OE 17 38 69 89 121 142 173 193 VCCO VCCINT VCCINT VCCINT VCCINT 70 88 174 192 dig_out3 dig_outn3 RAM_CLK J1 PROG_B R27 249 158 159 160 161 162 164 165 166 167 168 169 171 172 175 176 177 178 180 181 182 183 184 185 187 188 189 190 191 194 196 197 198 199 200 201 203 204 205 206 207 208 VCCO VCCO VCCO RAM_D3 RAM_D2 RAM_D1 RAM_D0 DNP clk_outn dig_out8 R77 RAM_D16 RAM_D15 RAM_D14 RAM_D13 RAM_D12 RAM_D11 RAM_D10 RAM_D9 RAM_D8 RAM_D7 RAM_D6 RAM_D5 RAM_D4 DNP dig_outn9 clk_out R23 RAM_D19 RAM_D18 RAM_D17 DNP dig_outn10 dig_out9 R22 131 130 128 127 126 125 124 123 122 120 119 117 116 115 114 113 111 110 109 108 107 106 dig_out10 R21 TDO TCK TMS IO_L01P_1/VRN_1 IO_L01N_1/VRP_1 VCCO_1 IO_L10P_1 IOL10N_1/VREF_1 IO IO_L27P_1 IO_L27N_1 IO_L28P_1 IO_L28N_1 IO IO_L31P_1 VCCO_1 IO_L31N_1/VREF_1 IO_L32P_1/GCLK4 IO_L32N_1/GCLK5 IO CCLK DONE IO/VREF_4 IO_L01N_4/VRP_4 IO_L01P_4/VRN_4 VCCO_4 IO IO/VREF_4 IO_L25N_4 IO_L25P_4 IO IO_L27N_4/DIN/D0 IO_L27P_4/D1 OI_L30N_4/D2 OI_L30P_4/D3 IO/VREF_4 VCCO_4 IO_L31N_4INIT_B IO_L31P_4/DOUT/B IO_L32N_4/GCLK1 IO_L32P_4/GCLK0 IO_L32P_0/GCLK6 IO_L32N_0/GCLK7 IO_L31P_0/VREF_0 IO_L31N_0 VCCO_0 IO IO_L30P_0 IO_L30N_0 IO_L27P_0 IO_L27P_0 IO IO_L25P_0 IO_L25N_0 IO/VREF_0 VCCO_0 IO_L01P_0/VRN_0 IO_L01N_0/VRP_0 IO/VREF_0 HSWAP_EN PROG_B TDI IO/VREF_5 IO_L32N_5/GCLK3 IO_L32P_5/GCLK2 IO_L31N_5/D4 VCCO_5 IO_L31P_5/D5 IO IO_L28N_5/D6 IO_L28P_5/D7 IO_L27N_5/VREF_5 IO_L27P_5 IO IO_L10N_5/VRP_5 IO_L10P_5/VRN_5 VCCO_5 IO_L01N_5/RDWR_B IO_L01P_5/CS_B M2 M0 M1 U7A XC3S200-5PQ208C 104 103 102 101 100 98 97 96 95 94 93 92 90 87 86 85 84 83 81 80 79 78 77 76 74 73 72 71 68 67 65 64 63 62 61 60 58 57 56 55 54 CCLK DONE RAM_A20 RAM_A19 SC3 VCCO RAM_A17 RAM_A16 RAM_A15 RAM_A14 RAM_A13 D0 D1 D2 D3 RAM_A12 VCCO INIT_B BUSY CCLK RAM_A11 R78 FPGA_spare_2 RAM_A10 RAM_A9 D4 4.7K VCCO D5 RAM_A8 D6 D7 FPGA_spare_1 RAM_A7 AF_FLAG RAM_A5 RAM_A6 R84 4.7K VCCO RDWR_B F_FLAG 249 249 249 R26 R28 R29 set to Slave Parallel VCCO VCCO PORn/ExtResetn RAM_D33 RAM_D32 dig_out9 dig_outn9 DNP dig_outn11 RAM_D46 RAM_D45 RAM_D44 RAM_D43 RAM_D42 RAM_D41 RAM_D40 RAM_D39 RAM_D38 RAM_D37 RAM_D36 RAM_D35 RAM_D34 dig_out10 dig_outn10 DNP dig_outn12 dig_out11 R20 VCCO dig_out11 dig_outn11 DNP dig_outn13 dig_out12 R75 IO_L40N_3/VREF3 IO_L40P_3 IO_L39N_3 VCCO_3 IO_L39P_3 IO_L24N_3 IO_L24P_3 IO_L23N_3 IO_L23P_3/VREF3 IO_L22N_3 IO_L22P_3 IO_L21N_3 IO_L21P_3 IO_L20N_3 IO_L20P_3 IO_L19N_3 IO_L19P_3 VCCO_3 IO_L17N_3 IO_L17P_3/VREF_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 RN3 dig_out12 dig_outn12 DNP dig_outn14 dig_out13 R11 RAM_D52 RAM_D51 RAM_D50 RAM_D49 RAM_D48 RAM_D47 dig_out13 dig_outn13 DNP dig_outn15 dig_out14 R74 156 dig_outn14 dig_out14 155 154 RAM_WE 153 152 dig_outn15 dig_out15 150 SD3 149 RAM_A18 148 RAM_D31 147 RAM_D30 146 RAM_D29 144 RAM_D28 143 RAM_D27 141 RAM_D26 140 RAM_D25 139 RAM_D24 138 RAM_D23 137 136 RAM_D22 135 RAM_D21 133 RAM_D20 132 dig_out14 dig_outn14 dig_out15 R10 IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO/VREF_2 VCCO_2 IO_L19N_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 IO_L21P_2 IO_L22N_2 IO_L22P_2 IO_L23N_2/VREF_2 IO_L23P_2 IO_L24N_2 IO_L24P_2 IO_L39N_2 VCCO_2 IO_L39P_2 IO_L40N_2 IO_L40P_2/VREF2 dig_out15 dig_outn15 VCCO DGND GND vdd2_anlg_sense DNP these 100 Ohms resistors for CMOS version VCC dig_out0 dig_outn0 RAM_D63 RAM_D62 RAM_D61 RAM_D60 RAM_D59 RAM_D58 RAM_D57 RAM_D56 RAM_D55 RAM_D54 RAM_D53 FPGA_spare_2 Dig_5V VCCO 52760-1879 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 IO_L16P_7 IO_L16N_7 VCCO_7 IO_L19P_7 IO_L19N_7/VREF_7 IO_L20P_7 IO_L20N_7 IO_L21P_7 IO_L21N_7 IO_L22P_7 IO_L22N_7 IO_L23P_7 IO_L23N_7 IO_L24P_7 IO_L24N_7 IO_L39P_7 VCCO_7 IO_L39N_7 IO_L40P_7 IO_L40N_7/VREF_7 IO_L40P_6/VREF_6 IO_L40N_6 IO_L39P_6 VCCO_6 IO_L39N_6 IO_L24P_6 IO_L24N_6/VREF_6 IO_L23P_6 IO_L23N_6 IO_L22P_6 IO_L22N_6 IO_L21P_6 IO_L21N_6 IO_L20P_6 IO_L20N_6 IO_L19P_6 IO_L19N_6 VCCO_6 IO_VREF_6 IO_L01P_6/VRN_6 IO_L01N_6/VRP_6 J3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 2 3 4 5 6 7 9 10 11 12 13 15 16 18 19 20 21 22 23 24 26 27 28 29 31 32 33 34 35 36 37 39 40 42 43 44 45 46 48 49 50 51 52 vdd2_lvds_sense vdd2_lvds dig_out2 dig_outn2 dig_out1 dig_outn1 Board_1.8V VCCO KMB001CEVAL Schematics XC3S50-4PQ208C 0.1uF 0.1uF VCCINT 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C49 C66 C68 C77 C71 C80 C84 C76 0.1uF C87 0.1uF 0.1uF C90 C91 VCCO 0.1uF C92 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF VCCO 0.1uF 0.1uF 0.1uF 0.1uF C93 C108 C58 C59 C60 C61 C65 C70 C79 C83 C73 INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREEMENT Title Size KMB-001C Number Date: File: FIGURE 1. FPGA, INPUT/OUTPUT MEZZANINE CONNECTOR 1 Revision B1 B 1/28/2009 Sheet of Z:\work\..\KMB-001_FPGA_rev_B1.SchDoc Drawn By: KMB001EVAL KMB001CEVAL Schematics (Continued) TPS79601KTTT U15 100pF C2 0.1uF C36 L29 TPS79601KTTT U3 TP9 Dig_5V TP3 2 10K DUT_POW 1 IN EN R69 .1uF C5 33uF C116 5 1 POW_EN 0.1uF C28 2 L23 MMZ2012R102A 0.1uF C27 EN FB FB dig_1.8V 5 C16 33uF 33pF C41 D2 1 R3 DNP R70 21K C32 C26 0.1uF 33uF T1 EDZ350/2 JP1 WSLG-.10CT-ND DLW5BSN351SQ2 1 2 5V_external R6 3 VCC 5 U23 LTC2609IGN-1 C46 .1uF C112 .1uF FIGURE 2. POWER V+ 3 4 Dig_5V OUT 1 board supply_I INA193 BLM41PG102SN1L L20 R2 2K board supply/3 Anlg_5V C107 330uF R56 1K DS1 2 C113 .1uF C109 330uF C110 .1uF U24 pin2 Anlg_5V U3 pin2 U1 pin2 Anlg_5V U14 pin2 Dig_5V U12 pin2 Dig_5V U5 pin2 Dig_5V U4 pin2 C45 .1uF BLM41PG102SN1L L7 JP3 DNP EGND EGND C44 .1uF C47 0.1uF C111 .1uF INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREEMENT Title KMB001C Size Number Revision B1 B Date: File: 2 1 vdd2_lvds_I U17 2 1 C123 33uF PJ-102AH DNP Anlg_5V FIFO_Vdd2_LDO_adj FIFO_Vdd3_LDO_adj FIFO_Ovdd2_LDO_adj SPARE_DAC1 Dig_5V 56.2K 56.2K 56.2K 56.2K U2 pin2 R115 R107 R55 R49 Dig_5V SCL SDA CA2 CA1 CA0 L27 Bead L26 Bead C120 8 9 7 10 11 R108 R100 R102 R109 C117 SC2 SD2 R42 R41 R101 1K 1K 1K 1K 1000pF 0 0 0 2 PJ-102AH 4 5 13 14 1 C39 VCC VoutA VoutB VoutC VoutD GND 1000pF R126 10K REFA REFB REFC REFD REFLO C121 3 6 12 15 2 200 C119 0.1uF 1000pF 16 R110 OUT C20 330uF 1 3 D1 R68 249 VB 1 MA2SD1000L 2.5V board supply 3 EGND J1 1000pF GND 2 4 EGND PD_reset VCC Vcc 4 3 EN Vin VCC V+ 0.1 Ohm LM4120IM5-2.5 U11 5 .1uF C48 R51 DNP vdd2_lvds 5 249 DNP FIFO_LDO_DAC_Ref U18 R1 0 VCC vdd2_lvds_sense/3 2 .1uF R7 1 vdd2_lvds_sense R62 10K 2 FIFO_Ovdd2_LDO_adj anlg_3.3V PTS525SM10SM DNP S1 R96 2V nominal 0.047uF 4 ERJ-1TRQF1R0U 4 3.3V Norminal TPS79633KTTT U12 4 IN OUT GND Anlg_5V GND Board_1.8V OUT 4 TP2 3 TP1 0.1uF C42 C38 1 vdd3_anlg_I Vin- TP4 Vin+ 0.1uF VCC 5 OUT INA193 GND 0.1uF C37 Vout V+ 2 C57 0.1uF 4 C62 0.1uF 3 C78 0.1uF GND C67 0.1uF D3 Ref 5 .1uF C106 R34 8K MMZ2012R102A 1 2 1 3 R91 R105 8K Anlg_5V 35.7K vdd3_anlg_sense/2 R106 21K Vin- R48 DNP U22 MMZ2012R102A TP10 FB vdd3_anlg_sense Vin- 3 GND EN 2 vdd3_anlg 1 C25 33uF D4 15pF C114 FIFO_Vdd3_LDO_adj GND GND C64 TPS79618KTTT U14 4 IN OUT POW_EN 1 R36 5 MMZ2012R102A MMZ2012R102A VCCO C63 3 2 C18 33uF 5 GND Dig_5V FB ERJ-1TRQF1R0U Vin+ MMZ2012R102A 6 3 GND EN 1 vdd2_anlg_I OUT L15 6 POW_EN 1 V+ 4 L28 L14 FPGA_IO 2.5V Norminal FB .1uF C31 L24 MMZ2012R102A L13 TPS79625KTTT U5 4 IN OUT 6 2 EN MMZ2012R102A MMZ2012R102A Dig_5V 5 .1uF C105 GND L5 R67 1 R99 L19 MMZ2012R102A 2K OUT 1 DNP R33 DNP 3 L4 DUT_ANLG_POW IN GND C17 2 GND C43 MMZ2012R102A MMZ2012R102A 33uF 0 Anlg_5V L18 6 R71 5 L3 6 FB R97 21K TPS79601KTTT U16 MMZ2012R102A 3 3 GND EN GND POW_EN 1 33pF R90 0 Anlg_5V vdd2_anlg_sense/3 MMZ2012R102A L17 MMZ2012R102A VCCINT 6 Dig_5V 1.2V nominal U21 R104 10K L16 MMZ2012R102A L2 3 L1 FPGA Core Supply vdd2_anlg Vin- vdd2_anlg_sense R46 DNP Vin+ 2 FIFO_Vdd2_LDO_adj TPS79601KTTT U4 2 4 IN OUT R35 0.51 Ohms C24 33uF D5 GND .1uF C30 TPS3801T50DCKR C118 5 2 R98 L25 MMZ2012R102A 4 FB 2 MR VDD EN 3 GND GND RESET 1 1K anlg_1.8V 33pF C115 Vin+ 0.1uF POW_EN 33uF DUT_ANLG_POW CHIP SUPPLY ERJ-1TRQF1R0U 4 GND 3 C29 5 FB 6 GND EN DUT_POW 5 OUT 1 1 PD_reset power down Vcc 1 2 3 IN GND 4.7K U1 VCC 2 6 Dig_5V GND R95 Anlg_5V GND Dig_5V 3.3V Norminal TPS79633KTTT U13 2 4 IN OUT 3 Dig_5V 1/28/2009 Sheet of Drawn By: Z:\work\..\KMB-001_Power_rev_B1.SchDoc KMB001EVAL KMB001CEVAL Schematics (Continued) OGP DNP R116 DNP R119 DNP R118 DNP PC7 RAM_A20 R121 DNP R120 DNP PC2 RAM_A19 R123 DNP R122 DNP PC5 RAM_A18 R125 DNP R124 DNP PC6 DQc DQc DQc DQc DQc DQc DQc DQc DQd DQd DQd DQd DQd DQd DQd DQd RAM_A0 RAM_A1 RAM_A2 RAM_A3 RAM_A4 RAM_A5 RAM_A6 RAM_A7 RAM_A8 RAM_A9 RAM_A10 RAM_A11 RAM_A12 RAM_A13 RAM_A14 RAM_A15 RAM_A16 RAM_A17 RAM_A20 RAM_A19 RAM_A18 38 39 42 43 84 PC4 A A A A A A A A A A A A A0 A1 A A A A NC(288M) NC(144M) NC(72M) NC(36M) NC(18M) 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 R117 FPGA_spare_1 100 99 83 82 81 50 49 48 47 46 45 44 37 36 35 34 33 32 RAM_A20 RAM_A19 RAM_A18 NC(288M) NC(144M) NC(72M) NC(36M) NC(18M) A A A A A A A A A A A A A0 A1 A A A A RAM_D15 RAM_D14 RAM_D13 RAM_D12 RAM_D11 RAM_D10 RAM_D9 RAM_D8 RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0 FPGA_spare_2 38 39 42 43 84 100 99 83 82 81 50 49 48 47 46 45 44 37 36 35 34 33 32 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0 RAM_A17 RAM_A16 RAM_A15 RAM_A14 RAM_A13 RAM_A12 RAM_A11 RAM_A10 RAM_A9 RAM_A8 RAM_A7 RAM_A6 RAM_A5 Populate these resistors for OGP DQb DQb DQb DQb DQb DQb DQb DQb DQa DQa DQa DQa DQa DQa DQa DQa 79 78 75 74 73 72 69 68 63 62 59 58 57 56 53 52 RAM_D31 RAM_D30 RAM_D29 RAM_D28 RAM_D27 RAM_D26 RAM_D25 RAM_D24 RAM_D23 RAM_D22 RAM_D21 RAM_D20 RAM_D19 RAM_D18 RAM_D17 RAM_D16 RAM_D63 RAM_D62 RAM_D61 RAM_D60 RAM_D59 RAM_D58 RAM_D57 RAM_D56 RAM_D55 RAM_D54 RAM_D53 RAM_D52 RAM_D51 RAM_D50 RAM_D49 RAM_D48 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 DQc DQc DQc DQc DQc DQc DQc DQc DQd DQd DQd DQd DQd DQd DQd DQd DQb DQb DQb DQb DQb DQb DQb DQb DQa DQa DQa DQa DQa DQa DQa DQa U10 79 78 75 74 73 72 69 68 63 62 59 58 57 56 53 52 RAM_D47 RAM_D46 RAM_D45 RAM_D44 RAM_D43 RAM_D42 RAM_D41 RAM_D40 RAM_D39 RAM_D38 RAM_D37 RAM_D36 RAM_D35 RAM_D34 RAM_D33 RAM_D32 VCCO 4.7K 4.7K 4.7K 4.7K RAM_WE RAM_CLK R83 88 89 33 ADV/LD OE DQPa DQPb DQPc DQPd WE CLK VDD1 0.1uF C11 0.1uF C12 0.1uF C15 0.1uF C56 0.1uF C55 0.1uF C53 VCCO 0.1uF C52 MMZ2012R102A L22 0.1uF C14 0.1uF C54 VDD1 0.1uF 0.1uF C50 C13 DNP 97 98 92 87 31 64 51 80 1 30 R93 R32 R40 R39 4.7K 4.7K 4.7K 4.7K VDD1 MMZ2012R102A L21 VCC 0.1uF VCCO R38 4.7K VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ R5 R4 R9 R73 85 86 VDD VDD VDD VDD RAM_OE CE2 CE1 CE3 CEN MODE ZZ 66 16 14 4 11 20 27 54 61 70 77 15 41 65 91 5 10 17 21 26 40 55 60 67 71 76 90 51 80 1 30 4.7K 15 41 65 91 DQPa DQPb DQPc DQPd WE CLK Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss 33 ADV/LD OE R8 97 98 92 87 31 64 NC NC NC BWa BWb BWc BWd Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss 88 89 CE2 CE1 CE3 CEN MODE ZZ CY7C1354CV25-250AXC 93 94 95 96 5 10 17 21 26 40 55 60 67 71 76 90 R82 U6 CY7C1354CV25-200AXC 66 16 14 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ RAM_WE RAM_CLK 85 86 NC NC NC 4 11 20 27 54 61 70 77 RAM_OE BWa BWb BWc BWd VDD VDD VDD VDD 93 94 95 96 MMZ2012R102A L8 VDD1 MMZ2012R102A L6 VCC 0.1uF 0.1uF 0.1uF 0.1uF VCCO 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C103 C98 C101 C89 C33 C99 C104 C34 C100 C23 C51 C35 DNP INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREEMENT Title FIGURE 3. MEMORY 3 KMB001EVAL KMB001CEVAL Schematics (Continued) 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C22 C72 C74 C75 C81 C85 C94 TP8 TP7 TP6 TP5 VCC 0.1uF R92 4.7K VCC 1 1 1 1 VCC 2.2uF VCC VB 10 11 17 18 2 C96 C97 12pF 12pF 22 23 24 25 26 27 28 29 30 J2 VB DM DP GND shield 1 2 3 90 Ohms differential transmission line 4 C82 ED90003 USB_CCLK scl sda 4.7nF 31 32 R80 1M TXD0 RXD0 TXD1 RXD1 Shield 40 41 42 43 76 52 51 56 55 54 USB_PROG_B F_FLAG_3V AF_FLAG_3V VCC U20 5 C95 4 0.1uF VDD RESET GND MR WDI 1 2 3 PORn 77 79 16 9 78 66 53 49 38 33 20 1 XTALOUT XTALIN DPLUS DMINUS INT4 T0 T1 T2 IFCLK RESERVED BKPT SCL SDA U8 CY7C68013A-100AXC RD# WR# TXD0 RXD0 TXD1 RXD1 PA0/INT0# PA1/INT1# PA2/SLOE PA3/WU2 PA4/FIFOADR0 PA5/FIFOADR1 PA6PKTEND PA7/FLAGD/SLCS# PE7/GPIFADR8 PC7/GPIFADR7 PC6/GPIFADR6 PC5/GPIFADR5 PC4/GPIFADR4 PC3/GPIFADR3 PC2/GPIFADR2 PC1/GPIFADR1 PC0/GPIFADR0 CLT5 CTL4 CTL3 CTL2/FLAGC CTL1/FLAGB CTL0/FLAGA RESET# WAKEUP 2 21 39 50 48 65 75 94 99 TPS3820-33DBVT CLKOUT 34 35 36 37 44 45 46 47 80 81 82 83 95 96 97 98 67 68 69 70 71 72 73 74 USB_D0 R19 USB_D1 R17 USB_D2 R18 USB_D3 R16 USB_D4 R14 USB_D5 R15 USB_D6 R12 USB_D7 R13 DUT_POW R94 249 PD2 I2C_res PD4 PD5 USB_DISC PD7 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K A0 A1 A2 Vss Vcc WP SCL SDA JP4 1 2 scl sda JUMPER FOR WRITE ENABLE DNP U19 R72 DNP DS3 USB_RDWR_B USB_D3 USB_BUSY USB_INIT_B USB_D4 USB_D5 USB_D6 VCC C69 USB_D7 USB_PROG_B USB_DONE USB_CCLK 0.1uF 93 64 63 62 61 60 59 58 57 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 100 4.7K USB_CCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 F_FLAG_3V USB_RDWR_B AF_FLAG_3V USB_D0 USB_D1 USB_D2 1 Y1 C86 NC 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 2A1 2A2 Vcc 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 F_FLAG RDWR_B AF_FLAG D7 D6 D5 D4 BUSY INIT_B D3 D2 D1 D0 PROG_B DONE CCLK FPGA D0 is MSB VCC SN74CB3T16210DGGR R85 NC NC NC ECS-240-12-4X 1 C88 8 7 6 5 13 14 15 249 C102 0.1uF R37 4.7K U9 1 2 3 4 24AA64A-I/SN PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 AGND AGND 1 RDY0/SLRD RDY1/SLWR RDY2 RDY3 RDY4 RDY5 12 19 USB_BUSY USB_DONE R76 GND GND GND GND GND GND GND GND GND 3 4 5 6 7 8 USB_INIT_B DS2 2 VCC 0.1uF VCC AVCC AVCC USB_DISC VCC VCC VCC VCC VCC VCC VCC VCC R89 4.7K PE6/T2EX PE5/INT6 PE4/RXD1OUT PE3/RXD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT VCC INT5# 92 91 90 89 88 87 86 85 84 C21 R88 4.7K 0.1uF 2 VCC Board ID PROM VCC VCC MAX1239MEEE+ U2 R50 4.7K VCC I2C_res 1 2 13 3 A0 A1 A2 reset to FPGA 0.1uF 0.1uF 0.1uF 0 0 0 1 2 3 4 5 6 7 8 16 R54 15 R60 14 R61 13 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11/REF Vdd 12 0.1uF C40 sda scl GND 10 9 SD1 SC1 11 C3 C4 0.1uF 0.1uF 4.7K R45 0.1uF 4.7K R111 0.1uF 4.7K R112 4.7K 0.1uF C6 C7 C8 to ID eeprom(daughter card) 6 5 4 3 2 1 C9 to ADC power measurement C10 to DUT (daughter card) 0.1uF SD0 SC0 SD1 SC1 SD2 SC2 SD3 SC3 R53 R52 R58 R57 R64 R63 R66 R65 R59 C19 4 5 6 7 9 10 11 12 TXD0 RXD0 TXD1 RXD1 1K 1K 1K 1K 1K 1K 1K 1K 1K C1 SCL SDA SD0 SC0 SD1 SC1 SD2 SC2 SD3 SC3 4.7K 16 VDD 14 15 VCC JP2 DNP molex 053047-0610 INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREEMENT Vss 4.7K R47 scl sda U24 vdd2_lvds_I vdd2_lvds_sense/3 board supply_I board supply/3 vdd2_anlg_I L9 vdd2_anlg_sense/3 L10 vdd3_anlg_I L11 vdd3_anlg_sense/2 L12 FIFO_LDO_DAC_Ref VCCO Title KMB001C 8 4.7K R114 C122 0.1uF VCC R44 VCC 4.7K PCA9546APW-T R103 VCC R113 VCC Size Number Revision B1 B Date: FIGURE 4. USB, MISC. 4 1/28/2009 Sheet 3 of 5 KMB001EVAL vdd2_anlg anlg_1.8V vdd3_anlg_sense vdd3_anlg anlg_3.3V Anlg_5V clk_out clk_outn dig_out8 dig_outn8 dig_out7 dig_outn7 dig_out6 dig_outn6 100 dig_outn8 dig_out7 R79 100 dig_outn7 dig_out6 R81 100 dig_outn6 dig_out5 R86 100 dig_outn5 dig_out4 R24 100 dig_outn4 dig_out3 R25 100 dig_outn3 dig_out2 R30 100 dig_outn2 dig_out1 R31 100 dig_outn1 dig_out0 R87 2.5V U7B dig_out2 dig_outn2 dig_out1 dig_outn1 dig_out0 dig_outn0 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 SD0 SC0 SD2 SC2 PORn/ExtResetn PD2 PD4 PD5 PD7 FPGA_spare_1 DGND GND VCCO dig_outn9 dig_out8 dig_outn8 RAM_A2 VCCO clk_out clk_outn dig_out7 dig_outn7 1.2V VCCINT VCCO 1 8 14 25 30 41 47 53 59 66 75 82 91 99 105 112 118 129 134 145 151 157 163 170 179 186 195 202 dig_out3 dig_outn3 dig_out12 dig_outn12 RAM_A0 dig_out11 dig_outn11 dig_out10 dig_outn10 RAM_A1 dig_out9 100 dig_outn0 dig_out5 dig_outn5 dig_out4 dig_outn4 dig_out13 dig_outn13 VCCO GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX RAM_A3 dig_out6 dig_outn6 dig_out5 dig_outn5 RAM_A4 dig_out4 dig_outn4 RAM_OE 17 38 69 89 121 142 173 193 VCCO VCCINT VCCINT VCCINT VCCINT 70 88 174 192 dig_out3 dig_outn3 RAM_CLK J1 PROG_B R27 249 158 159 160 161 162 164 165 166 167 168 169 171 172 175 176 177 178 180 181 182 183 184 185 187 188 189 190 191 194 196 197 198 199 200 201 203 204 205 206 207 208 VCCO VCCO VCCO RAM_D3 RAM_D2 RAM_D1 RAM_D0 100 clk_outn dig_out8 R77 RAM_D16 RAM_D15 RAM_D14 RAM_D13 RAM_D12 RAM_D11 RAM_D10 RAM_D9 RAM_D8 RAM_D7 RAM_D6 RAM_D5 RAM_D4 100 dig_outn9 clk_out R23 RAM_D19 RAM_D18 RAM_D17 100 dig_outn10 dig_out9 R22 131 130 128 127 126 125 124 123 122 120 119 117 116 115 114 113 111 110 109 108 107 106 dig_out10 R21 TDO TCK TMS IO_L01P_1/VRN_1 IO_L01N_1/VRP_1 VCCO_1 IO_L10P_1 IOL10N_1/VREF_1 IO IO_L27P_1 IO_L27N_1 IO_L28P_1 IO_L28N_1 IO IO_L31P_1 VCCO_1 IO_L31N_1/VREF_1 IO_L32P_1/GCLK4 IO_L32N_1/GCLK5 IO CCLK DONE IO/VREF_4 IO_L01N_4/VRP_4 IO_L01P_4/VRN_4 VCCO_4 IO IO/VREF_4 IO_L25N_4 IO_L25P_4 IO IO_L27N_4/DIN/D0 IO_L27P_4/D1 OI_L30N_4/D2 OI_L30P_4/D3 IO/VREF_4 VCCO_4 IO_L31N_4INIT_B IO_L31P_4/DOUT/B IO_L32N_4/GCLK1 IO_L32P_4/GCLK0 IO_L32P_0/GCLK6 IO_L32N_0/GCLK7 IO_L31P_0/VREF_0 IO_L31N_0 VCCO_0 IO IO_L30P_0 IO_L30N_0 IO_L27P_0 IO_L27P_0 IO IO_L25P_0 IO_L25N_0 IO/VREF_0 VCCO_0 IO_L01P_0/VRN_0 IO_L01N_0/VRP_0 IO/VREF_0 HSWAP_EN PROG_B TDI IO/VREF_5 IO_L32N_5/GCLK3 IO_L32P_5/GCLK2 IO_L31N_5/D4 VCCO_5 IO_L31P_5/D5 IO IO_L28N_5/D6 IO_L28P_5/D7 IO_L27N_5/VREF_5 IO_L27P_5 IO IO_L10N_5/VRP_5 IO_L10P_5/VRN_5 VCCO_5 IO_L01N_5/RDWR_B IO_L01P_5/CS_B M2 M0 M1 U7A XC3S200-5PQ208C 104 103 102 101 100 98 97 96 95 94 93 92 90 87 86 85 84 83 81 80 79 78 77 76 74 73 72 71 68 67 65 64 63 62 61 60 58 57 56 55 54 CCLK DONE RAM_A20 RAM_A19 SC3 VCCO RAM_A17 RAM_A16 RAM_A15 RAM_A14 RAM_A13 D0 D1 D2 D3 RAM_A12 VCCO INIT_B BUSY CCLK RAM_A11 R78 FPGA_spare_2 RAM_A10 RAM_A9 D4 4.7K VCCO D5 RAM_A8 D6 D7 FPGA_spare_1 RAM_A7 AF_FLAG RAM_A5 RAM_A6 R84 4.7K VCCO RDWR_B F_FLAG 249 249 249 R26 R28 R29 set to Slave Parallel VCCO VCCO PORn/ExtResetn RAM_D33 RAM_D32 dig_out9 dig_outn9 100 dig_outn11 RAM_D46 RAM_D45 RAM_D44 RAM_D43 RAM_D42 RAM_D41 RAM_D40 RAM_D39 RAM_D38 RAM_D37 RAM_D36 RAM_D35 RAM_D34 dig_out10 dig_outn10 100 dig_outn12 dig_out11 R20 VCCO dig_out11 dig_outn11 100 dig_outn13 dig_out12 R75 IO_L40N_3/VREF3 IO_L40P_3 IO_L39N_3 VCCO_3 IO_L39P_3 IO_L24N_3 IO_L24P_3 IO_L23N_3 IO_L23P_3/VREF3 IO_L22N_3 IO_L22P_3 IO_L21N_3 IO_L21P_3 IO_L20N_3 IO_L20P_3 IO_L19N_3 IO_L19P_3 VCCO_3 IO_L17N_3 IO_L17P_3/VREF_3 IO_L01N_3/VRP_3 IO_L01P_3/VRN_3 RN3 dig_out12 dig_outn12 100 dig_outn14 dig_out13 R11 RAM_D52 RAM_D51 RAM_D50 RAM_D49 RAM_D48 RAM_D47 dig_out13 dig_outn13 100 dig_outn15 dig_out14 R74 156 dig_outn14 dig_out14 155 154 RAM_WE 153 152 dig_outn15 dig_out15 150 SD3 149 RAM_A18 148 147 RAM_D31 146 RAM_D30 144 RAM_D29 143 RAM_D28 141 RAM_D27 140 RAM_D26 139 RAM_D25 138 RAM_D24 137 RAM_D23 136 135 RAM_D22 133 RAM_D21 132 RAM_D20 dig_out14 dig_outn14 dig_out15 R10 IO_L01N_2/VRP_2 IO_L01P_2/VRN_2 IO/VREF_2 VCCO_2 IO_L19N_2 IO_L19P_2 IO_L20N_2 IO_L20P_2 IO_L21N_2 IO_L21P_2 IO_L22N_2 IO_L22P_2 IO_L23N_2/VREF_2 IO_L23P_2 IO_L24N_2 IO_L24P_2 IO_L39N_2 VCCO_2 IO_L39P_2 IO_L40N_2 IO_L40P_2/VREF2 dig_out15 dig_outn15 VCCO DGND GND vdd2_anlg_sense DNP these 100 Ohms resistors for CMOS version VCC dig_out0 dig_outn0 RAM_D63 RAM_D62 RAM_D61 RAM_D60 RAM_D59 RAM_D58 RAM_D57 RAM_D56 RAM_D55 RAM_D54 RAM_D53 FPGA_spare_2 Dig_5V VCCO 52760-1879 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 IO_L01P_7/VRN_7 IO_L01N_7/VRP_7 IO_L16P_7 IO_L16N_7 VCCO_7 IO_L19P_7 IO_L19N_7/VREF_7 IO_L20P_7 IO_L20N_7 IO_L21P_7 IO_L21N_7 IO_L22P_7 IO_L22N_7 IO_L23P_7 IO_L23N_7 IO_L24P_7 IO_L24N_7 IO_L39P_7 VCCO_7 IO_L39N_7 IO_L40P_7 IO_L40N_7/VREF_7 IO_L40P_6/VREF_6 IO_L40N_6 IO_L39P_6 VCCO_6 IO_L39N_6 IO_L24P_6 IO_L24N_6/VREF_6 IO_L23P_6 IO_L23N_6 IO_L22P_6 IO_L22N_6 IO_L21P_6 IO_L21N_6 IO_L20P_6 IO_L20N_6 IO_L19P_6 IO_L19N_6 VCCO_6 IO_VREF_6 IO_L01P_6/VRN_6 IO_L01N_6/VRP_6 J3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 2 3 4 5 6 7 9 10 11 12 13 15 16 18 19 20 21 22 23 24 26 27 28 29 31 32 33 34 35 36 37 39 40 42 43 44 45 46 48 49 50 51 52 vdd2_lvds_sense vdd2_lvds dig_out2 dig_outn2 dig_out1 dig_outn1 Board_1.8V VCCO KMB001LEVAL Schematics XC3S50-4PQ208C 0.1uF 0.1uF VCCINT 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C49 C66 C68 C77 C71 C80 C84 C76 0.1uF C87 0.1uF 0.1uF C90 C91 VCCO 0.1uF C92 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF VCCO 0.1uF 0.1uF 0.1uF 0.1uF C93 C108 C58 C59 C60 C61 C65 C70 C79 C83 C73 INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREEMENT Title Size KMB-001L Number Date: File: FIGURE 5. FPGA, INPUT/OUTPUT MEZZANINE CONNECTOR 5 Revision B1 B 1/28/2009 Sheet of Z:\work\ \KMB 001 FPGA rev B1 SchDoc Drawn By: KMB001EVAL KMB001LEVAL Schematics (Continued) FIFO_Vdd2_LDO_adj L5 R67 MMZ2012R102A 2 Dig_5V TP3 10K DUT_POW 0.1uF C42 1 IN EN R69 .1uF C5 33uF C116 5 1 POW_EN 0.1uF C28 L23 MMZ2012R102A 0.1uF C27 EN FB FB dig_1.8V 5 C16 33uF 33pF C41 .1uF C32 C26 0.1uF 33uF 1 R3 DNP T1 EDZ350/2 JP1 WSLG-.10CT-ND R6 3 VCC 5 U23 LTC2609IGN-1 3 4 OUT 1 vdd2_lvds_I C46 .1uF C112 .1uF FIGURE 6. POWER V+ Dig_5V U17 OUT 1 board supply_I 1 INA193 BLM41PG102SN1L L20 R2 2K board supply/3 Anlg_5V C107 330uF R56 1K DS1 2 C113 .1uF C109 330uF C110 .1uF U24 pin2 Anlg_5V U3 pin2 U1 pin2 Anlg_5V U14 pin2 Dig_5V U12 pin2 Dig_5V U5 pin2 Dig_5V C45 .1uF BLM41PG102SN1L L7 JP3 DNP EGND EGND C44 .1uF C47 0.1uF C111 .1uF INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREEMENT Title KMB001L Size Number Revision B1 B Date: Fil 6 V+ C20 330uF 2 1 C123 33uF PJ-102AH DNP Anlg_5V FIFO_Vdd2_LDO_adj FIFO_Vdd3_LDO_adj FIFO_Ovdd2_LDO_adj SPARE_DAC1 U4 pin2 56.2K 56.2K 56.2K 56.2K Dig_5V R115 R107 R55 R49 U2 pin2 SCL SDA CA2 CA1 CA0 L27 Bead L26 Bead Dig_5V 8 9 7 10 11 R108 R100 R102 R109 C120 SC2 SD2 R42 R41 R101 1K 1K 1K 1K C117 0 0 0 2 PJ-102AH 4 5 13 14 1 1000pF VCC VoutA VoutB VoutC VoutD GND C39 R126 10K REFA REFB REFC REFD REFLO 1000pF 3 6 12 15 2 200 C121 16 R110 C119 0.1uF 1000pF 0.047uF 3 D1 R68 249 VB 1 MA2SD1000L 2.5V board supply 3 EGND PD_reset J1 1000pF GND 2 4 EGND VCC Vcc 4 3 EN Vin VCC vdd2_lvds 0.1 Ohm LM4120IM5-2.5 U11 5 .1uF C48 R51 DNP DLW5BSN351SQ2 1 2 5V_external 249 DNP FIFO_LDO_DAC_Ref U18 R1 0 VCC vdd2_lvds_sense/3 R70 21K FIFO_Ovdd2_LDO_adj R7 1 vdd2_lvds_sense R62 10K 2 3.3V Norminal anlg_3.3V D2 2 PTS525SM10SM DNP S1 R96 2V nominal C38 4 ERJ-1TRQF1R0U 4 5 GND Anlg_5V TPS79633KTTT U12 2 4 IN OUT GND Board_1.8V OUT 4 TP9 3 TP2 Vin- TP1 D3 5 3 TPS79601KTTT U3 TP4 Vin+ 0.1uF VCC Vout 1 vdd3_anlg_I INA193 GND 0.1uF C37 Ref OUT 2 C57 0.1uF 4 C62 0.1uF 3 C78 0.1uF 1 2 1 V+ MMZ2012R102A GND C67 0.1uF TP10 FB 5 .1uF C106 R34 8K Vin- 3 GND EN R91 R105 8K Anlg_5V 35.7K vdd3_anlg_sense/2 R106 21K U22 MMZ2012R102A GND GND C64 TPS79618KTTT U14 4 IN OUT POW_EN 1 R48 DNP FIFO_Vdd3_LDO_adj MMZ2012R102A VCCO C63 3 2 C18 33uF 5 GND Dig_5V FB vdd3_anlg_sense MMZ2012R102A L29 6 3 GND EN 2 vdd3_anlg 1 C25 33uF D4 15pF C114 L15 6 POW_EN 1 R36 5 L28 L14 FPGA_IO 2.5V Norminal FB .1uF C31 L24 MMZ2012R102A L13 TPS79625KTTT U5 4 IN OUT 6 2 EN MMZ2012R102A MMZ2012R102A Dig_5V 1 vdd2_anlg_I OUT Vin- DNP 1 R99 L19 MMZ2012R102A 2K Vin+ L4 V+ GND C17 DUT_ANLG_POW MMZ2012R102A 3 C43 5 .1uF C105 ERJ-1TRQF1R0U 1 0 R33 DNP 4 GND L18 MMZ2012R102A OUT GND L3 33uF IN 6 33pF R71 5 2 Anlg_5V 6 FB R97 21K TPS79601KTTT U16 MMZ2012R102A 3 3 GND EN GND POW_EN 1 R90 0 Anlg_5V vdd2_anlg_sense/3 MMZ2012R102A L17 MMZ2012R102A VCCINT 6 Dig_5V U21 R104 10K L16 MMZ2012R102A L2 1.2V nominal 3 L1 FPGA Core Supply TPS79601KTTT U4 2 4 IN OUT vdd2_anlg Vin- vdd2_anlg_sense R46 DNP 1 100pF C2 0.1uF C36 2 Vin+ .1uF C30 R35 0.51 Ohms C24 33uF D5 GND R98 33pF C115 5 2 L25 MMZ2012R102A 4 TPS3801T50DCKR C118 FB 2 MR VDD EN anlg_1.8V 3 GND GND RESET 1 1K 4 Vin+ 0.1uF POW_EN 33uF DUT_ANLG_POW DUT_POW 5 OUT GND 3 C29 5 FB 6 GND EN 1 2 3 IN GND 1 PD_reset power down Vcc U1 VCC 2 GND 4.7K Anlg_5V 6 Dig_5V GND R95 CHIP SUPPLY ERJ-1TRQF1R0U TPS79601KTTT U15 Dig_5V 3.3V Norminal TPS79633KTTT U13 2 4 IN OUT 3 Dig_5V 1/28/2009 Z\ k\ \KMB 001 P Sheet of B1 S hD D B KMB001EVAL KMB001LEVAL Schematics (Continued) OGP DNP R116 DNP R119 DNP R118 DNP PC7 RAM_A20 R121 DNP R120 DNP PC2 RAM_A19 R123 DNP R122 DNP PC5 RAM_A18 R125 DNP R124 DNP PC6 DQc DQc DQc DQc DQc DQc DQc DQc DQd DQd DQd DQd DQd DQd DQd DQd RAM_A0 RAM_A1 RAM_A2 RAM_A3 RAM_A4 RAM_A5 RAM_A6 RAM_A7 RAM_A8 RAM_A9 RAM_A10 RAM_A11 RAM_A12 RAM_A13 RAM_A14 RAM_A15 RAM_A16 RAM_A17 RAM_A20 RAM_A19 RAM_A18 38 39 42 43 84 PC4 A A A A A A A A A A A A A0 A1 A A A A NC(288M) NC(144M) NC(72M) NC(36M) NC(18M) 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 R117 FPGA_spare_1 100 99 83 82 81 50 49 48 47 46 45 44 37 36 35 34 33 32 RAM_A20 RAM_A19 RAM_A18 NC(288M) NC(144M) NC(72M) NC(36M) NC(18M) A A A A A A A A A A A A A0 A1 A A A A RAM_D15 RAM_D14 RAM_D13 RAM_D12 RAM_D11 RAM_D10 RAM_D9 RAM_D8 RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0 FPGA_spare_2 38 39 42 43 84 100 99 83 82 81 50 49 48 47 46 45 44 37 36 35 34 33 32 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0 RAM_A17 RAM_A16 RAM_A15 RAM_A14 RAM_A13 RAM_A12 RAM_A11 RAM_A10 RAM_A9 RAM_A8 RAM_A7 RAM_A6 RAM_A5 Populate these resistors for OGP DQb DQb DQb DQb DQb DQb DQb DQb DQa DQa DQa DQa DQa DQa DQa DQa 79 78 75 74 73 72 69 68 63 62 59 58 57 56 53 52 RAM_D31 RAM_D30 RAM_D29 RAM_D28 RAM_D27 RAM_D26 RAM_D25 RAM_D24 RAM_D23 RAM_D22 RAM_D21 RAM_D20 RAM_D19 RAM_D18 RAM_D17 RAM_D16 RAM_D63 RAM_D62 RAM_D61 RAM_D60 RAM_D59 RAM_D58 RAM_D57 RAM_D56 RAM_D55 RAM_D54 RAM_D53 RAM_D52 RAM_D51 RAM_D50 RAM_D49 RAM_D48 2 3 6 7 8 9 12 13 18 19 22 23 24 25 28 29 DQc DQc DQc DQc DQc DQc DQc DQc DQd DQd DQd DQd DQd DQd DQd DQd DQb DQb DQb DQb DQb DQb DQb DQb DQa DQa DQa DQa DQa DQa DQa DQa U10 79 78 75 74 73 72 69 68 63 62 59 58 57 56 53 52 RAM_D47 RAM_D46 RAM_D45 RAM_D44 RAM_D43 RAM_D42 RAM_D41 RAM_D40 RAM_D39 RAM_D38 RAM_D37 RAM_D36 RAM_D35 RAM_D34 RAM_D33 RAM_D32 VCCO 4.7K 4.7K 4.7K 4.7K RAM_WE RAM_CLK R83 85 86 88 89 33 ADV/LD OE DQPa DQPb DQPc DQPd WE CLK VDD1 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C11 C12 C15 C56 C55 C53 VCCO 0.1uF C52 MMZ2012R102A L22 0.1uF 0.1uF VDD1 0.1uF 0.1uF C14 C54 C50 C13 C51 DNP 97 98 92 87 31 64 51 80 1 30 R93 R32 R40 R39 4.7K 4.7K 4.7K 4.7K VDD1 MMZ2012R102A L21 VCC 0.1uF VCCO R38 4.7K VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ RAM_OE R5 R4 R9 R73 CE2 CE1 CE3 CEN MODE ZZ 66 16 14 4 11 20 27 54 61 70 77 51 80 1 30 4.7K VDD VDD VDD VDD 97 98 92 87 31 64 15 41 65 91 15 41 65 91 5 10 17 21 26 40 55 60 67 71 76 90 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss 33 DQPa DQPb DQPc DQPd WE CLK R8 NC NC NC BWa BWb BWc BWd Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss 88 89 ADV/LD OE 93 94 95 96 5 10 17 21 26 40 55 60 67 71 76 90 R82 CE2 CE1 CE3 CEN MODE ZZ CY7C1354CV25-250AXC VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ RAM_WE RAM_CLK 85 86 U6 CY7C1354CV25-200AXC 66 16 14 4 11 20 27 54 61 70 77 RAM_OE BWa BWb BWc BWd VDD VDD VDD VDD 93 94 95 96 NC NC NC 0.1uF 0.1uF 0.1uF 0.1uF VCCO 0.1uF 0.1uF C103 C98 C101 C89 C33 C35 MMZ2012R102A L8 VDD1 MMZ2012R102A L6 VCC 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C99 C104 C34 C100 C23 DNP INTERSIL PROPRIETARY AND CONFIDENTIAL SUBJECT TO NONDISCLOSUR FIGURE 7. MEMORY 7 KMB001EVAL KMB001LEVAL Schematics (Continued) 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF C22 C72 C74 C75 C81 C85 C94 TP8 TP7 TP6 TP5 VCC 0.1uF R92 4.7K VCC 1 1 1 1 VCC 2.2uF VCC VB 10 11 17 18 2 C96 C97 12pF 12pF 22 23 24 25 26 27 28 29 30 J2 VB DM DP GND shield 1 2 3 90 Ohms differential transmission line 4 C82 ED90003 USB_CCLK scl sda 4.7nF 31 32 R80 1M 40 41 42 43 TXD0 RXD0 TXD1 RXD1 Shield 76 52 51 56 55 54 USB_PROG_B VCC F_FLAG_3V AF_FLAG_3V U20 5 C95 4 0.1uF VDD RESET GND MR WDI 1 2 3 PORn 77 79 16 9 78 66 53 49 38 33 20 1 XTALOUT XTALIN DPLUS DMINUS INT4 T0 T1 T2 IFCLK RESERVED BKPT SCL SDA U8 CY7C68013A-100AXC RD# WR# TXD0 RXD0 TXD1 RXD1 PA0/INT0# PA1/INT1# PA2/SLOE PA3/WU2 PA4/FIFOADR0 PA5/FIFOADR1 PA6PKTEND PA7/FLAGD/SLCS# PE7/GPIFADR8 PC7/GPIFADR7 PC6/GPIFADR6 PC5/GPIFADR5 PC4/GPIFADR4 PC3/GPIFADR3 PC2/GPIFADR2 PC1/GPIFADR1 PC0/GPIFADR0 CLT5 CTL4 CTL3 CTL2/FLAGC CTL1/FLAGB CTL0/FLAGA RESET# WAKEUP 2 21 39 50 48 65 75 94 99 TPS3820-33DBVT CLKOUT 34 35 36 37 44 45 46 47 80 81 82 83 95 96 97 98 67 68 69 70 71 72 73 74 USB_D0 R19 USB_D1 R17 USB_D2 R18 USB_D3 R16 USB_D4 R14 USB_D5 R15 USB_D6 R12 USB_D7 R13 DUT_POW R94 249 PD2 I2C_res PD4 PD5 USB_DISC PD7 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K A0 A1 A2 Vss Vcc WP SCL SDA JP4 1 2 scl sda JUMPER FOR WRITE ENABLE DNP U19 R72 DNP DS3 USB_RDWR_B USB_D3 USB_BUSY USB_INIT_B USB_D4 USB_D5 USB_D6 VCC C69 USB_D7 USB_PROG_B USB_DONE USB_CCLK 0.1uF 93 64 63 62 61 60 59 58 57 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 100 4.7K USB_CCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 F_FLAG_3V USB_RDWR_B AF_FLAG_3V USB_D0 USB_D1 USB_D2 1 Y1 C86 NC 1A1 1A2 1A3 1A4 1A5 1A6 GND 1A7 1A8 1A9 1A10 2A1 2A2 Vcc 2A3 GND 2A4 2A5 2A6 2A7 2A8 2A9 2A10 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1OE 2OE 1B1 1B2 1B3 1B4 1B5 GND 1B6 1B7 1B8 1B9 1B10 2B1 2B2 2B3 GND 2B4 2B5 2B6 2B7 2B8 2B9 2B10 F_FLAG RDWR_B AF_FLAG D7 D6 D5 D4 BUSY INIT_B D3 D2 D1 D0 PROG_B DONE CCLK FPGA D0 is MSB VCC SN74CB3T16210DGGR R85 NC NC NC ECS-240-12-4X 1 C88 8 7 6 5 13 14 15 249 C102 0.1uF R37 4.7K U9 1 2 3 4 24AA64A-I/SN PB0/FD0 PB1/FD1 PB2/FD2 PB3/FD3 PB4/FD4 PB5/FD5 PB6/FD6 PB7/FD7 PD0/FD8 PD1/FD9 PD2/FD10 PD3/FD11 PD4/FD12 PD5/FD13 PD6/FD14 PD7/FD15 AGND AGND 1 RDY0/SLRD RDY1/SLWR RDY2 RDY3 RDY4 RDY5 12 19 USB_BUSY USB_DONE R76 GND GND GND GND GND GND GND GND GND 3 4 5 6 7 8 USB_INIT_B DS2 2 VCC 0.1uF VCC AVCC AVCC USB_DISC VCC VCC VCC VCC VCC VCC VCC VCC R89 4.7K PE6/T2EX PE5/INT6 PE4/RXD1OUT PE3/RXD0OUT PE2/T2OUT PE1/T1OUT PE0/T0OUT VCC INT5# 92 91 90 89 88 87 86 85 84 C21 R88 4.7K 0.1uF 2 VCC Board ID PROM VCC VCC MAX1239MEEE+ U2 R50 4.7K VCC I2C_res 1 2 13 3 A0 A1 A2 reset to FPGA 0.1uF 0.1uF 0.1uF 0 0 0 1 2 3 4 5 6 7 8 16 R54 15 R60 14 R61 13 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11/REF Vdd 12 0.1uF C40 sda scl GND 10 9 SD1 SC1 11 C3 C4 4.7K 0.1uF 4.7K R45 0.1uF 4.7K R111 0.1uF 4.7K R112 0.1uF C6 C7 C8 C9 to ID eeprom(daughter card) 6 5 4 3 2 1 C10 to ADC power measurement 0.1uF to DUT (daughter card) 0.1uF SD0 SC0 SD1 SC1 SD2 SC2 SD3 SC3 TXD0 RXD0 TXD1 RXD1 R53 R52 R58 R57 R64 R63 R66 R65 R59 C19 4 5 6 7 9 10 11 12 VCC JP2 1K 1K 1K 1K 1K 1K 1K 1K 1K C1 SCL SDA SD0 SC0 SD1 SC1 SD2 SC2 SD3 SC3 R44 16 VDD 14 15 vdd2_lvds_I vdd2_lvds_sense/3 board supply_I board supply/3 vdd2_anlg_I L9 vdd2_anlg_sense/3 L10 vdd3_anlg_I L11 vdd3_anlg_sense/2 L12 FIFO_LDO_DAC_Ref VCCO DNP molex 053047-0610 INTERSIL PROPRIETARY AND CONFIDENTIAL. SUBJECT TO NONDISCLOSURE AGREEMENT Vss 4.7K R47 scl sda U24 VCC Title KMB001L 8 4.7K R114 C122 0.1uF 4.7K VCC 4.7K PCA9546APW-T R103 VCC R113 VCC Size Number Revision B1 B Date: FIGURE 8. USB, MISC. 8 1/28/2009 Sheet 3 of 5 KMB001EVAL KMB001CEVAL Layers FIGURE 9. TOP LAYER 9 KMB001EVAL KMB001CEVAL Layers (Continued) FIGURE 10. GND PLANE 10 KMB001EVAL KMB001CEVAL Layers (Continued) FIGURE 11. MID LAYER 1 11 KMB001EVAL KMB001CEVAL Layers (Continued) FIGURE 12. POWER PLANE 12 KMB001EVAL KMB001CEVAL Layers (Continued) FIGURE 13. GND PLANE 2 13 KMB001EVAL KMB001CEVAL Layers (Continued) FIGURE 14. BOTTOM LAYER 14 KMB001EVAL KMB001CEVAL Layers (Continued) FIGURE 15. TOP OVERLAY 15 KMB001EVAL KMB001CEVAL Layers (Continued) FIGURE 16. BOTTOM OVERLAY Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding. For information regarding Intersil Corporation and its products, see www.intersil.com 16