HSP50415 TM Data Sheet March 2000 Wideband Programmable Modulator (WPM) File Number 4559.5 Features • Output Sample Rates . . . . . . . . . . . . . . . . . . to 100MSPS The HSP50415 Wideband Programmable Modulator (WPM) is a quadrature amplitude modulator/upconverter designed for wideband digital modulation. The WPM combines shaping and interpolation filters, a complex modulator, timing and carrier NCOs and dual DACs into a single package. The HSP50415 supports vector modulation, accepting up to 16-bit In phase (I) and Quadrature (Q) samples to generate virtually any quadrature AM or PM modulation format. A constellation mapper and 24 Symbol span interpolation shaping filter is provided for the input baseband signals. Gain adjustment is provided after the shaping FIR filter. A timing error generator in the input section allows the on-chip timing NCO to track the input timing. The WPM includes a Numerically Controlled Oscillator (NCO) driven interpolation filter, which allows the input and output sample rate to have a non-integer or variable relationship. This re-sampling feature simplifies use of sample rates that do not have harmonic or integer frequency relationships to the input data rate and decouples the carrier from the DATACLK. A complex quadrature modulator modulates the baseband data on a programmable carrier center frequency. The WPM offers digital output spurious Free Dynamic Range (SFDR) that exceeds 70dB at the maximum output sample rate of 100MSPS, for input sample rates as high as 25MSPS. X/SIN(X) rolloff compensation filtering is provided. Real 14-bit digital output data is available prior to the 12-bit DACs providing 20mA full scale output current. • Input Data Rates . . . . . . . . . . . . . . . . Up to 25MSPS (I/Q) • 32-Bit Programmable Carrier NCO • X/SIN(X) Rolloff Compensation • Programmable I and Q Shaping FIR Filters: - Up to 24 Symbol Span • Fixed or NCO Controlled Interpolation: - Interpolation Range . . . . . . . . . . . . . . . . . . 4 to > 128K - Digital PLL to Lock to Input Symbol Clock • Digital Signal Processing Capable of >70dB SFDR • Dual 12-bit D/A Processing Capable of >50 dB SFDR Applications • Wide-Band Digital Modulation • Base Station Modulators • HSP50415EVAL1 Evaluation Board Available Ordering Information PART NUMBER HSP50415VI TEMP RANGE (oC) -40 to 85 PACKAGE PKG. NO 100 Ld MQFP Q100.14x20 HSP50415EVAL1 Evaluation CCA, Development S/W, and User’s Manual Block Diagram W/R CONTROL µP INTERFACE CARRIER NCO COS DATA DATA INTERFACE/ FIFO Q DATACLK 2XSYMCLK REFCLK I SYMBOL NCO/ DIGITAL PLL 4-1 CONST MAP SHAPING/ INTERPOLATION FILTERS SHAPING/ INTERPOLATION FILTERS SIN COMPLEX MIXER 14 / DIGITAL OUT X SIN(X) 12-BIT DAC I OUT X SIN(X) 12-BIT DAC Q OUT CLK MULTIPLIER ANALOG PLL CLK CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 Functional Block Diagram 4-2 CE WR RD RESET ADDR<2:0> CDATA<7:0> INTREQ µP INTERFACE CARRIER NCO x2, 4, 8, 16 I GAIN x2 INTERPOLATION INTERPOLATION DIN<15:0> I ISTRB CONST. MAP DATACLK TXEN FEMPT DATA INTERFACE/ FIFO x2 TO > 8192 INTERPOLATION I GAIN COS INTERPOLATION FILTER FIR HALFBAND BYPASS BYPASS I OFFSET SIN COMPLEX MIXER BYPASS X SIN(X) 14 / IOUT<13:0> 12-BIT DAC IOUTB BYPASS Q GAIN IOUTA ICOMP1 ICOMP2 QCOMP2 QCOMP1 Q GAIN Q OFFSET FOVRFL Q FIR BYPASS INTERPOLATION FILTER X SIN(X) BYPASS BYPASS 12-BIT DAC HALFBAND BYPASS BYPASS QOUTA QOUTB SYSCLK 2XSYMCLK X2 LOCKDET REFCLK PHASE FREQ. ERROR DETECT LOOP FILTER SYMBOL NCO LOCK DETECTOR CLK DIVIDER ÷ 1, 2, 4, 8 REFLO REFIO SYSCLK/2 CLK MULTIPLIER X 1, 2, 4, 8, 16, 32 (VCO DIVIDER) VOLTAGE REF SYSCLK FSADJ ÷2 PHASE FREQUENCY DETECTOR APLL SELECTOR BYPASS CHARGE PUMP PLLRC VOLTAGE CONTROLLED OSCILLATOR CLK HSP50415 FFULL HSP50415 Pinout 100 LEAD MQFP DATACLK DIN0 DIN1 DIN2 DIN3 GND DIN4 VDD DIN5 DIN6 DIN7 DIN8 DIN9 DIN10 DIN11 DIN12 GND VDD DIN13 DIN14 TOP VIEW 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CDATA0 CDATA1 CDATA2 VDD CDATA3 CDATA4 GND CDATA5 CDATA6 CDATA7 RD WR GND CE ADDR0 ADDR1 ADDR2 REFCLK 2XSYMCLK INTREQ NC VDD RESET CLK GND DVDD DGND PLLRC PGND PVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 HSP50415 DVDD DGND QOUTB QOUTA AGND AVDD QCOMP1 QCOMP2 REFLO AGND REFIO FSADJ ICOMP2 AVDD ICOMP1 IOUTA IOUTB AGND RESV RESV 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 4-3 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DIN15 ISTRB TXEN LOCKDET FOVRFL FEMPTY FFULL GND SYSCLK/2 IOUT13 VDD IOUT12 IOUT11 IOUT10 IOUT9 IOUT8 GND IOUT7 IOUT6 VDD IOUT5 IOUT4 IOUT3 IOUT2 IOUT1 IOUT0 GND VDD RESV RESV HSP50415 Pin Descriptions NAME TYPE VDD - Digital power. GND - Digital ground. DVDD - DAC digital power. DGND - DAC digital ground. AVDD - DAC analog power. AGND - DAC analog ground. PVDD - PLL analog power. PGND - PLL analog ground. PLLRC I PLL loop filter provides for the addition of less expensive RC components in place of a crystal oscillator. The recommended values for this pin are detailed in the ‘System CLK Generation’ section. CLK I System and DAC clock input when APLL not in use, otherwise it is the reference to the APLL. SYSCLK/2 O Sample Clock Divided by Two. All digital output data and status pins are output from this clock. The polarity of SYSCLK/2 may be programmed via Register 2 bit-3. 2XSYMCLK O Tristatable Symbol NCO Clock Output Multiplied by Two. The polarity of 2XSYMCLK may be programmed via register 2 bit-15. REFCLK I External digital PLL reference clock input. DIN<15:0> I Data Bus. The DIN<15:0> bus loads the input data. DATACLK I Asynchronous data clock for DIN<15:0>. TXEN I DIN<15:0> may be optionally gated with the TXEN pin (burst mode) or input free-running as defined by register 2 bits 18-17. The polarity of TXEN may be programmed via register 2 bit-5. ISTRB I Data samples are input as I then Q serially with the ISTRB pin active with the I sample. The polarity of ISTRB may be programmed via Register 2 bit-4. CDATA<7:0> I/O µP Bidirectional Data Bus. The CDATA<7:0> data bus is used for loading the configuration data and sample vectors for modulation. CDATA7 is the MSB. RD I µP Read control input. WR I µP Write strobe input. CE I Chip enable input. ADDR<2:0> I µP Address Bus. The ADDR<2:0> bus is used for addressing the proper registers for loading the configuration data and sample vectors for modulation. ADDR2 is the MSB. INTREQ O Tristatable Active High Interrupt Request Output. The INTREQ output is enabled via register 2 bit-8. Register 9 bits 6-0 enable individual events for INTREQ. RESET DESCRIPTION While the RESET input is asserted (driven low), all processing halts and the WPM is reset. A software reset is also available via register 10H. IOUT<13:0> O Tristatable In-Phase Output Samples. IOUT<13:0> outputs are enabled via register 2 bit-7. QOUT<13:0> O Tristatable Quadrature Output Samples. QOUT<13:0> outputs are enabled via register 2 bit-6. The QOUT<13:0> outputs are not available on the MQFP package. FEMPT, FOVRFL, FFULL O Tristatable Status Flags for FIFO Level Monitoring. These outputs are enabled via register 2 bits 13-11. FIFO status thresholds and control are configured via register 2 bits 23-16. LOCKDET O Tristatable Status Flag of the Digital PLL. This may be used to generate an interrupt request via INTREQ. The LOCKDET output is enabled via register 2 bit-10. IOUTA, QOUTA O Current Outputs of the Device. Full scale output current is achieved when all input bits are set to binary 1. IOUTB, QOUTB O Complementary Current Outputs of the Device. Full scale output current is achieved on the complementary outputs when all input bits are set to binary 0. 4-4 HSP50415 Pin Descriptions (Continued) NAME TYPE DESCRIPTION ICOMP1, QCOMP1 I Compensation Pin for use in Reducing Bandwidth/Noise. Each pin should be individually decoupled to AVDD with a 0.1µF capacitor. To minimize crosstalk, the part was designed so that these pins must be connected externally, ideally directly under the device packaging. The voltage on these pins is used to drive the gates of the PMOS devices that make up the current cells. Only the ICOMP1 pin is driven and therefore QCOMP1 needs to be connected to ICOMP1, but de-coupled separately to minimize crosstalk. ICOMP2, QCOMP2 I Compensation Pin for Internal Bias Generation. Each pin should be individually decoupled to AGND with a 0.1µF capacitor. The voltage generated at these pins represents the voltage used to supply 2.0V nominal power to the switch drivers. This arrangement helps to minimize clock feedthrough to the current cell transistors for reduced glitch energy and improved spectral performance. REFLO I Reference Low Select. When the internal reference is enabled, this pin serves as the precision ground reference point for the internal voltage reference circuitry and therefore needs to have a good connection to analog ground to enable internal 1.2V reference. To disable the internal reference circuitry this pin should be connected to AVDD. REFIO I Reference voltage input if internal reference is disabled. Reference voltage output if internal reference is enabled. Use 0.1µF cap to ground when internal reference is enabled. FSADJ I Full Scale Current Adjust. Use a resistor to ground to adjust full scale output current. Full Scale Output Current = 32 x VFSADJ/RSET. Where VFSADJ is the voltage at this pin. VFSADJ tracks the voltage on the REFIO pin; which is typically 1.2V if the internal reference is used. RESV - Reserved. These pins must be floating (not connected) for proper operation. NC - No Connection. Pins may be connected to GND, AGND, DGND or left floating. Functional Description System CLK Generation The HSP50415 is a wideband programmable modulator that accepts an input quadrature data stream at programmable symbol rates of up to 25MSPS (QPSK) and outputs a modulated quadrature data stream at the final sample rate up to 100MHz. The allowable symbol rates depend on the modulation type selected (QPSK, 16QAM, etc.). The input data format is parallel with respect to the bits, but serial with respect to the I and Q samples and may be input at a constant symbol rate or burst in at a different rate. The HSP50415 can symbol map the input data stream per a user programmable look up table thus allowing any standard to be supported. The mapped symbols are then interpolated to the final sample rate and low-pass filtered in order to limit the spectral occupancy of the signal. The first stage filter coefficients are user programmable, with subsequent filter stages having fixed coefficients. The HSP50415 then modulates the symbol data at the final sample rate onto a carrier signal that is tunable from 0.023Hz - 50MHz (for a final sample rate of 100MHz) producing a quadrature signal. The signal may then be optionally X/SIN(X) filtered to compensate for the SIN(X)/X roll-off of the DACs. To correct for system (or DAC induced) gain imbalances between the In phase and Quadrature signals there is a final gain correction stage prior to the output. The final Intermediate Frequency (IF) digital output can be converted to differential analog signals via the onboard 12-bit DACs or may be optionally brought out as 14-bit digital data. The 100-pin MQFP package provides a real digital output at 1/2 the final sample rate. The HSP50415 receives I and Q input data serially at twice the input symbol rate. The data is converted to a parallel quadrature data stream at the symbol rate by the Front End Data Input Block. This data stream is upsampled to the final output sample rate of the device (FSout). This output sample rate (maximum rate of 100MHz) is used to clock the last stage of the digital logic and the dual 12-bit DACs and may be provided externally on the CLK pin or may be generated by an internal analog PLL (APLL). When enabled, the APLL uses the CLK pin as a reference and provides a selectable CLK multiplier of x2, x4, x8, x16 or x32 or CLK divider of /2, /4 or /8. 4-5 An external loop filter is required to be supplied at PLLRC. The recommend configuration is shown in Figure 1, with suggested component values calculated as: User Input Terms: APLLclkdivider=APLL CLK divider programmed input APLLvcodivider=APLL VCO divider programmed input Fclk=CLK frequency input Fscale=loop bandwidth divisor input Pm=loop phase margin input (degrees) Component calculation formulas: C1=(Fvcogain*Icp)/(wo*wo*sqrt(kk)) C2=kk*C1 R1=1/sqrt(Fvcogain*Icp*C1*sqrt(C2/C1)) Where: Fvcogain=231000000/APLLvcodivider Icp=0.000353 HSP50415 kk=(1+(sin(Pm*pi/180)))/(1-(sin(Pm*pi/180))) wo=2*pi*((Fclk/APLLclkdivider)/Fscale) driving the input DATACLK if a symbol rate synchronous (non-burst) mode is required. A MATLAB or Excel program for calculating the component values is available. For improved APLL performance, utilization of specific calculated values is recommended over the general purpose ones shown in Figure 1. The SYMBOL NCO is a 32-bit accumulator. The 32-bit frequency step (Phinc) is the sum of the user programmable 32-bit symbol Phinc and any error term generated by the Digital Phase Lock Loop (DPLL) while locking to an external symbol rate. The DPLL error term may be disabled by a control bit. The symbol rates supported are from 0.023Hz up to 25MHz (for FSout of 100MHz) with 32-bit frequency resolution. The formula for programming the symbol Phinc register is given as: Symbol NCO As the data flows through the device, the sample rate increases up to the final sample rate, with the SYMBOL NCO generating all of the necessary intermediate sample rate clocks. Each stage’s input and output sample rate is dependent on the interpolation rate through the stage. Figure 1 shows the various symbol clocks that are generated on the chip. The symbol rate clock (symclk) used internally is multiplied by 2 and output on pin 2XSYMCLK for use in symbolPhinc = (symbolRate / FSout) * 2^32 The SYMBOL NCO also has a counter mode in which the symbol clocks are generated upon the counter reaching the 16-bit user programmable rollover count value. This mode is useful for cases where the frequency is an integer number of the system clock (SYSCLK/2). BYPASS SYSCLK/2 DIN<15:0> DATACLK sysclk ÷2 DATA I INTERFACE FIFO Q CONST. MAP INT. FILTER FIR COMPLEX MIXER HALFBAND APLL SELECTOR X SIN(X) 12-BIT DAC I GAIN I OFFSET I GAIN PLLRC 2XSYMCLK symclk (symbol rate) X2 R1 (symbol rate X 1,2,4,8,16,32) C1 SYMBOL NCO Internal IC signal names are shown in lowercase. DC TO 20MHz: C1=690PF, C2=11NF, R1=120Ω 20 TO 100MHz: C1=130PF, C2=2NF, R1=620Ω FIGURE 1. SAMPLE RATE CLK GENERATION 4-6 C2 CLK IOUTA IOUTB HSP50415 TABLE 1. HSP50415 FILTER CONFIGURATIONS AND RESULTING SYMBOL NCO RATES BYPASS FIR FILTER FIR INTERPOLATION BYPASS HALFBAND FILTER INTERPOLATING FILTER DATA INPUT RATE SYMBOL NCO PHINC 0 x2 (Note) 0 Symbol Rate x 4 PhincLL x 4 0 x4 0 Symbol Rate x 8 PhincLL x 8 0 x8 0 Symbol Rate x 16 PhincLL x 16 0 x16 0 Symbol Rate x 32 PhincLL x 32 0 x2 (Note) 1 Symbol Rate x 4 PhincLL x 4 0 x4 1 Symbol Rate x 4 PhincLL x 4 0 x8 1 Symbol Rate x 8 PhincLL x 8 0 x16 1 Symbol Rate x 16 PhincLL x 16 1 Not applicable 0 Symbol Rate x 2 PhincLL x 2 1 Not applicable 1 Symbol Rate x 1 PhincLL x 1 NOTE: An optional decimate by two mode allows the device to achieve interpolation by a factor of two in the Shaping FIR. The SYMBOL NCO 32-bit Phinc value is adjusted automatically such that the SYMBOL NCO runs at the input rate of the interpolating filter, since this is the fastest rate prior to the FSout rate. Table 1 lists possible filter configurations of the HSP50415 and the resulting interpolating filter rate. This resulting rate is affected by rate adjustments (interpolation) in the previous filter blocks. Digital Phase Lock Loop The HSP50415 contains a Digital Phase Lock Loop (DPLL) that performs symbol tracking to an external symbol clock (REFCLK). The DPLL consists of a programmable phase/frequency error detector followed by a loop filter and lock detector stage. The phase/frequency error detector block diagram is shown in Figure 2. The DPLL uses two (integer) counters to give added frequency programming flexibility. The programmed symbol rates are functions of the both the REFCLK divider and the NCO divider (N = NCO divider + 1, see Figure 2), each of which can be changed separately. As an example, these two counters can be set to generate a non-integer output (NCO Symbol rate) frequency (16/3) of the input reference frequency (REFCLK). In this case NCO divider = 16, and REFCLK divider =3. If REFCLK is the desired symbol rate, then the REFCLK divider will be the same value as the NCO divider. If REFCLK is for example 2x the desired symbol rate, then the refClk divider will be 2x the NCO divider. REFCLK is divided down by the REFCLK divider. The internal symbol clk is divided down by the NCO divider. When the carry-out of the REFCLK divider is generated, the symbol NCO is sampled. The phase and frequency (dphi/dt) should be zero if the two rates are phase and frequency locked. If not, the sampled phase value is the phaseError. This value is subtracted from the previous phaseError to generate the frequency error. Both of these error terms are input to the loop filter which scales and integrates these error terms and produces a final symbol nco error term. This final error term gets added to the SYMBOL NCO to adjust the symbol rate to 4-7 try to track to the divided down external REFCLK input. The loop filter error term must be enabled in the software for this error term to be added to the symbol NCO. Otherwise the Digital PLL has no effect on the symbol rate. The minimum value the REFCLK divider and NCO divider values may be programmed to is the larger of 32/clkDivisor or 0x04, where clkDivisor is FSout/REFCLKrate. This is due to the minimum number of system clock (SYSCLK/2) cycles the loop filter requires to process the new error terms. The maximum rate of this clock is FSout/4 or 25MHz for FSout of 100MHz. The phaseError and freqError terms are input to the loop filter block which is a standard lead/lag type second order loop filter as shown in Figure 3. The loop filter requires 32 clock cycles to process a new error term. The phaseError is weighted by the lag gain and added to the freqError weighted by the frequency gain and this sum is accumulated to give the integral response. The lag accumulator is compared to upper and lower limits and forced to the limit value if either limit is exceeded. This keeps the SYMBOL NCO frequency within the expected symbol rate uncertainty and limits the pull in range. This accumulator output is then added to the phaseError weighted by the lead gain to get a proportional response. This lead term should be zeroed during initial tracking. The gain values are user programmable with a mantissa and exponent of the following format Gain = 01.MMMM * 2^(EEEEE-17) where MMMM denotes the 4-bit gain value and EEEEE is the 5-bit shift value. The phaseError and freqError signals may be monitored on the digital outputs for test or the lock detect pin may be used to monitor the symbol tracking phase error. The lock detect pin indicates whether the DPLL has phase locked to the external symbol clock. The lock detect status may also be used to generate an interrupt event. The lock detect block diagram is shown in Figure 4. HSP50415 NCO divider<13:0> REFCLK divider<7:0> REFCLK 8-BIT COUNTER 14-bit countValue TC carryOut 14-BIT COUNTER SYMBOL NCO 8 upper bits of phaseAccum FIFOFreqError<8*7,7:0> SYNC enable R CLK freqError<15:0> R _ phaseError<21:0> FIGURE 2. PHASE/FREQUENCY ERROR DETECTOR frequencyGain UL<31:0> freqError<15:0> LL<13:0> lagGain 41 / phaseError<21:0> LIMITER R DPLL PhincError<31:0> R leadGain FIGURE 3. DPLL LOOP FILTER lockIntegrator<8> LOCKDET positive lockedValue negative notLockedValue threshold<20:0> _ AO carryOut phaseErrorMag<20:0> AO analogPLLlockStatus A1 useAPLLlockStatus A1 Z R Z lockIntegrator<8:0> S S bit=1 indicates phaseErr > thld so NOT locked FIGURE 4. LOCK DETECTION BLOCK DIAGRAM The Lock Detector compares the magnitude of the phaseError to a programmable 21-bit threshold value. If the carry out from this comparison is “1” then the phaseError is greater than or equal to the threshold value and a negative value is added to the lock integrator. If the carry out is “0” then the phaseError is less than the threshold and a positive value is added. As the phaseError magnitude stays below the threshold level the lock integrator will grow from a negative number to a positive one thus indicating a locked condition. The lock integrator resets to a full-scale negative value. The sign bit of the lock integrator is output as the LOCKDET status flag. The values added or subtracted to the lock integrator are user selectable as follows in Table 2. 4-8 TABLE 2. LOCK INTEGRATOR ADDENDS LOCK FACTOR CARRY OUT 0xx 1 -0.5 111111000 1xx 1 -0.25 111111100 x00 0 +0.0625 000000001 x01 0 +0.1250 000000010 x10 0 +0.2500 000000100 x11 0 +0.5000 000001000 ADDEND BINARY VALUE HSP50415 Front-End Data Input Block The HSP50415 accepts input data in a parallel bit fashion with I and Q samples input serially as shown in Figure 5. The signal pins on the device that input data to the front-end are the DIN<15:0> bus, the ISTRB and TXEN control pins and the DATACLK pin. Iout<15:0> FRONT END DATA INPUT BLOCK Iin<15:0>, Qin<15:0> serial Data Stream at symbol Rate x2 Qout<15:0> at symbol rate FIGURE 5. SERIAL TO PARALLEL DATA CONVERSION All data is synchronous to the DATACLK. Further references to bit-widths will be with respect to a single channel (I and Q channels are identical). The input data may be from 1-bit up to 16-bits wide with bits positioned on the LSB’s of the bus. The data samples are input as I then Q serially with the ISTRB pin active with the I sample. The maximum data rate is 50MHz at FSout of 100MHz or twice the maximum symbol rate. The data written into the chip may be gated with the TXEN pin (burst Mode) or input free-running. The ISTRB and TXEN pins have user-programmable active states thus allowing spectral inversion to be implemented by simply changing the ISTRB polarity. Figure 6 shows the input data timing (assuming the ISTRB pin is an active high). DATACLK DIN<15:0> I Q I Q ISTRB FIGURE 6. I/Q INPUT DATA TIMING Once a valid pair of I and Q samples has been received, the data pair is written into the 256x32-bit FIFO. The data is read out of the FIFO at the symbol rate using the internally generated symbol clock which is synchronous to the clock pin. This internally generated symbol clock is available on the 2XSYMCLK pin of the chip. It has been multiplied up to twice the symbol rate to facilitate tying it to the DATACLK pin in symbol rate synchronous modes. The data is always input to the chip at twice the rate at which it is written to the FIFO since I and Q are input serially. In a symbol rate synchronous mode, the data is input to the front-end at twice the symbol rate, written to the FIFO at the symbol rate and read from the FIFO also at the symbol rate. This mode ensures that no FIFO overflow or underflow conditions will occur. Optionally, in a totally synchronous mode, the FIFO may be bypassed altogether if power conservation is critical. Reading data out of the FIFO for transmission may be optionally gated by the TXEN pin if the user wishes to burst the data into the chip and delay transmission of the data. If 4-9 the data reads are not gated, then after 2 FIFO locations have been written, data reads are initiated. Via userprogrammable bits, the data may be zeroed leaving the front-end if the FIFO runs out of data or in gated-read mode, if the TXEN pin is inactive. Conversely, writing data into the FIFO may be optionally disabled upon a FIFO full condition. Control of the starting address for the gated reads is userprogrammable where the address may be zeroed upon start of transmission or simply incremented from where it left off on the last transmission. The FIFO logic contains user programmable threshold detection (high and low thresholds) as well as full/empty detection. There are 4 status flags available to the user for FIFO level monitoring: FIFOOverFlow (FOVRFL), FIFOFull (FFULL), FIFOUnderFlow, and FIFO empty (FEMPT). These status flags may be monitored via 3 output pins: the underflow and empty share one pin with a user selectable function. Any one of these flags may be used to trigger an interrupt on the INTREQ pin if the mask register for that status bit is set. A rising edge of the status signal will set the interrupt status register bit and cause an external interrupt if enabled. The only way to clear the status bit and INTREQ pin is to write a “1” to the corresponding status register bit. Another feature of the FIFO is the adaptive symbol rate control logic. The internal symbol rate of the device is controlled by the digital PLL if enabled. Since the data is read out of the FIFO at the internal symbol rate, there may arise a need for the FIFO to adjust the symbol rate if the data is not being written in and read out at the same rate. This is achieved by either adding or subtracting a frequency error term to the digital PLL’s loop filter frequency term or by forcing the loop filter lag term to its programmed limit. If a FIFO overflow occurs, then the data is being written into the FIFO faster than it is being read out, which indicates the symbol rate needs to be increased thus speeding up the reads. This scenario would cause the FIFO to try to increase the final symbol rate error term by either adding the FIFO frequency error term (user programmable) to the loop filter’s frequency error term or force the loop filter lag accumulator to its programmed upper limit. If a FIFO underflow occurs, then the data is being read out of the FIFO faster than it is being written in and the FIFO would attempt to slow down the symbol rate by subtracting the frequency error term or by forcing the lag accumulator to its lower limit. This adaptive rate control is user programmable via Register 2 bits 21:20. Constellation Mapper The I/Q data pair from the Front End Input Block enters the constellation mapper at the internal symbol rate and is mapped via a user programmable look up table to new symbol data. The symbol mapping is only supported for I/Q bit widths of 4-bits (256-QAM) or less. The I data is concatenated with the Q data to form the 8-bit address (Iin<3:0>:Qin<3:0>) to the 256x8-bit RAM. The 8-bit data output from the RAM is the new symbol data in the form HSP50415 Iout<3:0>:Qout<3:0>. See Figure 7 for a constellation mapping example. For bit widths less than 4-bits the data in the RAM may simply be zero’s for the unused bit positions and the unused addresses since the HSP50415 will discard the unused bits. For example, if the user programs the number of bits to be 1 and the upper bits of the DIN<15:0> bus are tied to “0”, the user need only program addresses 0, 1, 16 and 17 since the other addresses will never be selected. In this example, the only data that is used will be memory address bits 4 and 0 since these map to I<0> and Q<0> respectively. For data bit widths larger than 4 bits or if mapping is not required, the constellation mapper may be bypassed. twoBitMode is a special processing mode where 2-bits at a time are computed. The gain through the filter is: A = (sum of coefficients) / interpolation rate The FIR filter contains saturation logic in the event that the final output peaks over 1.0. Table 3 outlines the filter characteristics for the various interpolation rates. TABLE 3. FIR FILTER CHARACTERISTICS 2-BITMODE INTERP. RATE SYMBOL SPAN # FILTER TAPS 0 x4 24 96 0 x8 20 160 Shaping FIR Filters 0 x16 16 256 Following the constellation mapping, the I/Q data pair is input to the programmable FIR filters for the first stage of interpolation. The interpolating FIR filters’ have programmable coefficients and must be loaded via the microprocessor interface. The I and Q filter stages are identical and may be loaded simultaneously or separately thus allowing for different gains and responses through the FIR filter if desired. The loading options are programmable including readback modes and will be discussed in detail in the ‘Microprocessor Interface’ section. Since the hardware for the I and Q filters is identical, further discussion will pertain to a single channel. 1 x4 12 48 1 x8 10 80 1 x16 8 128 The basic interpolation rates allowed through the FIR are x4, x8 or x16. An optional decimate by 2 mode is available that subsamples the output of the filter thus reducing the interpolation rate by a factor of 2. Each filter multiplication is implemented as a series of shifts and adds thus constraining the maximum input symbol rate as follows: The programmable coefficients are stored in RAM as bitsliced sums of products. The data exits the interpolating FIR filters as a parallel I<15:0> and Q<15:0> data stream at the interpolated sample rate. These filters may be totally bypassed if higher input symbol rates are required. When bypassed, the RAMs may be loaded with all zeros for power conservation. Post FIR Gain Control Following the FIR filter pair is a gain stage where I and Q are scaled equally. The programmable gain consists of a 6-bit mantissa and a 4-bit exponent stage. The equation for the gain is as follows: dataOut<15:0> = (dataIn<15:0> * 1.MMMMMM) * 2 ^ (EEEE - 11) symbolRateMax is the smaller of: (CLK * 2 * 2^twoBitMode) / (#bits * interpolationRate) and CLK/4 where CLK is the final sample rate clock (100MHz max), #bits is the data bit width of a single channel and where MMMMMM denotes the 6-bit gain value and EEEE is the 4-bit shift value. For a gain of 1.0 through this stage, program the mantissa to 0x00 and the exponent to 0xB. This stage is implemented with a signed 16-bit by unsigned 7-bit multiplier with the CONSTELLATION MAPPER Address DATA FROM FIFO I Q 16 / 16 / “0x0008” “0x000A” DATA TO SHAPING FILTERS 0x00 MAP ADDRESS 8 / LOOK-UP TABLE RAM 16 / “0x0009” 0x9B 16 / “0x000B” Address 0x8A is formed from the lower 4-bits of I and Q data 0xFF FIGURE 7. CONSTELLATION MAPPING 4-10 I “0x8A” Q Address 0x8A is previously loaded with data 0x9B via the control bus HSP50415 Fixed Coefficient 19-TAP Interpolating Halfband Following the post-FIR gain stage is a pair of fixed coefficient 19-tap interpolate by 2 halfband filters. The halfband filter may be totally bypassed if not required. If bypassed, the data to the filter is zeroed which reduces power consumption. The halfband filter coefficients are: 1, 0, -17, 0, 87, 0, -299, 0, 1252, 2048, 1252, 0, -299, 0, 87, 0, -17, 0, 1 The interpolate by 2 is accomplished via zero-stuffing and low-pass filtering. The output of this filter is rounded to 16bits. The output is checked for saturation and limited if necessary. The data exits the halfband filters as a parallel I<15:0> and Q<15:0> data stream at the interpolated sample rate. Figure 8 shows the frequency response of the HalfBand filter. 4-11 100 MAGNITUDE RESPONSE (dB) resulting 23-bit output rounded at bit position 5 (multOut<5>) to 17-bits. The extra bit is carried to check for overflow at the output of the shifter. The output of the multiplier (multOut<22:6>) is then shifted to the appropriate position per the exponent bits with a shift value of 0xB positioning the data at the top of the shifter. The final shifted output is then checked for saturation and limited to 16-bits before being output. 80 60 40 20 0 -20 -40 -60 -80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 NORMALIZED FREQUENCY (NYQUIST = 1) FIGURE 8. HALF-BAND FREQUENCY RESPONSE Interpolating Filter Following the halfband stage, the data enters the last stage of interpolating filters. Again, the I and Q filters are identical so the subsequent discussion will refer to a single channel. The data is input to the interpolating filter at this stage’s input sample rate which is dependent on the previous stage’s interpolation rate. At this stage the input sample rate clock is generated by the SYMBOL NCO. For every output sample generated, there is a 12-bit phase value that is also generated in the SYMBOL NCO (the top 12-bits of the phase accumulator). The Interpolator uses this phase value to compute output samples at the output sample rate (FSOUT) which is the final output sample rate of the chip. The nulls in the interpolation filter frequency response align with the interpolation images of the shaping filter. Input to this stage should be no greater than -2dB fullscale to prevent overflow. The impulse response of the Interpolation filter is shown in Figures 9 through 11 for an interpolate by 16 filter (the interpolation ratio, L, is equal to 16). This block may be bypassed if desired. Figures 12 through 17 depict the response for varying interpolation ratios. HSP50415 Typical Performance Curves 0 0 -10 INTERPOLATION FILTER RESPONSE -20 -20 -30 -30 MAGNITUDE (dB) MAGNITUDE (dB) -10 -40 -50 -60 -70 -80 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 0 512 1024 1536 2048 2560 3072 3584 INTERPOLATION FILTER RESPONSE -40 -120 4096 0 64 128 192 FIGURE 9. RESPONSE FOR L = 16; FOUT = 4096 0 0 -10 MAGNITUDE (dB) MAGNITUDE (dB) -30 INTERPOLATION FILTER RESPONSE -0.4 -0.5 -0.6 -60 -70 -80 -90 -100 -110 -0.9 -120 -1 0 8 16 24 32 40 48 56 64 0 72 512 1024 1536 2048 SAMPLE TIMES SAMPLE TIMES FIGURE 11. RESPONSE FOR L = 16; FOUT = 4096 FIGURE 12. RESPONSE FOR L = 2; FOUT = 4096 0 0 -10 -10 -20 -20 MAGNITUDE (dB) -30 MAGNITUDE (dB) 512 -50 -0.8 INTERPOLATION FILTER RESPONSE -50 448 -40 -0.7 -40 384 INTERPOLATION FILTER RESPONSE -20 -0.1 -0.3 320 FIGURE 10. RESPONSE FOR L = 16, FOUT = 4096 0.1 -0.2 256 SAMPLE TIMES SAMPLE TIMES -60 -70 -80 -30 -40 -50 -60 INTERPOLATION FILTER RESPONSE -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 512 1024 1536 SAMPLE TIMES FIGURE 13. RESPONSE FOR L = 4; FOUT = 4096 4-12 2048 0 512 1024 1536 SAMPLE TIMES FIGURE 14. RESPONSE FOR L = 5; FOUT = 4096 2048 HSP50415 Typical Performance Curves (Continued) 0 0 INTERPOLATION FILTER RESPONSE -20 -20 -30 -30 -40 -50 -60 -70 -80 -40 -50 -60 -70 -80 -90 -90 -100 -100 -110 -110 -120 -120 0 512 1024 1536 INTERPOLATION FILTER RESPONSE -10 MAGNITUDE (dB) MAGNITUDE (dB) -10 2048 0 512 1024 1536 2048 SAMPLE TIMES SAMPLE TIMES FIGURE 15. RESPONSE FOR L = 6; FOUT = 4096 FIGURE 16. RESPONSE FOR L = 8; FOUT = 4096 0 INTERPOLATION FILTER RESPONSE -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 512 1024 1536 2048 SAMPLE TIMES FIGURE 17. RESPONSE FOR L = 10; FOUT = 4096 Carrier NCO and Complex Mixer X/SIN(X) Compensation Filters Following the interpolating filter is the complex mixer stage where the quadrature data is modulated onto a carrier signal via a complex multiply operation resulting in a quadrature output sample. The carrier NCO has a 32-bit programmable frequency increment value which is programmed as follows: Following the complex mixer stage is a pair of fixed coefficient 11-tap X/SIN(X) compensation filters. The X/SIN(X) filter performs peaking to compensate for the SIN(X)/X rolloff that occurs at the output of the DACs. These filters may be totally bypassed if not required. The X/SIN(X) filter coefficients are: carrierPhinc = (carrierFrequency / FSout) * 2^32 The frequency may be positive or negative with a range from -50 to +50MHz (for FSout of 100MHz). The phase adder and accumulator are also 32-bits wide. 4-13 -1, 2, -4, 10, -34, 384, -34, 10, -4, 2, -1 The output is rounded to 16-bits. The output of the filter is not checked for saturation since the maximum sum of products is 486/512 (0.949) and overflow will never occur. The data exits the X/SIN(X) filters as a parallel I<15:0> and Q<15:0> data streams at the final sample rate. Figure 18 plots of the inverse sinc function, sinc function, and the effect of compensation. HSP50415 Voltage Reference 4 LOG MAGNITUDE (dB) 3 ISF 2 1 0 -1 -2 SINC -3 -4 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 NORMALIZED FREQUENCY FIGURE 18. X/SIN(X) FILTER RESPONSE I/Q Gain Imbalance Correction Stage Following the X/SIN(X) filter pair is a gain stage where I and Q are scaled independently. The programmable gain consists of a 10-bit scale factor and a 10-bit DC offset. The equation for the gain is as follows: dataOut<15:0> = (dataIn<15:0> * (1.0 +/0.00SSSSSSSSSS)) +/- 0.00DDDDDDDDDD Where SSSSSSSSSS denotes the 10-bit scale factor and DDDDDDDDDD is the 10-bit DC offset value. The scale factor may be optionally added or subtracted from 1.0 and the DC offset may optionally be added or subtracted to the result of the scale operation. For a gain of 1.0 through this stage, program the scale factor to 0x000 and the DC offset to 0x000 for both the I and Q values. The output is rounded to either 14-bits or 12-bits. The rounding options are programmable as shown in Table 4. TABLE 4. IQ GAIN CORRECTION STAGE ROUNDING OPTIONS RNDBITS<1:0> ROUND SELECTION 00 No rounding performed, data is truncated 01 Round to 14-bits 10 Round to 12-bits 11 Round in both positions If saturation does occur, the output is symmetrically limited. Digital to Analog (D/A) Converters The HSP50415 outputs using dual 12-bit, 150MSPS, high speed, low power, D/A converters. The converter provides 20mA of full scale output current and includes edgetriggered CMOS input data latches. Low glitch energy and excellent frequency domain performance is achieved by the DACs segmented current source architecture. The internal voltage reference of the device has a nominal value of + 1.2V with a ±10ppm/ oC drift coefficient over the full temperature range of the converter. It is recommended that a 0.1µF capacitor be placed as close as possible to the REFIO pin, connected to the analog ground. The REFLO pin selects the reference. The internal reference can be selected if REFLO is tied low (ground). If an external reference is desired, then REFLO should be tied high (the analog supply voltage) and the external reference driven into REFIO. The full scale output current of the converter is a function of the voltage reference used and the value of RSET. IOUT should be within the 2mA to 20mA range, though operation below 2mA is possible, with performance degradation. VFSADJ and VREFIO will be equivalent except for a small offset voltage. If the internal reference is used, VFSADJ will equal approximately 1.2V on the FSADJ. If an external reference is used, VFSADJ will equal the external reference. The calculation for IOUT(Full Scale) is: IOUT(Full Scale) = (VFSADJ/RSET) X 32. If the full scale output current is set to 20mA by using the internal voltage reference (1.2V) and a 1.91kΩ RSET resistor, then the input coding to output current is shown in Table 5. TABLE 5. INPUT CODING vs OUTPUT CURRENT INPUT CODE <D11D0> I/QOUTA (mA) I/QOUTB (mA) 11 11111 11111 10 00000 00000 00 00000 00000 20 10 0 0 10 20 Outputs The 5 MSBs for each DAC on the HSP50415 drive a thermometer decoder, which is a digital decoder that has a 5-bit binary coded input word with 25-1 (or 31) output bits, where the number of output bits that are active correlate directly to the input binary word. The HSP50415 uses a thermometer decoder to significantly minimize the output glitch energy for each DAC. I/QOUTA and I/QOUTB are complementary current outputs. The sum of the two currents is always equal to the full scale output current minus one LSB. If single ended use is desired, a load resistor can be used to convert the output current to a voltage. It is recommended that the unused output be either grounded or equally terminated. The voltage developed at the output must not violate the output voltage compliance range of 0.3V to 1.25V. RLOAD (the impedance loading each current output) should be chosen so that the desired output voltage is produced in conjunction with the output full scale current. If a known line impedance is to be driven, then the output load resistor should be chosen to match this impedance. The output voltage equation is: VOUT = IOUT X RLOAD. 4-14 HSP50415 These outputs can be used in a differential-to-single-ended arrangement to achieve better harmonic rejection. The SFDR measurements in this data sheet were performed with a 1:1 transformer on the output of the DAC (see Figure 19). With the center tap grounded, the output swing of I/QOUTA and I/QOUTB will be biased at zero volts. The loading as shown in Figure 19 will result in a 500mV signal at the output of the transformer if the full scale output current of the DAC is set to 20mA. VOUT = 2 x IOUT x REQ, where REQ is ~12.5Ω. R EQ IS THE IMPEDANCE LOADING EACH OUTPUT 50Ω V OUT = (2 x I OUT x R EQ)V I/QOUTA 100Ω HSP50415 50Ω I/QOUTB 50Ω 50Ω REPRESENTS THE SPECTRUM ANALYZER Offset Drift, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per degree oC. Offset Error, is measured by setting the data inputs to all logic low (all 0s) and measuring the output voltage through a known resistance. Offset error is defined as the maximum deviation of the output current from a value of 0mA. Output Settling Time, is the time required for the output voltage to settle to within a specified error band measured from the beginning of the output transition. The measurement is done by switching quarter scale. Termination impedance was 25Ω due to the parallel resistance of the 50Ω loading on the output and the oscilloscope’s 50Ω input. This also aids the ability to resolve the specified error band without overdriving the oscilloscope. FIGURE 19. DAC OUTPUTS Allowing the center tap to float will result in identical transformer output, however the output pins of the DAC will have positive DC offset. Since the DACs output voltage compliance range is -0.3V to +1.25V, the center tap may need to be left floating or DC offset in order to increase the amount of signal swing available. The 50Ω load on the output of the transformer represents the spectrum analyzer’s input impedance. Definition of DAC Specifications Differential Linearity Error, DNL, is the measure of the step size output deviation from code to code. Ideally the step size should be 1 LSB. A DNL specification of 1 LSB or less guarantees monotonicity. Full Scale Gain Drift, is measured by setting the data inputs to be all logic high (all 1s) and measuring the output voltage through a known resistance as the temperature is varied from TMIN to TMAX . It is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm of FSR (full scale range) per oC. Full Scale Gain Error, is the error from an ideal ratio of 32 between the output current and the full scale adjust current (through RSET). Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Internal Reference Voltage Drift, is defined as the maximum deviation from the value measured at room temperature to the value measured at either TMIN or TMAX . The units are ppm per oC. 4-15 Output Voltage Compliance Range, is the voltage limit imposed on the output. The output impedance should be chosen such that the voltage developed does not violate the compliance range. Reference Input Multiplying Bandwidth, is defined as the 3dB bandwidth of the voltage reference input. It is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. The frequency is increased until the amplitude of the output waveform is 0.707 (-3dB) of its original value. Microprocessor Interface The HSP50415 is highly configurable with 16 writable/readable control registers and four addresses reserved for generating internal control signals. The microprocessor interface (uPI) is a parallel bus type with the following device pins being used for I/O: CDATA<7:0>, ADDR<2:0>, CE and RD. These device pins are synchronous to the WR pin which is actually the clock for the uPI logic. Data is written to control words by writing to a sequence of address locations with the data present on the CDATA<7:0> bus. The uPI contains a 32-bit master register which is first loaded with the control word data one byte at a time, then downloaded to a slave register that is synchronous to the digital core clock (SYSCLK/2). The sequence of writes necessary to program control word 12, for example, with the value 0xAABBCCDD would be as shown in Table 6 and Figure 20. HSP50415 TABLE 7. READBACK OF CNTLWORD12 WR 0 ADDR<2:0> CDATA<7:0> DD 1 2 CC 3 BB AA 4 OC X ADDR<2: CDATA<7: 0> 0> CE X RD 5 0x0C 0 1 1 write to addrReg<4:0> 0 0xDD 0 0 x read CntlWord12<7:0> 1 0xCC 0 0 x read CntlWord12<15:8> 2 0xBB 0 0 x read CntlWord12<23:16> 3 0xAA 0 0 x read CntlWord12<31:24> CE RD FIGURE 20. CONTROL REGISTER LOADING SEQUENCE There should be at least 4 digital core clock cycles between writing to address 4 and reloading the MasterReg as the data from the MasterReg is being downloaded to slave registers synchronous to the core clock cycles and synchronization circuitry is required. The frequency of the WR pin may not exceed CLK/4 (25MHz max for CLK of 100MHz). To readback the value in control word 12, the following sequence of writes/reads shown in Table 7 should occur. Note that the RD pin is the Three-State control for the CDATA<7:0> bus with a logic 1 on the RD pin disabling the output drivers configuring the pins as inputs and a logic 0 on the RD pin enabling the output drivers making the pins outputs. The CE pin must be active for any read or write to the device to be processed. The ADDR<2:0>, CDATA<7:0> and CE pins when writing to the device (RD=1) are synchronous to the WR pin, but when reading (RD=0), the ADDR<2:0> and CE pins are not synchronous to the WR pin, and are actually mux controls to determine which byte of the read data is output on the CDATA<7:0> bus.: TABLE 6. SEQUENCE OF WRITES TO LOAD CNTLWORD12 ADDR<2:0 CDATA<7: > 0> CE RD WR INTERNAL OPERATION WR Writing and reading back the internal RAMs require a different sequence of writes and reads. Each RAM on the device is accessible through the uPI, with the FIFO only having readback capability. The user selects which memory to access and the access type (read or write) as well as the address mode by programming the memory configuration bits in ControlWord 0 as shown in Table 8. TABLE 8. CONTROL WORD 0 - MEMORY CONTROL BITS BIT # VALUE 7 x Not Used 6 0 Disable Memory Address Auto Increment Mode User must provide address 1 Auto-Increment Memory Address Mode Active 0 Memory R/W select: Write to Selected Memory 1 Memory R/W select: Read from Selected Memory 5 4:2 INTERNAL OPERATION DEFINITION 000 No Memory Access Active 001 I channel 64x72-bit coefficient RAM selected 010 Q channel 64x72-bit coefficient RAM selected 0 0xDD 0 1 1 write to MasterReg<7:0> 011 I and Q channel 64x72-bit coefficient RAMs selected for simultaneous access 1 0xCC 0 1 1 write to MasterReg<15:8> 100 256x8-bit constellation map RAM selected 2 0xBB 0 1 1 write to MasterReg<23:16> 101 256x32-bit FIFO RAM selected 110 Not Used 111 Not Used 00 Memory Word Select Bits <1:0>, load with 00 prior to starting load sequence 3 0xAA 0 1 1 write to MasterReg<31:24> 4 0x0C 0 1 1 MasterReg<31:0> -> cntlWord12<31:0> 4-16 1:0 Once these bits are programmed, the user loads up the masterReg<31:0> using the same sequence as shown in Table 8 followed by a write to internal address 0x0F to download the masterReg<31:0> data to the internal memory word buffer. If auto-increment address mode is selected then the user does not need to provide the memory address for the data; the address is generated sequentially internal to the device. If the 64x72-bit RAMs are selected for the HSP50415 memUpdate signal that loads the memory buffer from MasterReg<23:0>. Which section of the memory buffer gets the data is dependent on the memory word select counter shown in column 7 of Table 9. A memUpdate strobe increments the word select counter as well as updating the memBuffer. When the word select counter is equal to 2 and a memUpdate strobe occurs, memBuf<71:0> data is written to memAddr<7:0> of the I/Q coefficient RAMs and the mem word select counter is cleared ready for the next sequence of writes to the memory buffer. Writing to the constellation map RAM is much simpler as Table 10 demonstrates. access, then 72-bits of data must be loaded to the internal memory buffer per memory address. This is accomplished by performing three (3) 24-bit master to slave loads. Table 9 demonstrates the sequence of writes necessary to load memory location 0 of the I and Q channel coefficient RAMs simultaneously. If auto-increment address mode had been enabled, then the write to MasterReg<31:24> with the destination memory address would not have been required, as writing to Control Word 0 would reset the internal auto-increment address to 0. Writing a 0x0F to address 4 generates an internal TABLE 9. EXAMPLE SEQUENCE OF WRITES TO LOAD I/Q COEFFICIENT RAM ADDR<2:0> CDATA<7:0> CE RD WR INTERNAL OPERATION MEM WORD SELECT<1:0> 0 0x0C 0 1 1 write to MasterReg<7:0> xx 4 0x00 0 1 1 MasterReg<7:0> -> cntlWord0<7:0> 00 0 memData[0][7:0] 0 1 1 write to MasterReg<7:0> 00 1 memData[0][15:8] 0 1 1 write to MasterReg<15:8> 00 2 memData[0][23:16] 0 1 1 write to MasterReg<23:16> 00 4 0x0F 0 1 1 MasterReg<23:0> -> memBuf<23:0> 00 0 memData[0][31:24] 0 1 1 write to MasterReg<7:0> 01 1 memData[0][39:32] 0 1 1 write to MasterReg<15:8> 01 2 memData[0][47:40] 0 1 1 write to MasterReg<23:16> 01 4 0x0F 0 1 1 MasterReg<23:0> -> memBuf<47:24> 01 0 memData[0][55:48] 0 1 1 write to MasterReg<7:0> 10 1 memData[0][63:56] 0 1 1 write to MasterReg<15:8> 10 2 memData[0][71:64] 0 1 1 write to MasterReg<23:16> 10 3 0x00 (memAddr) 0 1 1 write to MasterReg<31:24> 10 4 0x0F 0 1 1 MasterReg<23:0> -> memBuf<71:48> 10 MasterReg<31:24> -> memAddr<7:0> 10 TABLE 10. EXAMPLE SEQUENCE OF WRITES TO LOAD CONSTELLATION MAP RAM ADDR<2:0> CDATA<7:0> CE RD WR INTERNAL OPERATION MEM WORD SELECT<1:0> 0 0x10 0 1 1 write to MasterReg<7:0> xx 4 0x00 0 1 1 MasterReg<7:0> -> cntlWord0<7:0> 00 2 memData[0][7:0] 0 1 1 write to MasterReg<23:16> 00 3 0x00 (memAddr) 0 1 1 write to MasterReg<31:24> 00 4 0x0F 0 1 1 MasterReg<23:16> -> memBuf<71:64> 00 MasterReg<31:24> -> memAddr<7:0> 00 4-17 HSP50415 will reset the byte counter to 0. A write to address 7 will increment the byte counter so the WR clock must be pulsed during the memory reads in order to increment the byte counter. Table 11 defines the sequence of writes/reads necessary to read back the I channel coefficient memory data at memory address 0x12. When writing to the constellation map RAM, when the word select counter is equal to 0 and a memUpdate strobe occurs, memBuf<71:64> data is written to memAddr<7:0> of the constellation map RAM. When reading back the memories, The sequence is similar to reading back the Control Words, except the uPI addresses written to are different. When reading back the I/Q channel coefficient memories, 9 bytes (72-bits) of data are read per memory address, the constellation map RAM contains 1 byte of data per address, while the FIFO RAM contains 4 bytes of data per address. An internal byte counter takes care of which byte is being read out with a write to address 6 with the memory address to be read back The constellation map RAM and the FIFO RAM are read back in a similar manner with fewer writes to address 7 since fewer bytes per address are read back. A synopses of the uPI address space functions is shown in Table 12, with Tables 13-32 providing detailed descriptions. TABLE 11. EXAMPLE SEQUENCE OF WRITES TO READ I COEFFICIENT RAM ADDR<2:0> CDATA<7:0> CE RD WR INTERNAL OPERATION MEM BYTE COUNT<3:0> 0 0x24 0 1 1 write to MasterReg<7:0> xx 4 0x00 0 1 1 MasterReg<7:0> -> cntlWord0<7:0> xx 6 0x12 (memAddr) 0 1 1 write to memReadAddr<7:0> 0 6 0x12 (memAddr) 0 1 1 write to memReadAddr<7:0> 0 7 memData[18][7:0] 0 0 1 read memData[18] byte 0 0 7 memData[18][15:8] 0 0 1 read memData[18] byte 1 1 7 memData[18][23:16] 0 0 1 read memData[18] byte 2 2 7 memData[18][31:24] 0 0 1 read memData[18] byte 3 3 7 memData[18][39:32] 0 0 1 read memData[18] byte 4 4 7 memData[18][47:40] 0 0 1 read memData[18] byte 5 5 7 memData[18][55:48] 0 0 1 read memData[18] byte 6 6 7 memData[18][63:56] 0 0 1 read memData[18] byte 7 7 7 memData[18][71:64] 0 0 1 read memData[18] byte 8 8 TABLE 12. MICROPROCESSOR INTERFACE ADDRESS SPACE DEFINITIONS ADDR <2:0> WR/RD INTERNAL OPERATION 0 wr Write to MasterReg<7:0> (CDATA<7:0> -> MasterReg<7:0>) 1 wr Write to MasterReg<15:8> (CDATA<7:0> -> MasterReg<15:8>) 2 wr Write to MasterReg<23:16> (CDATA<7:0> -> MasterReg<23:16>) 3 wr Write to MasterReg<31:24> (CDATA<7:0> -> MasterReg<31:24>) 4 wr Download MasterReg<31:0> -> Control Word x (x=CDATA<4:0>) 5 wr Write address of Control Word to be read back (CDATA<4:0> -> addrReg<4:0>) 6 wr Write address of Accessed Memory to be read back (CDATA<7:0> -> memAddr<7:0>) 7 wr Increment Memory Address Read Back Byte Counter (byteCount<3:0>) 0 rd Read ControlWordx<7:0> (x=addrReg<4:0>) 1 rd Read ControlWordx<15:8> (x=addrReg<4:0>) 2 rd Read ControlWordx<23:16> (x=addrReg<4:0>) 3 rd Read ControlWordx<31:24> (x=addrReg<4:0>) 4 rd Read byte # of MemWord<x> (x=memAddr<7:0>, byte # =byteCount<3:0>) 4-18 HSP50415 TABLE 12. MICROPROCESSOR INTERFACE ADDRESS SPACE DEFINITIONS (Continued) ADDR <2:0> WR/RD INTERNAL OPERATION 5 rd Read byte # of MemWord<x> (x=memAddr<7:0>, byte # =byteCount<3:0>) 6 rd Read byte # of MemWord<x> (x=memAddr<7:0>, byte # =byteCount<3:0>) 7 rd Read byte # of MemWord<x> (x=memAddr<7:0>, byte # =byteCount<3:0>) TABLE 13. HSP50415 REGISTER SUMMARY ADDRESS BIT WIDTH REGISTER NAME RESET VALUE 00H 8 Memory Write/Read Controls 0x00 01H 32 Device Configuration Controls 0x0000602B 02H 32 FIFO And I/O Control 0x00000000 03H 32 FIFO Upper Threshold and I Channel Gain 0xFF000002 04H 32 FIFO Lower Threshold and Q Channel Gain 0x00000002 05H 32 Gain and Phase Error Control 0x02FFFFFF 06H 32 Digital Loop Filter Control 0x50000000 07H 32 Lock Detect and Analog PLL Control 0x00400000 08H 8 Interrupt Status 0x00 09H 8 Interrupt Enable 0x00 0AH 32 Carrier Frequency 0x00000000 0BH 32 Symbol Frequency 0x00000000 0CH 32 Digital Loop Filter Upper Limit 0x7FFFFFFF 0DH 32 Digital Loop Filter Lower Limit 0x80000000 0EH FIFO Reset Strobe 0 0FH Memory Word Load Strobe 0 10H Soft Reset Signal 0 11H 19 12H Coefficient Ram Preload Data FIFO Write Strobe 0x00000 0 TABLE 14. MEMORY WRITE/READ CONTROL ADDRESS = 00H BIT NO. DESCRIPTION RESET STATE 7 Reserved 0 6 Auto Increment Memory Address 0 5 Memory R/W (Used in conjunction with bits 4:2) 0 = Write 1 = Read 0 4:2 Memory Access Select. 000B = No Access (note: must set no access for normal running of part) 001B = IfirMem Access 010B = QfirMem Access 011B = I+QfirMem Access 100B = Constellation Map Memory Access 101B = FIFO Access 1:0 Memory Word Select 4-19 000B 00 HSP50415 TABLE 15. DEVICE CONFIGURATION CONTROL ADDRESS = 01H BIT NO. 31:16 DESCRIPTION Symbol NCO Counter MaxCount<15:0> RESET STATE 0000H 15 Symbol NCO Counter Mode Enable 0B 14 Fast DAC delay 1B 13 Bypass Final Interpolation Filter 1B 12 2-bit Filter Mode. Input data at 2x rate with # taps used. 0B Shaping Filter Interpolation 00B = 4x 01B = 8x 10B = 16x 11B = reserved 00B 11:10 9:6 Data Bit Width NumBits/2B12-1 If Bit 12 = 0, 0000B = 1 bit 0001B = 2 bits… 1110B = 15 bits 1111B = 16 bits If Bit 12 = 1, 0000B = 2 bits 0001B = 4 bits… 1110B = 30 bits 1111B = 32 bits 0000B 5 X/Sin(X) Filter Bypass. 0 = Enable 1 = Bypass 1 4 Half Band Filter Enable 0 = Bypass 1 = Enable 0 3 Shaping Filter Bypass 0 = Enable 1 = Bypass 1 2 Decimate by 2 at output of Shaping Filter 0 = Disable 1 = Enable 0 1 Constellation Map Bypass 0 = Enable 1 = Bypass 1 0 FIFO Bypass 0 = Enable 1 = Bypass 1 4-20 HSP50415 TABLE 16. FIFO AND I/O CONTROL ADDRESS = 02H BIT NO. 31:24 DESCRIPTION FIFO Frequency Term 4 Loop Filter <7:0>. RESET STATE 00H 23 FIFO Full Stop Writing 0 22 FIFO Empty, Force 0 data 0 21:20 FIFO Threshold Mode 00B = Disable Threshold Logic and FIFOUnderFlow / FIFOOverFlow flags 01B = Enable Thresholds, Disable Symbol Rate Modifications 10B = Enable Thresholds and Modify Frequency Error Term 11B = Enable Thresholds and Force lag accumulator to Limit 00B 19 FIFO TXEN Zero Data. (Function: If FIFO Reads are gated with TXEN Pin then force data out of FIFO block to 0x0000 if TXEN is inactive.) 0 18 FIFO TXEN Enable Gated Write 0 = TXEN Pin gates writing to FIFO 1 = FIFO writes not gated by TXEN 0 17 FIFO TXEN Gated Read 0 = FIFO reads not gated by TXEN (reads begin after 2 FIFO locations written) 1 = TXEN Pin gates read from FIFO 0 16 FIFO Underflow/Empty Pin Function 0 = Output FIFO underflow status on Pin FEMPT 1 = Output FIFO empty status on Pin FEMPT 0 15 2XSYMCLK polarity 0 14 2XSYMCLK Three-State enable 0 = off 1 = enable output 0 13 FFULL, FIFO Full Output Enable 0 12 FOVRFL, FIFO Overflow Output Enable 0 11 FEMPT, FIFO Under/Empty Output Enable 0 10 LOCKDET Output Enable 0 9 SYSCLK/2 Output Enable 0 8 INTREQ Pin Output Enable 0 7 IOUT<13:0> Output Enable 0 6 QOUT<13:0> Output Enable 0 5 TXEN Polarity 0 = Active High 1 = Active Low 0 4 ISTRB Polarity. 0 = Active High (DIN<15:0> contains Isample when ISTRB is high) 1 = Active Low (DIN<15:0> contains Isample when ISTRB is low) 0 3 SYSCLK/2 polarity. 0 = IOUT<13:0>/QOUT<15:0> data out on falling edge 1 = IOUT<13:0>/QOUT<15:0> data out on rising edge 0 2 FIFO Gated Read No Address Reset 0 1 IDAC Power Enable 0 0 QDAC Power Enable 0 4-21 HSP50415 TABLE 17. I CHANNEL CALIBRATION ADDRESS = 03H BIT NO. DESCRIPTION RESET STATE 31:24 FIFO Threshold Upper Limit<7:0> FFH 23:14 I Scale Factor<9:0> 000H 13:4 I DC Offset <9:0> 000H 3 I Negate Scale Factor 0 2 I Subtract DC Offset 0 1:0 I Programmable Round 00B = No Rounding 01B = Round to 14-bits at output 10B = Round to 12-bits at output 11B = Round in both positions 10B TABLE 18. Q CHANNEL CALIBRATION ADDRESS = 04H BIT NO. DESCRIPTION RESET STATE 31:24 FIFO Threshold Lower Limit<7:0> FFH 23:14 Q Scale Factor<9:0> 000H 13:4 Q DC Offset <9:0> 000H 3 Q Negate Scale Factor 0 2 Q Subtract DC Offset 0 1:0 Q Programmable Round 00B = No Rounding 01B = Round to 14-bits at output 10B = Round to 12-bits at output 11B = Round in both positions 10B TABLE 19. GAIN AND PHASE ERROR CONTROL ADDRESS = 05H BIT NO. DESCRIPTION RESET STATE 31:26 Post Shaping Filter Gain 01.XXXXXX 25:22 Post Shaping Filter Shift<3:0> 1011B 21:8 N Count <13:0> for Phase Error Detector 3FFFH 7:0 M Count <7:0> for Phase Error Detector. (Minimum value = 4) 4-22 000000B FFH HSP50415 TABLE 20. DIGITAL LOOP FILTER CONTROL ADDRESS = 06H BIT NO. DESCRIPTION RESET STATE 31 Reserved 0 30 Invert Phase Error 1 29 Invert Frequency Error 0 28 Disable Offset Frequency 1 27:16 Loop Filter Gains: Bits 27:24 = lag[3:0] Bits 23:20 = frq[3:0] Bits 19:16 = lead[3:0] 000H 15:1 Loop Filter Shifts: Bits 15:11 = lag[4:0] Bits 10:6 = frq[4:0] Bits 5:1 = lead[4:0] 0000H 0 Zero Loop Filter Accumulator 0 TABLE 21. LOCK DETECT CONTROL ADDRESS = 07H BIT NO. 31 DESCRIPTION Use Analog PLL lock status bit for Lock Detection RESET STATE 0 30:28 Analog PLL VCO divider 000B = 1x 001B = 2x 010B = 4x 011B = 8x 100B = 16x 101B = 32x 000B 27:26 Analog PLL CLK divider 00B = /1 01B = /2 10B = /4 11B = /8 00B 25 Enable Analog PLL 0 24 Use Analog PLLCLK for CLK 0 23:3 Phase Error Threshold[20:0] 08000H 2:1 Less than Threshold Increment 00B = + 0.0625 01B = + 0.125 10B = + 0.25 11B = + 0.50 0 Greater than Threshold Decrement 0 = -0.50 1 = -0.25 4-23 00B 0 HSP50415 TABLE 22. INTERRUPT STATUS ADDRESS = 08H BIT NO. DESCRIPTION RESET STATE 7 Not Used 0 6 FIFO Full 0 5 FIFO Empty 0 4 FIFO Overflow 0 3 FIFO Underflow 0 2 Digital PLL Lock Detect 0 1 Analog PLL Lock Detect 0 0 Reset Done 0 TABLE 23. INTERRUPT ENABLE ADDRESS = 09H BIT NO. DESCRIPTION RESET STATE 7 Not Used 0 6 FIFO Full 0 5 FIFO Empty 0 4 FIFO Overflow 0 3 FIFO Underflow 0 2 Digital PLL Lock Detect 0 1 Analog PLL Lock Detect 0 0 Reset Done 0 TABLE 24. CARRIER FREQUENCY ADDRESS = 0AH BIT NO. 31:0 DESCRIPTION Carrier NCO Frequency Step RESET STATE 00000000H TABLE 25. SYMBOL FREQUENCY ADDRESS = 0BH BIT NO. 31:0 DESCRIPTION Symbol NCO Frequency Step RESET STATE 00000000H TABLE 26. DIGITAL LOOP FILTER UPPER LIMIT ADDRESS = 0CH BIT NO. 31:0 DESCRIPTION Digital Loop Filter Upper Limit RESET STATE 7FFFFFFFH TABLE 27. DIGITAL LOOP FILTER LOWER LIMIT ADDRESS = 0DH BIT NO. 31:0 DESCRIPTION Digital Loop Filter Lower Limit 4-24 RESET STATE 00000000H HSP50415 TABLE 28. FIFO RESET STROBE ADDRESS = 0EH BIT NO. DESCRIPTION RESET STATE NA Writing to control word 0x0E generates an internal FIFOReset strobe that resets the FIFO address pointers and flags. 0 TABLE 29. MEMORY BUFFER UPDATE STROBE ADDRESS = 0FH BIT NO. DESCRIPTION NA Writing to control word 0x0F generates an internal memBuf update strobe that downloads the appropriate MasterReg byte to the memory Buffer. RESET STATE 0 TABLE 30. SOFT RESET SIGNAL ADDRESS = 10H BIT NO. DESCRIPTION RESET STATE NA Writing to uPI address space 4 with CDATA<7:0> = 0x10 forces the internal soft Reset signal active. The soft Reset stays active until different CDATA<7:0> other than 0x10 is written to address space 4. 0 TABLE 31. SHAPING FIR ROUNDING AND BALANCE ADDRESS = 11H BIT NO. DESCRIPTION 19 I/Q FIR preLoad<18:0> filter seed value. RESET STATE 0 TABLE 32. FIFO DATA WRITE STROBE ADDRESS = 12H BIT NO. DESCRIPTION NA RESET STATE Strobe used to enable writes to FIFO - data from DIN<15:0.>, ISTRB interface. 0 Power Consumption Evaluation Kit The HSP50415 power consumption is as shown in Figure 21. The HSP50415EVAL1 is an evaluation kit for the HSP50415 wideband programmable modulator. The kit consists of an evaluation Circuit Card Assembly complete with the HSP50415 device and additional circuitry to provide for control via a computer parallel port. Windows based demonstration software is provided for full user programmability and control of all HSP50415 operational modes. Documentation includes a user’s manual, full evaluation board schematics and PCB layout materials. 1250 POWER CONSUMPTION (mW) 1200 VDD = 3.3VDC 1150 1100 1050 1000 950 900 850 WORST CASE SHAPING FILTER OFF HALF BAND OFF INTERPOLATION OFF 800 750 700 50 55 60 65 70 75 80 85 90 95 100 CLK FREQUENCY (MHz) FIGURE 21. POWER CONSUMPTION vs CLK FREQUENCY 4-25 HSP50415 Absolute Maximum Ratings Thermal Information Supply Voltage (VDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . .6V All Signal Pins . . . . . . . . . . . . . . . . . . . . (GND – 0.5V) to (VDD + 0.5V) ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2 Thermal Resistance (Typical, Note 2) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Vapor Phase Soldering, 1 Minute MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. Electrical Specifications VDD = +3.3V ±5%, TA = -40oC to 85oC, Unless Otherwise Specified PARAMETER TEST CONDITION MIN TYP MAX UNITS 3.15 3.3 3.45 V POWER SUPPLY CHARACTERISTICS Power Supply Voltage, AVDD, DVDD Supply Current (IVDD) IOUTFS = 20mA - 420 500 mA Power Dissipation IOUTFS = 20mA - - 1.75 W Supply Current (IVDD) Sleep Mode DAC in sleep mode CLK stopped - 4 6 mA Power Supply Rejection Single Supply -0.2 - +0.2 %FSR/V Input Logic Low Voltage, VIL - - 0.8 V Input Logic High Voltage, VIH 2.0 - - V µA DC CHARACTERISTICS: DIGITAL I/O Input Logic Low Current, IIL VIN = 0.0V -10 - 10 Input Logic High Current, IIH VIN = DVDD -10 - 10 µA Output Tristate Low Current, IXL -10 - 10 µA Output Tristate High Current, IXH -10 - 10 µA Input Capacitance, CIN (Note 1) - 6 - pF Output Logic Low Voltage, VOL IOL = 2mA - - 0.4 V Output Logic High Voltage, VOH IOH = -2mA 2.6 - - V Output Capacitance, COUT (Note 1) - 6 - pF AC CHARACTERISTICS: DIGITAL CONTROL AND PROCESSOR INTERFACE - - 100 MHz CLK High, TCH CLK Frequency, FCLK (Note 1) 4 - - ns CLK Low, TCL (Note 1) 4 - - ns RESET Setup Time, TRTS To CLK, (Note 1) 3 - - ns RESET Hold Time, TRTH From CLK, (Note 1) 1 - - ns RESET Pulsewidth, TRPW CLK Cycles, (Note 1) 10 - - Cycles - - CLK/4 MHz WR Frequency Setup Time, TS CDATA<7:0>, ADDR<2:0> and CE to WR, (Note 1) 15 - - ns Hold Time, TH CDATA<7:0>, ADDR<2:0> and CE from WR, (Note 1) 0 - - ns CDATA<7:0> Output Delay, TDA CDATA<7:0> from ADDR<2:0>, (Note 1) - - 20 ns CDATA<7:0> Output Delay, TDW CDATA<7:0> from WR, (Note 1) - - 20 ns DATACLK Frequency, FDCLK - - CLK / 2 MHz DATACLK High, TDCH 5 - - ns AC CHARACTERISTICS: DIGITAL I/Q DATA INPUT 4-26 HSP50415 Electrical Specifications VDD = +3.3V ±5%, TA = -40oC to 85oC, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITION DATACLK Low, TDCL MIN TYP MAX UNITS 5 - - ns Setup Time, TDS DIN<15:0>, TXEN, ISTRB to DATACLK, (Note 1) 8 - - ns Hold Time, TDH DIN<15:0>, TXEN, ISTRB from DATACLK, (Note 1) 0 - - ns AC CHARACTERISTICS: DIGITAL STATUS / DATA REFCLK Frequency, FRCK - - CLK / 4 MHz REFCLK High, TRCH 5 - - ns REFCLK Low, TRCL 5 - - ns - - 5 ns 12 - - Bits Digital Status & Output Data Delay, TDO From SYSCLK/2 Includes IOUT<13:0>, FIFO status pins, LOCKDET and INTREQ., (Note 1) ANALOG OUTPUT PERFORMANCE: Resolution Integral Linearity Error, INL “Best Fit” Straight Line (Note 4) - ±1 - LSB Differential Linearity Error, DNL (Note 4) - ±0.5 - LSB Offset Error, IOS (Note 4) -0.025 +0.025 % FSR Offset Drift Coefficient (Note 4) - 0.1 - ppm FSR/oC Full Scale Gain Error, FSE With External Reference (Notes 3, 4) -10 ±2 +10 % FSR With Internal Reference (Notes 3, 4) -10 ±1 +10 % FSR With External Reference (Note 4) - ±50 - ppm FSR/oC With Internal Reference (Note 4) - ±100 - ppm FSR/oC 2 - 20 mA - 30 - pF -1.0 - 1.25 V Gain Matching Between Channels -8 - +8 % FSR Offset Matching Between Channels - ±0.05 - % FSR - ±0.5 - Degrees - 1.23 - V (Note 1) - ±40 - ppm/oC Internal Reference Output Current Sink/Source (Note 1) Capability - ±0.1 - µA Reference Input Impedance (Note 1) - 1 - MΩ Reference Input Multiplying Bandwidth (Notes 1, 4) - 1.4 - MHz Full Scale Gain Drift Full Scale Output Current, IFS Output Capacitance (Note 1) Output Voltage Compliance Range (Note 1, 4) Phase Matching Between Channels (Note 1) VOLTAGE REFERENCE: Internal Reference Voltage, VREF Internal Reference Voltage Drift NOTES: 1. Parameter guaranteed by design or characterization and not production tested. 2. θJA is measured with the component mounted on an evaluation PC board in free air. 3. Gain Error measured as the error in the ratio between the full scale output current and the current through RSET (typically 625µA). Ideally the ratio should be 32. 4. See ‘Definition of DAC Specifications’ section. 4-27 HSP50415 Waveforms TCL TDCL TCH TDCH DATACLK CLK // TCLK TRTS TCLK = 1 / FCLK FIGURE 22. CLK AND RELATIVE RESET TIMING TDCLK = 1 / FDCLK FIGURE 23. TIMING RELATIVE TO DATACLK WR TRCL TRCH TH CDATA<7:0>, ADDR<2:0>, AND CE // REFCLK // TRCK TS TRCK = 1 / FRCK RD FIGURE 24. TIMING RELATIVE TO WR, LOADING SEQUENCE FIGURE 25. REFCLK TIMING WR TDA AND TDW SYSCLK/2 ADDR<2:0> ADDR. VALID TDO DATA VALID CDATA<7:0> IOUT<13:0>, FEMPT, FOVRFL, FFULL, LOCKDET, AND INTREQ VALID RD AND CE FIGURE 26. TIMING RELATIVE TO WR, READING SEQUENCE 4-28 TDH DIN<15:0>, TXEN, AND ISTRB TRPW RESET TDS TDCLK TRTH FIGURE 27. SYSCLK/2 RELATIVE TIMING HSP50415 Metric Plastic Quad Flatpack Packages (MQFP) Q100.14x20 (JEDEC MS-022GC-1 ISSUE B) D 100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE D1 -D- INCHES -A- -B- E E1 e PIN 1 SEATING A PLANE -H- 0.076 0.003 -C- 12o-16o 0.40 0.016 MIN 0.20 M C A-B S 0.008 0o MIN A2 A1 0o-7o L 12o-16o SYMBOL MIN MAX MIN MAX NOTES A - 0.134 - 3.40 - A1 0.010 - 0.25 - - A2 0.101 0.113 2.57 2.87 - b 0.009 0.015 0.22 0.38 6 b1 0.009 0.013 0.22 0.33 - D 0.908 0.918 23.08 23.32 3 D1 0.782 0.792 19.88 20.12 4, 5 E 0.673 0.681 17.10 17.30 3 E1 0.547 0.555 13.90 14.10 4, 5 L 0.029 0.040 0.73 1.03 - N 100 100 7 e 0.026 BSC 0.65 BSC - ND 30 30 - NE 20 20 Rev. 1 4/99 NOTES: D S 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. b 2. All dimensions and tolerances per ANSI Y14.5M-1982. b1 3. Dimensions D and E to be determined at seating plane -C- . 4. Dimensions D1 and E1 to be determined at datum plane -H- . 0.13/0.17 0.005/0.007 BASE METAL WITH PLATING MILLIMETERS 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 0.13/0.23 0.005/0.009 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 4-29 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029