Dual, 16-Bit, 1230 MSPS, TxDAC+ Digital-to-Analog Converter AD9146 The AD9146 TxDAC+® includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 3-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9146 comes in a 48-lead LFCSP. FEATURES Flexible LVDS interface allows byte or nibble load Single-carrier W-CDMA ACLR = 80 dBc at 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Integrated 2×/4× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Gain, dc offset, and phase adjustment for sideband suppression Multiple chip synchronization interfaces High performance, low noise PLL clock multiplier Digital inverse sinc filter Low power: 1.2 W at 1.0 GSPS, 800 mW at 500 MSPS, full operating conditions 48-lead, exposed paddle LFCSP PRODUCT HIGHLIGHTS 1. 2. APPLICATIONS Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies (IF). Proprietary DAC output switching technique enhances dynamic performance. Current outputs are easily configured for various singleended or differential circuit topologies. Compact LVDS digital interface offers reduced width data bus. Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point 3. GENERAL DESCRIPTION IQ Modulators: ADL5370, ADL537x family IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family Clock Drivers: AD9516, AD951x family Voltage Regulator Design Tool: ADIsimPower Additional companion products on the AD9146 product page 4. COMPANION PRODUCTS The AD9146 is a dual, 16-bit, high dynamic range digital-toanalog converter (DAC) that provides a sample rate of 1230 MSPS, permitting multicarrier generation up to the Nyquist frequency. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF DC fIF LO – fIF 2/4 DIGITAL BASEBAND PROCESSOR OFFSET AND GAIN ADJ SINC–1 I DAC ANTIALIASING FILTER SINC–1 Q DAC AQM PA LO 09691-001 2/4 OFFSET AND GAIN ADJ NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. AD9146 TABLE OF CONTENTS Features .............................................................................................. 1 Quadrature Phase Correction................................................... 34 Applications ....................................................................................... 1 DC Offset Correction ................................................................ 34 General Description ......................................................................... 1 Inverse Sinc Filter ....................................................................... 35 Product Highlights ........................................................................... 1 DAC Input Clock Configurations ................................................ 36 Companion Products ....................................................................... 1 Driving the DACCLK and REFCLK Inputs ........................... 36 Typical Signal Chain......................................................................... 1 Direct Clocking .......................................................................... 36 Revision History ............................................................................... 2 Clock Multiplication .................................................................. 36 Functional Block Diagram .............................................................. 3 PLL Settings ................................................................................ 37 Specifications..................................................................................... 4 Configuring the VCO Tuning Band ........................................ 37 DC Specifications ......................................................................... 4 Analog Outputs............................................................................... 38 Digital Specifications ................................................................... 5 Transmit DAC Operation.......................................................... 38 Digital Input Data Timing Specifications ................................. 5 Auxiliary DAC Operation ......................................................... 39 AC Specifications.......................................................................... 6 Interfacing to Modulators ......................................................... 40 Absolute Maximum Ratings............................................................ 7 Baseband Filter Implementation .............................................. 40 Thermal Resistance ...................................................................... 7 Driving the ADL5375-15 .......................................................... 40 ESD Caution .................................................................................. 7 Reducing LO Leakage and Unwanted Sidebands .................. 41 Pin Configuration and Function Descriptions ............................. 8 Device Power Management........................................................... 42 Typical Performance Characteristics ........................................... 10 Power Dissipation....................................................................... 42 Terminology .................................................................................... 14 Tx Enable ..................................................................................... 42 Theory of Operation ...................................................................... 15 Temperature Sensor ................................................................... 43 Serial Port Operation ................................................................. 15 Multichip Synchronization............................................................ 44 Data Format ................................................................................ 15 Synchronization with Clock Multiplication ............................... 44 Serial Port Pin Descriptions ...................................................... 15 Synchronization with Direct Clocking .................................... 45 Serial Port Options ..................................................................... 16 Data Rate Mode Synchronization ............................................ 45 Device Configuration Register Map and Descriptions ......... 17 FIFO Rate Mode Synchronization ........................................... 46 LVDS Input Data Ports .................................................................. 27 Additional Synchronization Features ...................................... 47 Byte Interface Mode ................................................................... 27 Interrupt Request Operation ........................................................ 48 Nibble Interface Mode ............................................................... 27 Interrupt Service Routine .......................................................... 48 FIFO Operation .......................................................................... 27 Interface Timing Validation .......................................................... 49 Interface Timing ......................................................................... 30 SED Operation............................................................................ 49 Digital Datapath.............................................................................. 31 SED Example .............................................................................. 50 Premodulation ............................................................................ 31 Example Start-Up Routine ............................................................ 51 Interpolation Filters ................................................................... 31 Device Configuration ................................................................ 51 Datapath Configuration ............................................................ 33 Derived PLL Settings ................................................................. 51 Determining Interpolation Filter Modes ................................ 33 Start-Up Sequence ...................................................................... 51 Coarse Modulation Mixing Sequences .................................... 34 Outline Dimensions ....................................................................... 52 Ordering Guide .......................................................................... 52 REVISION HISTORY 4/11—Revision 0: Initial Version Rev. 0 | Page 2 of 52 AD9146 FUNCTIONAL BLOCK DIAGRAM 16 DATA RECEIVER FIFO fDATA /2 PRE MOD HB1 I OFFSET 10 HB2 Q OFFSET INV SINC IOUT1N DAC_CLK 16 INVSINC_CLK PHASE CORRECTION INTP FACTOR HB2_CLK HB1_CLK MODE 10 1.2G IOUT2P DAC 2 AUX 16-BIT IOUT2N GAIN 2 16 FRAME GAIN 1 DCI IOUT1P DAC 1 AUX 16-BIT 16 D7P/D7N D0P/D0N 1.2G 10 INTERNAL CLOCK TIMING AND CONTROL LOGIC REF AND BIAS REFIO FSADJ DAC CLK_SEL PLL CONTROL SERIAL INPUT/OUTPUT PORT POWER-ON RESET DAC_CLK 0 1 PLL_LOCK CLOCK MULTIPLIER (2× TO 16×) CLK RCVR DACCLKP DACCLKN CLK RCVR REFCLKP REFCLKN 09691-002 CS SYNC IRQ RESET SCLK MULTICHIP SYNCHRONIZATION SDIO PROGRAMMING REGISTERS Figure 2. Rev. 0 | Page 3 of 52 AD9146 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Power Supply Rejection Ratio, AVDD33 Output Compliance Range Output Resistance Gain DAC Monotonicity Settling Time to Within ±0.5 LSB MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES AVDD33 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD18 POWER CONSUMPTION 2× Mode, fDAC = 500 MSPS, IF = 10 MHz PLL Off PLL On AVDD33 CVDD18 DVDD18 Power-Down Mode (Register 0x01 = 0xFC) POWER-UP TIME OPERATING RANGE 1 Min Typ 16 Max ±2.1 ±3.7 −0.001 −3.6 8.66 −0.3 −1.0 0 ±2 19.6 Unit Bits LSB LSB +0.001 +3.6 31.66 +0.3 +1.0 10 Guaranteed 20 % FSR % FSR mA % FSR/V V MΩ ns 0.04 100 30 ppm/°C ppm/°C ppm/°C 1.2 5 V kΩ 3.13 1.71 3.3 1.8 3.47 1.89 V V 1.71 1.8 1.89 V 56 58 343 19 mW mW mA mA mA mW ms °C 780 864 −40 Based on a 10 kΩ external resistor between FSADJ and AVSS. Rev. 0 | Page 4 of 52 8.5 260 +25 +85 AD9146 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input VIN Logic High Input VIN Logic Low CMOS OUTPUT LOGIC LEVEL Output VOUT Logic High Output VOUT Logic Low LVDS RECEIVER INPUTS 1 Input Voltage Range, VIA or VIB Input Differential Threshold, VIDTH Input Differential Hysteresis, VIDTHH to VIDTHL Receiver Differential Input Impedance, RIN LVDS Input Rate DAC CLOCK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage Maximum Clock Rate REFCLK INPUT (REFCLKP, REFCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage REFCLK Frequency PLL Mode SYNC Mode Test Conditions/Comments Max Unit 0.6 V V 0.4 V V 1.4 Applies to data, DCI, and FRAME inputs 825 −100 1575 +100 20 80 120 mV mV mV Ω See Table 5 100 Self-biased input, ac-coupled 500 1.25 2000 mV V MHz 500 1.25 2000 mV V 525 525 MHz MHz 1200 100 1 GHz ≤ fVCO ≤ 2.1 GHz See the Multichip Synchronization section for conditions 15.625 0 40 12.5 12.5 2.09 0.844 2.904 2.38 LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted. DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. Parameter LATENCY (DACCLK CYCLES) 1× Interpolation (With or Without Modulation) 2× Interpolation (With or Without Modulation) 4× Interpolation (With or Without Modulation) Inverse Sinc Typ 1.2 SERIAL PORT INTERFACE Maximum Clock Rate (SCLK) Minimum Pulse Width High (tPWH) Minimum Pulse Width Low (tPWL) Setup Time, SDIO to SCLK (tDS) Hold Time, SDIO to SCLK (tDH) Data Valid, SDIO to SCLK (tDV) Setup Time, CS to SCLK (tDCSB) 1 Min Value Unit 64 135 292 20 Cycles Cycles Cycles Cycles Rev. 0 | Page 5 of 52 MHz ns ns ns ns ns ns AD9146 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 70 MHz fDAC = 800 MSPS, fOUT = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 600 MSPS, fOUT = 50 MHz fDAC = 600 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 60 MHz fDAC = 800 MSPS, fOUT = 100 MHz NOISE SPECTRAL DENSITY (NSD), SINGLE-CARRIER W-CDMA fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 80 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), FOUR-CARRIER fDAC = 491.52 MSPS, fOUT = 15 MHz fDAC = 983.04 MSPS, fOUT = 80 MHz fDAC = 983.04 MSPS, fOUT = 200 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE-CARRIER fDAC = 983.04 MSPS, fOUT = 80 MHz fDAC = 983.04 MSPS, fOUT = 122.88 MHz Min Typ Max Unit 70 65 67 dBc dBc dBc 85 82 83 81 dBc dBc dBc dBc −162 −164 dBm/Hz dBm/Hz 75 77 76 dBc dBc dBc 82 80 dBc dBc Table 5. Maximum Rate (MSPS) with DVDD and CVDD Supply Regulation Interface Mode Byte (8 Bits) Nibble (4 Bits) Interpolation Factor 1× 2× (HB1) 2× (HB2) 4× 1× 2× (HB1) 2× (HB2) 4× fINTERFACE (MSPS) 1.8 V ± 5% 1.9 V ± 5% 1200 1230 1200 1230 1200 1230 1200 1230 1200 1230 1200 1230 1200 1230 1200 1230 fHB1 (MSPS) fHB2 (MSPS) fDAC (MSPS) 1.8 V ± 5% 1.9 V ± 5% 1.8 V ± 5% 1.9 V ± 5% 1.8 V ± 5% 1.9 V ± 5% 300 307.5 300 307.5 600 615 300 307.5 600 615 300 307.5 600 615 1200 1230 150 153.75 150 153.75 300 307.5 150 153.75 300 307.5 150 153.75 300 307.5 600 615 Rev. 0 | Page 6 of 52 AD9146 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter AVDD33 to AVSS, EPAD, CVSS DVDD18, CVDD18 to AVSS, EPAD, CVSS AVSS to EPAD, CVSS EPAD to AVSS, CVSS CVSS to AVSS, EPAD FSADJ, REFIO, IOUT1P, IOUT1N, IOUT2P, IOUT2N to AVSS D[7:0]P, D[7:0]N, FRAMEP, FRAMEN, DCIP, DCIN to EPAD DACCLKP, DACCLKN, REFCLKP, REFCLKN to EPAD RESET, IRQ, CS, SCLK, SDIO to EPAD Junction Temperature Storage Temperature Range The exposed pad (EPAD) of the 48-lead LFCSP must be soldered to the ground plane (AVSS). The EPAD provides an electrical, thermal, and mechanical connection to the board. Rating −0.3 V to +3.6 V −0.3 V to +2.1 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to AVDD33 + 0.3 V −0.3 V to DVDD18 + 0.3 V −0.3 V to CVDD18 + 0.3 V Typical θJA, θJB, and θJC values are specified for a 4-layer board and an 8-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA and θJB. Table 7. Thermal Resistance Package1 48-Lead LFCSP 48-Lead LFCSP 1 −0.3 V to DVDD18 + 0.3 V 125°C −65°C to +150°C PCB 4-layer 8-layer EPAD soldered to ground plane. ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 52 θJA 23.2 16.4 θJB 8.5 3.9 θJC 8.7 7.1 Unit °C/W °C/W AD9146 48 47 46 45 44 43 42 41 40 39 38 37 AVDD33 IOUT1P IOUT1N AVDD33 AVSS FSADJ REFIO AVSS AVDD33 IOUT2N IOUT2P AVDD33 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CVDD18 CVDD18 1 2 AD9146 TOP VIEW (Not to Scale) 36 35 34 33 RESET DVDD18 IRQ CS 32 31 30 29 28 27 26 25 SCLK SDIO TXENABLE DVDD18 D0N D0P D1N D1P NOTES 1. THE EXPOSED PAD (EPAD) MUST BE SOLDERED TO THE GROUND PLANE (AVSS). THE EPAD PROVIDES AN ELECTRICAL, THERMAL, AND MECHANICAL CONNECTION TO THE BOARD. 09691-003 D5P D5N D4P D4N DCIP DCIN FRAMEP FRAMEN D3P D3N D2P D2N 13 14 15 16 17 18 19 20 21 22 23 24 DACCLKP 3 DACCLKN 4 CVSS 5 REFCLKP 6 REFCLKN 7 DVDD18 8 D7P 9 D7N 10 D6P 11 D6N 12 PIN 1 INDICATOR Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Mnemonic CVDD18 CVDD18 DACCLKP DACCLKN CVSS REFCLKP REFCLKN DVDD18 D7P D7N D6P D6N D5P D5N D4P D4N DCIP DCIN FRAMEP FRAMEN D3P D3N D2P D2N D1P D1N D0P Description 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. DAC Clock Input, Positive. DAC Clock Input, Negative. Clock Supply Common. PLL Reference Clock Input, Positive. This pin has a secondary function as a synchronization input. PLL Reference Clock Input, Negative. This pin has a secondary function as a synchronization input. 1.8 V Digital Supply. Supplies power to digital core and digital data ports. Data Bit 7 (MSB), Positive. Data Bit 7 (MSB), Negative. Data Bit 6, Positive. Data Bit 6, Negative. Data Bit 5, Positive. Data Bit 5, Negative. Data Bit 4, Positive. Data Bit 4, Negative. Data Clock Input, Positive. Data Clock Input, Negative. Frame Input, Positive. Frame Input, Negative. Data Bit 3, Positive. Data Bit 3, Negative. Data Bit 2, Positive. Data Bit 2, Negative. Data Bit 1, Positive. Data Bit 1, Negative. Data Bit 0 (LSB), Positive. Rev. 0 | Page 8 of 52 AD9146 Pin No. 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Mnemonic D0N DVDD18 TXENABLE SDIO SCLK CS IRQ DVDD18 RESET AVDD33 IOUT2P IOUT2N AVDD33 AVSS REFIO FSADJ AVSS AVDD33 IOUT1N IOUT1P AVDD33 EPAD Description Data Bit 0 (LSB), Negative. 1.8 V Digital Supply. Supplies power to digital core and digital data ports. Active High Transmit Path Enable (CMOS). A low level on this pin clamps the DAC outputs to midscale. Serial Port Data Input/Output (CMOS). Serial Port Clock Input (CMOS). Serial Port Chip Select, Active Low (CMOS). Interrupt Request. Open-drain, active low output. Pull this pin high external to the device. 1.8 V Digital Supply. Supplies power to digital core and digital data ports. Reset, Active Low (CMOS). 3.3 V Analog Supply. Q DAC Positive Current Output. Q DAC Negative Current Output. 3.3 V Analog Supply. Analog Supply Common. 1.2 V Band Gap Voltage Reference Output. Should be decoupled to AVSS with a 0.1 μF capacitor. Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to AVSS. Analog Supply Common. 3.3 V Analog Supply. I DAC Negative Current Output. I DAC Positive Current Output. 3.3 V Analog Supply. The exposed pad (EPAD) must be soldered to the ground plane (AVSS). The EPAD provides an electrical, thermal, and mechanical connection to the board. Rev. 0 | Page 9 of 52 AD9146 TYPICAL PERFORMANCE CHARACTERISTICS –50 –60 –62 –55 –65 –70 –75 –80 50 100 150 200 250 300 350 400 4×, 200MSPS –74 –76 –80 0 100 150 200 250 300 350 400 Figure 7. Highest Digital Spur vs. fOUT over fDATA and Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA 10 0dBFS –6dBFS –12dBFS –18dBFS 0 –10 –60 –65 –70 –75 –80 –30 –40 –50 –60 0 50 100 150 200 250 300 350 400 fOUT (MHz) –90 Figure 5. Second Harmonic vs. fOUT over Digital Scale, 4× Interpolation, fDATA = 400 MSPS, IFS = 20 mA –50 VBW 10kHz STOP 600MHz SWEEP 7.22s (1001pts) Figure 8. Single-Tone Spectrum, 2× Interpolation, fDATA = 300 MSPS, fOUT = 101 MHz 10 0dBFS –6dBFS –12dBFS –18dBFS –55 START 1MHz #RES BW 10kHz 09691-089 –80 09691-077 –90 –20 –70 –85 0 –10 –60 AMPLITUDE (dBm) THIRD HARMONIC (dBc) 50 fOUT (MHz) AMPLITUDE (dBm) SECOND HARMONIC (dBc) –72 –78 Figure 4. Harmonics vs. fOUT over fDATA and Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA –55 2×, 300MSPS –70 300MSPS, SECOND HARMONIC 200MSPS, SECOND HARMONIC 300MSPS, THIRD HARMONIC 200MSPS, THIRD HARMONIC fOUT (MHz) –50 –68 09691-079 0 –66 09691-076 2×, 4×, 2×, 4×, –85 –90 –64 HIGHEST DIGITAL SPUR (dBc) HARMONICS (dBc) –60 –65 –70 –75 –80 –20 –30 –40 –50 –60 –70 –85 50 100 150 200 fOUT (MHz) 250 300 350 400 Figure 6. Third Harmonic vs. fOUT over Digital Scale, 4× Interpolation, fDATA = 400 MSPS, IFS = 20 mA Rev. 0 | Page 10 of 52 –90 START 1MHz #RES BW 10kHz VBW 10kHz STOP 800MHz SWEEP 9.63s (1001pts) Figure 9. Single-Tone Spectrum, 4× Interpolation, fDATA = 200 MSPS, fOUT = 151 MHz 09691-090 0 09691-078 –90 –80 AD9146 –45 –55 –50 –60 –55 PLL ON –65 –60 4×, 200MSPS 2×, 300MSPS IMD (dBc) IMD (dBc) –70 –75 –80 –65 PLL OFF –70 –75 –80 –85 –85 –90 100 150 200 250 300 350 400 fOUT (MHz) –95 –140 –70 –145 –75 –80 –165 150 200 250 fOUT (MHz) 300 350 400 09691-081 –90 100 –145 NSD (dBm/Hz) –65 –70 –75 –85 –165 150 200 250 100 150 200 250 300 350 400 –155 –160 100 50 –150 –80 50 400 SINGLE-TONE: 2×, 200MSPS SINGLE-TONE: 4×, 200MSPS W-CDMA: 2×, 200MSPS W-CDMA: 4×, 200MSPS –135 –140 0 0 –130 –60 –90 350 Figure 14. NSD vs. fOUT over Interpolation, Single-Tone and W-CDMA Signals, fDATA = 200 MSPS, Digital Scale = 0 dBFS, IFS = 20 mA, PLL Off 300 350 400 fOUT (MHz) Figure 12. IMD vs. fOUT over Full-Scale Current, 4× Interpolation, fDATA = 400 MSPS, Digital Scale = 0 dBFS –170 09691-082 IMD (dBc) –170 IFS = 10mA IFS = 20mA IFS = 30mA –55 300 fOUT (MHz) Figure 11. IMD vs. fOUT over Digital Scale, 4× Interpolation, fDATA = 400 MSPS, IFS = 20 mA –50 250 –155 –160 50 200 –150 –85 0 150 SINGLE-TONE: 2×, 200MSPS SINGLE-TONE: 4×, 200MSPS W-CDMA: 2×, 200MSPS W-CDMA: 4×, 200MSPS –135 NSD (dBm/Hz) IMD (dBc) –130 –65 –95 100 Figure 13. IMD vs. fOUT, 4× Interpolation, fDATA = 200 MSPS, Digital Scale = 0 dBFS, IFS = 20 mA, PLL On and PLL Off 0dBFS –6dBFS –12dBFS –18dBFS –60 50 fOUT (MHz) Figure 10. IMD vs. fOUT over fDATA and Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA –55 0 09691-084 50 0 50 100 150 200 fOUT (MHz) 250 300 350 400 09691-085 0 09691-083 –90 09691-080 –95 Figure 15. NSD vs. fOUT over Interpolation, Single-Tone and W-CDMA Signals, fDATA = 200 MSPS, Digital Scale = 0 dBFS, IFS = 20 mA, PLL On Rev. 0 | Page 11 of 52 AD9146 –64 –66 –66 –68 –68 ACLR (dBc) –64 –70 –72 –76 –76 –78 –78 40 80 120 160 200 240 280 320 360 400 440 480 –60 –80 09691-093 0 Figure 16. Four-Carrier W-CDMA ACLR vs. fOUT over Digital Scale, Adjacent Channel, 4× Interpolation, fDATA = 245.76 MSPS, PLL Off –60 –66 –66 –68 –68 ACLR (dBc) –64 –72 –72 –74 –76 –76 –78 –78 80 120 160 200 240 280 320 360 400 440 480 fOUT (MHz) Figure 17. Four-Carrier W-CDMA ACLR vs. fOUT over Digital Scale, First Alternate Channel, 4× Interpolation, fDATA = 245.76 MSPS, PLL Off –60 –80 09691-094 40 –66 –68 –70 –72 –74 –76 40 80 120 160 200 240 280 320 360 400 440 480 fOUT (MHz) 09691-086 –78 0 40 80 120 160 200 240 280 320 360 400 440 480 Figure 20. Four-Carrier W-CDMA ACLR vs. fOUT over Interpolation, First Alternate Channel, fDATA = 245.76 MSPS, PLL Off and PLL On –64 –80 0 fOUT (MHz) 0dBFS –3dBFS –6dBFS –62 120 160 200 240 280 320 360 400 440 480 –70 –74 0 80 2×, PLL OFF 2×, PLL ON 4×, PLL OFF 4×, PLL ON –62 –70 40 Figure 19. Four-Carrier W-CDMA ACLR vs. fOUT over Interpolation, Adjacent Channel, fDATA = 245.76 MSPS, PLL Off and PLL On –64 –80 0 fOUT (MHz) 0dBFS –3dBFS –6dBFS –62 ACLR (dBc) –72 –74 fOUT (MHz) ACLR (dBc) –70 –74 –80 2×, PLL OFF 2×, PLL ON 4×, PLL OFF 4×, PLL ON –62 09691-095 –62 ACLR (dBc) –60 0dBFS –3dBFS –6dBFS 09691-096 –60 Figure 18. Four-Carrier W-CDMA ACLR vs. fOUT over Digital Scale, Second Alternate Channel, 4× Interpolation, fDATA = 245.76 MSPS, PLL Off Rev. 0 | Page 12 of 52 AD9146 –60 2×, 2×, 4×, 4×, –62 –64 –60 PLL OFF PLL ON PLL OFF PLL ON –62 –64 –66 –68 –68 ACLR (dBc) ACLR (dBc) –66 –70 –72 –70 4 CARRIER –72 –74 1 CARRIER –76 –74 –78 –76 –80 –78 40 80 120 160 200 240 280 320 360 400 440 480 fOUT (MHz) –84 Figure 21. Four-Carrier W-CDMA ACLR vs. fOUT over Interpolation, Second Alternate Channel, fDATA = 245.76 MSPS, PLL Off and PLL On 80 120 160 200 240 280 320 360 400 440 480 Figure 23. W-CDMA ACLR vs. fOUT over Number of Carriers, Adjacent Channel, 4× Interpolation, fDATA = 245.76 MSPS, Digital Scale = −6 dBFS, PLL Off –25 –35 –22.2dBm –22.4dBm –22.7dBm –35 –22.7dBm –45 –55 –55 AMPLITUDE (dBm) –45 –65 –75 –85 –95 TOTAL CARRIER POWER –16.469dBm/15.36MHz CARRIER POWER OFFSET INTEG FILTER FREQ BW 1 –22.205dBm/3.84MHz ON 5MHz 10MHz 15MHz ACP-IBW LOWER dBc dBm –125 CENTER 200MHz #RES BW 30kHz VBW 3kHz TOTAL CARRIER POWER –16.873dBm/15.36MHz UPPER dBc dBm FILTER 3.84MHz –76.37 –98.78 –77.11 –99.52 ON 3.84MHz –77.45 –99.85 –77.49 –99.89 ON 3.84MHz –77.59 –99.99 –77.51 –99.91 ON –22.8dBm –95 –115 SPAN 49.68MHz SWEEP 1.371s –22.6dBm –85 –105 VBW 3kHz –22.9dBm –75 –115 CENTER 122MHz #RES BW 30kHz –23.3dBm –65 –105 09691-092 AMPLITUDE (dBm) 40 fOUT (MHz) –25 –125 0 CARRIER POWER OFFSET INTEG FILTER FREQ BW 1 –23.284dBm/3.84MHz ON 5MHz 10MHz 15MHz ACP-IBW LOWER dBc dBm SPAN 49.68MHz SWEEP 1.371s UPPER dBc dBm FILTER 3.84MHz –76.55 –99.49 –75.66 –98.60 ON 3.84MHz –76.73 –99.67 –75.68 –98.62 ON 3.84MHz –76.64 –99.59 –75.88 –98.83 ON Figure 24. Four-Carrier W-CDMA Performance, 4× Interpolation, fDATA = 245.76 MSPS, Digital Scale = −6 dBFS, fOUT = 200 MHz Figure 22. Four-Carrier W-CDMA Performance, 4× Interpolation, fDATA = 245.76 MSPS, Digital Scale = −6 dBFS, fOUT = 122 MHz Rev. 0 | Page 13 of 52 09691-091 0 09691-088 –82 09691-087 –80 AD9146 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the DAC output. Offset Error Offset error is the deviation of the output current from the ideal of 0 mA. For IOUT1P, 0 mA output is expected when all inputs are set to 0. For IOUT1N, 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference voltage drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in decibels relative to the carrier (dBc) between the measured power within a channel and that of its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. 0 | Page 14 of 52 AD9146 THEORY OF OPERATION High performance, small size, and low power consumption make the AD9146 a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband (SSB) transmitters. The AD9146 offers features that allow simplified synchronization with incoming data and between multiple devices. Auxiliary DACs are also provided on chip. The auxiliary DACs can be used for output dc offset compensation (for LO compensation in SSB transmitters) and for gain matching (for image rejection optimization in SSB transmitters). SERIAL PORT OPERATION The serial port is a flexible, synchronous serial communications port that allows easy interfacing to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9146. Single-byte or multiple-byte transfers are supported, as well as MSB first or LSB first transfer formats. SDIO 31 CS 33 SPI PORT The instruction byte contains the information shown in Table 9. Table 9. Serial Port Instruction Byte I7 (MSB) R/W I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 I0 (LSB) A0 R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation, and Logic 0 indicates a write operation. A6 to A0, Bit 6 to Bit 0 of the instruction byte, determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, A6 is the starting byte address. The remaining register addresses are generated by the device based on the LSB_FIRST bit (Register 0x00, Bit 6). SERIAL PORT PIN DESCRIPTIONS Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. Chip Select (CS) 09691-032 SCLK 32 DATA FORMAT Figure 25. Serial Port Interface Pins A communication cycle with the AD9146 has two phases. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first eight SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cycle—Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, along with the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the device. A logic high on the CS pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. From this state, the next eight rising SCLK edges represent the instruction bits of the current I/O operation. An active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. When the CS pin is high, the SDIO pin goes to a high impedance state. During the communication cycle, the CS pin should stay low. Serial Data I/O (SDIO) The SDIO pin is a bidirectional pin that functions as an input in write mode and as an output in read mode. Data is written into the device on this pin and read from the device on this pin. The configuration of the SDIO pin is controlled by Register 0x00, Bit 7. To enable readback of the register data, this bit must be set to 1. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one or more data bytes. Registers change immediately upon writing to the last bit of each transfer byte. Rev. 0 | Page 15 of 52 AD9146 INSTRUCTION CYCLE SERIAL PORT OPTIONS When LSB_FIRST = 1 (LSB first), the instruction and data bits must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte. Subsequent data bytes should follow from low address to high address. In LSB first mode, the serial port internal byte address generator increments for each data byte of the multibyte communication cycle. If the MSB first mode is active, the serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations. If the LSB first mode is active, the serial port controller data address increments from the data address written toward 0x7F for multibyte I/O operations. SDIO A0 A1 A2 A3 A4 A5 A6 R/W D00 D10 D20 D4N D5N D6N D7 N Figure 27. Serial Port Interface Timing, LSB First tDCSB tSCLK CS tPWH tPWL SCLK tDS SDIO tDH INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 28. Timing Diagram for Serial Port Register Write CS SCLK tDV SDIO DATA BIT n DATA BIT n – 1 Figure 29. Timing Diagram for Serial Port Register Read INSTRUCTION CYCLE DATA TRANSFER CYCLE CS R/W A6 A5 A4 A3 A2 A1 A0 D7N D6N D5N D30 D2 0 D1 0 D00 09691-033 SCLK SDIO 09691-034 SCLK 09691-035 When LSB_FIRST = 0 (MSB first), the instruction and data bits must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow from high address to low address. In MSB first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. CS Figure 26. Serial Port Interface Timing, MSB First Rev. 0 | Page 16 of 52 09691-036 The serial port can support both MSB first and LSB first data formats. This functionality is controlled by the LSB_FIRST bit (Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0). DATA TRANSFER CYCLE AD9146 DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS Table 10. Device Configuration Register Map Addr (Hex) 0x00 0x01 Register Name Comm Power control Extended delay length Bit 5 Reset Power down data receiver Enable extended delay Binary data format Enable PLL lock lost Q data first MSB swap Enable PLL locked Enable sync signal lost Interrupt enable 0 0 0 0x06 Event flag PLL lock lost PLL locked Sync signal lost 0x07 Event flag 0x08 Clock receiver control 0x0A PLL control 0x0C PLL control 0x0D PLL control 0x0E 0x0F 0x10 PLL status PLL status Sync control 0x11 0x12 Sync control Sync status 0x13 0x15 Sync status Data receiver status 0x16 DCI delay 0x17 0x18 FIFO control FIFO status 0x19 FIFO status 0x02 Tx enable control 0x03 Data format 0x04 Interrupt enable 0x05 Bit 7 SDIO Power down I DAC Bit 6 LSB_FIRST Power down Q DAC DACCLK REFCLK duty duty correction correction PLL PLL manual enable enable PLL Loop Bandwidth[1:0] N2[1:0] Bit 4 Bit 3 Bit 2 Power down aux ADC Power down aux DACs and reference Power down PLL Power down clocks Power down voltage reference Data/FIFO rate toggle Sync lost Sync locked FIFO Warning 1 FIFO Warning 2 Bit 0 Default 0x00 0x10 Power down FIFO Power down filters 0x00 Data Bus Width[1:0] DACCLK crosscorrection Enable sync signal locked Enable AED compare pass Sync signal locked AED compare pass REFCLK crosscorrection Enable AED compare fail AED compare fail 1 Enable SED compare fail SED compare fail 1 Enable FIFO Warning 2 0x00 0 0 0x00 FIFO Warning 1 FIFO Warning 2 N/A N/A 1 1 N0[1:0] 0xD1 N1[1:0] 0xD9 VCO Control Voltage[3:0] VCO Band Readback[5:0] Sync Averaging[2:0] Rising edge sync Sync Phase Request[5:0] N/A N/A 0x48 Sync Phase Readback[7:0] (6.2 format) LVDS LVDS LVDS DCI LVDS DCI LVDS data LVDS data FRAME FRAME level high level low level high level low level high level low DCI Delay[1:0] Delay bypass FIFO Phase Offset[2:0] FIFO soft FIFO soft align ack align request FIFO Level[7:0] Rev. 0 | Page 17 of 52 0x3F 0x40 PLL Charge Pump Current[4:0] PLL crosscontrol enable 0x00 Enable FIFO Warning 1 Manual VCO Band[5:0] PLL locked Sync enable Power down DACs Bit 1 0x00 N/A N/A N/A 0x00 0x04 N/A N/A AD9146 Addr (Hex) 0x1B Register Name Datapath control 0x1C HB1 control 0x1D HB2 control 0x1E 0x1F 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 Datapath config Chip ID I phase adj LSB I phase adj MSB Q phase adj LSB Q phase adj MSB I DAC offset LSB I DAC offset MSB Q DAC offset LSB Q DAC offset MSB I DAC FS adjust I DAC control 0x42 0x43 I aux DAC data I aux DAC control 0x44 0x45 Q DAC FS adjust Q DAC control 0x46 0x47 Q aux DAC data Q aux DAC control 0x48 Die temp range control Die temp LSB Die temp MSB SED control 0x49 0x4A 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x7F Compare I0 LSBs Compare I0 MSBs Compare Q0 LSBs Compare Q0 MSBs Compare I1 LSBs Compare I1 MSBs Compare Q1 LSBs Compare Q1 MSBs SED I LSBs SED I MSBs SED Q LSBs SED Q MSBs Revision Bit 7 Bypass premod Bit 6 Bypass sinc−1 Bit 5 1 Bit 4 Bit 3 Bit 2 Bit 1 Bypass Select phase sideband comp and dc offset HB1[1:0] HB2[5:0] This register must be changed from the default value for proper operation. Chip ID[7:0] I Phase Adj[7:0] Bit 0 Send I data to Q data Default 0xE4 Bypass HB1 Bypass HB2 1 0x00 I DAC FS Adj[9:8] 0x00 0x08 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xF9 0x01 I Aux DAC[9:8] 0x00 0x00 Q DAC FS Adj[9:8] 0xF9 0x01 Q Aux DAC[9:8] 0x00 0x00 I Phase Adj[9:8] Q Phase Adj[7:0] Q Phase Adj[9:8] I DAC Offset[7:0] I DAC Offset[15:8] Q DAC Offset[7:0] Q DAC Offset[15:8] I DAC FS Adj[7:0] I DAC sleep I Aux DAC[7:0] I aux DAC sign I aux DAC current direction I aux DAC sleep Q DAC FS Adj[7:0] Q DAC sleep Q Aux DAC[7:0] Q aux DAC sign SED compare enable Q aux DAC current direction Q aux DAC sleep FS Current[2:0] Sample error detected Reference Current[2:0] Die Temp[7:0] Die Temp[15:8] Autoclear enable 0x00 Compare fail Capacitor value Compare pass 0x02 N/A N/A 0x00 Compare Value I0LSB Compare Value I0MSB Compare Value Q0LSB Compare Value Q0MSB 0xB6 0x7A 0x45 0xEA Compare Value I1LSB Compare Value I1MSB Compare Value Q1LSB Compare Value Q1MSB Errors Detected INLSB Errors Detected INMSB Errors Detected QNLSB Errors Detected QNMSB Revision[3:0] 0x16 0x1A 0xC6 0xAA 0x00 0x00 0x00 0x00 N/A Rev. 0 | Page 18 of 52 AD9146 Table 11. Device Configuration Register Descriptions Register Name Comm Power Control Address (Hex) 0x00 0x01 Bits 7 Name SDIO 6 LSB_FIRST 5 Reset 7 6 5 2 6 Power down I DAC Power down Q DAC Power down data receiver Power down auxiliary ADC Power down auxiliary DACs and reference Power down clocks Extended delay length 5 Enable extended delay 4 Power down voltage reference 3 Power down PLL 2 Power down DACs 1 Power down FIFO 0 Power down filters 4 3 Tx Enable Control 0x02 Description SDIO pin operation. To enable data readback, set this bit to 1. 0 = SDIO operates as an input only. 1 = SDIO operates as a bidirectional input/output. Serial port communication, LSB or MSB first. 0 = MSB first. 1 = LSB first. The device is placed in reset when this bit is written high and remains in reset until the bit is written low. 1 = power down I DAC. 1 = power down Q DAC. 1 = power down the input data receiver. Default 0 1 = power down the auxiliary ADC for temperature sensor. 1 1 = power down the auxiliary DACs and the voltage reference. 0 1 = power down the clocks. Time delay from when the TXENABLE pin is brought high to when the DAC begins transmitting data. See the Tx Enable section for more information. 0 = delay the outputs by 12 to 13 DAC/64 clock edges. 1 = delay the outputs by 19 to 20 DAC/64 clock edges. The transmit delay, regardless of whether the extended delay option is selected, has an inherent fixed delay of 10 DAC clock cycles. When the extended delay is disabled, there is a minimum delay time in the outputs of 1 to 2 DAC/64 clock edges from when the TXENABLE pin is brought high. 0 = disable the extended delay option. Delays the outputs by 1 to 2 DAC/64 clock edges. 1 = enable the extended delay option. Delays the outputs based on the setting of Bit 6. 0 = no power-down of the internal voltage reference. 1 = power down the internal voltage reference when the TXENABLE pin is held low. 0 = no power-down of the on-chip PLL. 1 = power down the on-chip PLL when the TXENABLE pin is held low. 0 = no power-down of the DAC cores. 1 = power down the DAC cores when the TXENABLE pin is held low. 0 = no power-down of the FIFO. 1 = power down the FIFO when the TXENABLE pin is held low. 0 = no power-down of the interpolation filters. 1 = power down the interpolation filters when the TXENABLE pin is held low. 0 0 Rev. 0 | Page 19 of 52 0 0 0 0 0 0 0 0 0 0 0 AD9146 Register Name Data Format Address (Hex) 0x03 Bits 7 6 5 [1:0] Interrupt Enable 0x04 0x05 Event Flag 0x06 7 6 5 4 1 0 [7:5] 4 3 2 [1:0] 7 6 5 4 1 0 0x07 4 3 2 Name Binary data format Description 0 = input data is in twos complement format. 1 = input data is in binary format. Q data first Indicates I/Q data pairing on data input. 0 = I data sent to data receiver first. 1 = Q data sent to data receiver first. MSB swap Swaps the bit order of the data input port. 0 = order of the data bits corresponds to the pin descriptions. 1 = bit designations are swapped; most significant bits become the least significant bits. Data Bus Width[1:0] Data receiver interface mode. See the LVDS Input Data Ports section for information about the operation of the different interface modes. 00 = byte mode; 8-bit interface bus width. 01 = byte mode; 8-bit interface bus width. 10 = nibble mode; 4-bit interface bus width. 11 = invalid. Enable PLL lock lost 1 = enable interrupt for PLL lock lost. Enable PLL locked 1 = enable interrupt for PLL locked. Enable sync signal lost 1 = enable interrupt for sync signal lost. Enable sync signal locked 1 = enable interrupt for sync signal locked. Enable FIFO Warning 1 1 = enable interrupt for FIFO Warning 1. Enable FIFO Warning 2 1 = enable interrupt for FIFO Warning 2. Set to 0 Set these bits to 0. Enable AED compare pass 1 = enable interrupt for AED comparison pass. Enable AED compare fail 1 = enable interrupt for AED comparison fail. Enable SED compare fail 1 = enable interrupt for SED comparison fail. Set to 0 Set these bits to 0. PLL lock lost 1 = indicates that the PLL, which had been previously locked, has unlocked from the reference signal. This is a latched signal. PLL locked 1 = indicates that the PLL has locked to the reference clock input. Sync signal lost 1 = indicates that the sync logic, which had been previously locked, has lost alignment. This is a latched signal. Sync signal locked 1 = indicates that the sync logic has achieved sync alignment. This is indicated when no phase changes were requested for at least a few full averaging cycles. FIFO Warning 1 1 = indicates that the difference between the FIFO read and write pointers is 1. FIFO Warning 2 1 = indicates that the difference between the FIFO read and write pointers is 2. Note that all event flags are cleared by writing the respective bit high. AED compare pass 1 = indicates that the SED logic detected a valid input data pattern compared against the preprogrammed expected values. This is a latched signal. AED compare fail 1 = indicates that the SED logic detected an invalid input data pattern compared against the preprogrammed expected values. This latched signal is automatically cleared when eight valid I/Q data pairs are received. SED compare fail 1 = indicates that the SED logic detected an invalid input data pattern compared against the preprogrammed expected values. This is a latched signal. Note that all event flags are cleared by writing the respective bit high. Rev. 0 | Page 20 of 52 Default 0 0 0 00 0 0 0 0 0 0 000 0 0 0 00 N/A N/A N/A N/A N/A N/A N/A N/A N/A AD9146 Register Name Clock Receiver Control PLL Control Address (Hex) 0x08 Bits 7 6 5 Name DACCLK duty correction REFCLK duty correction DACCLK cross-correction 4 REFCLK cross-correction 7 PLL enable 6 PLL manual enable [5:0] [7:6] Manual VCO Band[5:0] PLL Loop Bandwidth[1:0] [4:0] PLL Charge Pump Current[4:0] [7:6] N2[1:0] 4 [3:2] PLL cross-control enable N0[1:0] [1:0] N1[1:0] 0x0E 7 PLL locked 0x0F [3:0] [5:0] VCO Control Voltage[3:0] VCO Band Readback[5:0] 0x0A 0x0C 0x0D PLL Status Description 1 = enable duty cycle correction on the DACCLK input. 1 = enable duty cycle correction on the REFCLK input. 1 = enable differential crossing correction on the DACCLK input. 1 = enable differential crossing correction on the REFCLK input. 1 = enable the PLL clock multiplier. The REFCLK input is used as the PLL reference clock signal. 1 = enable manual selection of the VCO band. The correct VCO band must be determined by the user and written to Bits[5:0]. Selects the VCO band to be used. Selects the PLL loop filter bandwidth. 00 = widest bandwidth. … 11 = narrowest bandwidth. Sets the nominal PLL charge pump current. 00000 = lowest current setting. … 11111 = highest current setting. PLL control clock divider. This divider determines the ratio of the DACCLK frequency to the PLL controller clock frequency. fPC_CLK must always be less than 75 MHz. 00 = fDACCLK/fPC_CLK = 2. 01 = fDACCLK/fPC_CLK = 4. 10 = fDACCLK/fPC_CLK = 8. 11 = fDACCLK/fPC_CLK = 16. 1 = enable PLL cross-point controller. PLL VCO divider. This divider determines the ratio of the VCO frequency to the DACCLK frequency. 00 = fVCO/fDACCLK = 1. 01 = fVCO/fDACCLK = 2. 10 = fVCO/fDACCLK = 4. 11 = fVCO/fDACCLK = 4. PLL loop divider. This divider determines the ratio of the DACCLK frequency to the REFCLK frequency. 00 = fDACCLK/fREFCLK = 2. 01 = fDACCLK/fREFCLK = 4. 10 = fDACCLK/fREFCLK = 8. 11 = fDACCLK/fREFCLK = 16. 1 = the PLL-generated clock is tracking the REFCLK input signal. VCO control voltage readback. See Table 22. Indicates the VCO band currently selected. Rev. 0 | Page 21 of 52 Default 0 0 1 1 0 1 000000 11 10001 11 1 10 01 N/A N/A N/A AD9146 Register Name Sync Control Sync Status Address (Hex) 0x10 Bits 7 6 Name Sync enable Data/FIFO rate toggle 3 Rising edge sync [2:0] Sync Averaging[2:0] 0x11 [5:0] Sync Phase Request[5:0] 0x12 7 6 [7:0] Sync lost Sync locked Sync Phase Readback[7:0] 5 4 LVDS FRAME level high LVDS FRAME level low 3 2 1 0 2 LVDS DCI level high LVDS DCI level low LVDS data level high LVDS data level low Delay bypass [1:0] DCI Delay[1:0] 0x13 Data Receiver Status DCI Delay 0x15 0x16 Description 1 = enable the synchronization logic. 0 = operate the synchronization at the FIFO reset rate. 1 = operate the synchronization at the data rate. 0 = sync is initiated on the falling edge of the sync input. 1 = sync is initiated on the rising edge of the sync input. Sets the number of input samples that are averaged in determining the sync phase. 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. 110 = 64. 111 = 128. This register sets the requested clock phase offset after sync. The offset unit is in DACCLK cycles. This register enables repositioning of the DAC output with respect to the sync input. The offset can also be used to skew the DAC outputs between the synchronized DACs. 000000 = 0 DACCLK cycles. 000001 = 1 DACCLK cycle. … 111111 = 63 DACCLK cycles. 1 = synchronization was attained but has been lost. 1 = synchronization has been attained. Indicates the averaged sync phase offset (6.2 format). If this value differs from the Sync Phase Request[5:0] value in Register 0x11, a sync timing error has occurred. For more information, see the Sync Status Bits section. 00000000 = 0.0. 00000001 = 0.25. … 11111110 = 63.50. 11111111 = 63.75. One or both LVDS FRAME input signals have exceeded 1.7 V. One or both LVDS FRAME input signals have crossed below 0.7 V. One or both LVDS DCI input signals have exceeded 1.7 V. One or both LVDS DCI input signals have crossed below 0.7 V. One or more LVDS Dx input signals have exceeded 1.7 V. One or more LVDS Dx input signals have crossed below 0.7 V. 0 = enable the on-chip DCI delay feature. Set the delay using Bits[1:0]. 1 = bypass the on-chip DCI delay feature. These bits control the delay applied to the DCI signal. The DCI delay affects the sampling interval of the DCI with respect to the Dx inputs. See Table 14. 00 = 105 ps delay of DCI signal. 01 = 375 ps delay of DCI signal. 10 = 615 ps delay of DCI signal. 11 = 720 ps delay of DCI signal. Rev. 0 | Page 22 of 52 Default 0 1 1 000 000000 N/A N/A N/A N/A N/A N/A N/A N/A N/A 0 00 AD9146 Register Name FIFO Control Address (Hex) 0x17 FIFO Status 0x18 Bits [2:0] Name FIFO Phase Offset[2:0] 7 6 2 FIFO Warning 1 FIFO Warning 2 FIFO soft align acknowledge FIFO soft align request 1 Datapath Control 0x19 0x1B [7:0] 7 6 5 2 1 FIFO Level[7:0] Bypass premod Bypass sinc−1 Set to 1 Bypass phase compensation and dc offset Select sideband 0 Send I data to Q data HB1 Control 0x1C [2:1] HB1[1:0] HB2 Control 0x1D 0 [6:1] Bypass HB1 HB2[5:0] 0 Bypass HB2 Description FIFO write pointer phase offset following FIFO reset. This is the difference between the read pointer and the write pointer values upon FIFO reset. The optimal value is nominally 4 (100). 000 = 0. 001 = 1. … 111 = 7. 1 = FIFO read and write pointers are within ±1. 1 = FIFO read and write pointers are within ±2. 1 = FIFO read and write pointers are aligned after a serial port initiated FIFO reset. 1 = request FIFO read and write pointer alignment via the serial port. Thermometer encoded measure of the FIFO level. 1 = bypass the fS/2 premodulator. 1 = bypass the inverse sinc filter. Set this bit to 1 for proper operation. 1 = bypass phase compensation and dc offset. Default 100 0 = the modulator outputs the high-side image. 1 = the modulator outputs the low-side image. The image is spectrally inverted compared to the input data. 1 = ignore Q data from the interface and disable the clocks to the Q datapath. Send I data to both the I and Q DACs. Modulation mode for I Side Half-Band Filter 1. 00 = input signal not modulated; filter pass band is from −0.4 to +0.4 of fIN1. 01 = input signal not modulated; filter pass band is from 0.1 to 0.9 of fIN1. 10 = input signal modulated by fIN1; filter pass band is from 0.6 to 1.4 of fIN1. 11 = input signal modulated by fIN1; filter pass band is from 1.1 to 1.9 of fIN1. 1 = bypass the first-stage interpolation filter. Modulation mode for I Side Half-Band Filter 2. 000000 = input signal not modulated; filter pass band is from −0.25 to +0.25 of fIN2. 001001 = input signal not modulated; filter pass band is from 0.0 to 0.5 of fIN2. 010010 = input signal not modulated; filter pass band is from 0.25 to 0.75 of fIN2. 011011 = input signal not modulated; filter pass band is from 0.5 to 1.0 of fIN2. 100100 = input signal modulated by fIN2; filter pass band is from 0.75 to 1.25 of fIN2. 101101 = input signal modulated by fIN2; filter pass band is from 1.0 to 1.5 of fIN2. 110110 = input signal modulated by fIN2; filter pass band is from 1.25 to 1.75 of fIN2. 111111 = input signal modulated by fIN2; filter pass band is from 1.5 to 2.0 of fIN2. 1 = bypass the second-stage interpolation filter. 0 Rev. 0 | Page 23 of 52 N/A N/A N/A 0 N/A 1 1 1 1 0 00 0 000000 0 AD9146 Register Name Datapath Config Chip ID I Phase Adj LSB I Phase Adj MSB Address (Hex) 0x1E Bits 0 Name Set to 1 0x1F 0x38 [7:0] [7:0] Chip ID[7:0] I Phase Adj[7:0] 0x39 [1:0] I Phase Adj[9:8] Q Phase Adj LSB Q Phase Adj MSB 0x3A [7:0] Q Phase Adj[7:0] 0x3B [1:0] Q Phase Adj[9:8] I DAC Offset LSB I DAC Offset MSB Q DAC Offset LSB Q DAC Offset MSB I DAC FS Adjust I DAC Control 0x3C [7:0] I DAC Offset[7:0] 0x3D [7:0] I DAC Offset[15:8] 0x3E [7:0] Q DAC Offset[7:0] 0x3F [7:0] Q DAC Offset[15:8] 0x40 [7:0] I DAC FS Adj[7:0] 0x41 7 [1:0] I DAC sleep I DAC FS Adj[9:8] I Aux DAC Data I Aux DAC Control 0x42 [7:0] I Aux DAC[7:0] 0x43 7 I aux DAC sign 6 I aux DAC current direction 5 [1:0] I aux DAC sleep I Aux DAC[9:8] [7:0] Q DAC FS Adj[7:0] Q DAC FS Adjust 0x44 Description Set this bit to 1 for proper operation. (The default value must be changed from 0 to 1.) This register identifies the device as an AD9146. See Register 0x39. Default 0 I Phase Adj[9:0] is used to insert a phase offset between the I and Q datapaths. This offset can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for more information. See Register 0x3B. 00 Q Phase Adj[9:0] is used to insert a phase offset between the I and Q datapaths. This offset can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for more information. See Register 0x3D. 00 I DAC Offset[15:0] is a value that is added directly to the samples written to the I DAC. See Register 0x3F. 00000000 Q DAC Offset[15:0] is a value that is added directly to the samples written to the Q DAC. See Register 0x41, Bits[1:0]. 00000000 1 = puts the I DAC into sleep mode (fast wake-up mode). I DAC FS Adj[9:0] sets the full-scale current of the I DAC. The full-scale current can be adjusted from 8.64 mA to 31.68 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. … 0x200 = 20.16 mA. … 0x3FF = 31.68 mA. See Register 0x43, Bits[1:0]. 0 01 0 = the I auxiliary DAC sign is positive, and the current is directed to the IOUT1P pin (Pin 47). 1 = the I auxiliary DAC sign is negative, and the current is directed to the IOUT1N pin (Pin 46). 0 = the I auxiliary DAC sources current. 1 = the I auxiliary DAC sinks current. 1 = puts the I auxiliary DAC into sleep mode. I Aux DAC[9:0] sets the magnitude of the auxiliary DAC current. The range is 0 mA to 2 mA, and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. … 0x3FF = 2.046 mA. See Register 0x45, Bits[1:0]. 0 Rev. 0 | Page 24 of 52 00001000 00000000 00000000 00000000 00000000 11111001 00000000 0 0 00 11111001 AD9146 Register Name Q DAC Control Address (Hex) 0x45 Q Aux DAC Data Q Aux DAC Control Die Temp Range Control Die Temp LSB Die Temp MSB SED Control Bits 7 [1:0] Name Q DAC sleep Q DAC FS Adj[9:8] 0x46 [7:0] Q Aux DAC[7:0] 0x47 7 Q aux DAC sign 6 Q aux DAC current direction 5 [1:0] Q aux DAC sleep Q Aux DAC[9:8] [6:4] FS Current[2:0] [3:1] Reference Current[2:0] 0 Capacitor value 0x49 [7:0] Die Temp[7:0] 0x4A [7:0] Die Temp[15:8] 0x67 7 SED compare enable 5 Sample error detected 3 Autoclear enable 1 Compare fail 0 Compare pass 0x48 Description 1 = puts the Q DAC into sleep mode (fast wake-up mode). Q DAC FS Adj[9:0] sets the full-scale current of the Q DAC. The full-scale current can be adjusted from 8.64 mA to 31.68 mA in step sizes of approximately 22.5 μA. 0x000 = 8.64 mA. … 0x200 = 20.16 mA. … 0x3FF = 31.68 mA. See Register 0x47, Bits[1:0]. Default 0 01 0 = the Q auxiliary DAC sign is positive, and the current is directed to the IOUT2P pin (Pin 38). 1 = the Q auxiliary DAC sign is negative, and the current is directed to the IOUT2N pin (Pin 39). 0 = the Q auxiliary DAC sources current. 1 = the Q auxiliary DAC sinks current. 1 = puts the Q auxiliary DAC into sleep mode. Q Aux DAC[9:0] sets the magnitude of the auxiliary DAC current. The range is 0 mA to 2 mA, and the step size is 2 μA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. … 0x3FF = 2.046 mA. Auxiliary ADC full-scale current. 000 = lowest current. … 111 = highest current. Auxiliary ADC reference current. 000 = lowest current. … 111 = highest current. Auxiliary ADC internal capacitor value. 0 = 5 pF. 1 = 10 pF. See Register 0x4A. 0 Die Temp[15:0] indicates the approximate die temperature. For more information, see the Temperature Sensor section. 1 = enable the SED circuitry. None of the flags in this register or the values in Register 0x70 through Register 0x73 are significant if the SED is not enabled. 1 = indicates an error was detected. The bit remains set until cleared. Any write to this register clears this bit to 0. 1 = enable autoclear mode. This activates Bit 1 and Bit 0 of this register and causes Register 0x70 through Register 0x73 to be autocleared when eight consecutive sample data sets are received error free. 1 = indicates an error was detected. This bit remains set until it is autocleared by the reception of eight consecutive errorfree comparisons or is cleared by a write to this register. 1 = indicates that the last sample comparison was error free. Rev. 0 | Page 25 of 52 00000000 0 0 00 000 001 0 N/A N/A 0 0 0 0 0 AD9146 Register Name Compare I0 LSBs Compare I0 MSBs Compare Q0 LSBs Compare Q0 MSBs Compare I1 LSBs Compare I1 MSBs Compare Q1 LSBs Compare Q1 MSBs SED I LSBs Address (Hex) 0x68 Bits [7:0] Name Compare Value I0LSB 0x69 [7:0] Compare Value I0MSB 0x6A [7:0] Compare Value Q0LSB 0x6B [7:0] Compare Value Q0MSB 0x6C [7:0] Compare Value I1LSB 0x6D [7:0] Compare Value I1MSB 0x6E [7:0] Compare Value Q1LSB 0x6F [7:0] Compare Value Q1MSB 0x70 [7:0] Errors Detected INLSB SED I MSBs 0x71 [7:0] Errors Detected INMSB SED Q LSBs 0x72 [7:0] Errors Detected QNLSB SED Q MSBs 0x73 [7:0] Errors Detected QNMSB Revision 0x7F [5:2] Revision[3:0] Description Compare Value I0LSB is the byte that is compared with the I0LSB input sample captured at the input interface. Compare Value I0MSB is the byte that is compared with the I0MSB input sample captured at the input interface. Compare Value Q0LSB is the byte that is compared with the Q0LSB input sample captured at the input interface. Compare Value Q0MSB is the byte that is compared with the Q0MSB input sample captured at the input interface. Compare Value I1LSB is the byte that is compared with the I1LSB input sample captured at the input interface. Compare Value I1MSB is the byte that is compared with the I1MSB input sample captured at the input interface. Compare Value Q1LSB is the byte that is compared with the Q1LSB input sample captured at the input interface. Compare Value Q1MSB is the byte that is compared with the Q1MSB input sample captured at the input interface. Errors Detected INLSB indicates which bits were received in error. Errors Detected INMSB indicates which bits were received in error. Errors Detected QNLSB indicates which bits were received in error. Errors Detected QNMSB indicates which bits were received in error. This value corresponds to the die revision number. 0011 = Die Revision 1. Rev. 0 | Page 26 of 52 Default 10110110 01111010 01000101 11101010 00010110 00011010 11000110 10101010 00000000 00000000 00000000 00000000 N/A AD9146 LVDS INPUT DATA PORTS When FRAME is high, data is sent to the I DAC; when FRAME is low, data is sent to the Q DAC. All four nibbles must be written to the device for proper operation. For 12-bit resolution devices, the data in the fourth nibble acts as a placeholder for the data framing structure. The complete timing diagram is shown in Figure 31. The AD9146 has one LVDS data port that receives data for both the I and Q transmit paths. The device can accept data in byte and nibble formats. In byte and nibble modes, the data is sent over 8-bit and 4-bit LVDS data buses, respectively. The pin assignments of the bus in each mode are shown in Table 12. Table 12. Data Bit Pair Assignments for Data Input Modes Mode Byte Nibble1 1 FIFO OPERATION MSB to LSB D7, D6, D5, D4, D3, D2, D1, D0 D5, D4, D3, D2 The AD9146 contains a 2-channel, 16-bit wide, eight-word deep FIFO designed to relax the timing relationship between the data arriving at the DAC input ports and the internal DAC data rate clock. The FIFO acts as a buffer that absorbs timing variations between the data source and the DAC, such as the clock-to-data variation of an FPGA or ASIC, which significantly increases the timing budget of the interface. In nibble mode, the unused pins can be left floating. The data is accompanied by DCI and FRAME signals. The DCI signal is a reference bit that is used to generate a double data rate (DDR) clock. The FRAME signal is required for controlling to which DAC the data is sent. All of the interface signals can be time aligned, so there is a maximum skew requirement on the bus. In some cases, it is best to delay the DCI signal for optimum timing. Figure 32 shows the block diagram of the datapath through the FIFO. The data is latched into the device, is formatted, and is then written into the FIFO register determined by the FIFO write pointer. The value of the write pointer is incremented every time a new word is loaded into the FIFO. Meanwhile, data is read from the FIFO register determined by the read pointer and fed into the digital datapath. The value of the read pointer is incremented every time data is read into the datapath from the FIFO. The FIFO pointers are incremented at the data rate (DACCLK rate divided by the interpolation ratio). BYTE INTERFACE MODE In byte mode, the DCI signal is a reference bit used to generate the data sampling clock and should be time aligned with the data. The most significant byte of the data should correspond to DCI high, and the least significant byte of the data should correspond to DCI low. The FRAME signal indicates to which DAC the data is sent. When FRAME is high, data is sent to the I DAC; when FRAME is low, data is sent to the Q DAC. The complete timing diagram is shown in Figure 30. Valid data is transmitted through the FIFO as long as the FIFO does not overflow or become empty. An overflow or empty condition of the FIFO occurs when the write pointer and read pointer point to the same FIFO location. This simultaneous access of data leads to unreliable data transfer through the FIFO and must be avoided. NIBBLE INTERFACE MODE In nibble mode, the DCI signal is a reference bit used to generate the data sampling clock and should be time aligned with the data. The FRAME signal indicates to which DAC the data is sent. DCI I1MSB I1LSB Q1MSB Q1LSB I2MSB I2LSB Q2MSB Q2LSB 09691-037 DATA[15:0] Q0LSB FRAME Figure 30. Timing Diagram for Byte Mode DCI I1N3 I1N2 I1N1 I1N0 Q1N3 Q1N2 Q1N1 Q1N0 I2N3 09691-038 DATA[15:0] Q0N0 FRAME Figure 31. Timing Diagram for Nibble Mode Rev. 0 | Page 27 of 52 AD9146 32 BITS WRITE POINTER READ POINTER REG 0 REG 1 DATA INPUT LATCH DATA FORMAT REG 2 32 32 REG 3 REG 4 I AND Q DATA PATHS 32 I AND Q DACS REG 5 REG 6 DCI FRAME READ POINTER RESET WRITE POINTER RESET REG 7 DACCLK ÷ INT RESET LOGIC DATA/FIFO RATE REG 0x10[6] SYNC 09691-039 FIFO SOFT ALIGN REQUEST REG 0x18[1] FIFO PHASE OFFSET REG 0x17[2:0] Figure 32. Block Diagram of FIFO When the AD9146 is powered on, the FIFO depth is unknown. To avoid a concurrent read and write to the same FIFO address and to ensure a fixed pipeline delay, it is important to reset the FIFO pointers to known states. The FIFO pointers can be initialized in two ways: via a write sequence to the serial port or by strobing the FRAME input. There are two types of FIFO reset: a relative reset and an absolute reset. A relative reset enforces a defined FIFO depth. An absolute reset enforces a particular write pointer value when the reset is initiated. A serial port initiated FIFO reset is always a relative reset. A FRAME strobe initiated reset can be either a relative or an absolute reset. Table 13. Summary of FIFO Resets FIFO Reset Signal Serial Port FRAME For a FRAME dependent FIFO reset to occur, an extended FRAME pulse must be sent to the part for proper operation. The extended FRAME pulse must be asserted high for an entire I and Q DAC data sample load. This corresponds to four data clock samples in byte mode and eight data clock samples in nibble mode (see Figure 33 and Figure 34, respectively). DCI DATA Q0LSB [15:0] • When synchronization is disabled or when it is configured for data rate mode synchronization, the FRAME strobe initiates a relative FIFO reset. The reference point of the relative reset is the position of the read pointer. When FIFO mode synchronization is chosen, the FRAME strobe initiates an absolute FIFO reset. I1MSB I1LSB Q1MSB Q1LSB I2MSB I2LSB Q2MSB Q2LSB EXTENDED FRAME Figure 33. Timing Diagram for Extended Frame Pulse (Byte Mode) The operation of the FRAME initiated FIFO reset depends on the synchronization mode chosen. • Synchronization Mode Disabled Data Rate FIFO Reset Relative Relative Relative Relative Relative Absolute 09691-097 Resetting the FIFO A summary of the synchronization modes and the types of FIFO reset used is provided in Table 13. DCI DATA Q0N0 [15:0] I1N3 I1N2 I1N1 I1N0 Q1N3 Q1N2 Q1N1 Q1N0 EXTENDED FRAME For more information about the synchronization function, see the Multichip Synchronization section. Rev. 0 | Page 28 of 52 Figure 34. Timing Diagram for Extended Frame Pulse (Nibble Mode) I2N3 09691-098 Nominally, data is written to and read from the FIFO at the same rate. This keeps the FIFO depth constant. If data is written to the FIFO faster than data is read out, the FIFO depth increases. If data is read out of the FIFO faster than data is written to it, the FIFO depth decreases. For optimum timing margin, the FIFO depth should be maintained near half full (a difference of 4 between the write pointer and read pointer values). The FIFO depth represents the FIFO pipeline delay and is part of the overall latency of the AD9146. AD9146 Serial Port Initiated FIFO Reset FRAME Initiated Absolute FIFO Reset A serial port initiated FIFO reset can be issued in any mode and always results in a relative FIFO reset. To initialize the FIFO data level through the serial port, Bit 1 of Register 0x18 should be toggled from 0 to 1 and back. When the write to this register is complete, the FIFO data level is initialized. When the initialization is triggered, the next time that the read pointer becomes 0, the write pointer is set to the value of the FIFO start level variable (Register 0x17, Bits[2:0]) upon initialization. By default, this value is 4, but it can be programmed to a value from 0 to 7. In FIFO rate synchronization mode, the write pointer of the FIFO is reset in an absolute manner. The synchronization signal aligns the internal clocks on the part to a common reference clock so that the pipeline delay in the digital circuit stays the same during power cycles. The synchronization signal is sampled by the DAC clock in the AD9146. The edge of the DAC clock used to sample the synchronization signal is selected by Bit 3 of Register 0x10. 1. 2. 3. 4. 5. 6. 7. 8. Program Register 0x17 to 0x05. Request FIFO level reset by setting Register 0x18, Bit 1, to 1. Verify that the part acknowledges the request by ensuring that Register 0x18, Bit 2, is set to 1. Remove the request by setting Register 0x18, Bit 1, to 0. Verify that the part drops the acknowledge signal by ensuring that Register 0x18, Bit 2, is set to 0. Read back Register 0x19 to verify that the pointer spacing is set to 3 (0x07) or 4 (0x0F). If the readback of Register 0x19 shows a pointer spacing of 2 (0x03), increment Register 0x17 to a spacing of 0x06 and repeat Step 2 through Step 5. Read back Register 0x19 again to verify that the pointer spacing is now set to 3 (0x07). If the readback of Register 0x19 shows a pointer spacing of 5 (0x1F) after Step 6, decrement Register 0x17 to a spacing of 0x04 and repeat Step 2 through Step 5. Read back Register 0x19 again to verify that the pointer spacing is now set to 4 (0x0F). FRAME Initiated Relative FIFO Reset To initiate a relative FIFO reset with the FRAME signal, the device must be configured in data rate mode (Register 0x10, Bit 6 = 1). When FRAME is asserted in data rate mode, the write pointer is set to 4 by default (or to the FIFO start level) the next time that the read pointer becomes 0 (see Figure 35). 0 1 2 3 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 1 2 FRAME WRITE POINTER 6 5 6 3 4 5 6 7 0 1 2 3 3 4 5 6 7 FIFO PHASE OFFSET[2:0] REG 0x17[2:0] = 101 7 0 1 2 Figure 36. FRAME Input vs. Write Pointer Value, FIFO Rate Mode Monitoring the FIFO Status The FIFO initialization and status can be read from Register 0x18. This register provides information about the FIFO status and whether the initialization was successful. The MSB of Register 0x18 is a FIFO warning flag that can optionally trigger a device IRQ. This flag indicates that the FIFO is close to emptying (FIFO level is 1) or overflowing (FIFO level is 7). In this case, data may soon be corrupted, and action should be taken. Note that, depending on the timing relationship between the DCI and the main DACCLK, the FIFO level value can be off by a ±1 count; that is, the readback of Register 0x19 can be 00011111 in the case of a +1 count and 00000111 in the case of a −1 count. Therefore, it is important to keep the difference between the read and write pointers to a value of at least 2. 09691-040 3 0 FIFO WRITE RESET FIFO WRITE RESETS FRAME WRITE POINTER 4 READ POINTER FIFO READ RESET The FIFO data level can be read from Register 0x19 at any time. The serial port reported FIFO data level is denoted as a 7-bit thermometer code (Base 1 code) of the write counter state relative to the absolute read counter being at 0. The optimum FIFO data level of 4 is therefore reported as a value of 00001111 in the status register. The primary function of the FRAME input is to indicate to which DAC the input data is written. Another function of the FRAME input is to initialize the FIFO data level value. This is done by asserting the FRAME signal high for at least the time interval required to load complete data to the I and Q DACs. This corresponds to four DCI periods in byte mode and eight DCI periods in nibble mode. READ POINTER SYNC 09691-041 The recommended procedure for a serial port FIFO data level initialization is as follows: The FRAME signal is used to reset the FIFO write pointer. In the FIFO rate synchronization mode, the FIFO write pointer is reset immediately after the FRAME signal is asserted high for at least the time interval required to load complete data to the I and Q DACs. The FIFO write pointer is reset to the value of the FIFO Phase Offset[2:0] bits in Register 0x17. FIFO rate synchronization is selected by setting Bit 6 of Register 0x10 to 0. Figure 35. FRAME Input vs. Write Pointer Value, Data Rate Mode Rev. 0 | Page 29 of 52 AD9146 INTERFACE TIMING Bypass DCI Delay Mode The timing diagram for the digital interface port is shown in Figure 37. The sampling point of the data bus nominally occurs 350 ps after each edge of the DCI signal and has an uncertainty of ±300 ps, as illustrated by the data valid window shown in Figure 37. The data and FRAME signals must be valid throughout this window. The data and FRAME signals may change at any time between data valid windows. An additional option for the timing of the data, DCI, and FRAME signals requires the DCI to be delayed by 90° ahead of the data and FRAME signals. In bypass DCI delay mode, the DCI signal is placed in the optimal data valid window outside the part, and the delay circuitry inside the part is bypassed. This mode provides a smaller sampling window that allows for a wider range of placement area for correct sampling edges. The bypass DCI delay mode is enabled by setting Bit 2 in Register 0x16 to 1. The resulting setup and hold times for this mode are as follows: The setup (tS) and hold (tH) times, with respect to the edges, are shown in Figure 37. The minimum setup and hold times are shown in Table 14. tDATA • • • tDATA Minimum setup time (tS): 0.27 ns Minimum hold time (tH): 0.09 ns Sampling interval: 0.36 ns Figure 38 shows the timing for the bypass DCI delay mode. DCI tDATA tDATA DATA VALID WINDOW DCI DATA VALID WINDOW tS tH tS tH 09691-042 DATA DATA tS Table 14. Data to DCI Setup and Hold Times DCI Delay Register 0x16, Bits[1:0] 00 01 10 11 Minimum Setup Time, tS (ns) 0.12 −0.01 −0.2 −0.28 Minimum Hold Time, tH (ns) 0.45 0.74 1.03 1.16 tS tH Sampling Interval (ns) 0.57 0.73 0.83 0.88 tH 09691-099 Figure 37. Timing Diagram for Input Data Port Figure 38. Timing Diagram for Input Data Port (Bypass DCI Delay Mode) The data interface timing can be verified using the sample error detection (SED) circuitry. See the Interface Timing Validation section for more information. Rev. 0 | Page 30 of 52 AD9146 DIGITAL DATAPATH HB1 HB2 PHASE AND OFFSET ADJUSTMENT SINC–1 Half-Band Filter 1 (HB1) HB1 has four modes of operation, as shown in Figure 40. The shape of the filter response is identical in each of the four modes. The four modes are distinguished by two factors: the filter center frequency and whether the input signal is modulated by the filter. MODE 0 Figure 39. Block Diagram of Digital Datapath MODE 3 The digital datapath can also be used to process an input data stream representing two independent real data streams, but the functionality is somewhat restricted. The premodulation block and any of the nonshifted interpolation filter modes can be used for an input data stream representing two independent real data streams. See the Coarse Modulation Mixing Sequences section for more information. –20 MAGNITUDE (dB) The digital datapath accepts I and Q data streams and processes them as a quadrature data stream. The signal processing blocks can be used when the input data stream is represented as complex data. –40 –60 –80 –100 0 PREMODULATION 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 FREQUENCY (× fIN1) (Hz) The half-band interpolation filters have selectable pass bands that allow the center frequencies to be moved in increments of one-half their input data rate. The premodulation block provides a digital upconversion of the incoming waveform by one-half the incoming data rate, fDATA. This can be used to frequency-shift baseband input data to the center of the interpolation filter pass band. INTERPOLATION FILTERS The transmit path contains two interpolation filters. Both interpolation filters provide a 2× increase in output data rate. The half-band (HB) filters can be individually bypassed or cascaded to provide 1×, 2×, or 4× interpolation ratios. Each half-band filter stage offers a different combination of bandwidths and operating modes. The bandwidth of the two half-band filters with respect to the data rate at the filter input is as follows: • • MODE 2 MODE 1 0 Bandwidth of HB1 = 0.8 × fIN1 Bandwidth of HB2 = 0.5 × fIN2 2.0 09691-045 PREMOD 09691-103 The block diagram in Figure 39 shows the functionality of the digital datapath. The digital processing includes a premodulation block, two half-band (HB) interpolation filters, phase and offset adjustment blocks, and an inverse sinc filter. Figure 40. HB1 Filter Modes As shown in Figure 40, the center frequency in each mode is offset by one-half the input data rate (fIN1) of the filter. Mode 0 and Mode 1 do not modulate the input signal. Mode 2 and Mode 3 modulate the input signal by fIN1. When operating in Mode 0 and Mode 2, the I and Q paths operate independently and no mixing of the data between channels occurs. When operating in Mode 1 and Mode 3, mixing of the data between the I and Q paths occurs; therefore, the data input into the filter is assumed to be complex. Table 15 summarizes the HB1 modes. Table 15. HB1 Filter Modes Mode 0 1 2 3 The usable bandwidth is defined as the frequency over which the filters have a pass-band ripple of less than ±0.001 dB and an image rejection of greater than +85 dB. As described in the Half-Band Filter 1 (HB1) section, the image rejection usually sets the usable bandwidth of the filter, not the pass-band flatness. The half-band filters operate in several modes, providing programmable pass-band center frequencies as well as signal modulation. The HB1 filter has four modes of operation, and the HB2 filter has eight modes of operation. Rev. 0 | Page 31 of 52 fCENTER DC fIN/2 fIN 3fIN/2 fMOD None None fIN fIN Input Data Real or complex Complex Real or complex Complex AD9146 0.02 MODE 1 MODE 3 0 MODE 5 MODE 7 –20 MAGNITUDE (dB) Figure 41 shows the pass-band filter response for HB1. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 16 shows the pass-band flatness and the stop-band rejection supported by the HB1 filter at different bandwidths. –40 –60 0 –100 0 –0.04 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 FREQUENCY (× fIN2) (Hz) 2.0 Figure 43. HB2, Odd Filter Modes –0.06 –0.08 0 09691-046 –0.10 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 FREQUENCY (× fIN1) (Hz) Figure 41. Pass-Band Detail of HB1 Table 16. HB1 Pass-Band and Stop-Band Performance by Bandwidth Pass-Band Flatness (dB) 0.001 0.0012 0.0033 0.0076 0.0271 0.1096 Bandwidth (% of fIN1) 80 80.4 81.2 82 83.6 85.6 Stop-Band Rejection (dB) 85 80 70 60 50 40 Half-Band Filter 2 (HB2) HB2 has eight modes of operation, as shown in Figure 42 and Figure 43. The shape of the filter response is identical in each of the eight modes. The eight modes are distinguished by two factors: the filter center frequency and whether the input signal is modulated by the filter. MODE 0 0 MODE 4 MODE 2 As shown in Figure 42 and Figure 43, the center frequency in each mode is offset by one-fourth the input data rate (fIN2) of the filter. Mode 0 through Mode 3 do not modulate the input signal. Mode 4 through Mode 7 modulate the input signal by fIN2. When operating in Mode 0 and Mode 4, the I and Q paths operate independently and no mixing of the data between channels occurs. When operating in the other six modes, mixing of the data between the I and Q paths occurs; therefore, the data input to the filter is assumed to be complex. Table 17 summarizes the HB2 modes. Table 17. HB2 Filter Modes Mode 0 1 2 3 4 5 6 7 MODE 6 –20 –40 –60 –80 –100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 FREQUENCY (× fIN2) (Hz) 1.6 1.8 2.0 09691-047 MAGNITUDE (dB) 0.2 09691-048 MAGNITUDE (dB) –80 –0.02 Figure 42. HB2, Even Filter Modes Rev. 0 | Page 32 of 52 fCENTER DC fIN/4 fIN/2 3fIN/4 fIN 5fIN/4 3fIN/2 7fIN/4 fMOD None None None None fIN fIN fIN fIN Input Data Real or complex Complex Complex Complex Real or complex Complex Complex Complex AD9146 Figure 44 shows the pass-band filter response for HB2. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 18 shows the pass-band flatness and stop-band rejection supported by the HB2 filter at different bandwidths. 0.02 MAGNITUDE (dB) 0 –0.02 Table 18. HB2 Pass-Band and Stop-Band Performance by Bandwidth Bandwidth (% of fIN2) 50 50.8 52.8 56 60 64.8 Pass-Band Flatness (dB) 0.001 0.0012 0.0028 0.0089 0.0287 0.1877 Stop-Band Rejection (dB) 85 80 70 60 50 40 DATAPATH CONFIGURATION –0.04 –0.06 –0.08 0 0.04 0.08 0.12 0.16 0.20 0.24 FREQUENCY (× fIN2) (Hz) 0.28 0.32 09691-049 –0.10 Configuring the AD9146 datapath starts with the application requirements of the input data rate, the interpolation ratio, the output signal bandwidth, and the output signal center frequency. Given these four parameters, the first step in configuring the datapath is to verify that the device supports the bandwidth requirements. The modes of the interpolation filters are then chosen. DETERMINING INTERPOLATION FILTER MODES Table 19 shows the recommended interpolation filter settings for a variety of filter interpolation factors, filter center frequencies, and signal modulation. The interpolation modes were chosen based on the final center frequency of the signal and by determining the frequency shift of the signal required. When these parameters are known and put in terms of the input data rate (fDATA), the filter configuration that comes closest to matching is selected from Table 19. Figure 44. Pass-Band Detail of HB2 Table 19. Recommended Interpolation Filter Modes (Register 0x1C and Register 0x1D) Interpolation Factor 4 4 4 4 4 4 4 4 2 2 2 2 1 HB1[1:0] 00 (Mode 0) 01 (Mode 1) 10 (Mode 2) 11 (Mode 3) 00 (Mode 0) 01 (Mode 1) 10 (Mode 2) 11 (Mode 3) 00 (Mode 0) 01 (Mode 1) 10 (Mode 2) 11 (Mode 3) Filter Modes HB2[5:0] 000000 001001 010010 011011 100100 101101 110110 111111 Bypass Bypass Bypass Bypass fSIGNAL Modulation DC DC1 fDATA fDATA1 2fDATA 2fDATA1 3fDATA 3fDATA1 DC DC1 fDATA fDATA1 fCENTER Shift 0 fDATA/2 fDATA 3fDATA/2 2fDATA 5fDATA/2 3fDATA 7fDATA/2 0 fDATA/2 fDATA 3fDATA/2 When HB1 Mode 1 or Mode 3 is used, enabling premodulation provides an additional frequency translation of the input signal by fDATA/2, which centers a baseband input signal in the filter pass band. Rev. 0 | Page 33 of 52 AD9146 COARSE MODULATION MIXING SEQUENCES The coarse digital quadrature modulation occurs within the interpolation filters. The modulation shifts the frequency spectrum of the incoming data by the frequency offset selected. The frequency offsets available are multiples of the input data rate. The modulation is equivalent to multiplying the quadrature input signal by a complex carrier signal, C(t), of the form Based on these two endpoints, the combined resolution of the phase compensation register is approximately 3.5°/1024 or 0.00342° per code. C(t) = cos(ωct) + j sin(ωct) In practice, this modulation results in the mixing functions shown in Table 20. DC OFFSET CORRECTION fS/8 Note that r = 2 2 As shown in Table 20, the mixing functions of most of the modes cross-couple samples between the I and Q channels. The I and Q channels operate independently only in fS/2 mode. This means that real modulation using both the I and Q DAC outputs can only be done in fS/2 mode. All other modulation modes require complex input data and produce complex output signals. QUADRATURE PHASE CORRECTION The purpose of the quadrature phase correction block is to enable compensation of the phase imbalance of the analog quadrature modulator following the DAC. If the quadrature modulator has a phase imbalance, the unwanted sideband appears with significant energy. Tuning the quadrature phase adjust value can optimize image rejection in single sideband radios. Figure 45 shows how the DAC offset current varies as a function of the I DAC Offset[15:0] and Q DAC Offset[15:0] values. With the digital inputs fixed at midscale (0x0000, twos complement data format), Figure 45 shows the nominal IOUTxP and IOUTxN currents as the DAC offset value is swept from 0 to 65,535. Because IOUTxP and IOUTxN are complementary current outputs, the sum of IOUTxP and IOUTxN is always 20 mA. Ordinarily, the I and Q channels have an angle of precisely 90° between them. The quadrature phase adjustment is used to change the angle between the I and Q channels. When I Phase Adj[9:0] (Register 0x38 and Register 0x39) is set to 1000000000, the I DAC output moves approximately 1.75° away from the Q DAC output, creating an angle of 91.75° between the channels. When I Phase Adj[9:0] is set to 0111111111, the I DAC output moves approximately 1.75° toward the Q DAC output, creating an angle of 88.25° between the channels. Rev. 0 | Page 34 of 52 20 0 15 5 10 10 5 15 0 0x0000 0x4000 0x8000 0xC000 20 0xFFFF DAC OFFSET VALUE Figure 45. DAC Output Currents vs. DAC Offset Value IOUTxN (mA) 3fS/4 The dc value of the I datapath and the Q datapath can be independently controlled by adjusting the I DAC Offset[15:0] and Q DAC Offset[15:0] values in Register 0x3C through Register 0x3F. These values are added directly to the datapath values. Care should be taken not to overrange the transmitted values. 09691-050 fS/4 Mixing Sequence I = I, −I, I, −I, … Q = Q, −Q, Q, −Q, … I = I, Q, −I, −Q, … Q = Q, −I, −Q, I, … I = I, −Q, −I, Q, … Q = Q, I, −Q, −I, … I = I, r(I + Q), Q, r(−I + Q), −I, −r(I + Q), −Q, r(I − Q), … Q = Q, r(Q − I), −I, −r(Q + I), −Q, r(−Q + I), I, r(Q + I), … IOUTxP (mA) Table 20. Modulation Mixing Sequences Modulation fS/2 Q Phase Adj[9:0] (Register 0x3A and Register 0x3B) works in a similar fashion. When Q Phase Adj[9:0] is set to 1000000000, the Q DAC output moves approximately 1.75° away from the I DAC output, creating an angle of 91.75° between the channels. When Q Phase Adj[9:0] is set to 0111111111, the Q DAC output moves approximately 1.75° toward the I DAC output, creating an angle of 88.25° between the channels. AD9146 –3.0 INVERSE SINC FILTER –3.2 MAGNITUDE (dB) The inverse sinc (sinc−1) filter is a nine-tap FIR filter. The composite response of the sinc−1 filter and the sin(x)/x response of the DAC is shown in Figure 46. The composite response has a pass-band ripple of less than ±0.05 dB up to a frequency of 0.4 × fDACCLK. To provide the necessary peaking at the upper end of the pass band, the inverse sinc filters shown have an intrinsic insertion loss of about 3.2 dB. Figure 46 shows the composite frequency response. The sinc−1 filter is disabled by default. It can be enabled by setting the bypass sinc−1 bit to 0 (Register 0x1B, Bit 6). –3.4 –3.6 –3.8 0 0.1 0.2 0.3 0.4 0.5 fOUT/fDAC Figure 46. Sample Composite Responses of the Sinc−1 Filter with sin(x)/x Roll-Off Rev. 0 | Page 35 of 52 09691-051 –4.0 AD9146 DAC INPUT CLOCK CONFIGURATIONS The AD9146 DAC sampling clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying uses the on-chip phase-locked loop (PLL), which accepts a reference clock operating at a submultiple of the desired DACCLK rate, most commonly the data input frequency. The PLL then multiplies the reference clock up to the desired DACCLK frequency, which can then be used to generate all the internal clocks required by the DAC. The clock multiplier provides a high quality clock that meets the performance requirements of most applications. Using the on-chip clock multiplier eliminates the need to generate and distribute the high speed DACCLK. when the clock input signal is between 800 mV p-p differential and 1.6 V p-p differential. Whether using the on-chip clock multiplier or sourcing the DACCLK directly, it is necessary that the input clock signal to the device have low jitter and fast edge rates to optimize the DAC noise performance. DIRECT CLOCKING Direct clocking with a low noise clock produces the lowest noise spectral density at the DAC outputs. To select the differential CLK inputs as the source for the DAC sampling clock, set the PLL enable bit (Register 0x0A, Bit 7) to 0. This powers down the internal PLL clock multiplier and selects the input from the DACCLKP and DACCLKN pins as the source for the internal DAC sampling clock. The second mode bypasses the clock multiplier circuitry and allows the DACCLK to be sourced directly to the DAC core. This mode enables the user to source a very high quality clock directly to the DAC core. Sourcing the DACCLK directly through the REFCLKP, REFCLKN, DACCLKP, and DACCLKN pins may be necessary in demanding applications that require the lowest possible DAC output noise, particularly when directly synthesizing signals above 150 MHz. The device also has duty cycle correction circuitry and differential input level correction circuitry. Enabling these circuits can provide improved performance in some cases. The control bits for these functions are in Register 0x08 (see Table 11). CLOCK MULTIPLICATION DRIVING THE DACCLK AND REFCLK INPUTS The on-chip PLL clock multiplication circuit can be used to generate the DAC sampling clock from a lower frequency reference clock. When the PLL enable bit (Register 0x0A, Bit 7) is set to 1, the clock multiplication circuit generates the DAC sampling clock from the lower rate REFCLK input. The functional diagram of the clock multiplier is shown in Figure 48. The differential DACCLK and REFCLK inputs share similar clock receiver input circuitry. Figure 47 shows a simplified circuit diagram of the inputs. The on-chip clock receiver has a differential input impedance of about 10 kΩ. It is self-biased to a commonmode voltage of about 1.25 V. The inputs can be driven by direct coupling differential PECL or LVDS drivers. The inputs can also be ac-coupled if the driving source cannot meet the input compliance voltage of the receiver. The clock multiplication circuit operates such that the VCO outputs a frequency, fVCO, equal to the REFCLK input signal frequency multiplied by N1 × N0. DACCLKP, REFCLKP fVCO = fREFCLK × (N1 × N0) The DAC sampling clock frequency, fDACCLK, is equal to 5kΩ The output frequency of the VCO must be chosen to keep fVCO in the optimal operating range of 1.0 GHz to 2.1 GHz. The frequency of the reference clock and the values of N1 and N0 must be chosen so that the desired DACCLK frequency can be synthesized and the VCO output frequency is in the correct range. Figure 47. Clock Receiver Input Simplified Equivalent Circuit The minimum input drive level to either of the clock inputs is 100 mV p-p differential. The optimal performance is achieved REG 0x06[7:6] PLL LOCK LOST PLL LOCKED REFCLKP/REFCLKN (PIN 6 AND PIN 7) PHASE DETECTION ADC LOOP FILTER REG 0x0E[3:0] VCO CONTROL VOLTAGE VCO ÷N1 ÷N0 REG 0x0D[1:0] N1 REG 0x0D[3:2] N0 DACCLK DACCLKP/DACCLKN (PIN 3 AND PIN 4) REG 0x0A[7] PLL ENABLE REG 0x0D[7:6] ÷N2 N2 PC_CLK Figure 48. PLL Clock Multiplication Circuit Rev. 0 | Page 36 of 52 09691-053 DACCLKN, REFCLKN fDACCLK = fREFCLK × N1 1.25V 09691-052 5kΩ AD9146 PLL SETTINGS Manual VCO Band Select Three settings for the PLL circuitry should be programmed to their nominal values. The PLL values shown in Table 21 are the recommended settings for these parameters. The device also has a manual band select mode (PLL manual enable, Register 0x0A, Bit 6 = 1) that allows the user to select the VCO tuning band. In manual mode, the VCO band is set directly with the value written to the manual VCO band bits (Register 0x0A, Bits[5:0]). To properly select the VCO band, follow these steps: Table 21. PLL Settings PLL Control Register PLL Loop Bandwidth[1:0] PLL Charge Pump Current[4:0] PLL Cross-Control Enable Register Address 0x0C 0x0C 0x0D Bits [7:6] [4:0] 4 Optimal Setting 11 10001 1 1. 2. 3. CONFIGURING THE VCO TUNING BAND The PLL VCO has a valid operating range from approximately 1.0 GHz to 2.1 GHz covered in 63 overlapping frequency bands. For any desired VCO output frequency, there may be several valid PLL band select values. The frequency bands of a typical device are shown in Figure 49. Device-to-device variations and operating temperature affect the actual band frequency range. Therefore, it is required that the optimal PLL band select value be determined for each individual device. 4. 5. 0 4 8 12 Table 22. VCO Control Voltage Range Indications PLL BAND 16 20 24 28 32 36 40 44 48 52 56 1200 1400 1600 1800 2000 2200 VCO FREQUENCY (MHz) 09691-054 60 1000 Put the device in manual band select mode by setting Register 0x0A, Bit 6 = 1. Sweep the VCO band over a range of bands that results in the PLL being locked. For each band, verify that the PLL is locked and read the PLL using the VCO control voltage bits (Register 0x0E, Bits[3:0]). Select the band that results in the control voltage being closest to the center of the range, that is, 1001 or 1000 (see Table 22). The resulting VCO band should be the optimal setting for the device. Write this value to the manual VCO band bits (Register 0x0A, Bits[5:0]). If desired, an indication of where the VCO is within the operating frequency band can be determined by querying the VCO control voltage. Table 22 shows how to interpret the PLL VCO control voltage value (Register 0x0E, Bits[3:0]). Figure 49. PLL Lock Range over Temperature for a Typical Device Automatic VCO Band Select The device has an automatic VCO band select feature on chip. Using the automatic VCO band select feature is a simple and reliable method of configuring the VCO frequency band. This feature is enabled by starting the PLL in manual mode, then placing the PLL in auto band select mode. This is done by setting Register 0x0A to a value of 0xCF, then to a value of 0xA0. When these values are written, the device executes an automated routine that determines the optimal VCO band setting for the device. The setting selected by the device ensures that the PLL remains locked over the full −40°C to +85°C operating temperature range of the device without further adjustment. (The PLL remains locked over the full temperature range even if the temperature during initialization is at one of the temperature extremes.) VCO Control Voltage (Register 0x0E, Bits[3:0]) 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Rev. 0 | Page 37 of 52 Indication Move to higher VCO band VCO is operating in the higher end of the frequency band VCO is operating within an optimal region of the frequency band VCO is operating in the lower end of the frequency band Move to lower VCO band AD9146 ANALOG OUTPUTS TRANSMIT DAC OPERATION 35 Figure 50 shows a simplified block diagram of the transmit path DACs. The DAC core consists of a current source array, a switch core, digital control logic, and full-scale output current control. The DAC full-scale output current (IFS) is nominally 20 mA. The output currents from the IOUT1P/IOUT2P and IOUT1N/ IOUT2N pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the DAC. The digital input code to the DAC determines the effective differential current delivered to the load. 30 5kΩ REFIO 0.1µF FSADJ IFS (mA) 0 0 200 400 IOUT1N 600 800 DAC GAIN CODE 1000 Figure 51. DAC Full-Scale Current vs. DAC Gain Code Transmit DAC Transfer Function IOUT2N Q DAC IOUT2P Q DAC FS ADJUST REGISTER 0x44 Figure 50. Simplified Block Diagram of DAC Core The DAC has a 1.2 V band gap reference with an output impedance of 5 kΩ. The reference output voltage appears on the REFIO pin. When using the internal reference, decouple the REFIO pin to AVSS with a 0.1 μF capacitor. Use the internal reference only for external circuits that draw dc currents of 2 μA or less. For dynamic loads or static loads greater than 2 μA, buffer the REFIO pin. If desired, the internal reference can be overdriven by applying an external reference (from 1.10 V to 1.30 V) to the REFIO pin. A 10 kΩ external resistor, RSET, must be connected from the FSADJ pin to AVSS. This resistor, along with the reference control amplifier, sets up the correct internal bias currents for the DAC. Because the full-scale current is inversely proportional to this resistor, the tolerance of RSET is reflected in the full-scale output amplitude. The full-scale current equation, where the DAC gain is set individually for the I and Q DACs in Register 0x40 and Register 0x44, respectively, is as follows: I FS = 5 CURRENT SCALING 10kΩ RSET 15 10 IOUT1P I DAC 20 09691-056 I DAC FS ADJUST REGISTER 0x40 09691-055 1.2V 25 VREF ⎛ 3 ⎞ × ⎜ 72 + ⎛⎜ × DAC gain ⎞⎟ ⎟ R SET ⎝ ⎝ 16 ⎠⎠ For the nominal values of VREF (1.2 V), RSET (10 kΩ), and DAC gain (512), the full-scale current of the DAC is typically 20.16 mA. The DAC full-scale current can be adjusted from 8.64 mA to 31.68 mA by setting the DAC gain parameter, as shown in Figure 51. The output currents from the IOUT1P/IOUT2P and IOUT1N/ IOUT2N pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the DAC. The digital input code to the DAC determines the effective differential current delivered to the load. IOUT1P/IOUT2P provide maximum output current when all bits are high. The output currents vs. DACCODE for the DAC outputs are expressed as DACCODE ⎤ I OUTxP = ⎡⎢ ⎥⎦ × I FS 2N ⎣ (1) I OUTxN = I FS − I OUTxP (2) N where DACCODE = 0 to 2 − 1. Transmit DAC Output Configurations The optimum noise and distortion performance of the AD9146 is realized when it is configured for differential operation. The common-mode error sources of the DAC outputs are significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Rev. 0 | Page 38 of 52 AD9146 IOUT1P –50 IFS = 10mA IFS = 20mA IFS = 30mA –55 –60 IMD (dBc) Figure 52 shows the most basic transmit DAC output circuitry. A pair of resistors, RO, is used to convert each of the complementary output currents to a differential voltage output, VOUT. Because the current outputs of the DAC are high impedance, the differential driving point impedance of the DAC outputs, ROUT, is equal to 2 × RO. Figure 53 illustrates the output voltage waveforms. –65 –70 VIP + –75 RO VOUTI –80 VIN – IOUT1N –85 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VCM (V) IOUT2P VQP + Figure 54. IMD vs. Output Common-Mode Voltage (fOUT = 161 MHz, RLOAD = 50 Ω Differential, IFS = 10 mA, 20 mA, and 30 mA) RO VOUTQ VQN – IOUT2N AUXILIARY DAC OPERATION 09691-057 RO 09691-004 RO The AD9146 has two auxiliary DACs: one associated with the I path and one associated with the Q path. These auxiliary DACs can be used to compensate for dc offsets in the transmitted signal. Each auxiliary DAC has a single-ended current that can sink or source current into either the positive (P) or negative (N) output of the associated transmit DAC. The auxiliary DAC structure is shown in Figure 55. Figure 52. Basic Transmit DAC Output Circuit +VPEAK VCM VB 0 VP I AUX DAC[9:0] VOUT –VPEAK 09691-058 VN I AUX DAC CURRENT DIRECTION Figure 53. Output Voltage Waveforms The common-mode signal voltage, VCM, is calculated as I AUX DAC SIGN I FS × RO 2 IOUT1P The peak output voltage, VPEAK, is calculated as I DAC IOUT1N VPEAK = IFS × RO 09691-061 VCM = Figure 55. Auxiliary DAC Structure With this circuit configuration, the single-ended peak voltage is the same as the peak differential output voltage. Transmit DAC Linear Output Signal Swing The control registers for the I and Q auxiliary DACs are Register 0x42, Register 0x43, Register 0x46, and Register 0x47. To achieve optimum performance, the DAC outputs have a linear output compliance voltage range that must be adhered to. The linear output signal swing is dependent on the full-scale output current, IFS, and the common-mode level of the output. Figure 54 shows the IMD performance vs. the output commonmode voltage at different full-scale currents. Rev. 0 | Page 39 of 52 AD9146 Figure 58 shows a fifth-order, low-pass filter. A common-mode choke is used between the I-V resistors and the remainder of the filter. This removes the common-mode signal produced by the DAC and prevents the common-mode signal from being converted to a differential signal, which can appear as unwanted spurious signals in the output spectrum. Splitting the first filter capacitor into two and grounding the center point creates a common-mode low-pass filter, providing additional commonmode rejection of high frequency signals. A purely differential filter can pass common-mode signals. INTERFACING TO MODULATORS The AD9146 interfaces to the ADL537x family of modulators with a minimal number of components. An example of the recommended interface circuitry is shown in Figure 56. IBBP IOUT1N IOUT2N 46 RBIN 50Ω IBBN 39 DRIVING THE ADL5375-15 The ADL5375-15 requires a 1500 mV dc bias and, therefore, requires a slightly more complex interface than most other Analog Devices modulators. It is necessary to level-shift the DAC output from a 500 mV dc bias to the 1500 mV dc bias required by the ADL5375-15. Level-shifting can be achieved with a purely passive network, as shown in Figure 57. In this network, the dc bias of the DAC remains at 500 mV, whereas the input to the ADL5375-15 is 1500 mV. This passive, levelshifting network introduces approximately 2 dB of loss in the ac signal. QBBN RBQN 50Ω IOUT2P RLI 100Ω RBQP 50Ω 38 RLQ 100Ω QBBP Figure 56. Typical Interface Circuitry Between the AD9146 and the ADL537x Family of Modulators The baseband inputs of the ADL537x family require a dc bias of 500 mV. The nominal midscale output current on each output of the DAC is 10 mA (one-half the full-scale current). Therefore, a single 50 Ω resistor to ground from each of the DAC outputs results in the desired 500 mV dc common-mode bias for the inputs to the ADL537x. The signal level can be reduced through the addition of the load resistor in parallel with the modulator inputs. The peak-to-peak voltage swing of the transmitted signal is VSIGNAL = I FS × AD9146 IOUT1P RBIP 45.3Ω 46 (2 × R B × R L ) RBIN 45.3Ω IOUT1N (2 × R B + R L ) IOUT2N 50Ω AD9146 38 IOUT2P RSIN 1kΩ RLIN 3480Ω 5V 22 IBBN 9 QBBN RLQN 3480Ω RSQP 1kΩ RLQP 3480Ω 5V 10 QBBP Figure 57. Passive, Level-Shifting Network for Biasing the ADL5375-15 33nH 22pF 56nH 33nH 56nH 2pF 50Ω RBQP 45.3Ω IBBP RLIP 3480Ω RBQN 45.3Ω Most applications require a baseband anti-imaging filter between the DAC and the modulator to filter out Nyquist images and broadband DAC noise. The filter can be inserted between the I-V resistors at the DAC output and the signal level setting resistor across the modulator input. This establishes the input and output impedances for the filter. 21 RSQN 1kΩ 39 BASEBAND FILTER IMPLEMENTATION ADL5375-15 RSIP 1kΩ 47 3pF 6pF 22pF 100Ω ADL537x 3pF Figure 58. DAC Modulator Interface with Fifth-Order, Low-Pass Filter Rev. 0 | Page 40 of 52 09691-063 RBIP 50Ω 09691-062 IOUT1P ADL537x 47 09691-064 AD9146 AD9146 REDUCING LO LEAKAGE AND UNWANTED SIDEBANDS Analog quadrature modulators can introduce unwanted signals at the LO frequency due to dc offset voltages in the I and Q baseband inputs, as well as feedthrough paths from the LO input to the output. The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output. This can be done using the auxiliary DACs (Register 0x42, Register 0x43, Register 0x46, and Register 0x47) or by using the digital dc offset adjustments (Register 0x3C through Register 0x3F). The advantage of using the auxiliary DACs is that none of the main DAC dynamic range is used to perform the dc offset adjustment. The disadvantage is that the common-mode level of the output signal changes as a function of the auxiliary DAC current. The opposite is true when the digital offset adjustment is used. Good sideband suppression requires both gain and phase matching of the I and Q signals. The I/Q phase adjust registers (Register 0x38 through Register 0x3B) and the DAC FS adjust registers (Register 0x40 and Register 0x44) can be used to calibrate the I and Q transmit paths to optimize sideband suppression. Rev. 0 | Page 41 of 52 AD9146 DEVICE POWER MANAGEMENT 1.0 POWER DISSIPATION 0.8 Maximum power dissipation can be estimated to be 20% higher than the typical power dissipation. 1.4 1.3 1.2 POWER DISSIPATION (W) 1.1 1.0 4× INTERPOLATION 0.9 0.8 0.7 0.6 0.4 0.3 0.2 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 fDATA (MSPS) 2× INTERPOLATION 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 09691-101 0 fDATA (MSPS) Figure 60. DVDD18 Power Dissipation vs. fDATA Without Inverse Sinc 0.40 0.35 0.30 0.25 0.20 4× INTERPOLATION 0.15 0.10 2× INTERPOLATION 0.05 0 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 fDATA (MSPS) Figure 61. CVDD18 Power Dissipation vs. fDATA with PLL Disabled Tx ENABLE The Tx enable feature provides additional power management techniques that can be implemented in system applications. The TXENABLE pin, when taken to a logic low, stops the transmission of data from the part and clamps the outputs to midscale. In addition, various portions of the DAC can be powered down while the pin is held low, depending on the power saving requirements of the system and the amount of wake-up time required when the pin is brought high. 09691-100 0 0.3 0 0.1 0 0.4 Register 0x02 contains the bit controls to power down these individual blocks: DAC cores, FIFO, interpolation filters, PLL, and the internal reference. Depending on the power-down bits selected, the necessary wake-up time and reprogramming of the DAC may vary. 2× INTERPOLATION 0.5 0.5 0.1 POWER DISSIPATION (W) Figure 59 through Figure 61 show the power dissipation of the AD9146 under a variety of operating conditions. All of the graphs were taken with data being supplied to both the I and Q DACs. The power consumption of the device does not vary significantly with changes in the coarse modulation mode selected or with the analog output frequency. Figure 59 shows the total power dissipation. Figure 60 and Figure 61 show the power dissipation of the DVDD18 and CVDD18 supplies. 4× INTERPOLATION 0.6 0.2 The DVDD18 supply powers all of the digital signal processing blocks of the device. The serial port I/O pins, the RESET pin, and the IRQ pin are also supplied from the DVDD18 power supply. The power consumption from this supply is a function of which digital blocks are enabled and the frequency at which the device is operating. The CVDD18 supply powers the clock receiver and clock distribution circuitry. The power consumption from this supply varies directly with the operating frequency of the device. CVDD18 also powers the PLL. The power dissipation of the PLL is typically 80 mA when enabled. 0.7 09691-102 The AVDD33 supply powers the DAC core circuitry. The power dissipation of the AVDD33 supply rail is independent of the digital operating mode and sample rate. The current drawn from the AVDD33 supply rail is typically 54 mA (188 mW) when the fullscale current of the I and Q DACs is set to the nominal value of 20 mA. Changing the full-scale current directly affects the supply current drawn from the AVDD33 rail. For example, if the full-scale current of the I DAC and the Q DAC is changed to 10 mA, the AVDD33 supply current drops by 20 mA to 34 mA. 0.9 POWER DISSIPATION (W) The AD9146 has three supply rails: AVDD33, DVDD18, and CVDD18. Figure 59. Total Power Dissipation vs. fDATA Without PLL and Inverse Sinc Rev. 0 | Page 42 of 52 AD9146 The Tx enable feature also allows for an extended delay from when the TXENABLE pin is brought high to when the DAC outputs begin transmitting the data present in the FIFO and datapath. Two different delay lengths are available. These delays allow the part to be set up properly during the delay time without transmitting false data and to begin receiving correct data after the datapath is flushed. The amount of delay time to be allotted for various wake-up times depends on the delay setting used, as well as which portions of the DAC are powered down and need to be reinitialized. Table 23 lists the minimum wait time required for the DAC to begin transmitting again after the TXENABLE pin is brought high. Regardless of the delay setting, there is an inherent fixed delay of 10 DAC clock cycles for all the options listed in Table 23 before the DAC begins transmitting. Additionally, because the Tx enable logic is timed from a divided-down rate of the DAC clock—specifically, DAC/64—the number of edges that the part waits for before allowing data to be transmitted from the DAC can vary. Because the synchronization between the DAC/64 clock and the Tx enable logic trigger is unknown, the number of DAC/64 clock edges that must be waited for before the outputs are released can vary by up to one cycle. Table 23. Wake-Up Time for Various Tx Enable Delay Settings Register 0x02 No extended delay (0x00) Extended Delay 0 (0x20) Extended Delay 1 (0x60) Number of DAC/64 Edges to Wait1 1 Additional DAC Edges to Wait 10 Minimum Wait Time2 360.82 ns 12 10 4.18 μs 19 10 6.611 μs • • • • • • • • fDATA = 184.32 MHz fDAC = 737.28 MHz Interpolation = 4× Inverse sinc on Tx enable filter power-down option selected Datapath flush time = 175 DAC clocks tDAC = 1.36 ns tDPFLUSH = 238 ns The minimum wake-up time with no delay setting is 360.82 ns (see Table 23). In this example, the time required to flush the datapath is only 238 ns. Therefore, if datapath flushing is done simultaneous to the TXENABLE pin being brought high, there is enough time for the flush to complete before the minimum possible time that the outputs can begin transmitting. For each individual case, the amount of time needed to flush the datapath must be accounted for when calculating the minimum time after which the DACs can begin transmitting data. The TXENABLE pin must be held high while the part is being powered up. After the part is powered up, the pin can be brought low to clamp the outputs, when desired. Note that the pin cannot be held low during power-up because the circuit logic is transition sensitive and the part must see a falling edge before it clamps the outputs. TEMPERATURE SENSOR 1 Values may vary by up to one DAC/64 cycle for the amount of wake-up time of each delay setting. 2 Values based on 737.28 MHz DAC rate condition; uses (number of DAC/64 + 10 DAC clocks) for calculation. For timing purposes and to ensure that incorrect data is flushed, the minimum wake-up time must be considered. This constraint determines how soon the datapath must begin to be flushed. Depending on which portions of the DAC are powered down using the Tx enable feature, the amount of time required to start setting up the part and flushing the datapaths must be adjusted. An appropriate delay setting is required to accommodate the earliest possible wake-up time needed for flushing before the outputs are enabled. In addition to the delays listed in Table 23, specific wake-up times for individual powered-down portions of the AD9146 must be accounted for during the preparation time. The following example provides a typical configuration that uses the Tx enable feature to power down the interpolation filters. This example provides guidelines for how to determine the amount of wake-up time to design in a system. The AD9146 has a band gap temperature sensor for monitoring the temperature change of the AD9146. The temperature must be calibrated against a known temperature to remove the partto-part variation on the band gap circuit used to sense the temperature. The DACCLK must be running at a minimum of 100 MHz to obtain a reliable temperature measurement. To monitor temperature change, the user must take a reading at a known ambient temperature for a single-point calibration of each AD9146 device. Tx = TREF + 7.7 × (Code_x − Code_ref)/1000 + 1 where: Code_x is the readback code at the unknown temperature, Tx. Code_ref is the readback code at the calibrated temperature, TREF. To use the temperature sensor, it must be enabled by setting Register 0x01, Bit 4, to 0. In addition, to obtain accurate readings, the die temperature range control register (Register 0x48) should be set to 0x02. Rev. 0 | Page 43 of 52 AD9146 MULTICHIP SYNCHRONIZATION Multiple devices are considered synchronized to each other when the state of the clock generation state machines is identical for all parts, and when time-aligned data is being read from the FIFOs of all parts simultaneously. Devices are considered synchronized to a system clock when there is a fixed and known relationship between the clock generation state machine and the data being read from the FIFO and a particular clock edge of the system clock. The AD9146 has provisions for enabling multiple devices to be synchronized to each other or to a system clock. The AD9146 supports synchronization in two different modes: data rate mode and FIFO rate mode. In data rate mode, the input data rate represents the lowest synchronized clock rate. In FIFO rate mode, the FIFO rate, which is the data rate divided by the FIFO depth of 8, represents the lowest rate clock. The advantage of FIFO rate synchronization is increased time between the setup and hold time windows for DCI changes relative to the DACCLK or REFCLK input. When the synchronization state machine is on in data rate mode, the elasticity of the FIFO is not used to absorb timing variations between the data source and the DAC, resulting in setup and hold time windows repeating at the input data rate. The method chosen for providing the DAC sampling clock directly affects the synchronization methods available. When the device clock multiplier is used, only data rate mode is available. When the DAC sampling clock is sourced directly, both data rate mode and FIFO rate mode synchronization are available. The following sections describe the synchronization methods for enabling both clocking modes and querying the status of the synchronization logic. The full synchronization methods described are used to align multiple dual DACs within one DACCLK cycle. To achieve synchronization within one DACCLK cycle, both the REFCLK and FRAME signals are required to perform back-end and front-end alignment. If synchronization does not need to be this accurate, other options can be used. In data rate mode or in FIFO rate mode, using soft alignment of the FIFO for multiple DACs synchronizes the DAC outputs within two data clock cycles (see the Serial Port Initiated FIFO Reset section). For more information about synchronization, see the AN-1093 Application Note, “Synchronization of Multiple AD9122 TxDAC+ Converters.” SYNCHRONIZATION WITH CLOCK MULTIPLICATION When using the clock multiplier to generate the DAC sample rate clock, the REFCLK input signal acts as both the reference clock for the PLL-based clock multiplier and as the synchronization signal. To synchronize devices, distribute the REFCLK signal with low skew to all the devices that need to be synchronized. Skew between the REFCLK signals of the different devices shows up directly as a timing mismatch at the DAC outputs. Because two clocks are shared on the same signal, an appropriate frequency must be chosen for the synchronization and REFCLK signals. The FRAME and DCI signals can be created in the FPGA along with the data. A circuit diagram of a typical configuration is shown in Figure 62. MATCHED LENGTH TRACES SYSTEM CLOCK FPGA REFCLKP/ REFCLKN FRAMEP/ FRAMEN DCIP/ DCIN LOW SKEW CLOCK DRIVER IOUT1P/ IOUT1N REFCLKP/ REFCLKN FRAMEP/ FRAMEN DCIP/ DCIN IOUT2P/ IOUT2N 09691-069 System demands may require that the outputs of multiple DACs be synchronized with each other or with a system clock. Systems that support transmit diversity or beamforming, where multiple antennas are used to transmit a correlated signal, require multiple DAC outputs to be phase aligned with each other. Systems with a time division multiplexing transmit chain may require one or more DACs to be synchronized with a system-level reference clock. Figure 62. Typical Circuit Diagram for Synchronizing Devices The Procedure for Synchronization When Using the PLL section outlines the steps required to synchronize multiple devices. The procedure assumes that the REFCLK signal is applied to all the devices, and that the PLL of each device is phase locked to it. The following procedure must be carried out on each individual device. Procedure for Synchronization When Using the PLL In the initialization of the AD9146, all the clock signals (DACCLK, DCI, FRAME, synchronization, and REFCLK) must be present and stable before the synchronization feature is turned on. Configure the AD9146 for data rate, periodic synchronization by writing 0xC8 to the sync control register (Register 0x10). Additional synchronization options are available (see the Additional Synchronization Features section). Read the sync status register (Register 0x12) to verify that the sync locked bit (Bit 6) is set high, indicating that the device achieved back-end synchronization, and that the sync lost bit (Bit 7) is low. These levels indicate that the clocks are running with a constant and known phase relative to the synchronization signal. Reset the FIFO by strobing the FRAME signal high for the time interval required to write two complete input data words. Resetting the FIFO ensures that the correct data is being read from the FIFO. This completes the synchronization procedure; all devices should now be synchronized. Rev. 0 | Page 44 of 52 AD9146 tSKEW REFCLKP(1)/ REFCLKN(1) REFCLKP(2)/ REFCLKN(2) tSDCI tHDCI 09691-070 DCIP(2)/ DCIN(2) FRAMEP(2)/ FRAMEN(2) Figure 63. Timing Diagram Required for Synchronizing Devices SAMPLE RATE CLOCK SYNC CLOCK LOW SKEW CLOCK DRIVER DACCLKP/ DACCLKN REFCLKP/ REFCLKN FRAMEP/ FRAMEN DCIP/ DCIN IOUT1P/ IOUT1N MATCHED LENGTH TRACES DACCLKP/ DACCLKN REFCLKP/ REFCLKN FRAMEP/ FRAMEN DCIP/ DCIN LOW SKEW CLOCK DRIVER IOUT2P/ IOUT2N 09691-071 FPGA Figure 64. Typical Circuit Diagram for Synchronizing Devices to a System Clock must be distributed with low skew to all the devices being synchronized. If the devices need to be synchronized to a master clock, use the master clock directly for generating the REFCLK input (see Figure 64). To maintain synchronization, the skew between the REFCLK signals of the devices must be less than tSKEW ns. When resetting the FIFO, the FRAME signal must be held high for the time interval required to write two complete input data words. A timing diagram of the input signals is shown in Figure 63. DATA RATE MODE SYNCHRONIZATION Figure 63 shows a REFCLK frequency equal to the data rate. Although this is the most common situation, it is not strictly required for proper synchronization. Any REFCLK frequency that satisfies the following equation is acceptable. (This equation is valid only when the PLL is used because only data rate mode is available with the PLL on.) The Procedure for Data Rate Synchronization When Directly Sourcing the DAC Sampling Clock section outlines the steps required to synchronize multiple devices in data rate mode. The procedure assumes that the DACCLK and REFCLK signals are applied to all the devices. The following procedure must be carried out on each individual device. fSYNC_I = fDACCLK/2N and fSYNC_I ≤ fDATA Procedure for Data Rate Synchronization When Directly Sourcing the DAC Sampling Clock where N = 0, 1, 2, or 3. As an example, a configuration with 4× interpolation and clock frequencies of fVCO = 1600 MHz, fDACCLK = 800 MHz, fDATA = 200 MHz, and fSYNC_I = 100 MHz is a viable solution. SYNCHRONIZATION WITH DIRECT CLOCKING When directly sourcing the DAC sample rate clock, a separate REFCLK input signal is required for synchronization. To synchronize devices, the DACCLK signal and the REFCLK signal Configure the AD9146 for data rate, periodic synchronization by writing 0xC8 to the sync control register (Register 0x10). Additional synchronization options are available (see the Additional Synchronization Features section). Read the sync locked bit (Register 0x12, Bit 6) to verify that the device is back-end synchronized. A high level on this bit indicates that the clocks are running with a constant and known phase relative to the synchronization signal. Rev. 0 | Page 45 of 52 AD9146 tDATA Reset the FIFO by strobing the FRAME signal high for two complete DCI periods. Resetting the FIFO ensures that the correct data is being read from the FIFO of each of the devices simultaneously. DACCLK/ REFCLK This completes the synchronization procedure; all devices should now be synchronized. DATA VALID WINDOW To ensure that each DAC is updated with the correct data on the same CLK edge, two timing relationships must be met on each DAC. • DCIP/DCIN and D[7:0]P/D[7:0]N must meet the setup and hold times with respect to the rising edge of DACCLK. REFCLK must also meet the setup and hold times with respect to the rising edge of DACCLK. When these conditions are met, the outputs of the DACs are updated within one DAC clock cycle of each other. The timing requirements of the input signals are shown in Figure 65. tHDCI Figure 66. Timing Diagram for Input Data Port (Data Rate Mode) DCI Delay Register 0x16, Bits[1:0] 00 01 10 11 DACCLKP(1)/ DACCLKN(1) DACCLKP(2)/ DACCLKN(2) Minimum Setup Time, tSDCI (ns) −0.07 −0.24 −0.39 −0.49 Minimum Hold Time, tHDCI (ns) 0.82 1.13 1.40 1.55 Sampling Interval (ns) 0.75 0.89 1.01 1.06 FIFO RATE MODE SYNCHRONIZATION tHSYNC REFCLKP(2)/ REFCLKN(2) tSDCI tSDCI tHDCI Table 24. DCI to DACCLK Setup and Hold Times tSKEW tSUSYNC tSDCI 09691-043 • DCI tHDCI 09691-072 DCIP(2)/ DCIN(2) FRAMEP(2)/ FRAMEN(2) Figure 65. Data Rate Synchronization Signal Timing Requirements, 2× Interpolation Figure 65 shows the synchronization signal timing with 2× interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is shown to be equal to the data rate. The maximum frequency at which the device can be resynchronized in data rate mode can be expressed as fSYNC_I = fDATA/2N where N is any non-negative integer. Generally, for values of N greater than or equal to 3, select the FIFO rate synchronization mode. When synchronization is used in data rate mode, the timing constraint between the DCI and DACCLK must be met according to Table 24. In data rate mode, the allowed phase drift between the DCI and DACCLK is limited to one DCI period. The DCI to DACCLK timing restriction is required to prevent corruption of the data transfer when the FIFO is constantly reset. The required timing between the DCI and DACCLK is shown in Figure 66. The Procedure for FIFO Rate Synchronization When Directly Sourcing the DAC Sampling Clock section outlines the steps required to synchronize multiple devices in FIFO rate mode. The procedure assumes that the DACCLK and REFCLK signals are applied to all the devices. The procedure must be carried out on each individual device. Procedure for FIFO Rate Synchronization When Directly Sourcing the DAC Sampling Clock Configure the AD9146 for FIFO rate, periodic synchronization by writing 0x88 to the sync control register (Register 0x10). Additional synchronization options are available (see the Additional Synchronization Features section). Read the sync locked bit (Register 0x12, Bit 6) to verify that the device is back-end synchronized. A high level on this bit indicates that the clocks are running with a constant and known phase relative to the synchronization signal. Reset the FIFO by strobing the FRAME signal high for two complete DCI periods. Resetting the FIFO ensures that the correct data is being read from the FIFO of each of the devices simultaneously. This completes the synchronization procedure; all devices should now be synchronized. To ensure that each DAC is updated with the correct data on the same CLK edge, two timing relationships must be met on each DAC. • • Rev. 0 | Page 46 of 52 DCIP/DCIN and D[7:0]P/D[7:0]N must meet the setup and hold times with respect to the rising edge of DACCLK. REFCLK must also meet the setup and hold times with respect to the rising edge of DACCLK. AD9146 Sync Status Bits When these conditions are met, the outputs of the DACs are updated within one DAC clock cycle of each other. The timing requirements of the input signals are shown in Figure 67. When the sync locked bit (Register 0x12, Bit 6) is set, it indicates that the synchronization logic has reached alignment. This alignment is determined when the clock generation state machine phase is constant. tSKEW DACCLKP(1)/ DACCLKN(1) Alignment takes from (11 + averaging) × 64 to (11 + averaging) × 128 DACCLK cycles. The sync locked bit can also trigger an IRQ, as described in the Interrupt Request Operation section. DACCLKP(2)/ DACCLKN(2) tSUSYNC tHSYNC When the sync lost bit (Register 0x12, Bit 7) is set, it indicates that a previously synchronized device has lost alignment. This bit is latched and remains set until cleared by overwriting the register. This bit can also trigger an IRQ, as described in the Interrupt Request Operation section. REFCLKP(2)/ REFCLKN(2) 09691-073 DCIP(2)/ DCIN(2) FRAMEP(2)/ FRAMEN(2) Figure 67. FIFO Rate Synchronization Signal Timing Requirements, 2× Interpolation Figure 67 shows the synchronization signal timing with 2× interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is shown to be equal to the FIFO rate. The maximum frequency at which the device can be resynchronized in FIFO rate mode can be expressed as fSYNC_I = fDATA/(8 × 2N) where N is any non-negative integer. ADDITIONAL SYNCHRONIZATION FEATURES Table 25 shows the required timing between the DACCLK and the synchronization clock when synchronization is used. This timing restriction applies to both data rate mode and FIFO rate mode. Table 25. Synchronization Setup and Hold Times Parameter tSKEW tSUSYNC tHSYNC Min −tDACCLK/2 100 330 Max +tDACCLK/2 Unit ps ps ps One-Time Synchronization When implementing the full multichip synchronization feature (with the REFCLK and FRAME signals aligned within one DACCLK cycle), the user may experience difficulty meeting the DACCLK to synchronization clock timing. In this case, a one-time synchronization method can be used. Before implementing the one-time synchronization, make sure that the synchronization signal is locked by checking both the sync signal locked and the sync signal lost flags (Bit 4 and Bit 5 in Register 0x06). It is also important that synchronization not be enabled before stable REFCLK signals are present from the FPGA or ASIC. For more information and a detailed flowchart of the one-time synchronization feature, see the AN-1093 Application Note, “Synchronization of Multiple AD9122 TxDAC+ Converters.” The sync phase readback bits (Register 0x13, Bits[7:0]) report the current clock phase in a 6.2 format. Bits[7:2] report which of the 64 states (0 to 63) the clock is currently in. When averaging is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, ¾). The lower two bits give an indication of the timing margin issues that may exist. If the synchronization sampling is error free, the fractional clock state should be 00. Timing Optimization The REFCLK signal is sampled by a version of the DACCLK. If sampling errors are detected, the opposite sampling edge can be selected to improve the sampling point. The sampling edge can be selected by setting Register 0x10, Bit 3 (1 = rising and 0 = falling). The synchronization logic resynchronizes when a phase change between the REFCLK signal and the state of the clock generation state machine exceeds a threshold. To mitigate the effects of jitter and prevent erroneous resynchronizations, the relative phase can be averaged. The amount of averaging is set by the sync averaging bits (Register 0x10, Bits[2:0]) and can be set from 1 to 128. The higher the number of averages, the more slowly the device recognizes and resynchronizes to a legitimate phase correction. Generally, the averaging should be made as large as possible while still meeting the allotted resynchronization time interval. Note that, if the average synchronization sampling result is in approximately the middle of the probability curve, the synchronization engine can be unstable, resulting in corrupted output. The value of the Sync Phase Request[5:0] bits (Register 0x11, Bits[5:0]) is the state to which the clock generation state machine resets upon initialization. By varying this value, the timing of the internal clocks, with respect to the REFCLK signal, can be adjusted. Every increment of the Sync Phase Request[5:0] value advances the internal clocks by one DACCLK cycle. This offset can be used for two purposes: to skew the outputs of two synchronized DAC outputs in increments of the DACCLK cycle, and to change the relative timing between the DAC output and the sync input (REFCLK). This may allow for a more optimal placement of the DCI sampling point in data rate synchronization mode. Rev. 0 | Page 47 of 52 AD9146 INTERRUPT REQUEST OPERATION The AD9146 provides an interrupt request output signal on Pin 34 (IRQ) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. The IRQ pin is an open-drain, active low output. Pull the IRQ pin high external to the device. This pin can be tied to the interrupt pins of other devices with open-drain outputs to wire-OR these pins together. When an interrupt enable bit is set low, the event flag bit reflects the current status of the EVENT_FLAG_SOURCE signal, and the event flag has no effect on the external IRQ pin. The latched version of an event flag (the INTERRUPT_SOURCE signal) can be cleared in two ways. The recommended way is by writing 1 to the corresponding event flag bit. A hardware or software reset also clears the INTERRUPT_SOURCE signal. INTERRUPT SERVICE ROUTINE The event flags provide visibility into the device. These flags are located in the two event flag registers, Register 0x06 and Register 0x07. The behavior of each event flag is independently selected in the interrupt enable registers, Register 0x04 and Register 0x05. When the flag interrupt enable is active, the event flag latches and triggers an external interrupt. When the flag interrupt is disabled, the event flag monitors the source signal, but the IRQ pin remains inactive. Interrupt request management starts by selecting the set of event flags that require host intervention or monitoring. The events that require host action should be enabled so that the host is notified when they occur. For events requiring host intervention upon IRQ activation, run the following routine to clear an interrupt request: 1. Figure 68 shows the IRQ-related circuitry and how the event flag signals propagate to the IRQ output. The INTERRUPT_ ENABLE signal represents one bit from the interrupt enable register. The EVENT_FLAG_SOURCE signal represents one bit from the event flag register. The EVENT_ FLAG_SOURCE signal represents one of the device signals that can be monitored, such as the PLL_LOCKED signal from the PLL phase detector or the FIFO_WARNING_1 signal from the FIFO controller. 2. 3. 4. 5. 6. When an interrupt enable bit is set high, the corresponding event flag bit reflects a positively tripped version of the EVENT_FLAG_ SOURCE signal; that is, the event flag bit is latched on the rising edge of the EVENT_FLAG_SOURCE signal. This signal also asserts the external IRQ pin. Read the status of the event flag bits that are being monitored. Set the interrupt enable bit low so that the unlatched EVENT_FLAG_SOURCE signal can be monitored directly. Perform any actions that may be required to clear the EVENT_FLAG_SOURCE. In many cases, no specific actions may be required. Read the event flag to verify that the actions taken have cleared the EVENT_FLAG_SOURCE. Clear the interrupt by writing 1 to the event flag bit. Set the interrupt enable bits of the events to be monitored. Note that some EVENT_FLAG_SOURCE signals are latched signals. These signals are cleared by writing to the corresponding event flag bit. For more information about each event flag, see Register 0x06 and Register 0x07 in Table 11. 0 1 EVENT_FLAG IRQ INTERRUPT_ENABLE EVENT_FLAG_SOURCE INTERRUPT_ SOURCE OTHER INTERRUPT SOURCES 09691-074 WRITE_1_TO_EVENT_FLAG DEVICE_RESET Figure 68. Simplified Schematic of IRQ Circuitry Rev. 0 | Page 48 of 52 AD9146 INTERFACE TIMING VALIDATION The SED has three flag bits (Register 0x67, Bit 5, Bit 1, and Bit 0) that indicate the results of the input sample comparisons. The sample error detected bit (Register 0x67, Bit 5) is set when an error is detected and remains set until cleared. The SED also provides registers that indicate which input data bits experienced errors (Register 0x70 through Register 0x73). These bits are latched and indicate the accumulated errors detected until cleared. The AD9146 provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED circuitry compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port. Differences between the captured values and the comparison values are detected and stored. Options are available for customizing SED test sequencing and error handling. Autosample error detection (AED) is an autoclear function in the SED. The autoclear mode has two effects: it activates the compare fail bit and the compare pass bit (Register 0x67, Bit 1 and Bit 0) and changes the behavior of Register 0x70 through Register 0x73. The compare pass bit is set if the last comparison indicated that the sample was error free. The compare fail bit is set if an error is detected. The compare fail bit is automatically cleared by the reception of eight consecutive error-free comparisons. When autoclear mode is enabled, Register 0x70 through Register 0x73 accumulate errors as previously described but are reset to all 0s after eight consecutive error-free sample comparisons are made. SED OPERATION The SED circuitry operates on a data set made up of four 16-bit input words divided into eight 8-bit input words, denoted as I0, Q0, I1, and Q1. To properly align the input samples, the first I data-word (that is, I0) is indicated by asserting FRAME for at least one complete input sample. Figure 69 shows the input timing of the interface in byte mode. The FRAME signal can be issued once at the start of the data transmission, or it can be asserted repeatedly at intervals coinciding with the I0 and Q0 data-words. DATA I0MSB I0LSB Q0MSB Q0LSB I1MSB I1LSB Q1MSB Q1LSB 09691-075 FRAME Figure 69. Timing Diagram of Extended FRAME Signal Required to Align Input Data for SED If desired, the sample error detected, compare pass, and compare fail flags can be configured to trigger the IRQ pin when active. This is done by enabling the appropriate bits in the event flag register (Register 0x07). Table 26 shows a progression of the input sample comparison results and the corresponding states of the error flags. Table 26. Progression of Input Sample Comparison Results and the Resulting SED Register Values Compare Results (Pass/Fail) Register 0x67, Bit 5 (sample error detected) Register 0x67, Bit 1 (compare fail) Register 0x67, Bit 0 (compare pass) Register 0x70 to Register 0x73 (Errors detected bits) 1 2 P 0 0 1 Z1 F 1 1 0 N2 F 1 1 0 N2 F 1 1 0 N2 P 1 1 1 N2 Z = all 0s. N = nonzero. Rev. 0 | Page 49 of 52 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 0 1 Z1 F 1 1 0 N2 P 1 1 1 N2 F 1 1 0 N2 AD9146 4. SED EXAMPLE Normal Operation 5. The following example illustrates the SED configuration for continuously monitoring the input data and assertion of the IRQ pin when a single error is detected. 1. 2. 3. Load the following comparison values. (Comparison values can be chosen arbitrarily; however, choosing values that require frequent bit toggling provides the most robust test.) Register 0x68: I0LSB Register 0x69: I0MSB Register 0x6A: Q0LSB Register 0x6B: Q0MSB Register 0x6C: I1LSB Register 0x6D: I1MSB Register 0x6E: Q1LSB Register 0x6F: Q1MSB Enable the SED error detect flag to assert the IRQ pin. (Set Register 0x05 to 0x04.) Begin transmitting the input data pattern. Write to Register 0x67 to enable the SED. (Set Register 0x67 to 0x80.) Clear the SED errors in Register 0x67 and Register 0x07. When the SED is first turned on, the FRAME signal may be detected immediately; therefore, the SED failure bit may be asserted due to the unknown initial FRAME status. For this reason, the SED compare fail status bit must be cleared at least once immediately after enabling the SED. If IRQ is asserted, read Register 0x67 and Register 0x70 through Register 0x73 to verify that a SED error was detected and to determine which input bits were in error. The bits in Register 0x70 through Register 0x73 are latched; therefore, the bits indicate any errors that occurred on those bits throughout the test (not only the errors that caused the error detected flag to be set). Enabling the alignment of the I0 sample as described in the SED Operation section requires the use of the FRAME signal. The timing diagrams for byte and nibble modes are the same as during normal operation and are shown in Figure 33 and Figure 34, respectively. Rev. 0 | Page 50 of 52 AD9146 EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9146, certain sequences should be followed. This section shows an example start-up routine. This example uses the configuration described in the Device Configuration section. Device Configuration Register Write Sequence: 0x00 Æ 0x20 /* Issue Software Reset */ 0x00 Æ 0x80 /* Enable 3-wire SPI */ 0x1E Æ 0x01 DEVICE CONFIGURATION The following device configuration is used for this example. /* Start PLL */ • • • • • • • • 0x0C Æ 0xE1 fDATA = 122.88 MSPS Interpolation is 4×, using HB1 = 10 and HB2 = 010010 Input data is baseband data fOUT = 140 MHz fREFCLK = 122.88 MHz PLL is enabled Inverse sinc filter is enabled Synchronization is enabled 0x0D Æ 0xD9 0x0A Æ 0xCF 0x0A Æ 0xA0 /* Verify PLL is Locked */ DERIVED PLL SETTINGS The following PLL settings can be derived from the device configuration. • • • • Read 0x0E /* Expect bit 7 = 0, bit 6 = 1 */ Read 0x06 /* Expect 0x5C */ 0x10 Æ 0x48 /* Choose Data Rate Mode */ 0x17 Æ 0x04 fDACCLK = fDATA × interpolation = 491.52 MHz fVCO = 4 × fDACCLK = 1966.08 MHz (1 GHz < fVCO < 2 GHz) N1 = fDACCLK/fREFCLK = 4 N2 = fVCO/fDACCLK = 4 /* Issue Software FIFO Reset */ 0x18 Æ 0x02 0x18 Æ 0x00 /* Verify FIFO Reset */ START-UP SEQUENCE Read 0x18 /* Expect 0x05 */ The following sequence configures the power clock and register write sequencing for reliable device start-up. Read 0x19 /* Expect 0x07 */ Power up Device (no specific power supply sequence is required) 0x1B Æ 0xA4 /* Enable Inverse Sinc */ Apply stable REFCLK input signal. Apply stable DCI input signal. /* Configure Interpolation Filters */ 0x1C Æ 0x04 0x1D Æ 0x24 Rev. 0 | Page 51 of 52 AD9146 OUTLINE DIMENSIONS 0.30 0.23 0.18 PIN 1 INDICATOR 37 36 48 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.45 0.40 0.35 EXPOSED PAD 24 SEATING PLANE 5.65 5.60 SQ 5.55 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF PIN 1 INDICATOR 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD. 02-14-2011-B 7.10 7.00 SQ 6.90 Figure 70. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 7 mm × 7 mm Body, Very Very Thin Quad (CP-48-13) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9146BCPZ AD9146BCPZRL AD9146-M5375-EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 48-lead LFCSP_WQ 48-lead LFCSP_WQ Evaluation Board Connected to ADL5375 Modulator Z = RoHS Compliant Part. ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09691-0-4/11(0) Rev. 0 | Page 52 of 52 Package Option CP-48-13 CP-48-13