STV0196B QPSK/BPSK DEMODULATOR AND FEC IC .. . . . FRONT-END INTERFACE I AND Q 6 BITS DIGITAL INPUTS AT 2Fs QPSK DEMODULATION (Two Modes : A and B) INPUT SYMBOL FREQUENCY (Fs) UP TO 30MSYMBOLS/S DIGITAL NYQUIST ROOT FILTER : ROLL-OFF VALUE OF 0.35 IN MODE A DIGITAL CARRIER LOOP : - ON-CHIP DEROTATOR AND TRACKING LOOP - CARRIER OFFSET INDICATOR - LOCK DETECTOR - C/N INDICATOR FOR DISH POSITIONING . . . DIGITAL TIMING RECOVERY : - INTERNAL TIMING ERROR EVALUATION AND FILTER - OUTPUT CONTROL SIGNAL FOR A 2Fs EXTERNAL VCO OR VCXO DIGITAL AGC : - INTERNAL SIGNAL POWER ESTIMATION AND FILTER - OUTPUT CONTROL SIGNAL FOR AGC (1 BIT PULSE DENSITY MODULATION) DESCRIPTION Designed for the fast growing direct broadcast satellite (DBS) digital TV receiver market, the SGS-THOMSON STV0196B Digital Satellite Receiver Front-end integrates all the functions needed to demodulate incoming digital satellite TV signals from the tuner : Nyquist filters, QPSK/BPSK demodulator, signal power estimator, automatic gain control, Viterbi decoder, deinterleaver, ReedSolomon decoder and energy dispersal descrambler. This high level of integration greatly reduces the package count and cost of a set top box. The demodulator blocks are suitable for a wide range of symbol rates while the advanced error correction functions guaranteea low error rate even with small receiver antennas or low power transmitters. The STV0196B has multistandard capability. It is fully compliant with the recently defined Digital Video Broadcasting (DVB) standard (already adopted by satellite TV operators in the USA, Europe and Asia) and also compatible with the main consumer digital satellite TV standards in use. FORWARD ERROR CORRECTION INNER DECODER : - VITERBI SOFT DECODER FOR CONVOLUTIONAL CODES, CONSTRAINT LENGTH M = 7, RATE 1/2 - PUNCTURED CODES 1/2, 2/3, 3/4, 5/6 AND 7/8 IN MODE A - AUTOMATIC OR MANUAL RATE AND PHASE RECOGNITION . . . DEINTERLEAVER : - WORD SYNCHRO EXTRACTION - CONVOLUTIVE DEINTERLEAVER OUTER DECODER : - IN MODE A : REED-SOLOMON DECODER FOR 16 PARITY BYTES ; CORRECTION OF UP TO 8 BYTE ERRORS - BLOCK LENGTHS : 204 IN MODE A - ENERGY DISPERSAL DESCRAMBLER PQFP64 (Plastic Package) ORDER CODE : STV0196B CONTROL I2C SERIAL BUS September 1996 1/23 STV0196B VSS VDD I5 I4 I3 I2 I1 I0 Q5 Q4 Q3 Q2 Q1 Q0 TEST TEST PIN CONNECTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 TEST 1 48 M_CLK TEST 2 47 MODE VS S 3 46 CLKREC VDD 4 45 VDD TEST 5 44 AGC TEST 6 43 VDD VS S 7 42 VS S VDD 8 41 VS S VS S 9 40 SDA VDD 10 39 SCL VS S 11 38 VDD VDD 12 37 VS S TEST 13 36 NRES TEST 14 35 D60 TEST 15 34 ERROR TEST 16 33 D/P 2/23 0196B-01.EPS VSS VDD STR_OUT CK_OUT VSS VDD D7 D6 D5 D4 D3 D2 D1 D0 TEST TEST 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 STV0196B PIN LIST Pin Number Pin Name Type Pin Description I [5..0] Q [5..0] M_CLK I I I In Phase Component, at twice the symbol frequency (2Fs). In Quadrature Component, at twice the symbol frequency (2Fs). Master Clock Input, 2Fs. Sampling Clock of the External A to D Converters. CLKREC AGC D60 O O O 1 Bit Control Signal for the External CLK VCO. It must be Low-pass Filtered. 1 Bit Control Signal for the External AGC. It must be Low-pass Filtered. M_CLK Divided by 60 D [7..0] O Output Data CK_OUT STR_OUT D/P ERROR O O O O Output Byte Clock Output Synchronization Byte Signal Data/Parity Signal Output Error Signal. Set in Case of uncorrected Block. SIGNAL INPUTS 51, 52, 53, 54, 55, 56 57, 58, 59, 60, 61, 62 48 FRONT END CONTROLS 46 44 35 SIGNAL OUTPUTS 26, 25, 24, 23, 22, 21, 20, 19 29 30 33 34 2 I C MICRO INTERFACE 39 40 SCL SDA I I/O Serial Clock Serial Data Bus 47 1, 2, 5, 6, 13, 14, 15, 16, 17, 18, 63, 64 3, 7, 9, 11, 28, 32, 37, 41, 42, 49 4, 8, 10, 12, 27, 31, 38, 43, 45, 50 36 MODE TEST I O 0 = Mode A, 1 = Mode B Reserved for Manufacturing Test. It must remain unconnected VSS I Ground References VDD I 3.3V Supply NRES I Negative Reset 0196B-01.TBL OTHER BLOCK DIAGRAM I[5...0] Q[5...0] CLKREC D60 NYQUIST FILTER DEROTATOR AGC TIMING RECOVERY DCO LOCK INDICATOR CARRIER OFFSET MEASURE CARRIER PHASE TRACKING LOOP C/N INDICATOR DIVIDE BY 60 VITERBI DECODER I2C BUS INTERFACE DEINTERLEAVER AGC M_CLK SCL SDA D/P REED SOLOMON DECODER ERROR STR_OUT CK_OUT 0196B-02.EPS ENERGY DESCRAMBLER MODE STV0196B VDD VSS D[7..0] 3/23 STV0196B FUNCTIONAL DESCRIPTION I - I2C BUS SPECIFICATION This is the standard I2C protocol. The device address is ”1101000” ; the first byte is therefore Hex D0 for a write operation and Hex D1 for a read operation. I.1 The The The The The The Write Operation first byte is the device address plus the direction bit (R/W = 0). second byte contains the internal address of the first register to be accessed. next byte is written in the internal register. following (if any) bytes are written in successive internal registers. transfer lasts until stop conditions are encountered. STV0196B acknowledges every byte transfer. I.2 - Read Operation The address of the first register to read is programmed in a write operation without data, and terminated by stop condition. Then another start is followed by the device address and R/W = 1 ; all successive bytes are now data read at successive positions starting from the initial address. The STV0196B acknowledges every byte transfer. Example : Write registers 0 to 3 with AA,BB,CC,DD Device Address, Write D0 Start Internal Address ACK ACK Data AA ACK Data BB ACK Data CC ACK Stop ACK Stop ACK Stop Read registers 2 and 3 Device Address, Write D0 Start Device Address, Read D1 Start ACK ACK Register Address 01 Data Read BB Data Read CC ACK I.3 - Identification Register This read only register gives the release number of the circuit in order to ensure software compatibility. The read value is Hex 83 for STV0196B and Hex 81 for STV0196. Internal Address : Hex 0B 1 0 0 0 Notes : - Unspecified register addresses must not be used. - All the unused bits in the registers must be programmed to 0. 4/23 0 0 1 1 STV0196B FUNCTIONAL DESCRIPTION (continued) I.4 - Register Map REGISTER HEX 00 INPUT CONFIGURATION REGISTER (R/W) Reset Value : Hex 04 0 -Q(1) or Q(0) input 1 Signed (1) or positive (0) I & Q inputs 2 Nyquist filtering on (1) / off (0) 3 BPSK (1), QPSK(0) 4 To be set to 0. 5 To be set to 0. 6 To be set to 0. 7 To be set to 0. REGISTER HEX 08 VSTATUS REGISTER (Read only) 0 PR[2..0] Current puncture rate identification 1 2 3 LK (1) synchro found, (0) searching puncture rate 4 PRF (1) puncture rate found, (0) searching puncture rate 5 unused set to (0) 6 unused set to (0) 7 CF (1) carrier found, (0) searching carrier REGISTERS HEX 01 TO HEX 05 VITERBI, PUNCTURE RATE THRESHOLDS (R/W) Reset Value : Hex 20 rate Hex01 VTH0 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0 1/2 Hex02 VTH1 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0 2/3 Hex03 VTH2 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0 3/4 Hex04 VTH3 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0 5/6 7/8 Hex05 VTH4 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0 or 6/7 REGISTER HEX 06 VSEARCH (VITERBI) (R/W) Reset Value : Hex 19 0 H[1..0] Sync counter hysteresis value 1 2 T[1..0] Sync search time out 3 4 VITERBI error rate averaging period. SN[1..0] C/N indicator averaging period. 5 6 F VITERBI operating status freeze (1) 7 A/M (0) automatic, (1) manual REGISTER HEX 07 VERROR REGISTER (Read only) REGISTER HEX 09 PUNCTURE RATE ENABLE (R/W) Reset Value : Hex 10 (mode A) 0 E0 (1) Puncture 1/2 enabled, (0) disabled 1 E1 (1) Puncture 2/3 enabled, (0) disabled 2 E2 (1) Puncture 3/4 enabled, (0) disabled 3 E3 (1) Puncture 5/6 enabled, (0) disabled 4 E4 (1) Puncture7/8 (mode A), 6/7 (mode B) (0) disabled 5 unused 6 7 REGISTER HEX 0A RS REGISTER (R/W) Reset Value : Hex B8 0 RS0 (1) output clock stopped during parity, (0) continuous 1 RS1 Output clock polarity 2 RS2 (1) all synchro words are Hex47, (0) synchro inversion disabled 3 RS3 Write error bit 4 RS4 Descrambler on (1), off (0) 5 RS5 Reed-Solomon on (1), off (0) 6 RS6 Normal operation (0), Reed-Solomon correction bytes to output (1) 7 RS7 De-interleaver on (1), off (0) 5/23 STV0196B FUNCTIONAL DESCRIPTION (continued) I.4 - Register Map (continued) REGISTER HEX 0B IDENTIFICATION REGISTER (Read only) Reset Value : Hex83 for STV0196B, Hex 81 for STV0196 REGISTER HEX 0C TIMING LOOP : TIME CONSTANT (R/W) Reset Value : Hex 45 0 1 beta_tmg coefficient 2 3 4 alpha_tmg coefficient 5 6 7 Istr external VCO/VCXO slope polarity (0) positive, (1) negative REGISTER HEX 10 CARRIER OFFSET EVALUATOR (Read only) Signed value ranging from 80 to 7F. REGISTER HEX 11 AGC CONTROL REGISTER (R/W) Reset Value : 18 Hex. 0 1 2 AGC reference level m 3 4 5 6 unused 7 Iagc REGISTER HEX 0D TIMING FREQUENCY REGISTER (R/W) Signed value ranging from 80 to 7F. REGISTER HEX 12 AGC INTEGRATOR (R/W) Signed value ranging from 80 to 7F. REGISTER HEX 0E CARRIER LOOP REGISTER (R/W) Reset Value : Hex A3 0 beta_carrier coefficient 1 2 3 unused 4 alpha_carrier coefficient 5 6 7 Deratator on (1), off (0) REGISTER HEX 13 AGC COEFFICIENT 0 G[2..0] AGC coefficient 1 2 3 4 unused 5 6 7 REGISTER HEX 0F DEROTATOR FREQUENCY REGISTER (R/W) Signed value ranging from 80 to 7F. REGISTER HEX 14 C/N INDICATOR (Read only) Value ranging from 00 to FF. 6/23 STV0196B FUNCTIONAL DESCRIPTION (continued) II - ADC INTERFACE II.1 - M_CLK Master Clock Input IV - TIMING RECOVERY This is the highest frequency clock of the chip, at twice the symbol frequency; all other clocks are derived from it. This clock should be output from an external VCO or VCXO, controlled by CLKREC output. M_CLK divided by 60 is available to the system (output D60). II.2 - I and Q Signal Inputs Those signals are coded on 6 bits, either in 2’s complement or as positive values : the choice is programmable via the Input Configuration register. The π/2 ambiguity inherent in QPSK is solved in the Error Correction part. A programmable bit in a mode register allows to multiply by -1 the data on Q input, in order to accommodate QPSK modulation with another convention of rotation sense ; (this is equivalent to a permutation of I and Q inputs, or a spectral symmetry). The timing loop comprises an external VCO or VCXO, running at twice the symbol frequency, controlled by the output CLKREC ; this signal is a pulse density modulated output, at the symbol frequency, and represents the filtered timing error. The loop is parametrised by two coefficients : alpha_tmg and beta_tmg ; the 12 bit filter output is converted into a pulse density modulation signal which should be filtered by an analog low pass filter before commanding the VCO. IV.1 - Timing Loop Registers Time Constant Register Internal Address : Hex0C Reset Value : Hex45 Istr Invert bit III - NYQUIST ROOT FILTER 0 0 1 0 0 -Q(1) or Q(0) input 0 Signed (1) or positive (0) I&Q Inputs 0 Nyquist filtering on (1)/off (0) 0 BPSK(1), QPSK(0) Input Configuration Register (the written value of each bit is the reset value) Internal Address : Hex00 0 0 alpha_tmg (1 to 6) 0 1 0 1 beta_tmg (0 to 9) The bit ”Istr” allows to change the polarity of the output signal, in order to accommodate both possibilities of external VCO : Istr 0 The I and Q components are filtered by a digital Nyquist root filter with the following features : - Input : separate I and Q streams, two samples per symbol. - Excess bandwidth : 0.35 in Mode A. - The filters may be bypassed ; in this case, the input flow is connected to the carrier and clock recovery section. 1 1 Loop Control VCO frequency raises when output average voltage raises VCO frequency decreases when output average voltage raises Timing Frequency Register Internal Address : Hex0D Signed number The value of this register, when the system is locked, is an image of the frequencyoffset; it should be as close as possible to 0 in order to have a symmetric capture range ; reading it allows optimal trimming of the timing VCO range. IV.2 - Loop Equations The external VCO is controlled by the output CLKREC followed by a low pass filter. The full analog swing of the output originates a relative frequency shift of 2∆f , depending on the characteristics of the external VCO (typically a fraction of percent). The frequency range is therefore f = f0 ( 1 ± ∆f). Neglecting the analog low pass filter on the pulse modulated output, this loop may be considered as a second order loop. 7/23 STV0196B FUNCTIONAL DESCRIPTION (continued) The natural frequency and the damping factor may be calculated by the following formulas : Fs ωn = √ β K0 Kd fn = 2π 2π where β is programmed by the timing register : β = 2beta_tmg. ∆f . 226 Kd is the phase detector ; its value depends on : Kd = 0.977m2 (in Mode A), the roll-off value and on the power of the signal. or Kd = 0.564m2 (in Mode B). where m is the programmed reference level (see AGC part), reset value : m = 24 Fs is the symbol frequency, ∆f is the half range of the VCO K0 is the constant of the VCO : K0 = Therefore fn = 19.2 10−6 ⋅ m ⋅ Fs ⋅ √ ∆f 2beta_tmg (Mode A) −6 beta_tmg or fn = 14.6 10 ⋅ m ⋅ Fs ⋅ √ ∆f 2 (Mode B) The damping factor is : ξ = α 2 K0Kd √ β with α = 2 alpha_tmg + 12 0.247 ⋅ m ⋅ √ ∆f ⋅ 2 alpha_tmg 0.188 ⋅ m ⋅ √ ∆f ⋅ 2alpha_tmg (Mode A) or ξ = (Mode B). √ 2 beta_tmg √ 2beta_tmg beta_tmg can only take value from 0 to 9 ; if beta_tmg = 0, the loop becomes a first order one. alpha_tmg can take any value from 1 to 6 ; if both alpha_tmg and beta_tmg are null, the loop is open ; the duty cycle of the CLKREC output is controlled by writting the timing frequency register. The next curve shows the natural frequency for a symbol frequency of 20Mbd, in Mode A, with nominal reference level m = 24 as a function of the VCO relative frequency half range ∆f, for different values of the register value beta_tmg. The followingchart gives the value of the damping factor as a function of the VCO relative range, for different combinations of alpha_tmg and beta_tmg, noticing that the damping factor only depends on the value of α or (2 . alpha_tmg - beta_tmg ). β √ or ξ = 8/23 STV0196B FUNCTIONAL DESCRIPTION (continued) Figure 1 : Natural Frequency for Fs = 20MBauds 100 be ta_tmg 9 8 7 6 5 4 3 2 1 10 1 0.1 0.0001 0.001 0196B-03.EPS NATURAL FREQUENCY (kHz) res e t value 0.01 VCO Re lative Fre quency Ra nge (∆f) Figure 2 : Damping Factor 10 8 7 re se t value 6 5 4 KSI 3 2 1 1 0 2alpha_tmg - beta _tmg 0.0001 0.001 0196B-04.EPS 0.1 0.01 VCO Relative Frequency Ra nge (∆f) Example : the VCO is trimmed from 39.9MHz to 40.1MHz when the VCO control output CLKREC goes from duty cycle 0 to 100%. The peak-to-peak relative range is therefore 0.5% and ∆f = 0.0025 ; the reset values of the parameters (alpha_tmg = 4, beta_tmg = 5) leads to a natural frequency of 2.6kHz, with a damping factor of 0.84. 9/23 STV0196B FUNCTIONAL DESCRIPTION (continued) The shaded area correspond to the reset values. V - CARRIER RECOVERY ; DEROTATOR The input of the circuit is a pair of demodulated signals ; however, there may subsist some phase error not corrected by the front end loop. Furthermore, the demodulation may be done at constant frequency; the tuner is trimmed in order to make the useful signal bandwidth centered on this demodulation frequency ; in that case, a carrier offset frequencymay subsist; it is fixed by the mean of the on-chip derotator which acts as a fine tuning carrier loop. The derotator frequency range is limited to an interval corresponding to ±Fs/16. V.1 - Loop Parameters Like the timing loop, the carrier loop is a second order system where two parameters α and β may be programmed respectively with alpha_car and beta_car. Carrier Loop Parameter Registers Internal Address : Hex0E Derotator ON/OFF 1 0 1 0 0 alpha_carrier 0 1 1 beta_carrier Derotator Frequency Register Internal Address : Hex0F beta_car (reg. value) 0 1 2 3 4 5 6 7 Tn = 2π/ωn (symb per) NA 907 642 454 321 227 160 113 22 31 44 62 88 125 177 NA NA NA fn (kHz) for F = 20Mbd alpha_car (reg. value) Damping Factor 0 NA NA NA NA 1 NA 0.89 0.63 0.44 0.31 0.22 0.16 0.11 2 NA 1.77 1.25 0.89 0.63 0.44 0.31 0.22 3 NA 3.54 2.51 1.77 1.25 0.89 0.63 0.44 4 NA 7.09 5.01 3.54 2.51 1.77 1.25 0.89 5 NA 14.18 10.03 7.09 5.01 3.54 2.51 1.77 VI - CARRIER OFFSET EVALUATOR An 8 bit register may be read at any time; it gives a signed value proportionnal to the carrier frequency offset according to the expression : ∆f = 1.8 . 10-6 . m2 . N . Fs (in mode A) where Fs is the symbol frequency, m the symbol module (AGC reference), N the read value. The maximum value for N is reached in nominal conditions for a carrier offset of 16% of Fs ; if greater, N remains saturated, giving a reliable sign indication over more than ±50% Fs range. Carrier Offset Register Internal Address : Hex10 Signed number This 8 bit R/W register may be written at any time to force the central frequency of the derotator to start the carrier research, or read, when the loop is locked,in order to know the current carrier offset (one LSB correspond to Fs/2048). V.2 - Loop Equations The natural pulsation is : ωn = 10−3 ⋅ fs ⋅ √ m ⋅ 2beta_car and the damping factor is : m ξ = 0.128 ⋅ 2alpha_car ⋅ √ . beta_car 2 where m is the reference value (see AGC registers). The next table gives for the nominal amplitude m = 24 the natural period (in symbols), and the damping factor for the possible values of alpha_car. As an example, the corresponding natural frequency is given assuming a symbol frequency of 20MBauds. 10/23 NA Signed number VI.1 - Lock Indicator This 1 bit Carrier Found flag may be read (see Viterbi Status register) at any time ; it indicates that a QPSK signal is found, and that the carrier loop is closed ; This flag allows to detect false lock that can happen if the loop bandwidth is small regarding the frequency offset. VII - CARRIER TO NOISE INDICATOR Internal Address : Hex14. Read only register. b7 b6 b5 b4 b3 b2 b1 b0 This register can be used to estimate the carrier to noise level (Eb/No) in a range from 4 to 16dB. The register value dependson both the AGC reference level ”m” (see paragraph VIII) and the control bits ”SN[1..0]” (see paragraph IX). For more details about how to use this register, please refer to the Annexe 1. STV0196B FUNCTIONAL DESCRIPTION (continued) VIII - AGC CONTROL IX - VITERBI DECODER AND SYNCHRONIZATION The modulusof the input is compared to a programmable threshold; the difference is scaled by the AGC coefficient, then integrated; the result is converted into a pulse density modulation signal to drive the AGC output ; it may be filtered by a simple analogue filter to control the gain command of any amplifier before the A to D converter. The convolutives codes are generated by the polynoms Gx = 171oct and Gy = 133oct. The Viterbi decoder computes for each symbol the metrics of the four possible paths, proportional to the square of the Euclidian distance between the received I and Q and the theoretical symbol value. The puncture rate and phase are estimated on the error rate basis. Five rates are allowed and may be enabled/disabled through register programming : 1/2, 2/3, 3/4,5/6, 7/8. In Mode B, 7/8 is replaced by 6/7. For each enabled rate, the current error rate is compared to a programmable threshold; if it is greater, anotherphase (or anotherrate) is tried until the good rate is obtained. A programmable hysteresis is added to avoid to loose the phase during short term perturbation. The rate may also be imposed by the external software, and the phase is incremented only on micro request ; the error rate may be read at any time in order to use other algorithm than implemented. The decoder is accessed via a set of 9 registers : The 8 integrator MSB’s may be read or written at any time by the micro; when written, the LSB’s are reset. The integrator value is the level of the AGC output, after low pass filtering ; it gives an image of the input signal power, whatever this signal is, and can be used to point the antenna. The coefficient may be reset by programmation; in that case, the AGC reduces to a programmable voltage synthesiser. The AGC reference level ”m” value impacts the value of the following functions : - carrier to noise indicator (see paragraph VII) - the carrier loop (see paragraph V.2) - the timing loop (paragraph IV.2) - carrier offset evaluator (paragraph VI) Control Registers Internal Addresses : Hex11 Iagc 0 0 Invert signal Reserved 1 1 0 0 0 AGC reference level (”m”) Threshold Value Internal Addresses : Hex12 AGC integrator value (signed) (Read/write register) Internal Addresses : Hex13 0 0 0 Reserved Threshold Registers (VTH0 to VTH4) Internal Address : Hex1 (VTH0) to 5 (VTH4) Reset Value : Hex20 0 0 0 1 0 G[2..0] : AGC coefficient The 8 bit signed value in the integrator is the image of the AGC output; reading this value gives an image of the RF signal power. A constant error on the modulus leads to a ramp at the output of the integrator with value : AGC_Int = 2AGC_Coeff-16 . error As a consequence, for the reset conditions, a constant signal of null value (error = 24) should cause the output AGC duty cycle to go from 100% to 0% in 222 symbol periods, or 8.7ms at 20MBauds. If Iagc is set, the sign of the integrator is inverted. VTH0 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0 rate 1/2 VTH1 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0 rate 2/3 VTH2 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0 rate 3/4 VTH3 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0 rate 5/6 VTH4 0 Th6 Th5 Th4 Th3 Th2 Th1 Th0 rate 7/8 or 6/7 For each register, bits 6 to 0 represent an error rate threshold : the average number of errors happening during 256 bit periods; the maximum programmable value is 127/256 (higher error rates are of no practical use). Puncture Rate Enable register Internal Address : Hex09 Reset Value : Hex10 (Mode A) 0 E4 : E3 : E2 : E1 : E0 : 0 0 E4 E3 E2 E1 E0 enablePuncturedRate 7/8(Mode A)or6/7(Mode B) enable Punctured Rate 5/6 enable Punctured Rate 3/4 enable Punctured Rate 2/3 enable Basic Rate 1/2 11/23 STV0196B FUNCTIONAL DESCRIPTION (continued) IX - VITERBI DECODER AND SYNCHRONIZATION (continued) Other Registers VSEARCH Internal Address : Hex06 A/M F SN [1..0] TO [1..0] H [1..0] A/M : Automatic/manual F : Freeze SN [1..0] : Averaging period. It gives the number of bits required to calculate the rate error : SN [1..0] Number of bits 00 1.024 01 4.096 10 16.384 11 65.536 Reset Value : SN=01 (4096 bits) The SN[1..0] bits also inpacts the C/N indicator (see paragraph VII). TO [1..0] : Time out value. It programs the maximum durationof the synchro word research in automatic mode; if no sync is found within this duration, the phase is incremented. Time out (in 1024 bit periods) 00 16 01 32 10 64 11 128 Reset Value : TO=10 (64K bit periods). synchro found ; this is the default (reset) mode. - if A/M=0 and F=1, the current puncture rate is frozen, if no sync is found, the phase is incremented, but not the rate number; this mode allows to shorten the recovery time in case of noisy conditions: the puncture rate is not supposed to change in a given channel. In a typical computer aided implementation, the research begins in automatic mode; the micro reads the error rate or the PRF flag in order to detect the captureof a signal; thenit switches F to 1, until a new channelis requested by the remote control. - if AM=1 : manual mode; in this case, only one puncture rate should be validated, the system is forced to this rate, on the current phase, ignoring the time-out registerandtheerror rate;in this mode, each 0 to 1 transition of the bit F leads to a phase incrementation, allowing full control of the operation by an external micro by choosing the lowest error rate : ResetValue: A/M=0, andF=0;automaticsearchmode VERROR (Read only register) Internal Address : Hex07 ERROR RATE TO [1..0] H [1..0] : Hysteresis value. It programs the maximum value of the Sync counter. Th e un it is t h e b loc k du rat io n (204 bytes in Mode A). Sync Counter max value (in blocks periods) 00 forbidden value 01 32 10 64 11 128 Reset Value : H=01 (32 blocks). H [1..0] In Mode A, the sync word is 47hex and it is complemented to B8hex for every 8th block. An Up/Down Sync counter counts whenever a sync word is recognized with the good timing, and counts down for each missing sync word ; this counter is bounded by a programmable maximum value; when this value is reached, the LK bit (”locked”) is set in VSTATUS register; when the event counter counts down until 0, this flag is reset. VSEARCH bit 7 (A/M) and bit 6 (F) programs the automatic/manual(or computer aided) search mode : - if A/M =0 and F=0 : automatic mode; successive enabled punctured rates are tried with all possible phases, until the system is locked and the block 12/23 At any time, the last value of the error rate may be read in this register (unlike VTH, the possible range is 0 to 255/256). VSTATUS (Read only register) Internal Address : Hex08 CF 0 0 PRF LK PR [2..0] CF : Carrier Found flag (see carrier recovery) CF when set, indicates that a QPSK signal is present at the input of the Viterbi decoder. PRF : Puncture Rate Found P RF indicat es t he sta te of th e pu n ct ure rat e re search : 0 fo r searching, 1 when found ; this bit is irrelevant in manual mode. LK : Locked/searchingthe sync word LK indicates the state of the sync word research: 0 forsearching, 1 when found. PR [2..0] : Current Puncture Rate It hold the current puncture rate indice with the correspondance : Punctured Rate Basic 1/2 Punctured 2/3 Punctured 3/4 Punctured 5/6 Punctured 7/8 (Mode A) or 6/7 (Mode B) Regiter Value PR[2..0] 100 000 001 010 011 STV0196B FUNCTIONAL DESCRIPTION (continued) X - CONVOLUTIONAL DE-INTERLEAVER This is a 204 x 12 convolutional interleaver in Mode A ; the periodicity of 204 bytes for sync byte is preserved. The de-interleaver may beskipped (see RS register). XI - REED-SOLOMON DECODER AND DESCRAMBLER The input blocks are 204 byte long with 16 parity bytes in Mode A; the synchro byte is the first byte of the block. Up to 8 byte errors may be fixed. Code Generator polynom: g(x) = (x - ω0) (x - ω1) (...) (x - ω15) over the Galois Field generated by : X8 + X4 + X3 + X2 + 1 = 0 Energy dispersal descrambler : Output energy dispersal descrambler generator : X15 + X14 + 1 The polynom is initialised every eight blocks with the sequence 100101010000000. The synchro words are unscrambled. Control register : RS register Internal Address : Hex0A The reset value is written in each register cell RS7 RS6 RS5 RS4 RS3 RS2 RS1 RS0 1 0 1 1 1 0 0 0 RS7 : De-interleaver Enable If 1, the input flow is deinterleaved. If 0, the flow is not affected. RS6 : If 0, Output data are corrected bytes (normal operating mode). If1, OutputdataareReed-Solomoncorrection bytes (error count mode) (see Note 1). RS5 : Reed-Solomon Enable If 1, the input code is corrected. If 0, no correction happens; all the data are fed to the descrambler. The error signal remains inactive. RS4 : Descrambler Enable If 1, the output flow from Reed-Solomon decoder is descrambled. If 0, the descrambler is desactived. RS3 : Write Error Bit If RS3=1, and uncorrectible error happens, the MSB of the first byte following the sync byte is forced to 1after descrambling. RS2 : Super Synchro Suppression If RS2=1, all synchro bytes are Hex47 in mode A. If RS2=0, the synchro is complemented every 8th packet. It allows, when scrambler is off, to provide RS coded signals for use in low-cost SMATV interface. RS1 : Output Clock Polarity If RS1=0, data and control signals change during high to low transition of CK_OUT. If RS1=1, they change during the low to high transition. RS0 : Output Clock Configuration If RS0=0, CK_OUT is continuous. If RS0=1, CK_OUT remains low during the parity bits. Note 1 : When RS6 = 1, the output data are the correction bytes applied to data incoming the Reed-Solomon block. The number of bits at 1 in these output data represent therefore the number of errors remaining at the output of VITERBI decoder. All null output data mean no error left after VITERBI decoding. Remark : Output datas are meaningless when error flag (Pin 34) is set to high level. Figure 3 No Error Da ta CK_OUT No Error Uncorre cte d P a cke t P a rity Da ta P a rity Da ta P a rity RS 0=0, RS 1=0 RS 0=1, RS 1=0 RS 0=0, RS 1=1 RS 0=1, RS 1 =1 0196B-05.EPS D/P S TR_OUT ERROR 13/23 STV0196B Symbol VDD VI Vo Tstg Toper PD Parameter Value -0.3 to 4 -0.3 to VDD + 0.3 -0.3 to VDD +0.3 -40 to +150 -10 to +85 1.5 Power Supply (1) Voltage on Input pins (2) Voltage on Output pins Storage Temperature Operating Ambient Temperature Power Dissipation Unit V V V o C o C W 0196B-02.TBL ABSOLUTE MAXIMUM RATINGS Maximum limits indicate where permanent device damages occur, continuous operation at these limits is not intended and should be limited to those conditions specified in section ”DC Electrical Specifications”. Notes : 1. All VDD to be tied together 2. SCL, SDA, NRES Pins can be tied to 5V ± 10% with an impedance ≥ 2kΩ (remark in these conditions the input leakage current becomes higher than 10µA). DC ELECTRICAL CHARACTERISTICS (VDD = 3.3V, Tamb = 25oC unless otherwise specified) Parameter Operating Voltage IDD Average Power Supply Current VIL VIH VIL VIH ILK C IN VOL VOH Input Logic Low Voltage except M_CLK Input Logic High Voltage except M_CLK Input Logic Low Voltage for M_CLK Input Logic High Voltage for M_CLK Input Leakage Current Input Capacitance Output Logic Low Voltage Output Logic High Voltage Test conditions o o 0 C ≤ Toper ≤ 70 C o o 0 C < Toper < 85 C, M_CLK ≤ 55MHz CLOAD = 20pF on all outputs, M_CLK = 60MHz M_CLK = 60MHz M_CLK = 60MHz Min. 3.0 3.15 Typ. Max. 3.3 3.6 3.3 3.45 300 480 -0.3 2.0 -0.3 2.2 0.8 3.6 0.8 3.6 10 VIN = 0V and VDD 3.5 CLOAD = 20pF, ILOAD = 2mA, M_CLK = 60MHz 0.5 2.4 Unit V V mA V V V V µA pF V V 0196B-03.TBL Symbol VDD Note :This product doesn’t withstand the MIL 883C Norm at 2kV, but only at 1.5kV (all VDD tied together). TIMING CHARACTERISTICS Symbol Parameter Min. Typ. Max. Unit 4 4 ns ns ns ns ns ns PRIMARY CLOCK (see Figure 4) tM_CLK tHIGH tLOW tR tF Master Clock Period Clock Clock Clock Clock o o 0 C ≤ Toper ≤ 70 C 0oC < Toper < 85oC High Time Low Time Rising Edge Falling Edge 16.6 18.2 6 6 I[5:0],Q[5:0] INPUT SPECIFICATION S (see Figure 5) tSU tH I,Q stable before M_CLK I,Q stable after M_CLK 4 4 ns ns D60 OUTPUT CHARACTERISTICS (see Figure 6) t60 D60 period (Tm_clk * 60) - 10 (Tm_clk*60) +10 ns Bit RS1 = 1 in register RS ( adr = 0x0A) (see Figure 7) D[7:0],D/P,STR_OUT,ERROR stable before CK_OUT Falling Edge tCKSU tCKH D[7:0],D/P,STR_OUT,ERROR stable after CK_OUT Falling Edge Bit RS1 = 0 in register RS ( adr = 0x0A) (see Figure 8) tCKSU D[7:0],D/P,STR_OUT,ERROR stable before CK_OUT Rising Edge tCKH D[7:0],D/P,STR_OUT,ERROR stable after CK_OUT Rising Edge 14/23 32 32 ns ns 32 32 ns ns 0196B-04.TBL D[7:0],D/P,CK_OUT,STR_OUT,ERROR OUTPUT CHARACTERISTICS STV0196B I2C BUS CHARACTERISTICS (see Figure 9) Parameter Test Conditions Min. Typ. Max. Unit VIL VIH Input Logic Low Voltage Input Logic High Voltage See Note 1 -0.3 2.0 0.8 5.5 V V VOL VOH Output Logic Low Voltage Output Logic High Voltage C LOAD = 20pF, ILOAD = 2mA, M_CLK = 60MHz, see Note 1 2.4 0.5 5.5 V V VIN = 0V to VDD, see Note 2 -10 10 µA ILK Input Leakage Current C IN Input Capacitance IOL Output Sink Current tSP Pulse W idth of Spikes which must be suppressed by the Input filter 0 50 ns fSCL SCL Clock Frequency 0 400 kHz tBUF Bus Free Time between a STOP and START Condition 1.3 µs tHD,STA Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. 0.6 µs Low Period of the SCL Clock High Period of the SCL Clock 1.3 0.6 µs µs tSU,STA Set-up Time for a repeated START Condition 0.6 µs tSU,STO Set-up Time for STOP Condition tHD,DAT Data Hold Time See Note 3 0 tSU,DAT Data Set-up Time See Note 4 100 tLOW tHIGH tR , tF CB 4. 5. pF 10 mA µs 0.6 Rise and Fall Time of both SDA and SCL See Note 5 signals Capacitive Load for each Bus Line Notes : 1. 2. 3. VOL = 0.5V 3.5 20 + 0.1 C B 0.9 µs ns 300 ns 400 pF An impedance higher than 2kΩ is required when SDA and SCL are tied to a 5V ± 10% voltage line. Leakage current exceeds ± 10µA when SDA and SCL are tied to a 5V ± 10% line. A device must internally provide a hold time of at least 300ns for the SDA signal (refered to the VIH Min. of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. The maximum tHD,DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal. A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but the requirement tSU,DAT ≥ 250ns must then be met. This will automatically be the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tR Max. + tSU,DAT = 1000 +250 = 1250ns (according to the standard-mode I2C bus specification) before the SCL line is released. CB = total capacitance of one bus line in pF. 15/23 0196B-03.BTBL Symbol STV0196B Figure 4 tF tR 2.0V M_CLK 0.8V tLOW 0196B-06.EPS tHIGH tM_CLK Figure 5 M_CLK (VIL + VIH) / 2 tS U 0196B-07.EPS I,Q tH Figure 6 t60 Figure 8 CK_OUT CK_OUT D[7:0], D/P . S TR_OUT, ERROR D[7:0], D/P . STR_OUT, ERROR tCKSU 0196B-09.EPS Figure 7 tCKH tCKS U tCKH 0196B-10.EPS 0196B-08.EPS D60 Figure 9 SDA tLOW tR tHD,S TA tF tSP SC L tHD,S TA 16/23 tHD,DAT tHIGH tS U,DAT tS U,S TA tS U,S TO 0196B-11.EPS tBUF 3.3V 5V 12V LNB Supply & Control 22µF 22µH 22µH 22µF 35V C3 100nF 0196B-12.EPS C1 100nF 100nF C2 VDDA VDDL 5VA 5V 12V 20V to 28V C4 100nF +5VA C8 100nF C5 100nF +12V C7 220µF +5VA BSFR68G15 TUNER +5VA C6 100nF R1 1kΩ C11 100nF I VDDL VDDA 100nF C16 100nF 100nF C18 C17 100nF C15 100nF C14 R3 68Ω C20 100nF C19 22µF R4 68Ω C10 100nF VDDA Q R2 1kΩ C21 100nF C22 22µF R31 8.2kΩ R30 22kΩ VDDL 9 VDDL 16 15 13 14 17 VDDL 64 63 62 61 18 11 12 60 59 58 57 56 55 54 53 52 19 20 21 22 23 24 25 26 27 10 9 8 7 6 5 4 3 2 51 4 C45 1 48 C36 1nF 11 3 C42 2 47 3 1 VDDL 4 45 Pins 38-43-50 C46 5 44 C35 1nF 6 43 42 C37 1nF 41 40 39 C48 8 VDDL 9 C49 VDDL 10 Pins 27-31 C43 VDDL VDDL 7 12 37 VDDL VDDL C44 11 38 VDDL STV0196B VDDL R37 82kΩ R34 82kΩ R32 39kΩ VDDL 14 C47 46 13 2 VDDL R36 8.2kΩ 12 LM324 10 50 S T V 0 1 9 0 C33 1nF 8 5 C12 22µF R19 560Ω 28 D1 BB909 R18 47Ω 5V R22 22kΩ R27 220kΩ 6 49 1 C23 100nF C25 39pF C13 100nF 74F04 R21 330Ω C26 82pF X1 40MHz L1 1µH 7 VDDL R20 10kΩ C24 220pF Q1 BF959 R23 10kΩ +5V C34 100nF 20 to 28V C50 14 35 15 34 Pins 4-3-10-12 C52 13 36 3.3kΩ C51 16 33 +5V 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 3.3kΩ VDDL VDDL 13 12 11 10 9 8 7 6 5 4 3 2 1 D0 D1 D2 D3 D4 D5 D6 D7 CK_OUT STR_OUT D/P ERROR I2C BUS DATA OUTPUTS RESET D/60 GND 1 SCL SDA STV0196B APPLICATION DIAGRAM : STV0196B/STV0190Fixed 20 MBauds Application 17/23 18/23 3.3V 5V 12V LNB Supply & Control 22µH 22µH 22µF 35V C3 100nF 0196B-13.EPS C1 100nF 100nF C2 22µF V DDA V DDL 5VA 5V 12V 20V to 28V C4 100nF +5VA C8 100nF C5 100nF +12V C7 220µF +5VA BSFR68G15 TUNER +5VA C6 100nF R1 1kΩ R2 1kΩ C11 I VDDL VDDA 74F04 C17 100nF 100nF C18 C20 100nF 6 5 4 3 2 16 15 14 17 13 12 18 11 20 21 22 23 19 S T V 0 1 9 0 24 25 26 27 28 10 9 8 C16 7 100nF C15 100nF C14 100nF R3 68Ω 1 R19 560Ω C31 33nF C32 1nF R26 10kΩ C21 100nF C33 10nF R27 220kΩ R25 10kΩ D2 2 x BB909A C30 220pF R18 47Ω 5V D1 R22 22kΩ L2 0.33µH C29 15pF C28 100nF C27 22µF C13 100nF C23 100nF C25 39pF C26 82pF R23 10kΩ R23 10Ω C19 22µF R4 68Ω 100nF C10 100nF VDDA C12 22µF V DDL Q R20 10kΩ C24 220pF R21 330Ω Q1 BF959 +5V C22 22µF R31 8.2kΩ R30 1kΩ R29 100kΩ R28 22kΩ 8 7 VDDL VDDL V DDL 9 6 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 4 C45 1 48 11 3 C42 2 47 14 1 3 4 45 V DDL 5 6 43 VDDL 42 C37 1nF 41 R33 1kΩ 40 39 C49 8 VDDL 9 C48 V DDL 10 Pins 27-31 C43 VDDL V DDL 7 12 37 V DDL V DDL C44 11 38 V DDL D3 5.1V R43 1kΩ +12V C50 14 35 15 34 C40 100nF Pins 4-3-10-12 C52 13 36 C41 22µF C39 22µF R40 22kΩ R41 68Ω STV0196B C35 1nF R37 82kΩ C46 Pins 38-43-50 C47 46 V DDL R36 8.2kΩ 44 R32 39kΩ R35 1kΩ 13 2 VDDL C36 1nF 12 LM324 10 5 C34 100nF 20 to 28V R34 82kΩ C30 2.2nF C51 16 33 3.3kΩ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VDDL VDDL TC74SU04 3.3kΩ +5V D0 D1 D2 D3 D4 D5 D6 D7 D/60 CKOUT STROUT D/P ERROR RESET SCL SDA VCO ADJ (PWM) STV0196B APPLICATION DIAGRAM : STV0196B/STV0190Multirate Application STV0196B ANNEXE 1 : C/N ESTIMATION The C/N indicator register permanently reports a value S which depends on the C/N level at the input of the STV0196B. The C/Nindicator offers a programmable sensitivity which allows a reliable C/N estimation over a wide Eb/No range (4dB to 16dB typically) ; this is particularly useful to optimize the dish positioning. Remark : In this note, we have assumed that : C Eb = ⋅ 2 (PR), PR : Puncture Rate N No The sensitivity of the C/N indicator is dependant on the SN bits of the register VSEARCH (Hex06) and on the AGC function reference level ”m”. A - SUGGESTED PROCEDURE TO RELIABLY ESTIMATE THE ACTUAL C/N As no simple mathematical low ensumes a good matching between the C/N indicator and the actual C/N, the method relies on a comparaison of the value S (reported by the C/N indicator) with a reference look-up table which has been realized under well controlled conditions. Basically there are 3 steps in the C/N estimation software. 1. To collect C/N indication (under adapted conditions). 2. Indication scaling and correction versus the puncture rate 3. Comparaison with the look-up table A.1 - To collect C/N Indication The purpose of this first step is to collect the C/N indicator with the appropriate sensitivity (SN bits and AGC reference level m). Basically : - The value reported by the C/N indicator is proportional to the Number of bits (at the output of the VITERBI decoder) selected by the SN bits. - The AGC reference level is only changed to appreciate the high Eb/No ratios. This second parameter has to be used with some care. Procedure : Before to make an estimation, the VSTATUS register (internal address Hex 08) must be checked to make sure that : - a carrier is actually present (bit 7) - puncture rate is found (bit 4) - puncture rate is known (bits 0-1-2) Remark : Optionally, it is possible to make an estimation without informations about the puncture rate (useful when the dish is still very far from optimum position), in such case the puncture rate is forced. The C/N indicator register has no overflow detection, so it is necessary to start the measure with the lowest sensitivity (SN = 00) and to gradually increase it (using SN bits). Due to the noise, the result S of the measure may have a lot of dispersion, consequently it is recommended to measure S several times (typically 100 times) and to calculate the average value. Remark : The requred duration tW between two readings of the register must be higher than : tW (Min.) = BC BR BR = 2 (Fs) x (PR) with BC : Bit Count (selected by SN bits) Fs : Symbol Rate PR : Puncture Rate When the current average value of the measure S is lower than 63, the measure is done again with a higher sensitivity. With this care the new C/N measure S does not overflow t he counter (the counting time is multiplied by 4 at each step). In practice some margin is given to this threshold : a higher sensitivity is selected when the average value of S is lower than 60. Wh en the maximum SN value is reached (SN = 11 ⇔ to 65 536 bits at the output of the VITERBI decoder), the sensitivity can be further increased by lowering the AGC reference level (p ara met er m, in t e rnal a dd res s He x11, bit 0 to bit 5). Remark : There is the need to change the AGC reference level only in case of high C/N conditions, then to change the reference level has no important influence on the bit error rate (BER). In other words, a completete C/N estimation can be run during the operation of the receiver. When the highest possible sensitivity is found the result S (average value) is ready for further process. 19/23 STV0196B ANNEXE 1 : C/n ESTIMATION (continued) A.2 - Scaling and Correction versus Puncture Rate Scaling This simple operation is recommended to easily compare data which have been recorded under different sensitivity conditions. To do so, the result S of the C/N indication is multiplied by a coefficient so that the scaled value would correspond to a measure done with the highest counting period (SN = 11). Remark : Scaling is not done for results which have beenrecordedafterchangingthe AGCreferencelevel. Scaling operation : Scaled_value = (S) x (factor) factor = 64 when C/N estimation is done with SN = 00 factor = 16 when C/N estimation is done with SN = 01 factor = 4 when C/N estimation is done with SN = 10 factor = 1 when C/N estimation is done with SN = 11 Correction versus puncture rate This correction is not required when a reference look-up table have been memorized for each possible puncture rate. When required, the correction is done with respect to the puncture rate PRref of the reference look-up table : PRcurrent Scorrected = (S) ⋅ PRref 20/23 PR current : the puncture currently identified with the bits 0,1,2 of VSTATUS register. A.3 - Comparing with the look-up table In the application the read value Srs (scaled and corrected) will seldom exactly match a value of the look-up table ; consequentlythere will be the need for some interpolation. To make it simple, a linear interpolation is preferred, with such a solution a good precision can be achieved when the look-up table is built with a small step for the C/N (or Eb/No). Interpolation Generally Ssr will be between two values of the reference look-up table : V(Min.) ≤ Ssr ≤ V(Max.), with V(Min.) corresponding C/N(Max.) and V(Max.) c orre sp on din g t o C/ N(Min.) (wit h t yp ica lly (C/N(Max.)) - (C/N(Min.)) = 0.5dB). The calculated C/N corresponding to Ssr is : V(Min.) − Ssr C/N = C/N(Max.) − C/N(Max.) − C/N(Min.) ⋅ V(Min.) − V(Max.) in above calculation C/N (or Eb/No) are given in algebraic value (not in dB). STV0196B ANNEXE 1 : C/n ESTIMATION (continued) B - FLOW CHART Following is a simplified flow chart. Normal Process C/N Estimation A Go to Tuning Routine N Y N Check VSTATUS OK SN < ----- 00 Collect C/N data 100 times and calculate average value SN < ----- SN + 1 Y S < 60 Scaling S SN = 11 Y N Correction versus Puncture Rate S < 40 m < ----- m - 4 Collect C/N data 100 times and calculate average value N S < 20 Y m < ----- m - 4 Collect C/N data 100 times and calculate average value Compare with look-up table T1 Compare with look-up table T2 Compare with look-up table T3 Output C/N estimation A N End of Estimation Y T1 : Look-up table for normal value of m (AGC reference level) T2 : Look-up table for m - 4 T3 : Look-up table for m - 8 0196B-17.EPS Restore AGC Reference Level to normal value Return to normal process 21/23 STV0196B ANNEXE 1 : C/n ESTIMATION (continued) C - RESULTS The results reported in the following table are typical values. When evaluating another application some differences may be especially noticed when Eb/No is higher than 10dB, in these conditions the characteristics of the tuner and the A/D converter may influence the results. Eb Conditions : Puncture rate : 2/3, 20MBauds signal, DVB encoding (RS : 188/204), C/N = 2 ⋅ (PR) No Eb/No (dB) Measurement Conditions S S Scaled 152 2.432 4.5 137 2.192 5 121 1.936 5.5 105 1.664 4 SN bits (hex) AGC, m (dec) 1 20 6 92 1.474 6.5 78 1.248 7 64 1.024 7.5 205 820 8 168 672 8.5 131 524 9 98 392 9.5 73 292 10 2 3 20 212 212 10.5 20 146 146 11 95 95 61 61 11.5 12 3 16 12.5 84 13 55 13.5 35 14 22 14.5 15 22/23 122 13 3 12 128 15.5 95 16 70 STV0196B PACKAGE MECHANICAL DATA 64 PINS - PLASTIC QUAD FLAT PACK D D1 A D3 A2 A1 48 33 49 32 0. 10mm E E1 E3 B B Seating Plane 17 64 16 1 C PMPQFP64.EPS L L1 e K PQFP64 A A1 A2 B C D D1 D3 e E E1 E3 K L L1 Min. 0.25 2.55 0.30 0.13 16.95 13.90 16.95 13.90 0.65 Millimeters Typ. 2.80 17.20 14.00 12.00 0.80 17.20 14.00 12.00 0.80 1.60 Max. 3.40 Min. 3.05 0.45 0.23 17.45 14.10 0.010 0.100 0.0118 0.005 0.667 0.547 17.45 14.10 0.667 0.547 0o (Min.), 7o (Max.) 0.95 0.026 Inches Typ. 0.110 0.677 0.551 0.472 0.0315 0.677 0.551 0.472 0.0315 0.063 Max. 0.134 0.120 0.0177 0.009 0.687 0.555 0.687 0.555 0.0374 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 23/23 PQFP64.TBL Dimensions