1EDI EiceDRIVER™ Enhanced 1EDI30J12CP Single JFET Driver IC Preliminary Datasheet Rev. 1.3, November 2014 Industrial Power Control Edition 2014-11-12 Published by Infineon Technologies AG 81726 Munich, Germany © 2014 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems and/or automotive, aviation and aerospace applications or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support, automotive, aviation and aerospace device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. 1EDI EiceDRIVER™ Enhanced 1EDI30J12CP Single JFET Driver IC Product Highlights • • • • Single driver for normally-on JFET Galvanic isolation Signal transmission via Coreless Transformer Supporting Direct Drive JFET Topology Features • • • • • • • Single channel isolated JFET driver Optimized for 1200V Infineon CoolSiCTM JFETs Extremely low propagation delay of typ. 80ns Extremly high common mode transient immunity of 100V/ns Minimal 3A rail-to-rail output Safe turn off during start up Supports bootstrap operation Description • The 1EDI30J12CP is an advanced single channel JFET gate driver. The driver is built to drive a normally-on CoolSiCTM JFET together with a low voltage P-channel MOSFET in a switching loss optimized Direct Drive JFET Topology. The device consists of two galvanic separated parts. The input signals are TTL level compatible with a highvoltage capability of up to 17.5V. The output chip is directly driving a CoolSiCTM JFET and MOSFET with rail to rail output stages. +5V to GND CoolSiCT M JFET • RgJ VCC1 JFDrv CVCC1 VCC2 From Controller GND1 MDrv IN VReg EN CVReg LV MOSFET RgM GND CVEE2 CLJFG VEE2 BSEN -25V to VCC2 1EDI30J12Cx Product Type Package 1EDI30J12CP PG-DSO-19-4 Preliminary Datasheet 2 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Table of Contents 1 Pin Configuration and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Representative Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.3.1 3.3.2 3.3.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Supply options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Normal start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Reverse start up with self-pinch-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bootstrap supply mode and start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Interlock between MOSFET Gate and JFET Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bootstrap Start up Mode Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 4.1 4.2 4.3 4.4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 6.1 6.2 6.3 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver Supply Set up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate clamping diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Layout, Thermal Layout, Layout Guide Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary Datasheet 3 14 14 15 15 16 21 21 23 24 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Pin Configuration and Description 1 Pin Configuration and Description The pin configuration for 1EDI30J12CP in a PG-DSO-19-4 wide body package is shown in Figure 1 and Table 1. N.C. 1 20 N.C. BSEN 2 19 VCC1 CLJFG 3 18 IN VREG 4 17 GND1 N.C. 5 VEE2 6 15 EN MDrv 7 14 N.C. JFDrv 8 13 N.C. VCC2 9 12 N.C. 10 11 N.C. N.C. PG-DSO-19-4 (300mil) Figure 1 Pin Configuration PG-DSO-19-4 Table 1 Pin Configuration 1EDI30J12CP in PG-DSO-19-4, Wide Body Pin Symbol Description 1 N.C. Internally not connected1) 2 BSEN Bootstrap Enable For bootstrap operation connect this pin to VCC2, for non bootstrap operation to VREG 3 CLJFG Reserved2) 4 VREG Voltage Regulator Output VREG is the output of the integrated linear regulator and the negative power supply for the gate drivers 5 N.C. Internally not connected1) 6 VEE2 Negative Power Supply Output Side VEE2 is the input of the integrated linear regulator 7 MDrv MOSFET Driver Output 8 JFDrv JFET Driver Output 9 VCC2 Positive Power Supply Output Side VCC2 is the positive supply input of the JFET driver and MOSFET driver, connected to the sources of the JFET and the MOSFET 10 N.C. Internally not connected1) 11 N.C. Internally not connected1) 12 N.C. Internally not connected1) 13 N.C. Internally not connected1) 14 N.C. Internally not connected1) Preliminary Datasheet 4 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Pin Configuration and Description Table 1 Pin Configuration 1EDI30J12CP in PG-DSO-19-4, Wide Body (cont’d) Pin Symbol Description 15 EN Driver Enable 17 GND1 Signal Ground Input Side 18 IN Driver Input 19 VCC1 Positive Supply Input Side 20 N.C. Internally not connected1) 1) Pads of N.C. pins must be left unconnected, separated from each other and floating for maximum creepage/clearance distance 2) Connect to JFDrv Pin or leave pin unconnected and floating Preliminary Datasheet 5 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Representative Block Diagram 2 Representative Block Diagram A simplified functional block diagram is given in Figure 2 representing the principle functionality of the driver. 1EDI30J12Cx x BSEN x VCC2 VCC1 x UVLO UVLO Voltage Supply Linear Regulator VCC2 x VREG x VEE2 EN x x JFDrv Input Logic IN x TX RX Logic VCC2 VREG x CLJFG x MDrv GND1 x VREG Figure 2 Representative Block Diagram Preliminary Datasheet 6 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Functional Description 3 Functional Description 3.1 Introduction The 1EDI30J12Cx is an advanced JFET (junction gate field-effect transistor) gate driver. The driver is built to drive a normally-on CoolSiCTM JFET together with a low voltage p-channel MOSFET in a switching loss optimized cascode operation called Direct Drive JFET Topology. As MOSFET (metal–oxide–semiconductor field-effect transistor; referred to as pMOS, LV MOSFET) a 30 V pchannel OptiMOSTM MOSFET with low RDSon is typically used (e.g. OptiMOSTM BSC030P03NS3 G). The driver consists of two galvanic separated parts. The inputs can be connected to any controller with varying signal levels. The pins can handle signals up to 17.5V, however the thresholds remains at TTL levels. The output side is connected to the high voltage side of the application, incorporates two rail to rail output stages. The two gate drivers, one for the JFET and one for the MOSFET, drive the gates between VCC2 and the regulated output VREG. The 1EDI30J12Cx supports two different start up modes selectable by the bootstrap enable pin BSEN. A specialized bootstrap operation mode for supplying the driver via a bootstrap diode. And a standard operation mode for direct supply realised with a floating isolated supply source. The output side has a built in linear voltage regulator to generate an accurate JFET driver supply voltage inside the window between pinch off voltage and punch through voltage of Infineon’s CoolSiCTM JFETs . In addition, the internal regulator separates the driver supply voltage from a common supply voltage for low side switches, so all low side switches could be supplied by one negative supply. Further in isolated supply topologies it offers the support of wide supply range due to preregulation. So voltage drops due to bad transformer coupling can be handled. Cascodes were introduced in the past for faster switching made possible by the elimination of the JFETs Cgd acting as a feedback to the control gate. The disadvantage by eliminating the feedback is that the dV/dt of the switch gets uncontrolled. New JFET devices like CoolSiCTM JFET offers a reduced gate charge, therefore driving the JFET gate directly offers advantages in controlling the switching speed with lower EMI and less ringing. 3.2 Theory of Operation The optimized cascode operation offered by the 1EDI30J12Cx driver called Direct Drive JFET Topology differs from the normal cascode in the way it is controlling the switch. The normal cascode controls the normally-on JFET by indirectly controlling the source potential of the JFET via the low-voltage MOSFET. In the Direct Drive JFET Topology the MOSFET is used to keep the normally-on JFET in a safe off-state during start up of the application as in the normal cascode. When the driver auxilliary supply voltage is high enough to release the Under Voltage Lock Out (UVLO) the MOSFET is permanently turned on and the JFET is driven directly according to the input signal. The input signal is transferred across the isolating Coreless Transformer (CLT) from input side to output side. A high at the input pin turns on the JFET. The 1EDI30J12Cx is a non inverting driver. When the VCC1 supply voltage has reached the turn on threshold and the signal at the EN pin is high, the input side is able to send the IN signal to the output side. Depending on the UVLO of the output side, the input signal is either ignored if |VVREG| is below the UVLO-onthreshold or is applied amplified at the gate of JFET. When the VCC1 voltage potential reaches the turn off threshold, the input side sends an off signal to the output side to ensure a defined switch off state before the driver is disabled. The driver can be disabled using the EN pin: in case the EN pin is pulled to low, the output is switched off regardless of the signal applied to the IN pin. Preliminary Datasheet 7 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Functional Description 3.2.1 Supply options Two different isolated supply configurations are possible depending on the reference node of the supply. 1. The external power supply is related to VCC2 (see Figure 3 high-side switch and Figure 10). This configuration is possible for both high and low-side switches, but each driver has to be separately supplied in order to guarantee the correct start up behavior. It is not possible to share the same supply among more than one driver. 2. The external power supply is related to the MOSFET drain potential (see Figure 3 low-side switches and Figure 12). This allows for using the same power supply to more than one driver stage as long as their MOSFET drains are connected to the same potential. Which makes this configuration most suitable to be used on drivers connected to low-side switches. HV supply L1 VCC1 +5V CVCC1 N GND HS_IN JFDrv VCC2 GND1 MDrv EN VReg IN CLJFG CVReg CVEE2 C -25V_HS VEE2 Load BSEN 1EDI30J12Cx +5V VCC1 CVCC1 GND PFC_IN +5V JFDrv GND1 MDrv EN VReg IN VCC1 CVCC1 VCC2 GND CVReg CLJFG CVEE2 LS_IN JFDrv VCC2 GND1 MDrv EN VREG IN CLJFG VEE2 VEE2 BSEN BSEN 1EDI30J12Cx 1EDI30J12Cx CVReg CVEE2 C -25V Figure 3 Application drawing for isolated supply (PFC+HB) Additionally it is possible to supply the driver via bootstrapping. In this supply mode a high-side driverstage can share the same isolated high-side supply (see Figure 6). It is also possible to transfer the power from the highside to a low-side driverstage via a bootrapping capacitor (see Figure 13). Further information about the bootstapping supply can be found in Chapter 3.2.4. 3.2.2 Normal start up This section describes a normal start up in which the auxiliary supplies of the driver are enabled before a voltage is applied over the switch (JFET drain to pMOS drain). The timing diagram of this start up is shown in Figure 4. The negative driver supply voltage is applied to VEE2. VREG is following the supply voltage ramp with the regulator drop of approximately 2V, depending on the capacitor size and the ramping speed of VEE2. When VREG reaches the UVLO threshold the driver is turning on the p-channel MOSFET. After MDrv has reached the onthreshold the JFET gate driver stage is active and follows the IN signals with a short propagation delay of typical 80ns. Preliminary Datasheet 8 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Functional Description VCC1 V VCC1on VVCC1off IN EN Output signals referenced to VCC2 VEE2 BSEN VREG VVREGoff VVREGon MDrv t PDOFF_EN JFDrv tPDON tPDOFF t PDON_EN Figure 4 Principle start up, auxiliary supplies present before a voltage is applied over the switch (Signal names are chosen equivalent to the pin names of the driver) 3.2.3 Reverse start up with self-pinch-off One of the biggest questions that arise when dealing with normally-on devices is the situation that comes up when the auxiliary power supply fails or is not ready at the point when the high voltage is applied over the switch. This event is depicted in Figure 5. Due to the normally-on behavior of the JFET and the cascoded normally-off MOSFET, the voltage is being blocked at the MOSFET. The Vds voltage that is building up over the switched-off MOSFET is being mirrored to the JFET Vgs voltage via the diode connecting the MOSFET drain to the JFET gate (see Chapter 6.2) until the level reaches the JFET pinch off voltage and the JFET itself blocks the voltage. When the JFET is pinched off a small current is still flowing through the JFET charging the capacitors CVEE2 and CVReg which supply the driver. In this way the JFET acts as a linear regulator powering the output stages of the driver at the pinch off voltage. As soon as the auxiliary supply is larger than the pinch off voltage the auxiliary supply is charging VEE2. As it reaches the under voltage lockout level, the JFET is kept off and the MOSFET is turned on. From this point onwards the driver is transmitting the IN signal to the JFET gate. This behavior of acting in a self-regulating manner enables the driver to also work in a bootstrapping scheme. Preliminary Datasheet 9 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Functional Description HV supply Start up auxiliary supply V VCC1on VCC1 VVCC1off -25V AUX IN EN Output signals referenced to VCC2 VEE2 VVJ FET _pinc h_off VREG VVREGoff V VREGon MDrv JFDrv tPDON tPDOFF tPDON_EN tPDOFF _EN Figure 5 Principle start up with the auxiliary supplies not present when voltage is applied over the switch (Signal names are chosen equivalent to the pin names of the driver) 3.2.4 Bootstrap supply mode and start up In bootstrap supply mode, the capacitors at VEE2 and VREG are charged to the pinch off voltage of the JFET as described in Chapter 3.2.3 (Infineon CoolSiCTM JFET family has the lowest gate threshold voltage at -12 V). When the BSEN pin is connected to VCC2 the bootstrap supply mode is active. In this case a lower UVLO threshold is used and the driver is active at approximately -9.0 V. After passing this lower UVLO threshold the driver is ready to receive IN signals from the input stage. This input signal is transferred to a switching logic which turns on the p-channel MOSFET. After the VMDrv has passed the MOSFET gate turn on threshold the JFET is turned on. The voltage drop across the MOSFET and JFET channel is nearly zero. The potential of VCC2 is identical to JFET drain voltage. A negative supply related to the JFET drain (positive potential of DC-link capacitor, half bridge supply) can charge the input capacitor CVEE2 through a high voltage bootstrap diode. An example of a high-side bootstrap supply can be seen in Figure 6. If the input stage is sending a low to the driving stage, first the JFET is turned off. After the JFDrv has passed the off threshold the MOSFET is turned off. The propagation delay in bootstrap mode is therefore enlarged by the MOSFET gate charging time. After VREG has passed the higher normal UVLO level, the MOSFET is permanently kept on and the delay changes to the fast Preliminary Datasheet 10 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Functional Description datasheet values of typical 80ns. A timing diagram showing the various signals in this startup mode is depicted in Figure 7. Figure 8 shows a diagram detailing the reason for the prolonged popagation delay. The longer propagation delay can be indicated to the input side by using an optocoupler. The optocoupler diode is inserted between BSEN and VCC2. During the start up phase in bootstrap mode BSEN is applying an output current of at least 2 mA while IN is high. During the bootstrap start up phase the power dissipation in the driver is increased. Therefore, the controller has to make sure that the driver does not remain in bootstrap start up mode for longer periods of time in order not to overheat the driver. During the boostrap start-up phase, the propagation delay is larger and the effective JFET conduction time shorter compared to standard operating mode. This means, the controller has to take care to compensate for the longer propagation delays and shorter on-times, e.g. in a half-bridge configuration, the dead-times have to be increased. After the start-up phase is finished, the controller has to reduce the dead-times to normal operating values, not to risk body-diode conduction over long periods of time, which can lead to higher power dissipation of the JFETs. 800V +5V VCC1 CVCC1 GND LS_IN +5V JFDrv GND1 MDrv EN VReg IN CLJFG VCC1 CVCC1 VCC2 GND CVReg CVEE2 LS_IN VCC1 +5V CVCC1 GND LS_IN VCC2 GND1 MDrv EN VReg IN VEE2 BSEN BSEN EN VReg IN CLJFG VCC1 +5V CVCC1 VCC2 MDrv CVReg CVEE2 1EDI30J12Cx JFDrv GND1 -25V_H CLJFG VEE2 1EDI30J12Cx C JFDrv GND CVReg CVEE2 LS_IN JFDrv VCC2 GND1 MDrv EN VREG IN CLJFG VEE2 VEE2 BSEN BSEN 1EDI30J12Cx CVReg CVEE2 C 1EDI30J12Cx -25V Figure 6 Application drawing for high side bootstrap supply (FB) Preliminary Datasheet 11 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Functional Description HV supply Start up auxiliary supply VVCC1on VCC1 V VCC1off IN EN Output signals referenced to VCC2 VEE2 V VJ FET _pinc h_off VVREGonBS VREG V VREGon V VREGoff MDrv JFDrv t PDONBS tPDON t PDOFFBS t PDOFF tPDOFF _EN tPDON_EN tPDOFFBS tPDONBS Bootstrap Start up Phase I_BSEN Figure 7 Start up bootstrap supply mode for high side located cascodes (BSEN connected to VCC2) (Signal names are chosen equivalent to the pin names of the driver) IN IN 50% JFDrv 50% JFDrv 50% 50% MDrv MDrv a) Figure 8 VCC2-1.9V VCC2-19V tPDON tPDOFF b) tPDONBS tPDOFFBS Timing of IN to JFDrv, a) normal mode, b) bootstrap mode Preliminary Datasheet 12 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Functional Description 3.3 Protection Features 3.3.1 Active Shut Down The Active Shut Down feature ensures MOSFET off-state under all circumstances even if the output side supply is inactive. The p-channel MOSFET gate is held actively high until VREG is passing the output UVLO thresholds of the driver. 3.3.2 Interlock between MOSFET Gate and JFET Gate The JFET can only be switched on, if the MOSFET is on, otherwise the low voltage MOSFET will be destroyed by overvoltage. To ensure proper operation of the cascode, the driver is monitoring the MOSFET gate voltage at MDrv pin and the JFET gate voltage at JFDrv pin. Only if the MOSFET is on, indicated by MDrv pin having low potential, the JFET is allowed to turn on. Similar in opposite direction, MOSFET turn off is only allowed if the JFET is in its off state. 3.3.3 Bootstrap Start up Mode Indicator The 1EDI30J12Cx indicates at BSEN pin that the driver has entered the bootstrap start up phase with an output current of min 2mA to drive an opto coupler if IN signal is driven high. Preliminary Datasheet 13 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Characteristics 4 Characteristics Unless otherwise noticed, voltages of the input side signals (pins VCC1, IN, EN, GND1) are measured with respect to input ground (pin GND1), all other voltages are measured with respect to positive output supply (pin VCC2). Currents in the following tables are defined as positive currents flowing out of the pin (unless otherwise specified). The voltage levels are valid if other ratings are not violated. 4.1 Absolute Maximum Ratings Absolute maximum ratings are listed in Table 2. Stresses above the max. values may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. For the same reason make sure that any capacitors that will be connected to pins VCC1 and VCC2 are discharged before assembling the application circuit. Table 2 Absolute Maximum Ratings Parameter Symbol Limit Values Min. Unit Remarks Max. Positive supply voltage input side VVCC1 -0.3 Voltage at pin IN, EN VIN -0.3 Input to output isolating voltage VISO -1200 Negative supply voltage output side (VEE2) VVEE2 -30 VVCC2+0.3 V Voltage at pin BSEN VBSEN VVREG-0.3 VVCC2+0.3 V Voltage at pin VREG VVREG -21 VVCC2+0.3 V VEE2 max dV/dt |dVVEE2| Voltage at pin JFDrv VJFDrv VVREG-0.3 VVCC2+0.3 V Voltage at pin MDrv VMDrv VVREG-0.3 VVCC2+0.3 V Junction temperature TJ -40 150 °C Storage temperature TS -55 150 °C 2)3) Maximum power dissipation PTOT 1.0 W PG-DSO-19-4, TA=25°C ESD capability VESD 2 kV Human Body Model4) 1) 2) 3) 4) 18 VVCC1+0.3 V +1200 125 — V V 1) V/ms CVReg= 2.2µF With reference to GND1 Prolonged storage at high temperatures reduces the lifetime of the product Tested according to EIA/JESD22-A103D According to EIA/JESD22-A114-B (discharging at 100pF Capacitor through 1.5kΩ Resistor) Preliminary Datasheet 14 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Characteristics 4.2 Thermal Characteristics Table 3 Thermal Characteristics Parameter Symbol Values Unit Remarks K/W PG-DSO-19-4, TA=25°C; Layout: Figure 16 Typ. Thermal resistance Junction-Ambient 4.3 Operating Range Table 4 Operating Range Parameter RthJA25 Symbol 85 Limit Values Min. Positive supply voltage input side VVCC1 Logic input voltage input side (IN, EN) VIN Unit Remarks Max. 4.75 17.5 V 0 VVCC1 V Negative supply voltage output side (VEE2) VVEE2 -28 -22 V VREG in regulation, full PSRR Negative supply voltage output side (VEE2) VVEE2 -28 -19 V VVREG > VVREGoff1) Output capacitance for VREG CVREG 0.22 2.2 µF from VREG to VCC21), ESRCVREG < 15mOhm Common mode transient immunity |dVISO/dt| — 100 V/ns 1) Junction temperature TJ -40 150 °C 1)2) 1) The parameter is not subject to production test - verified by design/characterization 2) According to product qualification conditions (tested according to EIA/JESD22-A108D) Preliminary Datasheet 15 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Characteristics 4.4 Electrical Characteristics The electrical characteristics involve the spread of values given within the specified supply voltage and junction temperature range TJ from -40°C to 150°C. Typical values represent the nominal values related to TJ=25°C. Unless otherwise noticed, voltages of the input side signals (pins VCC1, IN, EN, GND1) are measured with respect to input ground (pin GND1) all other voltages are measured with respect to positive output supply (pin VCC2). Supply voltages are VVCC1 = 5 V and VVEE2 = -25 V if not otherwise mentioned. The following characteristics are specified • • • • • Power Supply (Table 5) Logic Input (Table 6) JFET Driver (Table 7) MOSFET Driver (Table 8) Dynamic Characteristics (Table 9) Table 5 Power Supply Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition VCC1 quiescent current IVCC1qu1 — 430 650 µA IN = statically low, EN = statically high VCC1 quiescent current IVCC1qu2 120 240 500 µA EN = statically low VCC1 supply current IVCC1supp — 1.2 1.6 mA IN = 1MHz VCC1 turn on threshold VVCC1on 4.15 4.55 4.75 V VCC1 turn off threshold VVCC1off 3.9 4.25 4.55 V VCC1 turn on/off hysteresis VVCC1hys 0.15 VEE2 quiescent current 1 IVEE2qu1 — 380 500 µA output chip off due to UVLO VEE2 quiescent current 2 IVEE2qu2 — 800 1100 µA IN = low, output chip on VREG output voltage1)2) VVREG0 -19.5 -18.85 -18.1 V 1µF from VREG to VCC2, VVEE2< -22V, Load 0mA VREG output voltage loaded1)2) VVREG50 -19.0 -18.25 -17.5 V 1µF from VREG to VCC2, VVEE2< -22V, Load 50mA VREG turn on threshold1)3) VVREGon -17.4 -16.9 -16.4 V VVREGoff -17.0 -16.4 -16.0 V VREG turn off threshold 1)3) 1)3) VREG turn on/off hysteresis VVREGhys V 0.5 V VREG turn on threshold BS1)3) VVREGonBS -9.8 -9.5 -9.0 V VBSEN > -3V1) VREG turn off threshold BS1)3) VVREGoffBS -9.2 -8.8 -8.3 V VBSEN > -3V1) V VBSEN > -3V1) mA including loads from MDrv and JFDrv VREG turn on/off hysteresis BS1)3) VVREGhysBS VREG load current IVREG 0.7 50 1) Voltage refer to VCC2 2) DC voltage 3) ULVO threshold output chip Preliminary Datasheet 16 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Characteristics Table 6 Logic Input Parameter Symbol Values Min. IN, EN low input voltage VINL IN, EN high input voltage VINH IN, EN input current ΙIN BSEN low input voltage VBSENL BSEN high input voltage VBSENH BSEN output current ΙBSEN BSEN output current ΙBSENPD Table 7 Typ. Unit Max. 1.0 2.0 V V 30 400 µA VVREG + 2.0 V VVREG + 3.0 -70 Note / Test Condition VIN=VVCC1 V -3.5 -2 mA VBSEN > VVREG + 5.7V, VIN = high, VVREGon < VVREG < VVREGonBS -38 -15 µA VIN= low Unit Note / Test Condition JFET Driver (Reference is VCC2) Parameter Symbol High Level Output Voltage VJFDrvH High Level Output Peak Current IJFDrvH Output Voltage at low state VJFDrvL Values Min. Typ. Max. -2.0 -1.75 V IJFDrv=200mA; -4.0 -3.5 V IJFDrv=2A; — -4.1 V IJFDrv=3A1) 3.0 4.0 A 1) VVREG + 0.17 VVREG + 0.35 V IJFDrv=-200mA; VVREG + 1.9 VVREG + 4.0 V IJFDrv=-2A; — 3.0 V IJFDrv=-3A1) Low Level Output Peak Current IJFDrvL -3.0 -4.0 A 1) Rise Time JFDrv tJFDrvR — 23 30 ns Fall Time JFDrv tJFDrvF — 22 35 ns CLOADJ= 4.7 nF, VL=20% to VH 80% Unit Note / Test Condition 1) The parameter is not subject to production test - verified by design/characterisation Table 8 MOSFET Driver (Reference is VCC2) Parameter High Level Output Voltage Preliminary Datasheet Symbol VMDrvH Values Min. Typ. -1.75 -1.35 V IMDrv=150mA -4.0 -3.15 V IMDrv=1.5A 17 Max. Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Characteristics Table 8 MOSFET Driver (Reference is VCC2) (cont’d) Parameter Symbol High Level Output Peak Current IMDrvH Output Voltage at Low State VMDrvL Values Min. Typ. 2 3 Unit Note / Test Condition A 1) Max. VVREG +0.26 VVREG +0.55 V IMDrv=-150mA VVREG +1.0 VVREG -2.1 V IMDrv=-0.5A 2.0 — V IMDrv=-1.0A1) Low Level Output Peak Current IMDrvL -2 -1 A 1) Rise Time MDrv tMDrvR 65 110 ns Fall Time MDrv tMDrvF 165 270 ns VVREG=19V, CLOADM= 22 nF, VL 20% to VH 80% Unit Note / Test Condition VVCC1=5V, CLOADJ= 100 pF, VIN=50%, VJFDrv=50%, VEN=H TJ=25°C 1) The parameter is not subject to production test - verified by design/characterisation Table 9 Dynamic Characteristics Parameter Symbol Values Min. Typ. Max. Input to output propagation delay ON (IN: L to H) tPDON 53 80 106 ns Input to output propagation delay OFF (IN: H to L) tPDOFF 53 80 106 ns Enable to output propagation delay ON (EN: L to H) tPDON_EN 170 290 390 ns Enable to output propagation delay OFF (IN: H to L) tPDOFF_EN 60 110 140 ns Input to output propagation delay distortion tPDON-tPDOFF tPDDISTO -4.0 12 ns VVCC1=5V, CLOADJ= 100 pF, VIN=50%, VJFDrv=50%, VEN=H Input to output propagation delay distortion due to temp tPDDISTOT -20 20 ns 1) Input to output propagation delay ON bootstrap mode2) tPDONBS 300 ns VVREG=-19V, VVCC1=5V, CLOADJ= 100 pF, CLOADM=22nF, VIN=50%, VJFDrv=50% Input to output propagation delay OFF bootstrap mode2) tPDOFFBS 300 ns VVREG=-19V, VVCC1=5V, CLOADJ= 100 pF, CLOADM=22nF, VIN=50%, VMDRV=-1.9V IN input pulse surpression TMININ 68 ns Switching frequency fSW 2 MHz 29 40 VVCC1=5V, CLOADJ= 100 pF, VEN=50%, VJFDrv=50%, VIN=H VVCC1=5V 1) The parameter is not subject to production test - verified by design/characterisation 2) See Figure 8 Preliminary Datasheet 18 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Outline Dimensions 5 Outline Dimensions FOOTPRINT DOCUMENT NO. Z8B00160774 DIM A A1 b c D E E1 e N L h T F1 F2 F3 Figure 9 MILLIMETERS MIN MAX 2.65 0.10 0.30 0.30 0.51 0.23 0.32 12.60 13.00 10.00 10.65 7.40 7.60 1.27 BSC 19 0.40 1.27 0.25 0.75 0° 8° 9.73 0.65 1.67 SCALE INCHES MIN 0.004 0.012 0.009 0.496 0.394 0.291 MAX 0.104 0.012 0.020 0.013 0.512 0.419 0.299 0 1.0 0 1.0 2mm EUROPEAN PROJECTION 0.050 BSC 19 0.016 0.010 0° 0.050 0.030 8° 0.383 0.026 0.066 ISSUE DATE 19.04.2011 REVISION 02 PG-DSO-19-4 Preliminary Datasheet 19 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Outline Dimensions Notes 1. You can find all of our packages, sorts of packing and others in our Infineon Internet Page “Products”: http://www.infineon.com/cms/en/product/technology/packages/. Preliminary Datasheet 20 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Application Hints 6 Application Hints This chapter gives some hints on how the auxiliary supplies can be set up to supply the driver. 6.1 Driver Supply Set up Figure 10 shows the standard topology where the auxiliary supply is connected between VCC2 and VEE2. In this case the internal regulator is used to create the -19 V VReg supply. +5V CVCC1 GND IN VCC1 +5V CVCC1 JFDrv VCC2 GND1 GND MDrv EN VReg IN CLJFG CVReg CVEE2 Isolated, floating IN VCC1 VCC2 GND1 MDrv EN VReg IN -22V … -28V VEE2 CVEE2 Isolated, floating CLJFG -22V … -28V BSEN 1EDI30J12Cx Figure 10 CVReg VEE2 BSEN a) JFDrv b) 1EDI30J12Cx Isolated and floating supply, a) cascode configuration, b) only JFET It is also possible to supply the driver with -19 V directly. In this case (shown in Figure 11) the pins VReg and VEE2 are shorted and CVEE2 as well as the corresponding diode are not needed. It has to be made sure that the -19 V supply is accurate within +/- 5 %. +5V CVCC1 GND IN VCC1 +5V CVCC1 JFDrv VCC2 GND1 GND MDrv EN VReg IN CLJFG VEE2 CVReg IN -19V +/- 5% Figure 11 JFDrv VCC2 GND1 EN Isolated, floating IN MDrv CVReg VReg Isolated, floating CLJFG -19V +/- 5% VEE2 BSEN a) VCC1 BSEN 1EDI30J12Cx b) 1EDI30J12Cx Isolated and floating direct supply, a) cascode configuration, b) only JFET The third option of connecting the auxiliary supply is to connect it between the MOSFET drain and VEE2 (Figure 12). Since the auxiliary power supply is not connected to the reference node of the driver stage (VCC2) an additional 10 Ω resistor is needed between the power supply and the VEE2 pin. This resistor limits the current coming from the supply when current is switched through the MOSFET. When a current is switched through the MOSFET a voltage is induced in the parasitic inductances of the MOSFET which leads to a voltage difference between the reference node of the driver and the supply reference node. As in the first described method the internal regulator is active and supplies the driver stages with the needed -19 V. When using this power supply option for switches which MOSFET drains are connected to the same node and potential one power supply can be used to power two or more driver stages. The best example are the low side switches in a H-bridge (see Figure 6 and Figure 14). Preliminary Datasheet 21 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Application Hints +5V CVCC1 GND IN VCC1 JFDrv VCC2 GND1 MDrv EN VREG IN CLJFG CVReg CVEE2 -22V … -28V VEE2 Isolated, fixed BSEN 1EDI30J12Cx Figure 12 MOSFET drain related supply An alternative method of supplying the low-side driver is via a bootstrapping scheme from the high-side supply (shown in Figure 13). This cascaded bootstrap supply transfers the needed energy via a bootstrapping capacitor (CBS) to the low-side. Additional information on how to activate the bootstrap mode can be found in Chapter 3.2.4 Bootstrap supply mode and start up. HV supply GND VCC1 IN GND MDrv VReg CVReg CVEE2 CLJFG HS_IN Bootstrap HS BSEN GND EN LS_IN IN +5V CVCC1 GND MDrv CVReg CVEE2 CLJFG LS_IN VReg IN CLJFG CVEE2 -19V … -28V Bootstrap HS VCC1 JFDrv VCC2 GND1 MDrv EN VReg IN CLJFG CVReg CVEE2 VEE2 BSEN Figure 13 EN CVReg 1EDI30J12Cx VEE2 a) MDrv BSEN JFDrv VReg VCC2 GND1 CBS VCC2 GND1 HV related JFDrv VEE2 Bootstrap LS 1EDI30J12Cx VCC1 VCC1 -19V … -28V VEE2 +5V CVCC1 +5V CVCC1 VCC2 GND1 EN HS_IN HV related JFDrv Bootstrap LS +5V CVCC1 HV supply BSEN 1EDI30J12Cx b) 1EDI30J12Cx Cascaded bootstrap supply, a) cascode configuration, b) only JFET In case a normally off behavior is not needed or desired the JFET can be used without the cascoded MOSFET. Topologies depicting a normally on circuit are shown in Figure 10 b), Figure 11 b) and Figure 13 b). In these cases a short circuit in a failure event cannot be prevented due to the fact that every safety aspect of the Direct Drive JFET Topology is deactivated. Preliminary Datasheet 22 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Application Hints 800V +5V VCC1 CVCC1 GND LS_IN +5V JFDrv GND1 MDrv EN VReg IN CLJFG VCC1 CVCC1 VCC2 GND CVReg CVEE2 LS_IN +5V VCC1 CVCC1 GND LS_IN VCC2 GND1 MDrv EN VReg IN VEE2 BSEN BSEN +5V EN VReg IN CLJFG VCC1 CVCC1 VCC2 MDrv CVReg CVEE2 1EDI30J12Cx JFDrv GND1 -25V_H CLJFG VEE2 1EDI30J12Cx C JFDrv CVReg CVEE2 GND LS_IN JFDrv VCC2 GND1 MDrv EN VREG IN CLJFG VEE2 VEE2 BSEN BSEN 1EDI30J12Cx CVReg CVEE2 C 1EDI30J12Cx -25V Figure 14 Application drawing for high side bootstrap supply (FB), low-side normally-on (refer to Figure 6 for low-side normally-off variant) Figure 14 shows a full bridge with a normally-on low-side configuration. The high-side stages are powered with bootstrapping while the low-side stages are powered with an isolated and fixed supply that is GND related. The corresponding normally-off variant can be seen in Figure 6 6.2 Gate clamping diode The external gate clamping diode connects the JFET gate to the MOSFET drain potential. In case the auxiliary power supply of the driver is not active due to power supply failure or reverse startup this diode ensures the normally-off behavior of the circuit. Due to the normally-on behavior of the JFET and the cascoded normally-off MOSFET, the voltage is being blocked at the MOSFET. The Vds voltage that is building up over the switched-off MOSFET is being mirrored to the JFET Vgs voltage via gate clamping diode connecting the MOSFET drain to the JFET gate until the level reaches the JFET pinch off voltage and the JFET itself blocks the voltage (see Chapter 3.2.3). The voltage rating of the diode is mainly depenent on the parasitic inductance between JFET source and MOSFET drain times the current change over time. An Infineon BAS16 diode capable of blocking 80 V should be sufficient for most layouts. A resistor should be placed in series with the diode to limit the current through the diode. It has to be matched to the maximum current rating of the used diode. Typically it should be around 5 times larger than the gate resistance in order not to slow down the turn-on of the JFET. Preliminary Datasheet 23 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Application Hints 6.3 Reference Layout, Thermal Layout, Layout Guide Lines In this chapter the reference and thermal layouts are displayed. Please contact our local sales team for additional information about placement priorities. RGJ CVREG Figure 15 Typical layout of a1EDI30J12CP driver stage Figure 16 Thermal reference layout of a 1EDI30J12CP driver stage Preliminary Datasheet 24 PMOS BSC30P03NS3G DVREG DVEE2 LCR CVCC1 CVCC1.2 RGM 1EDI30J12CP IN CVEE2 LCD EN Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP Application Hints Thermal Vias 35µm copper 50x40x1.5mm FR4 1.5mm 35µm copper Figure 17 PCB Stack - Thermal reference layout Preliminary Datasheet 25 Rev. 1.3, 2014-11-12 EiceDRIVER™ Enhanced 1EDI30J12CP 1EDI EiceDRIVER™ Enhanced 1EDI30J12Cx Revision History: 2014-11-12, Rev. 1.31) Previous Revision: 1.2 Page Subjects (major changes since last revision) --- Removed 1EDI30J12CL (150mil variant) --- 1) Preliminarydatasheeet may be changed without notice. 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VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited. Last Trademarks Update 2011-11-11 Preliminary Datasheet Rev. 1.3, 2014-11-12 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG