[AK4254] AK4254 7 AK4254 7 2 2 CMOS 6dB DC AK4254 DVD DTV AV 7 2 6dB Sync-tip LPF : 6MHz / 2.7 ∼ 3.6V Ta=-40 ∼ +85°C 30pin VSOP 0.1uF VIN1 0.1uF VIN2 0.1uF VIN3 0.1uF VIN4 0.1uF VIN5 0.1uF VIN6 0.1uF VIN7 µP I/F (I2C, 3 ) SW1 LPF +6dB VOUT1 Sync-tip Clamp SW2 AVDD AVSS LPF +6dB TEST VOUT2 PDN P/S I2C/SEL22 Clock CDTI/SDA/SEL21 CCLK/SCL/SEL20 CSN/SEL12 Control Clock Generator Generator I/F CAD1/SEL11 Charge Charge CAD0/SEL10 Pump Pump CVDD2 CP2 CN2 CVEE2 CVSS2 1uF CVSS1 1 uF CVEE1 1uF CP1 CN1 CVDD1 1uF Figure 1. Block Diagram MS0586-J-01 2007/08 -1- [AK4254] AK4254VF AKD4254 -40 ∼ +85°C 30pin VSOP CVDD1 1 30 CVDD2 CP1 2 29 CP2 CN1 3 28 CN2 CVSS1 4 27 CVSS2 CVEE1 5 26 CVEE2 VOUT1 6 25 VOUT2 AVDD 7 24 PDN AVSS 8 23 I2C/SEL22 TEST 9 22 CDTI/SDA/SEL21 P/S 10 21 CCLK/SCL/SEL20 VIN1 11 20 CSN/SEL12 VIN2 12 19 CAD1/SEL11 VIN3 13 18 CAD0/SEL10 VIN4 14 17 VIN7 VIN5 15 16 VIN6 AK4254 Top View MS0586-J-01 2007/08 -2- [AK4254] No. 1 Pin Name CVDD1 I/O - 2 CP1 O 3 CN1 I 4 CVSS1 - 5 CVEE1 O 6 7 8 VOUT1 AVDD AVSS O - 9 TEST I 10 P/S I 11 12 13 14 15 16 17 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 CAD0 SEL10 CAD1 SEL11 I I I I I I I I I I I CSN I SEL12 CCLK SCL SEL20 CDTI SDA SEL21 I I I I I I/O I I2C I SEL22 I 18 19 20 21 22 23 Function Charge Pump Power Supply pin, 2.7V∼3.6V Positive Charge Pump Capacitor Terminal 1 Pin Connect to CN1 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. Negative Charge Pump Capacitor Terminal 1 Pin Connect to CP1 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP pin. Non polarity capacitors can also be used. Charge Pump Ground Pin, 0V Connect to VEE1 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CVSS1 pin. Non polarity capacitors can also be used. Negative Voltage Output Pin for Video Amplifier 1 Connect to CVSS1 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CVSS1 pin. Non polarity capacitors can also be used. Video Output #1 Pin Analog Power Supply Pin, 2.7V∼3.6V Analog Ground Pin, 0V Test Pin This pin should be connected to AVSS. Parallel/Serial Control Mode Pin “L”: Serial Control Mode, “H”: Parallel Control Mode Video Input #1 Pin Video Input #2 Pin Video Input #3 Pin Video Input #4 Pin Video Input #5 Pin Video Input #6 Pin Video Input #7 Pin Chip Address 0 in Serial Control Mode Input Selector 1 Control #0 Pin in Parallel Control Mode Chip Address 1 in Serial Control Mode Input Selector 1 Control #1 Pin in Parallel Control Mode Chip Select Pin in Serial Control Mode, I2C pin = “L” This pin should be connected to AVSS in Serial Control Mode. I2C pin =“H” Input Selector 1 Control #2 Pin in Parallel Control Mode Control Data Clock Pin in Serial Control Mode, I2C pin = “L” Control Data Clock Pin in Serial Control Mode, I2C pin = “H” Input Selector 2 Control #0 Pin in Parallel Control Mode Control Data Input Pin in Serial Control Mode, I2C pin = “L” Control Data Pin in Serial Control Mode, I2C pin = “H” Input Selector 2 Control #1 Pin in Parallel Control Mode Control Mode Select Pin in Serial Control Mode “L”: 3-wire Serial Mode, “H”: I2C Bus mode Input Selector 2 Control #2 Pin in Parallel Control Mode MS0586-J-01 2007/08 -3- [AK4254] No. Pin Name I/O 24 PDN I 25 VOUT2 O 26 CVEE2 O 27 CVSS2 - 28 CN2 I 29 CP2 O 30 Note: CVDD2 - Function Power-Down Mode Pin When at “L”, the AK4254 is in the power-down mode and held in reset, the AK4254 must always be reset upon power-up in Serial Control Mode (P/S pin = “L”). Video Output #2 Pin. Negative Voltage Output Pin for Video Amplifier 2 Connect to CVSS2 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CVSS2 pin. Non polarity capacitors can also be used. Charge Pump Ground Pin, 0V Connect to CVEE2 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CVSS2 pin. Non polarity capacitors can also be used. Negative Charge Pump Capacitor Terminal 2 Pin Connect to CP2 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP2 pin. Non polarity capacitors can also be used. Positive Charge Pump Capacitor Terminal 2 Pin Connect to CN2 with a 1.0μF capacitor that has the low ESR (Equivalent Series Resistance) over all temperature range. When this capacitor has the polarity, the positive polarity pin should be connected to the CP2 pin. Non polarity capacitors can also be used. Charge Pump Power Supply Pin, 2.7V∼3.6V CADO/SEL10, CADT/SEL11, CSN/SEL12, CCLK/SCL/SEL20, CDTI/SDA/SEL21, I2C/SEL22 Classification Pin Name Analog Digital VIN1-7 CSN/SEL12 AVDD MS0586-J-01 AVSS 2007/08 -4- [AK4254] (AVSS=CVSS1=CVSS2=0V; Note: 1) Parameter Power Supply (Note: 2) Input Current (any pins except for supplies) Input Voltage (Note: 3) (VIN1-7, I2C/SEL22, CDTI/SDA/SEL21, CCLK/SCL/SEL20, CSN/SEL12, CAD1/SEL11, CAD0/SEL10, PDN, P/S pins) Ambient Operating Temperature Storage Temperature Note: 1. Note: 2. AVSS CVDSS1, CVSS2 Note: 3. SDA, SCL pins max (AVDD pin +0.3)V, CN1, CN2 pin Symbol AVDD CVDD1 CVDD2 IIN VIN min -0.3 -0.3 -0.3 -0.3 max 4.0 4.0 4.0 ±10 AVDD+0.3 or 4.0 Units V V V mA V Ta Tstg -40 -65 85 150 °C °C max 4.0V WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. (AVSS=CVSS1=CVSS2=0V; Note: 1) Parameter Power Supply (Note: 4) Symbol AVDD CVDD1, CVDD2 Min 2.7 Typ 3.0 AVDD max 3.6 Units V V Note: 4. AVDD CVDD1, CVDD2 *AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet. DC (Ta = -40∼85°C; AVDD=CVDD1=CVDD2=2.7V∼3.6V) Parameter Symbol High-Level Input Voltage VIH Low-Level Input Voltage VIL Low-Level Output Voltage VOL (SDA pin: Iout= 3mA) Input Leakage Current Iin MS0586-J-01 min 70%AVDD - typ - max 30%AVDD 0.4 Units V V V - - ± 10 μA 2007/08 -5- [AK4254] (Ta = 25°C; AVDD=CVDD1=CVDD2=3.0V; unless otherwise specified. Note: 5, Note: 6) Parameter Conditions min typ max Units Gain Input=0.3Vp-p, 100kHz 5.3 6 6.7 dB Frequency Response Response at 6MHz -2.0 +2.0 dB Input=0.3Vpp, Sin Wave Response at 27MHz -40 -20 dB (0dB at 100kHz) Group Delay Distortion 10 100 ns |GD3MHz GD6MHz| Dynamic Output Signal f=100kHz, maximum with distortion < 1.0%. 2.52 Vpp Inter channel Isolation f=4.43MHz, 1Vp-p input 65 dB S/N Reference Level = 0.7Vp-p, 65 dB BW= 100kHz to 6MHz. Differential Gain 0.7Vpp 5steps modulated staircase. +0.4 % Chrominance & burst are 280mVpp, 4.43MHz. Differential Phase 0.7Vpp 5steps modulated staircase. +2.5 Degree Chrominance & burst are 280mVpp, 4.43MHz. Load Resistance R1+R2 (Note: 9) 140 150 Ω 400 pF Load Capacitance C1 (Note: 9) 15 pF C2 (Note: 9) Power Supply Current AVDD+CVDD1+CVDD2 20 30 mA Normal Operation (PDN pin = “H”;Note: 7) AVDD+CVDD1+CVDD2 10 100 Power-Down Mode μA (PDN pin = “L”, Note: 8) Note: 5. Note: 6. Input Sync Tip Level=-0.43V∼-0.14V( ) Horizontal Line Sync Pulse=4.0μs ∼5.4μs, Equalizing Pulse=2.0μs ∼2.7μs, Serration Pulse=4.0μs ∼5.4μs Note: 7. VIN Note: 8. (P/S, I2C/SEL22, CDTI/SDA/SEL21, CCLK/SCL/SEL20, SN/SEL12, CAD1/SEL11, CAD0/SEL10) AVSS Note: 9. Refer to the Figure 2. R1 75 Ω VOUT R2 75 Ω C2 max: 15pF (C2) C1 max: 400pF (C1) Figure 2. Load Resistance R1+R2 and Load Capacitance C1/C2. MS0586-J-01 2007/08 -6- [AK4254] (Ta =-40∼85°C; AVDD=CVDD1=CVDD2=2.7V∼3.6V; CL = 20pF) Parameter Symbol Control Interface Timing (3-wire Serial Mode) tPDCS PDN “↑” to CSN “↓” tCCK CCLK Period tCCKL CCLK Pulse Width Low tCCKH Pulse Width High tCDS CDTI Setup Time tCDH CDTI Hold Time tCSW CSN “H” Time tCSS CSN “↓” to CCLK “↑” tCSH CCLK “↑” to CSN “↑” 2 Control Interface Timing (I C Bus mode): SCL Clock Frequency fSCL PDN “↑” to SDA “↓” @SCL = “H” tPDSD Bus Free Time Between Transmissions tBUF Start Condition Hold Time tHD:STA (prior to first clock pulse) Clock Low Time tLOW Clock High Time tHIGH Setup Time for Repeated Start Condition tSU:STA SDA Hold Time from SCL Falling (Note: 10) tHD:DAT SDA Setup Time from SCL Rising tSU:DAT Rise Time of Both SDA and SCL Lines tR Fall Time of Both SDA and SCL Lines tF Setup Time for Stop Condition tSU:STO Pulse Width of Spike Noise tSP Suppressed by Input Filter Capacitive load on bus Cb Reset Timing tPD PDN Pulse Width (Note: 11) Note: 10. 300ns(SCL ) Note: 11. PDN pin Min typ max 150 200 80 80 40 40 150 50 50 Units ns ns ns ns ns ns ns ns ns 1.3 1.3 0.6 400 - kHz μs μs μs 1.3 0.6 0.6 0 0.1 0.6 0 0.3 0.3 50 μs μs μs μs μs μs μs μs ns - 400 pF 150 ns “L” PDN pin = “L” Note: 12. I2C is a registered trademark of Philips Semiconductors. MS0586-J-01 2007/08 -7- [AK4254] VIH PDN VIL tPDCS VIH CSN VIL tCSS tCCK tCCKL tCCKH VIH CCLK VIL tCDH tCDS C0 C1 CDTI A4 R/W WRITE VIH VIL (3-wire Serial mode) tCSW VIH CSN VIL tCSH VIH CCLK CDTI VIL D3 D2 D1 WRITE VIH D0 VIL (3-wire Serial mode) VIH PDN VIL tPDSD VIH SDA VIL tLOW tR tHIGH tF VIH SCL VIL tHD:STA tHD:DAT tSU:DAT Start tSU:STA Start 2 I C Bus mode MS0586-J-01 1 2007/08 -8- [AK4254] VIH SDA VIL tLOW tBUF tR tHIGH tF tSP VIH SCL VIL tHD:STA Stop tHD:DAT tSU:DAT tSU:STA Start tSU:STO Start I2C Bus mode Stop 2 tPD VIH PDN VIL MS0586-J-01 2007/08 -9- [AK4254] PDN pin PDN pin “L” “H” PDN pin “L” AK4254 PDN pin = “L” (P/S pin =“H”) AK4254 P/S pin=“H” PDN pin L H H SEL12-10 pin x “LLL” “LLL” Table 1. VOUT1 PDN pin L H H CVEE1 pin GND GND -CVDD1 VOUT1 pin GND GND Video (x: Don’t Care) (Parallel Control Mode) SEL22-20 pin x “LLL” “LLL” Table 2. VOUT2 CVEE2 pin GND GND -CVDD2 VOUT2 pin GND GND Video (x: Don’t Care) (Parallel Control Mode) (PDN pin= “L”) AK4254 PDN pin “L” VOUT1-2 GND (PDN pin= “H”) AK4254 7:2 = “H”) SEL12-10 pin (P/S pin SEL22-20 pin SEL12 pin L L L L H H H H Note: 13. SEL11 pin SEL10 pin VOUT1 pin L L Off Note: 13) L H VIN1 H L VIN2 H H VIN3 L L VIN4 L H VIN5 H L VIN6 H H VIN7 Off GND Table 3. Input Selector 1 (Parallel Control Mode) MS0586-J-01 2007/08 - 10 - [AK4254] SEL22 pin L L L L H H H H Note: 14. SEL21 pin SEL20 pin VOUT2 L L Off Note: 14) L H VIN1 H L VIN2 H H VIN3 L L VIN4 L H VIN5 H L VIN6 H H VIN7 Off GND Table 4. Input Selector 2 (Parallel Control Mode) (P/S pin = “L”) AK4254 P/S pin= “L” PDN pin L H H SEL 12-10 bit x “000” “000” Table 5. VOUT1 PDN pin L H H AK4254 VOUT1 pin GND GND Video (x: Don’t Care) (Serial Control Mode) SEL 22-20 bit x “000” “000” Table 6. VOUT2 (a) CVEE1 pin GND GND -CVDD1 CVEE2 pin GND GND -CVDD2 VOUT2 pin GND GND Video (x: Don’t Care) (Serial Control Mode) (PDN pin= “L”) PDN pin “L” VOUT1-2 GND (b) (PDN pin= “H”) (P/S pin = “L”) SEL12 bit 0 0 0 0 1 1 1 1 Note: 15. SEL12-10 bit SEL11 bit SEL10 bit VOUT1 pin 0 0 Off Note: 15) 0 1 VIN1 1 0 VIN2 1 1 VIN3 0 0 VIN4 0 1 VIN5 1 0 VIN6 1 1 VIN7 Off GND Table 7. Input Selector 1 (Serial Control Mode) MS0586-J-01 SEL22-20 bit (default) 2007/08 - 11 - [AK4254] SEL22 bit 0 0 0 0 1 1 1 1 Note: 16. AK4254 SEL21 bit SEL20 bit VOUT2 pin 0 0 Off Note: 16) 0 1 VIN1 1 0 VIN2 1 1 VIN3 0 0 VIN4 0 1 VIN5 1 0 VIN6 1 1 VIN7 Off GND Table 8. Input Selector 2 (Serial Control Mode) (default) 150Ω LPF (Figure 3) (Figure 4) 0V (Figure 3) Ca Cb DC 1.0μF CP VSS ESR( ) (Figure 3) Note: 17 AK4254 (CVEE>-0.8V) -0.6V(typ) Note: 17. Input Sync Tip Level=-0.43V∼-0.14V( ) Horizontal Line Sync Pulse=4.0μs ∼5.4μs Equalizing Pulse=2.0μs ∼2.7μs Serration Pulse=4.0μs ∼5.4μs AK4254 CVDD1 Charge Pump CP1 CN1 Negative Power CVSS1 (+) 1uF Cb CVEE1 1uF (+) Ca Figure 3. MS0586-J-01 2007/08 - 12 - [AK4254] AK4254 75Ω VOUT1 (VOUT2) 75Ω 0V Figure 4. Video AK4254 I2C Bus mode (I2C pin = “H”) 3-wire Serial mode (I2C pin = “L”) 1. 3-wire Serial Mode (I2C pin = “L”) 3 I/F (CSN, CCLK, CDTI pin) I/F Chip address (C1,C0 CAD1,CAD0 pin ), Read/Write (1bit, “1” , ), Register address (MSB first, 5bits) Control Data (MSB first, 8bits) Chip Address CCLK “↓” “↑” CSN “ ” 16 CCLK“ ” 1 CSN “H” CCLK 5MHz (max) PDN pin= “L” CSN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CCLK CDTI C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 C1,C0: R/W: A4-A0: D7-D0: Chip Address: (C1 = CAD1, C0 = CAD0) READ/WRITE (1: WRITE ) Register Address Control Data Figure 5. 3-wire Serial mode I/F MS0586-J-01 2007/08 - 13 - [AK4254] 2. I2C Bus mode AK4254 I2C Bus mode (max: 400kHz) 2-1. WRITE I2C Bus mode (Start Condition) (Figure 12) (R/W) (Figure 7) Figure 6 “H” SCL 5 AK4254 SDA R/W SDA IC “L” “H” 7 CAD0-1 pin 8 (Figure 13) R/W “0” “00100” 2 (Acknowledge) “1” 2 ( (Figure 8) 3 (Figure 9) AK4254 (Stop Condition) (Figure 12) ) 8 SCL MSB first 8 “H” 7 SDA AK4254 “0” MSB first “L” “H” 1 “01H” “00H” “H” SCL SDA “L” S T A R T SDA “H” “L” “H” SDA (Figure 14) SCL S T O P R/W = "0" Slave S Address Sub Address(n) Data(n) A C K Data(n+1) A C K A C K Data(n+x) A C K P A C K A C K Figure 6. Data Transfer Sequence at the I2C-Bus Mode 0 0 1 0 0 CAD1 CAD0 Figure 7. The First Byte (CAD1,CAD0=CAD1,CAD0 pin 0 0 0 0 0 R/W ) 0 0 A0 D2 D1 D0 Figure 8. The Second Byte D7 D6 D5 D4 D3 Figure 9. Byte Structure after the second byte MS0586-J-01 2007/08 - 14 - [AK4254] 2-2. READ R/W “1” AK4254 READ “01H” “00H” AK4254 2 READ 2-2-1. AK4254 (READ WRITE ) “n” “n+1” = “1”) AK4254 READ (R/W bit 1 READ S T A R T SDA S T O P R/W = "1" Slave S Address Data(n+1) Data(n) A C K Data(n+2) A C K A C K Data(n+x) A C K A C K P A C K Figure 10. CURRENT ADDRESS READ 2-2-2. READ (R/W bit = “1”) WRITE WRITE AK4254 (R/W bit = “1”) (R/W bit = “0”) READ AK4254 1 READ S T A R T SDA S T A R T R/W = "0" Slave S Address Slave S Address Sub Address(n) A C K A C K S T O P R/W = "1" Data(n) A C K Data(n+1) A C K Data(n+x) A C K A C K P A C K Figure 11. RANDOM ADDRESS READ MS0586-J-01 2007/08 - 15 - [AK4254] SDA SCL S P start condition stop condition Figure 12. START and STOP Conditions DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 2 1 8 9 S clock pulse for acknowledgement START CONDITION Figure 13. Acknowledge on the I2C-Bus SDA SCL data line stable; data valid change of data allowed Figure 14. Bit Transfer on the I2C-Bus MS0586-J-01 2007/08 - 16 - [AK4254] Addr 00H 01H Register Name Input Selector Control (Reserved) D7 0 0 D6 SEL22 0 D5 SEL21 0 D4 SEL20 0 D3 0 0 D2 SEL12 0 D1 SEL11 0 D0 SEL10 0 D3 0 0 D2 SEL12 0 D1 SEL11 0 D0 SEL10 0 The PDN pin = “L” resets the all registers to their default values. (Note: 18) “0” (Note: 19) Addr 00H “1” 00H Register Name Input Selector Control Default D7 0 0 D6 SEL22 0 SEL12-10: Input Selector 1 Control (Table 7) “000” VOUT1 GND SEL22-20: Input Selector 2 Control (Table 8) “000” VOUT2 GND D5 SEL21 0 MS0586-J-01 D4 SEL20 0 2007/08 - 17 - [AK4254] Figure 15∼Figure 17 (AKD4254) + 1u + 1u 1 CVDD1 CVDD2 30 2 CP1 CP2 29 3 CN1 CN2 28 4 CVSS1 CVSS2 27 5 CVEE1 CVEE2 26 6 VOUT1 VOUT2 25 7 AVDD PDN 24 8 AVSS SEL22 23 9 TEST SEL21 22 10 P/S SEL20 21 11 VIN1 SEL12 20 12 VIN2 SEL11 19 + + + 10u 1u 75 75 Video out Power Supply 3V 1u AK4254 Video out 0.1u 0.1u DSP or μP 0.1u Video in 0.1u 0.1u 0.1u 13 VIN3 SEL10 18 14 VIN4 VIN7 17 15 VIN5 VIN6 16 0.1u Video in 0.1u Figure 15. Typical Connection Diagram (Parallel Control Mode) 1u 1u + + 1 CVDD1 CVDD2 30 2 3 CP1 CP2 29 CN1 CN2 28 4 CVSS1 CVSS2 27 5 CVEE1 CVEE2 26 6 VOUT1 VOUT2 25 10u 0.1u + 7 AVDD PDN 24 8 AVSS I2C 23 9 TEST CDTI 22 10 P/S CCLK 21 11 VIN1 CSN 20 12 VIN2 CAD1 19 13 VIN3 CAD0 18 14 VIN4 VIN7 17 15 VIN5 VIN6 16 + 1u 1u 75 75 Video out Power Supply 3V + AK4254 Video out 0.1u DSP or μP 0.1u Video in 0.1u 0.1u 0.1u 0.1u 0.1u Video in Figure 16. Typical Connection Diagram (Serial Control Mode: 3-wire Serial Mode) MS0586-J-01 2007/08 - 18 - [AK4254] 1u 1u + + 1 CVDD1 CVDD2 30 2 3 CP1 CP2 29 CN1 CN2 28 4 5 CVSS1 CVSS2 27 CVEE1 CVEE2 26 0.1u + 6 VOUT1 7 8 VOUT2 25 AVDD PDN 24 AVSS I2C 23 9 TEST SDA 22 10 P/S SCL 21 11 VIN1 CSN 20 12 VIN2 CAD1 19 13 VIN3 CAD0 18 14 VIN4 VIN7 17 15 VIN5 VIN6 16 Video out 10u + 1u 1u 75 75 Power Supply 3V + AK4254 Video out 0.1u DSP or μP 0.1u 0.1u Video in 0.1u 0.1u 0.1u 0.1u Video in Figure 17. Typical Connection Diagram (Serial Control Mode: I2C Bus mode) 1. AVDD, CVDD1-2 AVSS, CVSS1-2 PC 2. AK4254 0.1uF DC Figure 15∼Figure 17 3. 4. AK4254 150ohm Figure 1 2 MS0586-J-01 +6dB(typ) 2007/08 - 19 - [AK4254] 30pin VSOP (Unit: mm) 1.5MAX *9.7±0.1 0.3 30 16 15 1 0.22±0.1 7.6±0.2 5.6±0.1 A 0.15 +0.10 -0.05 0.65 0.12 M 0.45±0.2 +0.10 0.08 0.10 -0.05 1.2±0.10 Detail A NOTE: Dimension "*" does not include mold flash. MS0586-J-01 2007/08 - 20 - ASAHI KASEI [AK4254] AKM AK4254VF XXXBYYYYC XXXBYYYYC Date code identifier XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character) Date (YY/MM/DD) 07/02/20 07/08/10 Revision 00 01 Reason Page Contents 6 Interchannel Isolation: typ.50dB Æ typ.65dB 7 PDN “↑” to CSN “↓”: tPDCS PDN “↑” to SDA “↓” @SCL = “H” : tPDSD 8 WRITE (tPDCS I2C Bus mode 1 (tPDSD ) Figure15 Figure16 Figure17 (CVSS1 CVSS2 GND ) 17 MS0586-J-01 ) 2007/08 - 21 - ASAHI KASEI [AK4254] • • • • • • MS0586-J-01 2007/08 - 22 -