HS-2420RH Radiation Hardened Fast Sample and Hold July 1995 Features Description • Maximum Acquisition Time The HS-2420RH is a radiation hardened monolithic circuit consisting of a high performance operational amplifier with its output in series with an ultra-low leakage analog switch and MOSFET input unity gain amplifier. - 10V Step to 0.1%. . . . . . . . . . . . . . . . . . . . . . . . . . . 4µs - 10V Step to 0.01%. . . . . . . . . . . . . . . . . . . . . . . . . . 6µs • Maximum Drift Current . . . . . . . . . . . . . . . . . . . . . .10nA (Maximum Over Temperature) With an external hold capacitor connected to the switch output, a versatile, high performance sample-and-hold or track-andhold circuit is formed. When the switch is closed, the device behaves as an operation amplifier, and any of the standard op amp feedback networks may be connected around the device to control gain, frequency response, etc. When the switch is opened the output will remain at its last level. • TTL Compatible Control Input • Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . .≥80dB • Total Gamma Dose. . . . . . . . . . . . . . . . . 1 x 105 RAD(SI) • No Latch-Up Performance as a sample-and-hold compares very favorably with other monolithic, hybrid, modular, and discrete circuits. Accuracy to better than 0.01% is achievable over the temperature range. Fast acquisition is coupled with superior droop characteristics, even at high temperatures. High slew rate, wide bandwidth, and low acquisition time produce excellent dynamic characteristics. The ability to operate at gains greater than 1 frequently eliminates the need for external scaling amplifiers. Applications • Data Acquisition Systems • D to A Deglitcher • Auto Zero Systems • Peak Detector • Gated Op Amp The device may also be used as a versatile operational amplifier with a gated output for applications such as analog switches, peak holding circuits, etc. Ordering Information PART NUMBER HS1-2420RH-Q Pinout TEMPERATURE RANGE PACKAGE -55oC to +125oC 14 Lead CerDIP Functional Diagram 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE (CerDIP) MIL-STD-1835, GDIP1-T14 TOP VIEW OFFSET ADJUST 3 IN- 1 14 SAMPLE/HOLD CONTROL IN+ 2 13 GND OFFSET ADJUST 3 - INPUT 12 NC 4 1 - + + INPUT V+ 5 7 - OUTPUT + 2 OFFSET ADJUST 4 14 Pin DIP 11 HOLD CAPACITOR V- 5 10 NC NC 6 9 V+ OUTPUT 7 8 NC 14 HS-2420RH SAMPLE/ HOLD CONTROL 13 5 11 GND VHOLD CAPACITOR NOTE: Pin Numbers Correspond to DIP Package Only. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com | Copyright © Intersil Corporation 1999 1 Spec Number File Number 518855 3554.1 Specifications HS-2420RH Absolute Maximum Ratings Reliability Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . +40V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±24V Digital Input Voltage (S/H Pin) . . . . . . . . . . . . . . . . . . . . . .+8V, -15V Output Current . . . . . . . . . . . . . . . . . . . . . . . Short Circuit Protected Storage Temperature Range . . . . . . . . . . . . . .-65oC < TA < +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +275oC Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Thermal Resistance θJA θJC CerDIP Package . . . . . . . . . . . . . . . . . . . 74oC/W 18oC/W Maximum Power Dissipation at +125oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W If Device Power Exceeds Package Dissipation Capability, Derate Linearly at the Following Rate CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5mW/oC ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤2000V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Recommended Operating Conditions Operating Temperature Range . . . . . . . . . . . . .-55oC < TA < +125oC Operating Supply Voltage (± VSUPPLY) . . . . . . . . . . . . . . . . . . . ±15V Analog Input Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10V Logic Level Low (VIL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 0.8V Logic Level High (VIH) . . . . . . . . . . . . . . . . . . . . . . . . . 2.0V to 5.0V TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified PARAMETER Input Offset Voltage SYMBOL CONDITIONS VIO TEMPERATURE MIN MAX UNITS 1 +25oC -4 4 mV 2, 3 Input Bias Current IB+ 1 2, 3 IB- Input Offset Current Open Loop Voltage Gain IIO +AVS -AVS Common Mode Rejection Ratio -CMRR +CMRR Output Current +IO -IO Output Voltage Swing +VOP RL = 2kΩ, CL = 50pF, VOUT = +10V +125oC +25oC -55oC, +125oC -6 6 mV -200 200 nA -400 400 nA 1 -200 200 nA 2, 3 -55oC, +125oC -400 400 nA 1 +25oC -50 50 nA 2, 3 -55oC, +125oC -100 100 nA 1 +25oC 25 - kV/V 2, 3 -55oC, +125oC 25 - kV/V 1 +25oC 25 - kV/V 2, 3 -55oC, +125oC 25 - kV/V 1 +25oC 80 - dB 2, 3 -55oC, +125oC 80 - dB 1 +25oC 80 - dB 2, 3 -55oC, +125oC 80 - dB 1 +25oC +15.0 - mA VOUT = -10V 1 +25oC -15.0 - mA RL = 2kΩ, CL = 50pF 1 +25oC +10.0 - V RL = 2kΩ, CL = 50pF, VOUT = -10V V+ = 25V, V- = -5V, VOUT = +10V, VS/H = 10.8V V+ = 5V, V- = -25V, VOUT = -10V, VS/H = 9.2V VOUT = +10V -55oC, +125oC -10.0 - V 1 +25oC - -10.0 V 2, 3 -55oC, +125oC - -10.0 V +ICC 1 +25oC - 5.5 mA -ICC 1 +25oC -3.5 - mA 1 +25oC 80 - dB -VOP Power Supply Rejection Ratio -55oC, +25oC 2, 3 Power Supply Current LIMITS GROUP A SUBGROUPS +PSRR -PSRR RL = 2kΩ, CL = 50pF V+ = 10V and 20V, V- = -15V and -15V 2, 3 V+ = 15V and 15V, V- = -10V and -20V -55oC, +125oC 80 - dB 1 +25oC 80 - dB 2, 3 -55oC, +125oC 80 - dB Spec Number 2 518855 Specifications HS-2420RH TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified PARAMETER Digital Input Current SYMBOL IIN1 CONDITIONS TEMPERATURE MIN MAX UNITS 1 +25oC - 800 µA VIN1 = 0V -55oC, 2, 3 IIN2 VIN2 = 5.0V VIL VIH ID VIN = 0V, RL = 2kΩ, CL = 50pF, S/H = 4.0V - 800 µA - 20 µA - 20 µA 1 +25oC - 0.8 V 2, 3 -55oC, +125oC - 0.8 V 1 +25oC 2.0 - V -55oC, -55oC, 2, 3 Drift Current +125oC +25oC 1 2, 3 Digital Input Voltage LIMITS GROUP A SUBGROUPS +125oC +125oC +125oC 2 2.0 - V -10 10 nA TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample), VIH = 2.0V (Hold), CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified PARAMETER Hold Step Error Transient Response Rise Time and Fall Time TEMPERATURE MIN MAX UNITS VS/H = 0V and 4V, tRISE (VS/H) ≈ 30ns (Note 1) 9 +25oC -20 20 mV CL = 50pF, RL = 2kΩ, AV = +1, VOUT = 200mVP-P 9 +25oC - 100 ns 9 +25oC - 100 ns 9 +25oC - 40 % 9 +25oC - 40 % 9 +25oC 3.5 - V/µs 9 +25oC 3.5 - V/µs SYMBOL VERROR TR(TR) TR(TF) Transient Response Overshoot TR(+OS) Transient Response Slew Rate TR(+SR) TR(-OS) TR(-SR) LIMITS GROUP A SUBGROUP CONDITIONS CL = 50pF, RL = 2kΩ, AV = +1, VOUT = 200mVP-P CL = 50pF, RL = 2kΩ, AV = +1, VOUT = 10VP-P NOTE: 1. VERROR = VOUT (VS/H = 0V) - VOUT (VS/H = 4V) TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample), VIH = 2.0V (Hold), CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified LIMITS PARAMETER SYMBOL Hold Mode Feedthrough Attenuation VATTEN Gain Bandwidth Product Acquisition Time (0.1%) Acquisition Time (0.01%) CONDITIONS NOTE TEMPERATURE +25oC, -55oC, MIN MAX UNITS 70 - dB RL = 2kΩ, CL = 50pF, AV = +1, VIN = 20VP-P, fIN = 50kHz 1 GBWP RL = 2kΩ, CL = 50pF, AV = +1, VIN = 100mVP-P 1 +25oC 2.5 - MHz +tACQ (0.1%) RL = 2kΩ, CL = 50pF, AV = +1, VOUT = 0V and +10V 1 +25oC - 4 µs -tACQ (0.1%) RL = 2kΩ, CL = 50pF, AV = +1, VOUT = 0V and -10V 1 +25oC - 4 µs +tACQ (0.01%) RL = 2kΩ, CL = 50pF, AV = +1, VOUT = 0V and +10V 1 +25oC - 6 µs -tACQ (0.01%) 1 +25oC - 6 µs RL = 2kΩ, CL = 50pF, AV = +1, VOUT = 0V and -10V +125oC NOTE: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are characterized upon initial design release and upon design changes which would affect these characteristics. Spec Number 3 518855 Specifications HS-2420RH TABLE 4. DC ELECTRICAL PERFORMANCE CHARACTERISTICS POST 100KRAD Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample); VIH = 2.0V (Hold); CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified PARAMETER SYMBOL CONDITIONS LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS Input Offset Voltage VIO 1 +25oC -6 6 mV Input Bias Current IB+ 1 +25oC -400 400 nA IB- 1 +25oC -400 400 nA 1 +25oC -100 100 nA 1 +25oC 25 - kV/V 25 - kV/V 25 - kV/V 25 - kV/V Input Offset Current Open Loop Voltage Gain IIO +AVS -AVS Common Mode Rejection Ratio -CMRR +CMRR Output Current +IO -IO Output Voltage Swing +VOP RL = 2kΩ, CL = 50pF, VOUT = +10V 2, 3 RL = 2kΩ, CL = 50pF, VOUT = -10V 1 2, 3 V+ = 25V, V- = -5V, VOUT = +10V, VS/H = 10.8V V+ = 5V, V- = -25V, VOUT = -10V, VS/H = 9.2V VOUT = +10V VOUT = -10V RL = 2kΩ, CL = 50pF Power Supply Current RL = 2kΩ, CL = 50pF +ICC -ICC Power Supply Rejection Ratio +PSRR -PSRR Digital Input Current IIN1 IIN2 V+ = 10V and 20V, V- = -15V and -15V dB 2, 3 -55oC, +125oC 80 - dB 1 +25oC 80 - dB 2, 3 VIL - dB 1 +12.0 - mA 1 +25oC -12.0 - mA 1 +25oC +10.0 - V +10.0 - V - -10.0 V 2, 3 -55oC, +125oC - -10.0 V 1 +25oC - 5.5 mA 1 +25oC -3.5 - mA 1 +25oC 80 - dB 80 - dB 80 - dB 80 - dB -55oC, +125oC +25oC -55oC, +125oC 1 +25oC - 800 µA 2, 3 -55oC, +125oC - 800 µA 1 +25oC - 20 µA - 20 µA - 0.8 V - 0.8 V 2.0 - V 2.0 - V -10 10 nA 1 VIN = 0V, RL = 2kΩ, CL = 50pF, S/H = 4.0V +125oC +25oC 2, 3 ID -55oC, 1 2, 3 Drift Current +125oC 80 1 VIH -55oC, +25oC 2, 3 Digital Input Voltage +125oC - 2, 3 VIN2 = 5.0V -55oC, 80 1 VIN1 = 0V +25oC +25oC 2, 3 V+ = 15V and 15V, V- = -10V and -20V +125oC 1 2, 3 -VOP -55oC, 2 -55oC, +125oC +25oC -55oC, +125oC +25oC -55oC, +125oC +125oC Spec Number 4 518855 Specifications HS-2420RH TABLE 4A. AC ELECTRICAL PERFORMANCE CHARACTERISTICS POST 100KRAD Device Tested at V+ = +15V, V- = -15V, VIL = 0.8V (Sample), VIH = 2.0V (Hold), CH = 1000pF, -Input Tied to Output, Unless Otherwise Specified LIMITS PARAMETER Hold Step Error Transient Response Rise Time and Fall Time SYMBOL GROUP A SUBGROUP TEMPERATURE MIN MAX UNITS VS/H = 0V and 4V, tRISE (VS/H) ≈ 30ns (Note 1) 9 +25oC -20 20 mV CL = 50pF, RL = 2kΩ, AV = +1, VOUT = 200mVP-P 9 +25oC - 100 ns 9 +25oC - 100 ns 9 +25oC - 40 % 9 +25oC - 40 % 9 +25oC 2.0 - V/µs 9 +25oC 2.0 - V/µs CONDITIONS VERROR TR(TR) TR(TF) Transient Response Overshoot TR(+OS) CL = 50pF, RL = 2kΩ, AV = +1, VOUT = 200mVP-P TR(-OS) Transient Response Slew Rate TR(+SR) CL = 50pF, RL = 2kΩ, AV = +1, VOUT = 10VP-P TR(-SR) NOTE: 1. VERROR = VOUT (VS/H = 0V) - VOUT (VS/H = 4V) TABLE 5. BURN-IN DELTA PARAMETERS (TA = +25oC) PARAMETERS DELTA LIMITS VIO ±2.0mV IBIAS ±75nA IIO ±75nA TABLE 6. APPLICABLE SUBGROUPS GROUP A SUBGROUPS MIL-STD-883 METHOD TESTED FOR -Q RECORDED FOR -Q Initial Test 100% 5004 1, 9 1 Interim Test 100% 5004 1, 9, ∆ 1, ∆ PDA 100% 5004 1, ∆ Final Test 100% 5004 2, 3, 10, 11 Group A (Note 1) Sample 5005 1, 2, 3, 9, 10, 11 Subgroup B5 Sample 5005 1, 2, 3 Subgroup B6 Sample 5005 1 Group D Sample 5005 1 Group E, Subgroup 2 Sample 5005 1 CONFORMANCE GROUP 1, 2, 3 NOTE: Alternate Group A testing may be exercised in accordance with Method 5005 of MIL-STD-883. Spec Number 5 518855 HS-2420RH Test Circuits ALL RESISTORS = ±1% ALL CAPACITORS = ±10% VDC 100kΩ 10kΩ +VCC -VCC S/H 2 S2 1 1 2 A S7 1 S4 2 100kΩ - DUT S7 1 50Ω 2 1 S1 2 1 1 OPEN GND + NULL AMP + 3 X1 X-1 S5 2 BUFFER CH = 1000pF S6 50Ω S3 2 1 50pF 2kΩ 3 +VCC 1MΩ VAC ILOAD - 50Ω + AOUT 4 3 2 EOUT S8 1 FIGURE 1. TEST FIXTURE SCHEMATIC (SWITCH POSITIONS S1 - S8 DETERMINE CONFIGURATION) +5V SINEWAVE INPUT IN2 IN1 IN3 IN4 IN5 IN6 IN7 IN8 A2 A1 EN +15V -15V - - VOUT DUT + VOUT + OUT -15V +15V DUT VIN 2kΩ 2kΩ 50pF CH = 1000pF 50Ω S/H 50pF CH = 1000pF A0 SAMPLE/HOLD CONTROL INPUT GBWP is the Frequency of VINPUT at which: NOTE: Compute Hold Mode Feedthrough Attenuation from the Formula: VOUT 20 log ---------------------- = – 3dB VINPUT VOUT HOLD FeedthroughAttenuation = 20 log ----------------------------------- VIN HOLD Where VOUT HOLD = Peak-Peak Value of Output Sinewave during the Hold Mode. FIGURE 3. GAIN BANDWIDTH PRODUCT FIGURE 2. HOLD MODE FEEDTHROUGH ATTENUATION Spec Number 6 518855 HS-2420RH Test Circuits (Continued) SEND SAMPLE COMMAND SET t2 TO 7µs INITIALLY FINE tACQ MEASUREMENT LOOP COURSE tACQ MEASUREMENT LOOP INCREMENT t2 BY 50ns (50ns LONGER DELAY) DIGITIZE V1 AT t1 (≈10µs) DIGITIZE V2 AT t2 DECREMENT t2 BY 50ns DIGITIZE V1 AT t1 (≈10µs) CALCULATE V1 - V2 IS ∆V ≥ 0.01%? YES DIGITIZE V2 AT t2 NO DECREMENT t2 BY 50ns YES RECORD tACQ NO CALCULATE V1 - V2 IS ∆V ≥ 0.01%? NOTE: See Test Diagram, Timing Diagram FIGURE 4. ACQUISITION TIME (tACQ TO 0.01% IS SHOWN, tACQ TO 0.1% IS DONE IN THE SAME MANNER) t1 V1 HS-2420RH - V1 DIGITIZER - COMPUTER CONTROLLER + + V2 DIGITIZER 2kΩ 1000pF 0V t1 OR ≈10µs 0V -10V V2 50pF +10V t2 DELAY CONTROL DELAY S/H CONTROL t2 VARIABLE DELAY FIGURE 5 Spec Number 7 518855 HS-2420RH Timing Waveforms 10V VIN (POS tACQ CASE) 0V 2V S/H CONTROL 0.01% OR 0.1% ENVELOPE 0V 10V DUT OUTPUT (POS tACQ CASE) 0V t1 ≈ 10µs (t1 DIGITIZER COMMAND) t1 t2 (t2 DIGITIZER COMMAND) t2 FIGURE 6. TIMING DIAGRAM FOR ACQUISITION TIME, (POSITIVE tACQ CASE) VFINAL VPEAK +V 0V 90% 10% INPUT 10% 0V 90% VFINAL VPEAK -V +OS, tR tR -OS, tF FIGURE 7A tF FIGURE 7B FIGURE 7. OVERSHOOT, RISE AND FALL TIME WAVEFORMS +V +V +V +V 75% 25% 25% 75% INPUT -V -V -V -V +SL ∆t -SL FIGURE 8A ∆t FIGURE 8B FIGURE 8. SLEW RATE WAVEFORMS Typical Performance Curves VSUPPLY = ±15VDC, TA = +25oC, CH = 1000pF, Unless Otherwise Specified 1000 1000 LOWER 3dB FREQUENCY = 10Hz DRIFT DURING HOLD AT +25oC mV/s OUTPUT NOISE “HOLD” MODE 100 HOLD STEP OFFSET ERROR (mV) 1.0 0.1 100 mV RMS UNITY GAIN PHASE MARGIN (DEG) 10 10 UNITY GAIN BANDWIDTH (MHz) MIN SAMPLE TIME SLEW RATE/ FOR 0.1% ACCURACY CHARGE RATE 10V SWINGS (ms) V/(ms) 0.01 10pF 100pF 1000pF 0.01mF 0.1mF EQUIV. INPUT NOISE “SAMPLE” MODE - 100K SOURCE RESISTANCE EQUIV. INPUT NOISE “SAMPLE” MODE - 0K SOURCE RESISTANCE 1 10 1.0mF CH VALUE 100 1K 10K 100K 1M BANDWIDTH FIGURE 9. TYPICAL SAMPLE AND HOLD PERFORMANCE AS A FUNCTION OF HOLDING CAPACITOR FIGURE 10. BROADBAND NOISE CHARACTERISTICS Spec Number 8 518855 HS-2420RH Typical Performance Curves VSUPPLY = ±15VDC, TA = +25oC, CH = 1000pF, Unless Otherwise Specified (Continued) 1000 OPEN LOOP VOLTAGE GAIN (dB) 100 ID (pA) 100 10 CH = 1000pF 60 40 CH = 1.0µF 20 CH = 0.1µF 0 -20 1 -50 -25 0 +25 +50 +75 TEMPERATURE (oC) +100 +125 10 -30 -40 -50 -60 -70 -80 -90 100 1K 10K 100K 1M 100 1K 10K 100K FREQUENCY (Hz) 1M 10M 100M FIGURE 12. OPEN LOOP FREQUENCY RESPONSE OPEN LOOP PHASE ANGLE (DEGREES) FIGURE 11. DRIFT CURRENT vs TEMPERATURE ATTENUATION (dB) CH = 0.01µF CH = 100pF 80 10M 0 CH = 0.01µF CH =1000pF 20 CH = 1.0µF 40 CH = 0.1µF 60 80 100 CH ≤ 100pF 120 140 160 180 200 220 240 10 100 1K ±10V SINUSOIDAL INPUT FREQUENCY (Hz) 10K 100K 1M 10M 100M FREQUENCY (Hz) FIGURE 13. HOLD MODE FEEDTHROUGH ATTENUATION CH = 1000pF FIGURE 14. OPEN LOOP PHASE RESPONSE Burn-In Circuit Irradiation Circuit HS-2420RH CERAMIC DIP 1 R1 2 +IN 3 4 OFF ADJ OFF ADJ 5 -V -15V C2 D2 -IN 6 7 NC OUT S/H CTL 14 GND 13 NC 12 GND V2 NC 10 NC 14 2 13 3 12 4 11 5 10 6 9 7 8 GND HOLD CAP 11 +V 1 R +15V 9 8 D1 C1 NOTES: R1 = 100kΩ ±5% (per socket) C1 = C2 = 0.1µF (one per row) or 0.01µF (one per socket) D1 = D2 = 1N4002 or equivalent (per board) V1 NOTES: V1 = +15V V2 = -15V R = 100kΩ Spec Number 9 518855 HS-2420RH HOLD STEP VOLTAGE (V) S/H CONTROL +10 V+ CH +5 -10 -5 +5 +10 DC INPUT VOLTAGE (V) -5 CH = 0.1µF + -10 CH = 10,000pF CH = 1000pF -15 + - HS-2420RH -20 -25 -IN -30 CH = 100pF +IN OUT V- 100kΩ OFFSET TRIM (±25mV RANGE) -35 FIGURE 14. HOLD STEP vs INPUT VOLTAGE FIGURE 15. BASIC SAMPLE-AND-HOLD (TOP VIEW) 0.002RF INPUT RF +IN HS-2420RH -IN S/H CONTROL OUTPUT OUT INPUT RI -IN HS-2420RH OUTPUT RF OUT +IN S/H CONTROL S/H CONTROL INPUT RI 0.002RI S/H CONTROL INPUT -RF GAIN ~ RI GAIN ~ I + FIGURE 16. INVERTING CONFIGURATION -RF RI FIGURE 17. NONINVERTING CONFIGURATION Offset and Gain Adjustment Offset Adjustment The offset voltage of the HS-2420RH may be adjusted using a 100kΩ trim pot, as shown in Figure 15. The recommended adjustment procedure is: The recommended procedure for adjusting gain error is: 1. Perform offset adjustment. 2. Apply the nominal input voltage that should produce a +10V output. 1. Apply zero volts to the sample-and-hold input, and a square wave to the S/H control. 3. Adjust the trim pot for +10V output in the hold mode. 2. Adjust the trim pot for zero volts output in the hold mode. 4. Apply the nominal input voltage that should produce a -10V output. Gain Adjustment The linear variation in pedestal voltage with sample-and-hold input voltage causes a -0.06% gain error (CH = 1000pF). In some applications (D/A deglitcher, A/D converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sample-and-hold. The two circuits shown below demonstrate how to adjust gain error at the sample-and-hold. 5. Measure the output hold voltage (V-10 NOMINAL). Adjust the trim pot for an output hold voltage of ( V-10 NOMINAL ) + ( – 10V ) ---------------------------------------------------------------------------2 Spec Number 10 518855 11 GND S/H CTL Q3 RP Q12 Q10 Q8 R5 Q7 Q11 Q16 Q103 R11 Q14 Q13 Q9 R3 Q106 Q105 Q5 Q17 Q18 Q19 Q15 Q2 Q22 Q21 Q20 Q25 Q24 Q6 Q4 Q23 Q26 IN+ Q27 R13 Q42 Q39 Q31 Q28 Q29 Q35 Q33 R1 Q43 Q40 Q38 Q34 R2 OFFSET ADJUST Q32 Q30 IN- Q44 Q41 Q56 Q57 Q55 Q100 Q45 Q101 Q50 Q48 C4 Q53 Q51 Q63 Q60 R7 C2 Q46 Q54 Q52 Q62 Q102 Q59 Q78 Q68 Q67 Q58 Q64 Q71 Q70 Q69 C3 15pF Q73 Q66 Q65 Q81 Q80 Q79 Q76 R8 Q75 Q72 C5 V- R14 Q77 R10 OUT R9 CH Q74 V+ HS-2420RH Schematic Spec Number 518855 HS-2420RH Intersil Space Level Product Flow -Q Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) (Note 1) 100% Initial Electrical Test (T0) 100% Static Burn-In, Condition A, 240 Hours, +125oC or Equivalent, Method 1015 GAMMA Radiation Verification (Each Wafer) Method 1019, 4 Samples/Wafer, 0 Rejects 100% Interim Electrical Test 1 (T1) 100% Die Attach 100% Delta Calculation (T0-T1) 100% Nondestructive Bond Pull, Method 2023 100% PDA, Method 5004 (Note 2) Sample - Wire Bond Pull Monitor, Method 2011 100% Final Electrical Test Sample - Die Shear Monitor, Method 2019 or 2027 100% Fine/Gross Leak, Method 1014 100% Internal Visual Inspection, Method 2010, Condition A 100% Radiographic (X-Ray), Method 2012 (Note 3) CSI and/or GSI Pre-Cap (Note 7) 100% External Visual, Method 2009 100% Temperature Cycle, Method 1010, Condition C, 10 Cycles Sample - Group A, Method 5005 (Note 4) 100% Constant Acceleration, Method 2001, Condition per Method 5004 Sample - Group C, Method 5005 (Notes 5, 6) Sample - Group B, Method 5005 (Note 5) 100% Data Package Generation (Note 8) 100% PIND, Method 2020, Condition A CSI and/or GSI Final (Note 7) 100% External Visual 100% Serialization NOTES: 1. Modified SEM Inspection, not compliant to MIL-STD-883, Method 2018. This device does not meet the Class S minimum metal step coverage of 50%. The metal does meet the current density requirement of <2E5A/cm2. Data provided upon request. 2. Failures from subgroup 1 and deltas are used for calculating PDA. The maximum allowable PDA = 5%. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. 5. Group B and D inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for Group B test, Group B samples, Group D test and Group D samples. 6. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group D generic data. Generic data is not guaranteed to be available and is therefore not available in all cases. 7. CSI and/or GSI inspections are optional and will not be performed unless required by the P.O. When required, the P.O. should include separate line items for CSI Pre-Cap inspection, CSI Final Inspection, GSI Pre-Cap inspection, and/or GSI Final Inspection. 8. Data Package Contents: Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity). Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage. GAMMA Radiation Report. Contains Cover page, disposition, RAD Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil. X-Ray report and film. Includes penetrometer measurements. Screening, Electrical, and Group A attributes (Screening attributes begin after package seal). Lot Serial Number Sheet (Good units serial number and lot number). Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test. Group B and D attributes and/or Generic data is included when required by the P.O. The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 12 518855 HS-2420RH Metallization Topology DIE DIMENSIONS: 97 mils x 61 mils x 19 mils WORST CASE CURRENT DENSITY: 2.0 x 105A/cm2 METALLIZATION: Type: Al Thickness: 16kÅ ±2kÅ TRANSISTOR COUNT: 78 PROCESS: Bipolar-DI GLASSIVATION: Type: Silox Thickness: 14kÅ ±2kÅ Metallization Mask Layout HS-2420RH S/H CONTROL (14) -IN (1) +IN (2) (13) GND OFF ADJ (3) OFF ADJ (4) (11) HOLD CAP V- (5) (7) OUT (9) V+ All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Spec Number 13 518855