HA-5340 Data Sheet September 1998 File Number 2859.3 700ns, Low Distortion, Precision Sample and Hold Amplifier Features The HA-5340 combines the advantages of two sample/ hold architectures to create a new generation of monolithic sample/hold. High amplitude, high frequency signals can be sampled with very low distortion being introduced. The combination of exceptionally fast acquisition time and specified/characterized hold mode distortion is an industry first. Additionally, the AC performance is only minimally affected by additional hold capacitance. • Fast Hold Mode Settling Time (0.01%). . . . . . . . . . . . 200n To achieve this level of performance, the benefits of an integrating output stage have been combined with the advantages of a buffered hold capacitor. To the user this translates to a front-end stage that has high bandwidth due to charging only a small capacitive load and an output stage with constant pedestal error which can be nulled out using the offset adjust pins. Since the performance penalty for additional hold capacitance is low, the designer can further minimize pedestal error and droop rate without sacrificing speed. Low distortion, fast acquisition, and low droop rate are the result, making the HA-5340 the obvious choice for high speed, high accuracy sampling systems. For a Military temperature range version request the HA-5340/883 data sheet. Ordering Information PART NUMBER TEMP. RANGE (oC) PKG. NO. PACKAGE • Fast Acquisition Time (0.01%) . . . . . . . . . . . . . . . . . 700ns • Low Distortion (Hold Mode) . . . . . . . . . . . . . . . . . . -72dBc (VIN = 200kHz, fS = 450kHz, 5VP-P) • Bandwidth Minimally Affected By External CH • Fully Differential Analog Inputs • Built-In 135pF Hold Capacitor • Pin Compatible with HA-5320 Applications • High Bandwidth Precision Data Acquisition Systems • Inertial Navigation and Guidance Systems • Ultrasonics • SONAR • RADAR Pinouts HA-5340 (PDIP) TOP VIEW -IN 1 14 S/H CONTROL +IN 2 13 SUPPLY GND OFFSET ADJ. 3 12 NC 11 EXTERNAL HOLD CAP. HA3-5340-5 0 to 75 14 Ld PDIP E14.3 OFFSET ADJ. 4 HA9P5340-5 0 to 75 16 Ld SOIC M16.3 V- 5 10 NC SIG. GND 6 9 V+ OUTPUT 7 8 NC Functional Diagram CHOLD EXTERNAL (OPTIONAL) ADJUST OFFSET 3 11 4 HA-5340 (SOIC) TOP VIEW 7 CHOLD 120pF -IN +IN S/H CONTROL 1 CCOMP 15pF 2 7 OUT -IN 1 16 S/H CONTROL +IN 2 15 SUPPLY GND OFFSET ADJ. 3 14 NC OFFSET ADJ. 4 13 NC NC 5 14 V- 6 9 V+ 5 V- 13 6 SUPPLY SIGNAL GND GND 1 EXTERNAL 12 HOLD CAP. 11 NC SIG. GND 7 10 NC OUTPUT 8 9 V+ CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 HA-5340 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals. . . . . . . . . . . . . . . . . . . . 36V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24V Digital Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8V, -6V Output Current, Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 90 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 95 N/A Maximum Junction Temperature (Plastic Package, Note 1) . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range HA-5340-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Supply Voltage Range (Typical) . . . . . . . . . . . . . . . . . ±12V to ±18V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Maximum power dissipation must be designed to maintain the junction temperature below 150oC for the plastic packages. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications VSUPPLY = ±15.0V; CH = Internal = 135pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold). Non-Inverting Unity Gain Configuration (Output tied to -Input), RL = 2kΩ, CL = 60pF, Unless Otherwise Specified HA-5340-5 TEMP. (oC) MIN TYP MAX UNITS Input Voltage Range Full -10 - +10 V Input Resistance (Note 3) 25 - 1 - MΩ Input Capacitance 25 - - 3 pF Input Offset Voltage 25 - - 1.5 mV Full - - 3.0 mV Offset Voltage Temperature Coefficient Full - - 30 µV/oC PARAMETER TEST CONDITIONS INPUT CHARACTERISTICS Bias Current Offset Current Common Mode Range ±10V, Note 4 CMRR 25 - ±70 - nA Full - - ±350 nA 25 - ±50 - nA Full - - ±350 nA Full -10 - +10 V 25 - 83 - dB Full 72 - - dB TRANSFER CHARACTERISTICS Gain DC 25 110 140 - dB Gain Bandwidth Product CH External = 0pF Full - 10 - MHz CH External = 100pF Full - 9.6 - MHz CH External = 1000pF Full - 6.7 - MHz Rise Time 200mV Step 25 - 20 30 ns Overshoot 200mV Step 25 - 35 50 % Slew Rate 10V Step 25 40 60 - V/µs VIH Full 2.0 - - V VIL Full - - 0.8 V VIL = 0V Full - 7 40 µA VIH = 5V Full - 4 40 µA TRANSIENT RESPONSE DIGITAL INPUT CHARACTERISTICS Input Voltage Input Current 2 HA-5340 Electrical Specifications VSUPPLY = ±15.0V; CH = Internal = 135pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold). Non-Inverting Unity Gain Configuration (Output tied to -Input), RL = 2kΩ, CL = 60pF, Unless Otherwise Specified (Continued) HA-5340-5 TEMP. (oC) MIN TYP MAX Output Voltage Full -10 - +10 V Output Current Full -10 - +10 mA Full 0.6 0.9 - MHz 25 - 0.05 0.1 Ω Full - 0.07 0.15 Ω PARAMETER TEST CONDITIONS UNITS OUTPUT CHARACTERISTICS Full Power Bandwidth (Note 5) Output Resistance Hold Mode Sample Mode 25 - 325 400 µVRMS Hold Mode 25 - 325 400 µVRMS Signal to Noise Ratio (RMS Signal to RMS Noise) VIN = 200kHz, 20VP-P Full - 115 - dB Total Harmonic Distortion VIN = 200kHz, 5VP-P Full -90 -100 - dBc VIN = 200kHz, 10VP-P Full -76 -82 - dBc VIN = 200kHz, 20VP-P Full -70 -74 - dBc VIN = 500kHz, 5VP-P Full -66 -75 - dBc VIN = 10VP-P, f1 = 20kHz, f2 = 21kHz Full -78 -83 - dBc VIN = 200kHz, 5VP-P 25 - 76 - dB VIN = 200kHz, 10VP-P 25 - 76 - dB VIN = 200kHz, 5VP-P 25 - -72 - dBc VIN = 200kHz, 10VP-P 25 - -66 - dBc VIN = 200kHz, 20VP-P 25 - -56 - dBc VIN = 100kHz, 5VP-P 25 - -84 - dBc VIN = 100kHz, 10VP-P 25 - -71 - dBc VIN = 100kHz, 20VP-P 25 - -61 - dBc VIN = 20kHz, 5VP-P 25 - -95 - dBc VIN = 50kHz, 5VP-P 25 - -91 - dBc VIN = 100kHz, 5VP-P 25 - -82 - dBc VIN = 10VP-P (f1 = 20kHz, f2 = 21kHz) 25 - -79 - dBc Total Output Noise DC to 10MHz DISTORTION CHARACTERISTICS SAMPLE MODE Intermodulation Distortion HOLD MODE (50% Duty Cycle S/H) Signal to Noise Ratio (RMS Signal to RMS Noise) fS = 450kHz Total Harmonic Distortion fS = 450kHz fS = 450kHz fS = 2fIN(Nyquist) Intermodulation Distortion fS = 450kHz SAMPLE AND HOLD CHARACTERISTICS Acquisition Time 10V Step to 0.01% 10V Step to 0.1% Droop Rate CH = Internal 25 - 700 - ns Full - - 900 ns 25 - 430 600 ns 25 - 0.1 - µV/µs Full - - 95 µV/µs Hold Step Error VIL = 0V, VIH = 4.0V, tR = 5ns 25 - 15 - mV Hold Mode Settling Time To ±1mV Full - 200 300 ns Hold Mode Feedthrough 20VP-P, 200kHz, Sine Full - -76 - dB EADT (Effective Aperture Delay Time) 25 - -15 - ns Aperture Uncertainty 25 - 0.2 - ns 3 HA-5340 Electrical Specifications VSUPPLY = ±15.0V; CH = Internal = 135pF; Digital Input: VIL = +0.8V (Sample), VIH = +2.0V (Hold). Non-Inverting Unity Gain Configuration (Output tied to -Input), RL = 2kΩ, CL = 60pF, Unless Otherwise Specified (Continued) HA-5340-5 TEMP. (oC) MIN TYP MAX UNITS Positive Supply Current Full - 19 25 mA Negative Supply Current Full - 19 25 mA Full 75 82 - dB PARAMETER TEST CONDITIONS POWER SUPPLY CHARACTERISTICS PSRR 10% Delta NOTES: 3. Derived from Computer Simulation only, not tested. 4. +CMRR is measured from 0V to +10V, -CMRR is measured from 0V to -10V. 5. Based on the calculation FPBW = Slew Rate/2πVPEAK (VPEAK = 10V). Test Circuits and Waveforms 1 2 S/H CONTROL INPUT 14 -INPUT OUTPUT 7 VO +INPUT 11 S/H CONTROL NC HA-5340 (CH = 135pF = INTERNAL) FIGURE 1. HOLD STEP ERROR AND DROOP RATE HOLD (+4.0V) SAMPLE (0V) S/H CONTROL HOLD (+4.0V) SAMPLE (0V) S/H CONTROL ∆VO VO ∆t VO NOTES: 7. Observe the voltage “droop”, ∆VO/∆t. 8. Measure the slope of the output during hold, ∆VO/∆t. VP NOTE: 9. Droop can be positive or negative - usually to one rail or the other not to GND. 6. Observe the “hold step” voltage VP. FIGURE 2. HOLD STEP ERROR FIGURE 3. DROOP RATE TEST V+ V IN ANALOG MUX OR SWITCH 20VP-P 200kHz SINE WAVE AIN S/H CONTROL INPUT VHA-5340 NOTE: 9 1 -IN 2 +IN 14 S/H CONTROL 5 10. Feedthrough in VOUT OUT SUPPLY GND 13 TO SUPPLY COMMON 7 REF COM 6 TO SIGNAL GND FIGURE 4. HOLD MODE FEEDTHROUGH ATTENUATION 4 V OUT dB = 20 log --------------- where: V IN VOUT = VP-P, Hold Mode, VIN = VP-P HA-5340 Application Information capacitor types offer good performance over the specified operating temperature range. The HA-5340 has the uncommitted differential inputs of an op amp, allowing the Sample and Hold function to be combined with many conventional op amp circuits. See the Intersil Application Note AN517 for a collection of circuit ideas. The hold capacitor terminal (pin 11) remains at virtual ground potential. Any PC connection to this terminal should be kept short and “guarded” by the ground plane, since nearby signal lines or power supply voltages will introduce errors due to drift current. Layout A printed circuit board with ground plane is recommended for best performance. Bypass capacitors (0.01µF to 0.1µF, ceramic) should be provided from each power supply terminal to the Supply Ground terminal on pin 13. ®Teflon is a registered Trademark of Dupont Corporation. Typical Application Figure 5 shows the HA-5340 connected as a unity gain noninverting amplifier - its most widely used configuration. As an input device for a fast successive - approximation A/D converter, it offers very high throughput rate for a monolithic IC sample/hold amplifier. Also, the HA-5340’s hold step error is adjustable to zero using the Offset Adjust potentiometer, to deliver a 12-bit accurate output from the converter. The ideal ground connections are pin 6 (SIG. GND) directly to the system Signal Ground, and pin 13 (Supply Ground) directly to the system Supply Common. Hold Capacitor The HA-5340 includes a 135pF MOS hold capacitor, sufficient for most high speed applications (the Electrical Specifications section is based on this internal capacitor). Additional capacitance may be added between pins 7 and 11. This external hold capacitance will reduce droop rate at the expense of acquisition time, and provide other trade-offs as shown in the Performance Curves. The HA-5340 output circuit does not include short circuit protection, and consequently its output impedance remains low at high frequencies. Thus, the step changes in load current which occur during an A/D conversion are absorbed at the S/H output with minimum voltage error. A momentary short circuit to ground is permissible, but the output is not designed to tolerate a short of indefinite duration. The hold capacitor CH should have high insulation resistance and low dielectric absorption, to minimize droop errors. Teflon®, polystyrene and polypropylene dielectric -15V +15V OFFSET ADJUST ≈ ±15mV CH 50kΩ 3 4 5 9 11 HI - 774 120pF 1 2 VIN 7 13 15pF INPUT 14 S/H CONTROL H S 13 6 5 9 SYSTEM POWER GROUND DIGITAL OUTPUT CONVERT HA - 5340 SYSTEM SIGNAL GROUND R/C ANALOG COMMON NOTE: Pin Numbers Refer to DIP Package Only. FIGURE 5. TYPICAL HA-5340 CONNECTIONS; NONINVERTING UNITY GAIN MODE 5 HA-5340 Typical Performance Curves TA = 25oC, VS = ±15V, Unless Otherwise Specified 4V S/H CONTROL S/H CONTROL 0V 4V 0V 10V 0pF 470pF 0V 1000pF VOUT FIGURE 7. TACQ vs ADDITIONAL CH 2300 ACQUISITION TIME TO ±1mV (ns) DROOP RATE (µV/µs) FIGURE 6. TACQ POS 0 TO +10 STEP 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 125oC 100oC 75oC 2100 1900 1700 1500 1300 1100 900 700 1 10 100 0 1000 400 800 1200 1600 2000 2400 EXTERNAL HOLD CAPACITANCE (pF) EXTERNAL HOLD CAPACITANCE (pF) FIGURE 8. DROOP RATE vs HOLD CAPACITANCE FIGURE 9. ACQUISITION TIME (0.01%) vs HOLD CAPACITANCE 20 13 11 VIH = 4V CH = 470pF HOLD STEP ERROR (mV) CH = INTERNAL TEMPERATURE = 25oC 12 HOLD STEP ERROR (mV) 2200pF VOUT 10 9 8 7 VIH = 3V 6 5 4 3 2 10 0 VIH = 4V 1 0 5 10 15 TRISE (ns) FIGURE 10. HOLD STEP ERROR vs TRISE 6 20 -10 -55 -35 -15 0 25 50 75 100 TEMPERATURE (oC) FIGURE 11. HOLD STEP ERROR vs TEMPERATURE 125 HA-5340 Typical Performance Curves TA = 25oC, VS = ±15V, Unless Otherwise Specified 20 12 10 8 6 4 (Continued) VIH = 4V, CH = INTERNAL tR = 5ns, 10ns, 20ns TRISE = 5ns TA = 25oC HOLD STEP ERROR (mV) HOLD STEP ERROR (mV) 14 10 5ns 10ns 20ns 0 VIH = 4V 2 0 200 400 600 800 -10 -55 1000 -35 -15 0 50 75 100 125 FIGURE 13. HOLD STEP ERROR vs TEMPERATURE 180 0 0 PHASE -90 AV = +100, ±15V AND ±12V SUPPLIES (NOTE) 180 40 MAGNITUDE CH = 1000pF 20 PHASE ANGLE (DEGREES) 90 20 MAGNITUDE (dB) MAGNITUDE PHASE ANGLE (DEGREES) MAGNITUDE (dB) FIGURE 12. HOLD STEP ERROR vs HOLD CAPACITANCE 40 25 TEMPERATURE (oC) EXTERNAL HOLD CAPACITANCE (pF) 90 CH = 470pF CH = 0pF 0 0 PHASE -180 -90 CH = 1000pF CH = 470pF 1K 10K 100K 1M 10M CH = 0pF NOTE: ±15V and ±12V supplies trace the same line within the width of the line, therefore only one line is shown. 1K FIGURE 14. CLOSED LOOP PHASE/GAIN -20 1M 10M FIGURE 15. CLOSED LOOP PHASE/GAIN HA-5320 SAMPLE AND HOLD MODES HA-5320 SAMPLE AND HOLD MODES -40 THD (dBc) -40 THD (dBc) 100K -20 fSAMPLE ≅ 450kHz VOUT = 5VP-P -60 10K -180 AV = +100 HA-5340 HOLD MODE -60 HA-5340 HOLD MODE -80 -80 HA-5340 SAMPLE MODE HA-5340 SAMPLE MODE -100 -100 0 100K 200K 300K 400K FREQUENCY (Hz) FIGURE 16. THD vs FREQUENCY 7 500K 5 VOUT P-P 10 at 200kHz, fSAMPLE ≅ 450kHz FIGURE 17. THD vs VOUT 20 HA-5340 Die Characteristics DIE DIMENSIONS: PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos) Silox Thickness: 12kÅ ± 2.0kÅ Nitride Thickness: 3.5kÅ ± 1.5kÅ 84mils x 139mils x 19mils METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ± 2kÅ SUBSTRATE POTENTIAL (Powered Up): VTRANSISTOR COUNT: 196 Metallization Mask Layout (11) EXTERNAL HOLD CAP HA-5340 SUPPLY (13) GND S/H (14) CONTROL (9) +VSUPPLY -IN (1) (7) OUTPUT (7) OUTPUT +IN (2) -VSUPPLY (5) OFFSET ADJ (4) OFFSET ADJ (3) (6) SIG GND All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 8