INTERSIL HS

HS-2420RH
®
Data Sheet
February 2003
FN3554.3
Radiation Hardened Fast Sample and Hold
Features
The HS-2420RH is a radiation hardened monolithic circuit
consisting of a high performance operational amplifier with
its output in series with an ultra-low leakage analog switch
and MOSFET input unity gain amplifier.
• Electrically Screened to SMD # 5962-95669
With an external hold capacitor connected to the switch output,
a versatile, high performance sample-and-hold or track-andhold circuit is formed. When the switch is closed, the device
behaves as an operation amplifier, and any of the standard op
amp feedback networks may be connected around the device
to control gain, frequency response, etc. When the switch is
opened the output will remain at its last level.
Performance as a sample-and-hold compares very favorably
with other monolithic, hybrid, modular, and discrete circuits.
Accuracy to better than 0.01% is achievable over the
temperature range. Fast acquisition is coupled with superior
droop characteristics, even at high temperatures. High slew
rate, wide bandwidth, and low acquisition time produce
excellent dynamic characteristics. The ability to operate at
gains greater than 1 frequently eliminates the need for
external scaling amplifiers.
The device may also be used as a versatile operational
amplifier with a gated output for applications such as analog
switches, peak holding circuits, etc.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-95669. A “hot-link” is provided
on our website for downloading.
• QML Qualified per MIL-PRF-38535 Requirements
• Maximum Acquisition Time
- 10V Step to 0.1% . . . . . . . . . . . . . . . . . . . . . . . . . . 4µs
- 10V Step to 0.01% . . . . . . . . . . . . . . . . . . . . . . . . . 6µs
• Maximum Drift Current . . . . . . . . . . . . . . . . . . . . . . . 10nA
(Maximum Over Temperature)
• TTL Compatible Control Input
• Power Supply Rejection . . . . . . . . . . . . . . . . . . . . . ≥ 80dB
• Total Dose . . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
• No Latch-Up
Applications
• Data Acquisition Systems
• D to A Deglitcher
• Auto Zero Systems
• Peak Detector
• Gated Op Amp
Ordering Information
INTERNAL
MKT. NUMBER
ORDERING NUMBER
5962R9566901VCC
HS1B-2420RH-Q
TEMP. RANGE
(oC)
-55 to 125
Functional Diagram
OFFSET
ADJUST
Pinout
14 LEAD METAL-SEALED SIDE-BRAZED CERAMIC DIP
MIL-STD-1835, CDIP2-T14
TOP VIEW
3
- INPUT
4
1
-
+
+ INPUT
V+
5
-
+
7
OUTPUT
2
IN- 1
14 SAMPLE/HOLD
CONTROL
IN+ 2
13 GND
OFFSET ADJUST 3
12 NC
OFFSET ADJUST 4
11 HOLD CAPACITOR
V- 5
10 NC
NC 6
9 V+
OUTPUT 7
8 NC
1
14
HS-2420RH
SAMPLE/
HOLD
CONTROL
13
5
11
GND VHOLD
CAPACITOR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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HS-2420RH
Test Circuits
ALL RESISTORS = ±1%
ALL CAPACITORS = ±10%
VDC
100kΩ
10kΩ
+VCC -VCC
2
S2
2
1
1
S7
S/H
A
1
S4
DUT
S7
1
50Ω
1
50Ω
2
1
S1
2
1 OPEN
GND
+
2
100kΩ
-
NULL
AMP
+
3
X1
X-1
S5
2
BUFFER
CH =
1000pF
S6
S3
2
1 50pF
2kΩ
3
+VCC
1MΩ
VAC
ILOAD
-
50Ω
+
AOUT
4
3
2
EOUT
S8
1
FIGURE 1. TEST FIXTURE SCHEMATIC (SWITCH POSITIONS S1 - S8 DETERMINE CONFIGURATION)
+5V
SINEWAVE
INPUT
IN2
IN1
IN3
IN4
IN5
IN6
IN7
IN8
A2
A1
EN
+15V
-15V
-
-
VOUT
DUT +
VOUT
+
OUT
-15V
+15V
DUT
2kΩ
VIN
2kΩ
50pF
CH =
1000pF
50Ω
S/H
50pF
CH =
1000pF
A0
SAMPLE/HOLD
CONTROL INPUT
NOTE: Compute Hold Mode Feedthrough Attenuation from the
Formula:
 V OUT HOLD
FeedthroughAttenuation = 20 log  --------------------------------
 V IN HOLD 
NOTE: GBWP is the Frequency of VINPUT at which:
 V OUT 
20 log  --------------------- = – 3dB
 V INPUT
Where VOUT HOLD = Peak-Peak Value of Output Sinewave during
the Hold Mode.
FIGURE 2. HOLD MODE FEEDTHROUGH ATTENUATION
2
FIGURE 3. GAIN BANDWIDTH PRODUCT
HS-2420RH
Test Circuits
(Continued)
SEND SAMPLE
COMMAND
SET t2 TO 7µs
INITIALLY
FINE tACQ
MEASUREMENT LOOP
COURSE tACQ
MEASUREMENT LOOP
INCREMENT t2
BY 50ns
(50ns LONGER DELAY)
DIGITIZE V1
AT t1 (≈10µs)
DIGITIZE V2
AT t2
DECREMENT
t2 BY 50ns
DIGITIZE V1
AT t1 (≈10µs)
CALCULATE V1 - V2
IS ∆V ≥ 0.01%?
YES
DIGITIZE V2
AT t2
NO
DECREMENT
t2 BY 50ns
YES
RECORD
tACQ
NO
CALCULATE V1 - V2
IS ∆V ≥ 0.01%?
NOTE: See Test Diagram, Timing Diagram
FIGURE 4. ACQUISITION TIME (tACQ TO 0.01% IS SHOWN, tACQ TO 0.1% IS DONE IN THE SAME MANNER)
t1
V1
HS-2420RH
V1 DIGITIZER
-
-
COMPUTER
CONTROLLER
+
+
V2 DIGITIZER
2kΩ
1000pF
0V
t1
OR
≈10µs
0V
-10V
V2
50pF
+10V
t2 DELAY
CONTROL
DELAY
S/H
CONTROL
t2
VARIABLE
DELAY
FIGURE 5.
3
HS-2420RH
Timing Waveforms
10V
VIN
(POS tACQ CASE)
0V
S/H CONTROL
0V
2V
0.01% OR 0.1%
ENVELOPE
10V
DUT OUTPUT
(POS tACQ CASE)
0V
t1 ≈ 10µs
(t1 DIGITIZER COMMAND)
t1
t2
t2
(t2 DIGITIZER COMMAND)
FIGURE 6. TIMING DIAGRAM FOR ACQUISITION TIME, (POSITIVE tACQ CASE)
+V
0V
VFINAL
VPEAK
90%
10%
INPUT
10%
0V
90%
-V
+OS, tR
-OS, tF
tR
FIGURE 7A.
VFINAL
VPEAK
tF
FIGURE 7B.
FIGURE 7. OVERSHOOT, RISE AND FALL TIME WAVEFORMS
+V
+V
+V
+V
75%
25%
25%
75%
INPUT
-V
-V
+SL
-V
∆t
FIGURE 8B.
FIGURE 8A.
FIGURE 8. SLEW RATE WAVEFORMS
4
-V
∆t
-SL
HS-2420RH
Typical Performance Curves
VSUPPLY = ±15VDC , TA = 25oC, CH = 1000pF, Unless Otherwise Specified
1000
1000
LOWER 3dB FREQUENCY = 10Hz
DRIFT DURING HOLD AT
25oC mV/s
OUTPUT NOISE
“HOLD” MODE
100
10
1.0
100
mVRMS
HOLD STEP
OFFSET ERROR
(mV)
UNITY GAIN PHASE
MARGIN (DEG)
10
UNITY GAIN
BANDWIDTH
(MHz)
MIN SAMPLE TIME
SLEW RATE/
FOR 0.1% ACCURACY
CHARGE RATE
10V SWINGS (ms)
V/(ms)
0.1
0.01
10pF
100pF
1000pF
0.01mF
EQUIV. INPUT NOISE
“SAMPLE” MODE - 100K
SOURCE RESISTANCE
EQUIV. INPUT NOISE
“SAMPLE” MODE - 0K
SOURCE RESISTANCE
0.1mF
1
10
1.0mF
100
1K
FIGURE 9. TYPICAL SAMPLE AND HOLD PERFORMANCE
vs HOLDING CAPACITOR
100K
1M
FIGURE 10. BROADBAND NOISE CHARACTERISTICS
1000
OPEN LOOP VOLTAGE GAIN (dB)
100
ID (pA)
100
10
1
-50
-25
0
25
50
TEMPERATURE (oC)
75
100
125
-50
-60
-70
-80
-90
10K
100K
1M
10M
±10V SINUSOIDAL INPUT FREQUENCY (Hz)
FIGURE 13. HOLD MODE FEEDTHROUGH ATTENUATION
CH = 1000pF
5
40
CH = 1.0µF
20
CH = 0.1µF
0
-20
100
1K
10K
100K
1M
10M
100M
FIGURE 12. OPEN LOOP FREQUENCY RESPONSE
OPEN LOOP PHASE ANGLE (DEGREES)
-40
1K
CH = 1000pF
60
FREQUENCY (Hz)
-30
100
CH = 0.01µF
CH = 100pF
80
10
FIGURE 11. DRIFT CURRENT vs TEMPERATURE
ATTENUATION (dB)
10K
BANDWIDTH
CH VALUE
0
CH = 0.01µF
CH =1000pF
20
CH = 1.0µF
40
CH = 0.1µF
60
80
100
CH ≤ 100pF
120
140
160
180
200
220
240
10
100
1K
10K
100K
1M
10M
FREQUENCY (Hz)
FIGURE 14. OPEN LOOP PHASE RESPONSE
100M
HS-2420RH
Burn-In Circuit
Irradiation Circuit
HS-2420RH CERDIP
1
R1
2
+IN
3
4
OFF
ADJ
OFF
ADJ
5
-V
-15V
C2
D2
6
7
S/H
CTL 14
-IN
GND 13
NC 12
GND
V2
NC 10
+V
OUT
NC
14
2
13
3
12
4
11
5
10
6
9
7
8
GND
HOLD
CAP 11
NC
1
R
+15V
9
D1
8
C1
NOTES:
NOTES:
R1 = 100kΩ ±5% (per socket)
C1 = C2 = 0.1µF (one per row) or 0.01µF (one per socket)
D1 = D2 = 1N4002 or equivalent (per board)
V1 = +15V
V2 = -15V
R = 100kΩ
HOLD STEP VOLTAGE (V)
V1
S/H
CONTROL
+10
V+
CH
+5
-10
-5
+5
+10
DC INPUT VOLTAGE (V)
-5
CH = 0.1µF
-
-10
CH = 1000pF
-15
+
-
+
CH = 10,000pF
HS-2420RH
-20
-25
-IN
-30
CH = 100pF
-35
FIGURE 15. HOLD STEP vs INPUT VOLTAGE
+IN
OUT
V-
100kΩ
OFFSET TRIM
(±25mV RANGE)
FIGURE 16. BASIC SAMPLE-AND-HOLD (TOP VIEW)
0.002RF
INPUT
RF
+IN
HS-2420RH
-IN
S/H
CONTROL
OUTPUT
OUT
INPUT
RI
-IN
HS-2420RH
OUTPUT
RF
OUT
+IN
S/H
CONTROL
RI
S/H CONTROL
INPUT
0.002RI
-RF
S/H CONTROL
INPUT
GAIN ~
FIGURE 17. INVERTING CONFIGURATION
6
-RF
GAIN ~ I +
RI
FIGURE 18. NONINVERTING CONFIGURATION
RI
HS-2420RH
Offset and Gain Adjustment
Offset Adjustment
The offset voltage of the HS-2420RH may be adjusted using
a 100kΩ trim pot, as shown in Figure 15. The recommended
adjustment procedure is:
1. Apply 0V to the sample-and-hold input, and a square
wave to the S/H control.
2. Adjust the trim pot for 0V output in the hold mode.
Gain Adjustment
The linear variation in pedestal voltage with sample-and-hold
input voltage causes a -0.06% gain error (CH = 1000pF). In
some applications (D/A deglitcher, A/D converter) the gain
error can be adjusted elsewhere in the system, while in other
applications it must be adjusted at the sample-and-hold. The
two circuits shown below demonstrate how to adjust gain
error at the sample-and-hold.
The recommended procedure for adjusting gain error is:
1. Perform offset adjustment.
2. Apply the nominal input voltage that should produce a
+10V output.
3. Adjust the trim pot for +10V output in the hold mode.
4. Apply the nominal input voltage that should produce a -10V
output.
5. Measure the output hold voltage (V-10 NOMINAL). Adjust
the trim pot for an output hold voltage of:
( V-10 NOMINAL ) + ( – 10V )
-----------------------------------------------------------------------2
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HS-2420RH
Die Characteristics
WORST CASE CURRENT DENSITY:
2.0 x 105A/cm2
DIE DIMENSIONS:
TRANSISTOR COUNT:
97 mils x 61 mils x 19 mils
78
METALLIZATION:
PROCESS:
Type: Al
Thickness: 16kÅ ± 2kÅ
Bipolar-Di
GLASSIVATION:
Type: Silox
Thickness: 14kÅ ± 2kÅ
Metallization Mask Layout
HS-2420RH
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