74LVC1G38-Q100
2-input NAND gate; open drain
Rev. 1 — 27 November 2013
Product data sheet
1. General description
The 74LVC1G38-Q100 provides a 2-input NAND function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device as translator in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V).
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Open drain outputs
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Multiple package options
74LVC1G38-Q100
NXP Semiconductors
2-input NAND gate; open drain
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
74LVC1G38GW-Q100
40 C to +125 C
TSSOP5
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
74LVC1G38GV-Q100
40 C to +125 C
SC-74A
plastic surface-mounted package; 5 leads
SOT753
4. Marking
Table 2.
Marking
Type number
Marking code[1]
74LVC1G38GW-Q100
YB
74LVC1G38GV-Q100
YB
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
<
1
A
1
Y 4
2
B
4
2
Logic symbol
%
001aab716
001aab717
Fig 1.
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Fig 2.
*1'
DDE
IEC logic symbol
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
/9&*4
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9&&
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DDD
Fig 4.
Pin configuration for SOT353-1 and SOT753
74LVC1G38_Q100
Product data sheet
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Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
2 of 13
74LVC1G38-Q100
NXP Semiconductors
2-input NAND gate; open drain
6.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
A
1
data input
B
2
data input
GND
3
ground (0 V)
Y
4
data output
VCC
5
supply voltage
7. Functional description
Table 4.
Function table[1]
Input
Output
A
B
L
L
Z
L
H
Z
H
L
Z
H
H
L
[1]
Y
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF state.
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
Conditions
VI < 0 V
[1]
Min
Max
Unit
0.5
+6.5
V
50
-
mA
0.5
+6.5
V
VI
input voltage
IOK
output clamping current
VO > VCC or VO < 0 V
-
50
mA
VO
output voltage
Active mode
[1][2]
0.5
+6.5
V
Power-down mode
[1][2]
0.5
+6.5
V
-
50
mA
IO
output current
ICC
supply current
-
100
mA
IGND
ground current
100
-
mA
Tstg
storage temperature
65
+150
C
-
300
mW
total power dissipation
Ptot
VO = 0 V to VCC
Tamb = 40 C to +125 C
[3]
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3]
For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
74LVC1G38_Q100
Product data sheet
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74LVC1G38-Q100
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2-input NAND gate; open drain
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Symbol
Parameter
VCC
Conditions
Min
Typ
Max
Unit
supply voltage
1.65
-
5.5
V
VI
input voltage
0
-
5.5
V
VO
output voltage
Active mode
0
-
5.5
V
Disable mode; VCC = 1.65 V to 5.5 V
0
-
5.5
V
Power-down mode; VCC = 0 V
0
-
5.5
V
Tamb
ambient temperature
40
-
+125
C
t/V
input transition rise and VCC = 1.65 V to 2.7 V
fall rate
VCC = 2.7 V to 5.5 V
-
-
20
ns/V
-
-
10
ns/V
10. Static characteristics
Table 7.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = 40 C to +85
VIH
VIL
VOL
Conditions
Min
Typ
Max
Unit
C[1]
HIGH-level input voltage
LOW-level input voltage
LOW-level output voltage
VCC = 1.65 V to 1.95 V
0.65VCC
-
-
V
VCC = 2.3 V to 2.7 V
1.7
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35VCC
V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3VCC
V
VI = VIH or VIL
-
-
-
IO = 100 A; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.45
V
IO = 8 mA; VCC = 2.3 V
-
-
0.3
V
IO = 12 mA; VCC = 2.7 V
-
-
0.4
V
IO = 24 mA; VCC = 3.0 V
-
-
0.55
V
IO = 32 mA; VCC = 4.5 V
-
-
0.55
V
II
input leakage current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
-
0.1
5
A
IOZ
OFF-state output current
VI = VIH or VIL; VO = VCC or GND;
VCC = 5.5 V
-
0.1
10
A
IOFF
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
-
0.1
10
A
ICC
supply current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
-
0.1
10
A
ICC
additional supply current
VI = VCC 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V; per pin
-
5
500
A
CI
input capacitance
-
2.5
-
pF
74LVC1G38_Q100
Product data sheet
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Rev. 1 — 27 November 2013
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2-input NAND gate; open drain
Table 7.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VCC = 1.65 V to 1.95 V
0.65VCC
-
-
V
Tamb = 40 C to +125 C
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
LOW-level output voltage
VOL
VCC = 2.3 V to 2.7 V
1.7
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 4.5 V to 5.5 V
0.7VCC
-
-
V
VCC = 1.65 V to 1.95 V
-
-
0.35VCC
V
VCC = 2.3 V to 2.7 V
-
-
0.7
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3VCC
V
VI = VIH or VIL
-
-
-
IO = 100 A; VCC = 1.65 V to 5.5 V
-
-
0.1
V
IO = 4 mA; VCC = 1.65 V
-
-
0.70
V
IO = 8 mA; VCC = 2.3 V
-
-
0.45
V
IO = 12 mA; VCC = 2.7 V
-
-
0.60
V
IO = 24 mA; VCC = 3.0 V
-
-
0.80
V
IO = 32 mA; VCC = 4.5 V
-
-
0.80
V
II
input leakage current
VI = 5.5 V or GND;
VCC = 0 V to 5.5 V
-
-
100
A
IOZ
OFF-state output current
VI = VIH or VIL; VO = VCC or GND;
VCC = 5.5 V
-
-
200
A
IOFF
power-off leakage current VI or VO = 5.5 V; VCC = 0 V
-
-
200
A
ICC
supply current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
-
-
200
A
ICC
additional supply current
VI = VCC 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V; per pin
-
-
5000
A
[1]
All typical values are measured at VCC = 3.3 V and Tamb = 25 C.
11. Dynamic characteristics
Table 8.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter
tpd
propagation delay
74LVC1G38_Q100
Product data sheet
40 C to +85 C
Conditions
40 C to +125 C
Unit
Min
Typ[1]
Max
Min
Max
VCC = 1.65 V to 1.95 V
1.0
3.0
10.0
1.0
12.5
ns
VCC = 2.3 V to 2.7 V
0.5
1.8
6.0
0.5
7.5
ns
VCC = 2.7 V
0.5
2.5
5.0
0.5
6.5
ns
VCC = 3.0 V to 3.6 V
0.5
2.3
4.5
0.5
5.7
ns
VCC = 4.5 V to 5.5 V
0.5
1.5
3.9
0.5
4.9
ns
A, B to Y; see Figure 5
[2]
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Rev. 1 — 27 November 2013
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5 of 13
74LVC1G38-Q100
NXP Semiconductors
2-input NAND gate; open drain
Table 8.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6.
Symbol Parameter
CPD
40 C to +85 C
Conditions
power dissipation
capacitance
Min
Max
Min
Max
-
6
-
-
-
[3]
VCC = 3.3 V;
VI = GND to VCC
40 C to +125 C
Typ[1]
[1]
Typical values are measured at Tamb = 25 C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2]
tpd is the same as tPZL and tPLZ.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
Unit
pF
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
12. Waveform and test circuit
VI
A, B input
VM
GND
t PLZ
t PZL
VCC
Y output
VM
VOL
VX
001aab719
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 5.
The input (A, B) to output (Y) propagation delays
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
1.65 V to 1.95 V
0.5VCC
0.5VCC
VOL + 0.15 V
2.3 V to 2.7 V
0.5VCC
0.5VCC
VOL + 0.15 V
2.7 V
1.5 V
1.5 V
VOL + 0.3 V
3.0 V to 3.6 V
1.5 V
1.5 V
VOL + 0.3 V
4.5 V to 5.5 V
0.5VCC
0.5VCC
VOL + 0.3 V
74LVC1G38_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
6 of 13
74LVC1G38-Q100
NXP Semiconductors
2-input NAND gate; open drain
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Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 6.
Test circuit for measuring switching times
Table 10.
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr, tf
CL
RL
tPZL, tPLZ
1.65 V to 1.95 V
VCC
2.0 ns
30 pF
1 k
VCC
2.3 V to 2.7 V
VCC
2.0 ns
30 pF
500
VCC
2.7 V
2.7 V
2.5 ns
50 pF
500
VCC
3.0 V to 3.6 V
2.7 V
2.5 ns
50 pF
500
VCC
4.5 V to 5.5 V
VCC
2.5 ns
50 pF
500
VCC
74LVC1G38_Q100
Product data sheet
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Rev. 1 — 27 November 2013
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74LVC1G38-Q100
NXP Semiconductors
2-input NAND gate; open drain
13. Package outline
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74LVC1G38_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
8 of 13
74LVC1G38-Q100
NXP Semiconductors
2-input NAND gate; open drain
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Package outline SOT753 (SC-74A)
74LVC1G38_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
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NXP Semiconductors
2-input NAND gate; open drain
14. Abbreviations
Table 11.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 12.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LVC1G38_Q100 v.1
20131127
Product data sheet
-
-
74LVC1G38_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
10 of 13
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NXP Semiconductors
2-input NAND gate; open drain
16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LVC1G38_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
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2-input NAND gate; open drain
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
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Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LVC1G38_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 November 2013
© NXP B.V. 2013. All rights reserved.
12 of 13
74LVC1G38-Q100
NXP Semiconductors
2-input NAND gate; open drain
18. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 3
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
Recommended operating conditions. . . . . . . . 4
Static characteristics. . . . . . . . . . . . . . . . . . . . . 4
Dynamic characteristics . . . . . . . . . . . . . . . . . . 5
Waveform and test circuit . . . . . . . . . . . . . . . . . 6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 10
Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Contact information. . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 27 November 2013
Document identifier: 74LVC1G38_Q100