74AUP1G08-Q100 Low-power 2-input AND gate Rev. 1 — 31 January 2013 Product data sheet 1. General description The 74AUP1G08-Q100 provides the single 2-input AND function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V HBM JESD22-A114F Class 3A. Exceeds 5000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Low static power consumption; ICC = 0.9 A (maximum) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of VCC IOFF circuitry provides partial Power-down mode operation 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74AUP1G08GW-Q100 40 C to +125 C Name Description Version TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.25 mm SOT353-1 4. Marking Table 2. Marking Type number Marking code[1] 74AUP1G08GW-Q100 pE [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram A 1 B 2 A 1 Y & 4 4 Y 2 B mna113 Fig 1. Logic symbol mna221 mna114 Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning $83*4 % $ *1' 9&& < DDD Fig 4. Pin configuration SOT353-1 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 2 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate 6.2 Pin description Table 3. Pin description Symbol Pin Description B 1 data input A 2 data input GND 3 ground (0 V) Y 4 data output VCC 5 supply voltage 7. Functional description Table 4. Function table[1] Input Output A B Y L L L L H L H L L H H H [1] H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current Conditions Min Max Unit 0.5 +4.6 V 50 - mA [1] 0.5 +4.6 V 50 - mA [1] 0.5 +4.6 V - 20 mA VI < 0 V VI input voltage IOK output clamping current VO < 0 V VO output voltage Active mode and Power-down mode IO output current VO = 0 V to VCC ICC supply current - +50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 250 mW total power dissipation Ptot Tamb = 40 C to +125 C [2] [1] The minimum input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP5 packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K. 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 3 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate 9. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC Conditions Min Max Unit supply voltage 0.8 3.6 V VI input voltage 0 3.6 V VO output voltage Active mode 0 VCC V Power-down mode; VCC = 0 V 0 3.6 V 40 +125 C 0 200 ns/V Typ Max Unit Tamb ambient temperature t/V input transition rise and fall rate VCC = 0.8 V to 3.6 V 10. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 0.8 V 0.70 VCC - - V VCC = 0.9 V to 1.95 V 0.65 VCC - - V Tamb = 25 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage 74AUP1G08_Q100 Product data sheet VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30 VCC V VCC = 0.9 V to 1.95 V - - 0.35 VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.1 - - V IO = 1.1 mA; VCC = 1.1 V 0.75 VCC - - V IO = 1.7 mA; VCC = 1.4 V 1.11 - - V IO = 1.9 mA; VCC = 1.65 V 1.32 - - V IO = 2.3 mA; VCC = 2.3 V 2.05 - - V VI = VIH or VIL IO = 3.1 mA; VCC = 2.3 V 1.9 - - V IO = 2.7 mA; VCC = 3.0 V 2.72 - - V IO = 4.0 mA; VCC = 3.0 V 2.6 - - V VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.31 V IO = 1.9 mA; VCC = 1.65 V - - 0.31 V IO = 2.3 mA; VCC = 2.3 V - - 0.31 V IO = 3.1 mA; VCC = 2.3 V - - 0.44 V IO = 2.7 mA; VCC = 3.0 V - - 0.31 V IO = 4.0 mA; VCC = 3.0 V - - 0.44 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 4 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.1 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.2 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.2 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.5 A ICC additional supply current VI = VCC 0.6 V; IO = 0 A; VCC = 3.3 V - - 40 A CI input capacitance VCC = 0 V to 3.6 V; VI = GND or VCC - 0.8 - pF CO output capacitance VO = GND; VCC = 0 V - 1.7 - pF VCC = 0.8 V 0.70 VCC - - V VCC = 0.9 V to 1.95 V 0.65 VCC - - V VCC = 2.3 V to 2.7 V 1.6 - V V [1] Tamb = 40 C to +85 C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage - VCC = 3.0 V to 3.6 V 2.0 - - VCC = 0.8 V - - 0.30 VCC V VCC = 0.9 V to 1.95 V - - 0.35 VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.1 - - V IO = 1.1 mA; VCC = 1.1 V 0.7 VCC - - V IO = 1.7 mA; VCC = 1.4 V 1.03 - - V IO = 1.9 mA; VCC = 1.65 V 1.30 - - V IO = 2.3 mA; VCC = 2.3 V 1.97 - - V IO = 3.1 mA; VCC = 2.3 V 1.85 - - V IO = 2.7 mA; VCC = 3.0 V 2.67 - - V IO = 4.0 mA; VCC = 3.0 V 2.55 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.1 V IO = 1.1 mA; VCC = 1.1 V - - 0.3 VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.37 V IO = 1.9 mA; VCC = 1.65 V - - 0.35 V IO = 2.3 mA; VCC = 2.3 V - - 0.33 V IO = 3.1 mA; VCC = 2.3 V - - 0.45 V IO = 2.7 mA; VCC = 3.0 V - - 0.33 V IO = 4.0 mA; VCC = 3.0 V - - 0.45 V - - 0.5 A VI = VIH or VIL VI = VIH or VIL II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.5 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.6 A 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 5 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 0.9 A ICC additional supply current VI = VCC 0.6 V; IO = 0 A; VCC = 3.3 V - - 50 A [1] Tamb = 40 C to +125 C HIGH-level input voltage VIH LOW-level input voltage VIL VOH HIGH-level output voltage LOW-level output voltage VOL VCC = 0.8 V 0.75 VCC - - V VCC = 0.9 V to 1.95 V 0.70 VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.25 VCC V VCC = 0.9 V to 1.95 V - - 0.30 VCC V VCC = 2.3 V to 2.7 V - - 0.7 V VCC = 3.0 V to 3.6 V - - 0.9 V VI = VIH or VIL IO = 20 A; VCC = 0.8 V to 3.6 V VCC 0.11 - - V IO = 1.1 mA; VCC = 1.1 V 0.6 VCC - - V IO = 1.7 mA; VCC = 1.4 V 0.93 - - V IO = 1.9 mA; VCC = 1.65 V 1.17 - - V IO = 2.3 mA; VCC = 2.3 V 1.77 - - V IO = 3.1 mA; VCC = 2.3 V 1.67 - - V IO = 2.7 mA; VCC = 3.0 V 2.40 - - V IO = 4.0 mA; VCC = 3.0 V 2.30 - - V IO = 20 A; VCC = 0.8 V to 3.6 V - - 0.11 V IO = 1.1 mA; VCC = 1.1 V - - 0.33 VCC V IO = 1.7 mA; VCC = 1.4 V - - 0.41 V VI = VIH or VIL IO = 1.9 mA; VCC = 1.65 V - - 0.39 V IO = 2.3 mA; VCC = 2.3 V - - 0.36 V IO = 3.1 mA; VCC = 2.3 V - - 0.50 V IO = 2.7 mA; VCC = 3.0 V - - 0.36 V IO = 4.0 mA; VCC = 3.0 V - - 0.50 V II input leakage current VI = GND to 3.6 V; VCC = 0 V to 3.6 V - - 0.75 A IOFF power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V - - 0.75 A IOFF additional power-off leakage current VI or VO = 0 V to 3.6 V; VCC = 0 V to 0.2 V - - 0.75 A ICC supply current VI = GND or VCC; IO = 0 A; VCC = 0.8 V to 3.6 V - - 1.4 A ICC additional supply current VI = VCC 0.6 V; IO = 0 A; VCC = 3.3 V - - 75 A [1] [1] One input at VCC 0.6 V, other input at VCC or GND. 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 6 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6 Symbol Parameter Min Typ [1] Max Unit VCC = 0.8 V - 17.0 - ns VCC = 1.1 V to 1.3 V 2.6 5.1 10.8 ns VCC = 1.4 V to 1.6 V 1.6 3.7 6.5 ns VCC = 1.65 V to 1.95 V 1.3 3.0 5.2 ns VCC = 2.3 V to 2.7 V 1.1 2.4 4.0 ns VCC = 3.0 V to 3.6 V 1.0 2.2 3.5 ns VCC = 0.8 V - 20.6 - ns VCC = 1.1 V to 1.3 V 2.4 6.0 12.5 ns VCC = 1.4 V to 1.6 V 2.0 4.3 7.6 ns VCC = 1.65 V to 1.95 V 1.7 3.6 6.1 ns VCC = 2.3 V to 2.7 V 1.4 2.9 4.8 ns VCC = 3.0 V to 3.6 V 1.3 2.7 4.2 ns VCC = 0.8 V - 24.1 - ns VCC = 1.1 V to 1.3 V 3.4 6.8 14.2 ns VCC = 1.4 V to 1.6 V 2.3 4.9 8.6 ns VCC = 1.65 V to 1.95 V 1.9 4.0 6.9 ns VCC = 2.3 V to 2.7 V 1.7 3.4 5.5 ns VCC = 3.0 V to 3.6 V 1.5 3.1 4.8 ns VCC = 0.8 V - 34.4 - ns VCC = 1.1 V to 1.3 V 4.6 9.1 19.4 ns VCC = 1.4 V to 1.6 V 3.4 6.4 11.5 ns VCC = 1.65 V to 1.95 V 2.6 5.3 9.1 ns VCC = 2.3 V to 2.7 V 2.3 4.5 7.2 ns VCC = 3.0 V to 3.6 V 2.2 4.2 6.2 ns Conditions Tamb = 25 C; CL = 5 pF tpd propagation delay A, B to Y; see Figure 5 [2] Tamb = 25 C; CL = 10 pF tpd propagation delay A, B to Y; see Figure 5 [2] Tamb = 25 C; CL = 15 pF tpd propagation delay A, B to Y; see Figure 5 [2] Tamb = 25 C; CL = 30 pF tpd propagation delay 74AUP1G08_Q100 Product data sheet A, B to Y; see Figure 5 [2] All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 7 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate Table 8. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6 Symbol Parameter Conditions Min Typ [1] Max Unit Tamb = 25 C power dissipation capacitance f = 1 MHz; VI = GND to VCC CPD VCC = 0.8 V - 2.5 - pF VCC = 1.1 V to 1.3 V - 2.7 - pF VCC = 1.4 V to 1.6 V - 2.8 - pF VCC = 1.65 V to 1.95 V - 2.9 - pF VCC = 2.3 V to 2.7 V - 3.5 - pF VCC = 3.0 V to 3.6 V - 4.0 - pF [1] All typical values are measured at nominal VCC. [2] tpd is the same as tPLH and tPHL. [3] [3] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of the outputs. Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6 Symbol Parameter 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max VCC = 1.1 V to 1.3 V 2.1 11.7 2.1 12.9 ns VCC = 1.4 V to 1.6 V 1.5 7.5 1.5 8.3 ns VCC = 1.65 V to 1.95 V 1.3 6.1 1.3 6.7 ns VCC = 2.3 V to 2.7 V 1.0 4.8 1.0 5.3 ns VCC = 3.0 V to 3.6 V 0.9 4.3 0.9 4.8 ns VCC = 1.1 V to 1.3 V 2.2 13.6 2.2 15.0 ns VCC = 1.4 V to 1.6 V 1.8 8.9 1.8 9.8 ns VCC = 1.65 V to 1.95 V 1.6 7.2 1.6 7.9 ns VCC = 2.3 V to 2.7 V 1.3 5.7 1.3 6.3 ns VCC = 3.0 V to 3.6 V 1.2 4.7 1.2 5.2 ns CL = 5 pF tpd propagation delay A, B to Y; see Figure 5 [1] CL = 10 pF tpd propagation delay 74AUP1G08_Q100 Product data sheet A, B to Y; see Figure 5 [1] All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 8 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 6 Symbol Parameter 40 C to +85 C Conditions 40 C to +125 C Unit Min Max Min Max VCC = 1.1 V to 1.3 V 3.1 15.7 3.1 17.3 ns VCC = 1.4 V to 1.6 V 2.1 10.1 2.1 11.2 ns VCC = 1.65 V to 1.95 V 1.8 8.2 1.8 9.0 ns VCC = 2.3 V to 2.7 V 1.6 6.5 1.6 7.2 ns VCC = 3.0 V to 3.6 V 1.5 5.9 1.5 6.5 ns CL = 15 pF propagation delay tpd [1] A, B to Y; see Figure 5 CL = 30 pF propagation delay tpd [1] [1] A, B to Y; see Figure 5 VCC = 1.1 V to 1.3 V 4.1 21.8 4.1 24.0 ns VCC = 1.4 V to 1.6 V 2.9 13.6 2.9 15.0 ns VCC = 1.65 V to 1.95 V 2.4 10.9 2.4 12.1 ns VCC = 2.3 V to 2.7 V 2.2 8.6 2.2 9.5 ns VCC = 3.0 V to 3.6 V 2.1 7.5 2.1 8.3 ns tpd is the same as tPLH and tPHL. 12. Waveforms VI VM A, B input GND t PHL t PLH VOH VM Y output mna614 VOL Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage drops that occur with the output load. Fig 5. The data input (A or B) to output (Y) propagation delays Table 10. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 VCC 0.5 VCC VCC 3.0 ns 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 9 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate VCC VEXT 5 kΩ G VI VO DUT CL RT RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 6. Test circuit for measuring switching times Table 11. Test data Supply voltage Load VEXT [1] VCC CL RL 0.8 V to 3.6 V 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M [1] tPLH, tPHL tPZH, tPHZ tPZL, tPLZ open GND 2 VCC For measuring enable and disable times RL = 5 k. For measuring propagation delays, setup and hold times and pulse width, RL = 1 M. 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 10 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1.25 mm E D SOT353-1 A X c y HE v M A Z 5 4 A2 A (A3) A1 θ 1 Lp 3 L e w M bp detail X e1 0 1.5 3 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(1) e e1 HE L Lp v w y Z(1) θ mm 1.1 0.1 0 1.0 0.8 0.15 0.30 0.15 0.25 0.08 2.25 1.85 1.35 1.15 0.65 1.3 2.25 2.0 0.425 0.46 0.21 0.3 0.1 0.1 0.60 0.15 7° 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT353-1 Fig 7. REFERENCES IEC JEDEC JEITA MO-203 SC-88A EUROPEAN PROJECTION ISSUE DATE 00-09-01 03-02-19 Package outline SOT353-1 (TSSOP5) 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 11 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model 15. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP1G08_Q100 v.1 20130131 Product data sheet - - 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 12 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74AUP1G08_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. 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NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 13 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74AUP1G08_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 31 January 2013 © NXP B.V. 2013. All rights reserved. 14 of 15 74AUP1G08-Q100 NXP Semiconductors Low-power 2-input AND gate 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 31 January 2013 Document identifier: 74AUP1G08_Q100