BGS15MA12 SP5T Rx Diversity Switch Data Sheet Revision 3.1 - 2016-05-11 Power Management & Multimarket Edition 2016-05-11 Published by Infineon Technologies AG 81726 Munich, Germany c 2016 Infineon Technologies AG All Rights Reserved. LEGAL DISCLAIMER The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. BGS15MA12 Revision History Document No.: BGS15MA12__v3.1.pdf Revision History: Rev. v3.1 Previous Version: Revision v3.0 - 2015-07-24 Page Subjects (major changes since last revision) 20 Carrier Tape drawing updated (Fig. 12) Trademarks of Infineon Technologies AG TM TM TM TM TM TM TM TM TM TM TM µHVIC , µIPM , µPFC , AU-ConvertIR , AURIX , C166 , CanPAK , CIPOS , CIPURSE , CoolDP , CoolGaN , TM TM TM TM TM TM TM TM TM TM COOLiR , CoolMOS , CoolSET , CoolSiC , DAVE , DI-POL , DirectFET , DrBlade , EasyPIM , EconoBRIDGE , TM TM TM TM TM TM TM TM TM EconoDUAL , EconoPACK , EconoPIM , EiceDRIVER , eupec , FCOS , GaNpowIR , HEXFET , HITFET , TM TM TM TM TM TM TM TM TM TM HybridPACK , iMOTION , IRAM , ISOFACE , IsoPACK , LEDrivIR , LITIX , MIPAQ , ModSTACK , my-d , TM TM TM TM TM TM TM TM TM NovalithIC , OPTIGA , OptiMOS , ORIGA , PowIRaudio , PowIRStage , PrimePACK , PrimeSTACK , PROFET , TM TM TM TM TM TM TM TM TM PRO-SIL , RASIC , REAL3 , SmartLEWIS , SOLID FLASH , SPOC , StrongIRFET , SupIRBuck , TEMPFET , TM TM TM TM TM TRENCHSTOP , TriCore , UHVIC , XHP , XMC . Other Trademarks All referenced product or service names and trademarks are the property of their respective owners. Trademarks updated November 2015 Data Sheet 3 Revision 3.1 - 2016-05-11 BGS15MA12 Contents 1 Features 5 2 Product Description 5 3 Maximum Ratings 6 4 Operation Ranges 8 5 RF Characteristics 9 6 MIPI RFFE Specification 11 7 Application Information 17 8 Package Information 19 List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 BGS15MA12 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MIPI to RF Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Settling Time Definition: a) when the device is already in Active Mode. b) when changing from Low Power Mode to Active Mode. After Power-Up of VIO the device is set to Low Power Mode. An additional MIPI instruction is necessary to set the switch to Active Mode. This case is covered by b). . . . . . . . . . . . . . . . . . . . . . . . . Received clock signal constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus active data receiver timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus park cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bus active data transmission timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Requirements for VIO-initiated reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGS15MA12 Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BGS15MA12 Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATSLP-12-4 Package Outline (top, side and bottom views) . . . . . . . . . . . . . . . . . . . . . . . . . Marking Specification (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprint Recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATSLP-12-4 Carrier Tape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 10 12 13 13 14 14 17 18 19 19 20 20 List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 Ordering Information . . . . Maximum Ratings, Table I . Maximum Ratings, Table II . Operation Ranges . . . . . RF Input Power . . . . . . . RF Characteristics . . . . . MIPI Features . . . . . . . . Startup Behavior . . . . . . MIPI RFFE operating timing Register Mapping . . . . . . Truth Table, Register_0 . . Pin Definition and Function Bill of Materials . . . . . . . Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 7 8 8 9 11 11 12 15 16 17 18 Revision 3.1 - 2016-05-11 BGS15MA12 BGS15MA12 SP5T Rx Diversity Switch 1 Features • Low insertion loss • Low harmonic generation • High port-to-port-isolation • Suitable for LTE / WCDMA Rx Applications • 0.1 to 2.9 GHz coverage • No decoupling capacitors required if no DC applied on RF lines • On chip control logic including ESD protection • Integrated MIPI RFFE interface operating in 1.1 to 1.95 V voltage range • Software programmable MIPI RFFE USID • Direct to battery supply • Small form factor 1.1 mm x 1.9 mm • No power supply blocking required • High EMI robustness • RoHS and WEEE compliant package 2 Product Description The BGS15MA12 RF MOS switch is specifically designed for LTE and WCDMA diversity applications. This SP5T offers low insertion loss and low harmonic generation in termination mode. The switch is controlled via a MIPI RFFE controller. The on-chip controller allows power-supply voltages from 1.1 to 1.95 V. The switch features direct-connect-to-battery functionality and DC-free RF ports. Unlike GaAs technology, external DC blocking capacitors at the RF Ports are only required if DC voltage is applied externally. The BGS15MA12 RF Switch is manufactured in Infineon’s patented MOS technology, offering the performance of GaAs with the economy and integration of conventional CMOS including the inherent higher ESD robustness. The device has a very small size of only 1.1 x 1.9 mm2 and a maximum height of 0.65 mm. Table 1: Ordering Information Type Package Marking Chip BGS15MA12 ATSLP-12-4 S4 m4829 Data Sheet 5 Revision 3.1 - 2016-05-11 BGS15MA12 RX1 RX2 RX3 RX4 RX5 AI SP5T VBAT VIO MIPI-RFFE ControlOInterface GND SSEL1 SCLK SDATA SSEL2 Figure 1: BGS15MA12 Block diagram 3 Maximum Ratings Table 2: Maximum Ratings, Table I at TA = 25 ◦C, unless otherwise specified Parameter Symbol Values Min. Typ. Max. Unit Note / Test Condition Frequency Range f 0.1 – – GHz 1) Supply voltage VBAT -0.5 – 6.0 V – 150 ◦ C – C – Storage temperature range TSTG -55 – Junction temperature Tj – – 125 ◦ RF input power at all RX ports PRF_RX – – 27 dBm CW 2) VESD_CDM -1 – +1 V All pins 3) VESD_HBM -1 – +1 kV Digital, digital versus RF -1 – +1 kV RF ESD capability, CDM ESD capability, HBM 1) There is also a DC connection between switched paths. The DC voltage at RF ports VRFDC has to be 0V. Charged-Device Model JESD22-C101. Simulates charging/discharging events that occur in production equipment and processes. Potential for CDM ESD events occurs whenever there is metal-to-metal contact in manufacturing. 3) Human Body Model ANSI/ESDA/JEDEC JS-001-2012 (R=1.5 kΩ, C=100 pF). 4) IEC 61000-4-2 (R=330 Ω, C=150 pF), contact discharge. 2) Field-Induced Data Sheet 6 Revision 3.1 - 2016-05-11 BGS15MA12 Table 3: Maximum Ratings, Table II at TA = 25 ◦C, unless otherwise specified Parameter Maximum DC-voltage on RF- Symbol VRFDC Values Min. Typ. Max. 0 – 0 Unit Note / Test Condition V No DC voltages allowed on Ports and RF-Ground RF-Ports RFFE Supply Voltage VIO -0.5 – RFFE Control Voltage Lev- V -0.7 – 3 V – VIO+0.7 V – els at SCLK, SDATA, SSEL1, (max. SSEL2 3) Data Sheet 7 Revision 3.1 - 2016-05-11 BGS15MA12 4 Operation Ranges Table 4: Operation Ranges Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. VBAT 2.2 – 5.5 V – Supply current IBAT – 80 200 µA – Supply current in standby IBAT_SB – 0.5 1 µA VIO=low or MIPI low-power Supply voltage 3) 3) mode mode RFFE supply voltage VIO 1.1 1.8 1.95 V – VIH 0.7*VIO – VIO V – RFFE input low voltage VIL 0 – 0.3*VIO V – RFFE output high voltage2) VOH 0.8*VIO – VIO V – RFFE output low voltage VOL 0 – 0.2*VIO V – RFFE control input capaci- CCtrl – – 2 pF – IVIO – 15 – µA Idle State 85 ◦ – 1) RFFE input high voltage 1) 2) tance RFFE supply current Ambient temperature 1) SCLK, TA -30 25 C SDATA, SSEL1 and SSEL2 2) SDATA 3) T ◦ ◦ A = −30 C - 85 C, VBAT = 2.2 - 5.5 V Table 5: RF Input Power Parameter RX ports (50 Ω) Data Sheet Symbol PRF_RX Values Min. Typ. Max. – – 24 8 Unit Note / Test Condition dBm – Revision 3.1 - 2016-05-11 BGS15MA12 5 RF Characteristics Table 6: RF Characteristics at TA = −30 ◦C–85 ◦C, PIN = 0 dBm, Supply Voltage VBAT= 2.2 V–5.5 V, unless otherwise specified Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. 0.2 0.28 0.35 dB 700–1000 MHz 0.25 0.35 0.5 dB 1700–2200 MHz 0.3 0.42 0.6 dB 2300–2700 MHz 20 30 – dB 700–1000 MHz 18 28 – dB 1700–2200 MHz 12 22 – dB 2300–2700 MHz 24 34 – dB 700–1000 MHz 17 27 – dB 1700–2200 MHz 15 25 – dB 2300–2700 MHz 26 36 – dB 700–1000 MHz 21 31 – dB 1700–2200 MHz 18 28 – dB 2300–2700 MHz >30 – – dBm -95 -75 dBc 1) Insertion Loss All RX Ports IL 1) Return Loss All RX Ports Isolation all RX Ports Isolation RX Ports to AI RL ISO ISO P1 dB Compression Point, Extrapolated All RX Ports P1dB Harmonic Generation up to 12.75 GHz All RX Ports PHarm – 20 dBm, 50 Ω, CW mode ◦ 2) Intermodulation Distortion in Rx Band (TA = 25 C, VBAT= 2.6 V) IMD2, low IMD2low – -115 -105 dBm IMD3 IMD3 – -125 -110 dBm IMD2, high IMD2high – -120 -110 dBm RF Rise Time RX Port On/Off ton/off 0.5 1 5 µs MIPI to RF Time tINT 0.5 1.5 5 µs Power Up Settling Time t PUS – 10 25 µs Tx = 10 dBm, Interferer = −15 dBm, 50 Ω Switching Time 90 % OFF to 90 % ON; 90 % ON to 90 % OFF 50 % last SCLK falling flank to 90 % ON, Fig. 2 After power down mode, Fig. 3 1) On application board with a RF low-Q two element matching network at the antenna port 2) On application board with shunt inductor, Min/Max-values measured with phase shifter. Data Sheet 9 Revision 3.1 - 2016-05-11 BGS15MA12 SDATA TINT SCLK 90% RF Signal Figure 2: MIPI to RF Time VBAT VIO SDATA SCLK a) TPUP VBAT VIO SDATA SCLK b) TPUP Figure 3: Power-Up Settling Time Definition: a) when the device is already in Active Mode. b) when changing from Low Power Mode to Active Mode. After Power-Up of VIO the device is set to Low Power Mode. An additional MIPI instruction is necessary to set the switch to Active Mode. This case is covered by b). Data Sheet 10 Revision 3.1 - 2016-05-11 BGS15MA12 6 MIPI RFFE Specification All sequences are implemented according to the ’MIPI Alliance Specification for RF Front-End Control Interface’ document version 1.10 - 26. July 2011. Table 7: MIPI Features Feature Supported Comment Register write command sequence Yes Register read command sequence Yes Extended register write command sequence No Up to 4 Bytes Extented register read command sequence No Up to 4 Bytes Register 0 write command sequence Yes Trigger function Yes Programmable USID Yes Trigger assignment to each control register is supported 3 register command sequence and extended register command sequence Status Register Yes Register for debugging Reset Yes By VIO, Power Mode and RFFE_STATUS Group SID Yes SSEL1 and SSEL2 pins Yes External pins for changing USID: SSEL1=0 & SSEL2=0 → 1000, SSEL1=0 & SSEL2=1 → 1001, SSEL1=1 & SSEL2=0 → 1010, SSEL1=1 & SSEL2=1 → 1011 Full speed write Yes Half speed read Yes Full speed read Yes Table 8: Startup Behavior Feature State Comment Power status LOW POWER The chip is in low power mode after startup Trigger function ENABLED Trigger function is enabled after startup. Trigger function can be disabled via PM_TRIG register. Data Sheet 11 Revision 3.1 - 2016-05-11 BGS15MA12 Table 9: MIPI RFFE Operating Timing Parameter Symbol SCLK Frequency FSCLK SCLK Period TSCLK Values Unit Note / Test Condition 26 MHz Full speed – 13 MHz Half speed 0.038 – 32 µs Full speed 0.077 – 32 µs Half speed 11.25 – – ns Full speed, see Fig. 4 24 – – ns Half speed, see Fig. 4 11.25 – – ns Full speed, see Fig. 4 24 – – ns Half speed, see Fig. 4 1 – – ns Full speed, see Fig. 5 2 – – ns Half speed, see Fig. 5 5 – – ns Full speed, see Fig. 5 5 – – ns Half speed, see Fig. 5 – – 10 ns Full speed, see Fig. 6 – – 18 ns Half speed, see Fig. 6 – – 10.25 ns Full speed, see Fig. 7 – – 22 ns Half speed, see Fig. 7 2.1 – 6.5 ns Full speed, see Fig. 7 Min. Typ. Max. 0.032 – 0.032 SCLK Low Period TSCLKIL SCLK High Period TSCLKIH SDATA Setup Time TS SDATA Hold Time TH SDATA Release Time TSDATAZ Time for Data Output TD SDATA Rise/Fall Time TSDATAOTR 2.1 – 10 ns Half speed, see Fig. 7 VIO Rise Time TVIO-R 10 – 450 µs See Fig. 8 VIO Reset Time TVIO-RST 10 – – µs See Fig. 8 Reset Delay Time TSIGOL 0.12 – – µs See Fig. 8 TSCLKIH TSCLKIL VTPmax VTNmin Figure 4: Received clock signal constraints Data Sheet 12 Revision 3.1 - 2016-05-11 BGS15MA12 VTPmax SCLK VTPmin TS TH TS TH VTPmax SDATA VTPmin Figure 5: Bus active data receiver timing requirements VTPmax SCLK VTNmin TSDATAZ VOHmin SDATA VOLmax Bus Park Cycle Signal driven Signal not driven, pull down only TSDATAZ is measured from SCLK VTN level for a device receiving SCLK and driving SDATA lines Figure 6: Bus park cycle timing Data Sheet 13 Revision 3.1 - 2016-05-11 BGS15MA12 VTPmax SCLK VTPmin TD TD TSDATAOTR TSDATAOTR VOHmin SDATA VOLmax Figure 7: Bus active data transmission timing specification TSIGOL VIO (V) VIOmax Not To Scale VIOmin SCLK & SDATA must be held at low level from deassertion of VIO until the end of TSIGOL TVIO-RST All slave registers set/reset to manufacturer‘s defaults TVIO-R VVIO-RST (0.2V) Time Figure 8: Requirements for VIO-initiated reset Data Sheet 14 Revision 3.1 - 2016-05-11 BGS15MA12 Table 10: Register Mapping Register Address 0x0000 0x001D Register Name Function Description REGISTER_0 PRODUCT_ID Data Bits 7:0 7:0 MODE_CTRL PRODUCT_ID 0x001E MANUFACTURER_ID 7:0 MANUFACTURER_ID [7:0] 0x001C PM_TRIG 7:6 PWR_MODE Switch control This is a read-only register. However, during the programming of the USID a write command sequence is performed on this register, even though the write does not change its value. This is a read-only register. However, during the programming of the USID, a write command sequence is performed on this register, even though the write does not change its value. 00: Normal operation 01: Default settings (STARTUP) 10: Low power (LOW POWER) 11: Reserved If this bit is set, trigger 2 is disabled. When all triggers disabled, if writing to a register that is associated to trigger 2, the data goes directly to the destination register. If this bit is set, trigger 1 is disabled. When all triggers disabled, if writing to a register that is associated to trigger 1, the data goes directly to the destination register. If this bit is set, trigger 0 is disabled. When all triggers disabled, if writing to a register that is associated to trigger 0, the data goes directly to the destination register. A write of a one to this bit loads trigger 2’s registers. A write of a one to this bit loads trigger 1’s registers. A write of a one to this bit loads trigger 0’s registers. These are read-only bits that are reserved and yield a value of 0b00 at readback. These bits are read-only. However, during the programming of the USID, a write command sequence is performed on this register even though the write does not change its value. Programmable USID. Performing a write to this register using the described programming sequences will program the USID in devices supporting this feature. These bits store the USID of the device. 0x001F MAN_USID 5 TRIGGER_MASK_2 4 TRIGGER_MASK_1 3 TRIGGER_MASK_0 2 TRIGGER_2 1 TRIGGER_1 0 TRIGGER_0 7:6 SPARE 5:4 MANUFACTURER_ID [9:8] 3:0 USID Default 00000000 11010000 Broadcast_ID Support No No Trigger Support Yes No R/W R/W R 00011010 No No R 10 Yes No R/W 0 No No 0 No No 0 No No 0 Yes No 0 Yes No 0 Yes No 00 No No R/W R/W 01 USID_Sel12 =00 → 1000, USID_Sel12 =01 → 1001, USID_Sel12 =10 → 1010, USID_Sel12 =11 → 1011 Continued on next page Data Sheet 15 Revision 3.1 - 2016-05-11 BGS15MA12 Table 10: Register Mapping – Continued from previous page Register Address 0x001A Register Name RFFE_STATUS Data Bits 7 6 5 4 3 2 1 0 0x001B GROUP_SID 7:4 3:0 Function Description SOFTWARE RESET 0: Normal operation 1: Software reset Command sequence received with parity error - discard command. Command length error Address frame parity error = 1 0 Data frame with parity error 0 Read command to an invalid address Write command to an invalid address Read command with a BROADCAST_ID or GROUP_SID 0 0 0 COMMAND_FRAME_ PARITY_ERR COMMAND_LENGTH_ERR ADDRESS_FRAME_ PARITY_ERR DATA_FRAME_ PARITY_ERR READ_UNUSED_REG WRITE_UNUSED_REG BID_GID_ERR RESERVED GROUP_SID Default 0 Trigger Support No R/W R/W No No R No No R/W 0 0 0 0 Group slave ID Broadcast_ID Support No Table 11: Modes of Operation (Truth Table, Register_0) REGISTER_0 Bits State Mode D7 D6 D5 D4 D3 D2 D1 D0 1 Isolation x x x 0 0 0 0 0 2 RX1-AI x x x 0 0 0 0 1 3 RX2-AI x x x 0 0 0 1 0 4 RX3-AI x x x 0 1 0 0 0 5 RX4-AI x x x 0 0 1 0 0 6 RX5-AI x x x 1 0 0 0 0 7 RX1&RX2-AI x x x 0 0 0 1 1 8 RX2&RX3-AI x x x 0 1 0 1 0 9 RX3&RX4-AI x x x 0 1 1 0 0 10 RX4&RX5-AI x x x 1 0 1 0 0 11 RX1&RX3-AI x x x 0 1 0 0 1 12 RX2&RX4-AI x x x 0 0 1 1 0 13 RX3&RX5-AI x x x 1 1 0 0 0 14 RX1&RX4-AI x x x 0 0 1 0 1 15 RX2&RX5-AI x x x 1 0 0 1 0 16 RX1&RX5-AI x x x 1 0 0 0 1 Data Sheet 16 Revision 3.1 - 2016-05-11 BGS15MA12 7 Application Information Pin Configuration and Function 1 12 10 13 2 3 11 4 5 9 8 6 7 Figure 9: BGS15MA12 Pin Configuration (top view) Table 12: Pin Definition and Function Pin No. Name Function 1 SLK MIPI RFFE Clock (Input) 2 VIO MIPI RFFE Power Supply 3 RX5 RF-Port RX No. 5 4 RX4 RF-Port RX No. 4 5 RX3 RF-Port RX No. 3 6 RX2 RF-Port RX No. 2 7 RX1 RF-Port RX No. 1 8 SSEL1 MIPI SEL Port No. 1 (Input) 9 SSEL2 MIPI SEL Port No. 2 (Input) 10 AI RF-Input Port 11 VBAT Power Supply 12 SDATA MIPI RFFE Data (Input / Output) 13 GND Ground Data Sheet 17 Revision 3.1 - 2016-05-11 BGS15MA12 Application Board Configuration RX1 RX2 RX3 RX4 RX5 AI SP5T VBAT=2.8V VIO=1.8V C1 (optionalp C2 (optionalp MIPI-RFFE ControlNInterface SCLK SDATA GND C3 (optionalp C4 (optionalp SSEL1=0/1.8V SSEL2=0/1.8V Figure 10: BGS15MA12 Application Schematic Table 13: Bill of Materials Table Name Value Package Manufacturer Function C1 (optional) 1 nF 0201 Various RF Bypass1) C2 (optional) 1 nF 0201 Various RF Bypass1) C3 (optional) 1 nF 0201 Various RF Bypass1) C4 (optional) 1 nF 0201 Various RF Bypass1) N1 BGS15MA12 ATSLP-12-4 Infineon RF MOS Switch 1) RF bypass recommended to mitigate power supply noise Data Sheet 18 Revision 3.1 - 2016-05-11 BGS15MA12 8 Package Information Top view Bottom view 9 6 10 5 11 4 12 0.4 B 8 3 2 1 0.1 A 0.1 A 0.1 B 7 0.2 ±0.05 12x 0.2 ±0.05 12x Pin 1 marking 0.2 ±0.05 0.1 B 0.4 4 x 0.4 = 1.6 A 0.05 MAX. STANDOFF 1.9 ±0.05 1.1±0.05 0.75 ±0.05 0.6 ±0.05 2 x 0.4 = 0.8 ATSLP-12-1, -2, -3, -4, -5, -7-PO V03 Figure 11: ATSLP-12-4 Package Outline (top, side and bottom views) 12 Type code Date code (YW) Pin 1 marking ATSLP-12-1, -2, -3, -4, -5, -7-MK V03 Figure 12: Marking Specification (top view) Data Sheet 19 Revision 3.1 - 2016-05-11 BGS15MA12 0.4 0.4 0.25 0.25 0.25 Copper 0.8 0.4 0.4 0.8 0.25 0.25 Stencil apertures Solder mask ATSLP-12-1, -2, -3, -4, -5, -7-FP V01 Figure 13: Footprint Recommendation 4 8 2.1 Pin 1 marking 0.75 1.3 ATSLP-12-1, -2, -3, -4, -5, -7-TP V02 Figure 14: ATSLP-12-4 Carrier Tape Data Sheet 20 Revision 3.1 - 2016-05-11 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG