BGS110MN20 SP10T Diversity Antenna Switch with MIPI RFFE Interface Data Sheet Revision 3.1 - June 23, 2016 Power Management & Multimarket Edition June 23, 2016 Published by Infineon Technologies AG 81726 Munich, Germany c 2016 Infineon Technologies AG All Rights Reserved. LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY, CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT. THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION. INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND (INCLUDING WITHOUT LIMITATION WARRANTIES OF NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY) WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN THIS APPLICATION NOTE. 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BGS110MN20 Revision History Document No.: BGS110MN20_v31.pdf Revision History: 3.1 Previous Version: 3.0 Page Subjects (major changes since last revision) 01 NDA disclaimer removed Trademarks of Infineon Technologies AG AURIXTM , C166TM , CanPAKTM , CIPOSTM , CIPURSETM , CoolGaNTM , CoolMOSTM , CoolSETTM , CoolSiCTM , CORECONTROLTM , CROSSAVETM , DAVETM , DI-POLTM , DrBLADETM , EasyPIMTM , EconoBRIDGETM , EconoDUALTM , EconoPACKTM , EconoPIMTM , EiceDRIVERTM , eupecTM , FCOSTM , HITFETTM , HybridPACKTM , ISOFACETM , IsoPACKTM , i-WaferTM , MIPAQTM , ModSTACKTM , my-dTM , NovalithICTM , OmniTuneTM , OPTIGATM , OptiMOSTM , ORIGATM , POWERCODETM , PRIMARIONTM , PrimePACKTM , PrimeSTACKTM , PROFETTM , PRO-SILTM , RASICTM , REAL3TM , ReverSaveTM , SatRICTM , SIEGETTM , SIPMOSTM , SmartLEWISTM , SOLID FLASHTM , SPOCTM , TEMPFETTM , thinQ!TM , TRENCHSTOPTM , TriCoreTM . Other Trademarks Advance Design SystemTM (ADS) of Agilent Technologies, AMBATM , ARMTM , MULTI-ICETM , KEILTM , PRIMECELLTM , REALVIEWTM , THUMBTM , µVisionTM of ARM Limited, UK. ANSITM of American National Standards Institute. AUTOSARTM of AUTOSAR development partnership. BluetoothTM of Bluetooth SIG Inc. CAT-iqTM of DECT Forum. COLOSSUSTM , FirstGPSTM of Trimble Navigation Ltd. EMVTM of EMVCo, LLC (Visa Holdings Inc.). EPCOSTM of Epcos AG. FLEXGOTM of Microsoft Corporation. HYPERTERMINALTM of Hilgraeve Incorporated. MCSTM of Intel Corp. IECTM of Commission Electrotechnique Internationale. IrDATM of Infrared Data Association Corporation. ISOTM of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLABTM of MathWorks, Inc. MAXIMTM of Maxim Integrated Products, Inc. MICROTECTM , NUCLEUSTM of Mentor Graphics Corporation. MIPITM of MIPI Alliance, Inc. MIPSTM of MIPS Technologies, Inc., USA. muRataTM of MURATA MANUFACTURING CO., MICROWAVE OFFICETM (MWO) of Applied Wave Research Inc., OmniVisionTM of OmniVision Technologies, Inc. OpenwaveTM of Openwave Systems Inc. RED HATTM of Red Hat, Inc. RFMDTM of RF Micro Devices, Inc. SIRIUSTM of Sirius Satellite Radio Inc. SOLARISTM of Sun Microsystems, Inc. SPANSIONTM of Spansion LLC Ltd. SymbianTM of Symbian Software Limited. TAIYO YUDENTM of Taiyo Yuden Co. TEAKLITETM of CEVA, Inc. TEKTRONIXTM of Tektronix Inc. TOKOTM of TOKO KABUSHIKI KAISHA TA. UNIXTM of X/Open Company Limited. VERILOGTM , PALLADIUMTM of Cadence Design Systems, Inc. VLYNQTM of Texas Instruments Incorporated. VXWORKSTM , WIND RIVERTM of WIND RIVER SYSTEMS, INC. ZETEXTM of Diodes Zetex. Last Trademarks Update 2014-07-17 Data Sheet 3 Revision 3.1 - June 23, 2016 BGS110MN20 Contents Contents 1 Features 5 2 Product Description 5 3 Maximum Ratings 6 4 Operation Ranges 7 5 RF Characteristics 8 6 MIPI RFFE Specification 10 7 Pin Definition and Package Outline 14 List of Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 BGS110MN20 block diagram . . . . . . . . . . . MIPI to RF Time . . . . . . . . . . . . . . . . . . Received clock signal constraints . . . . . . . . . Bus active data receiver timing requirements . . Bus park cycle timing . . . . . . . . . . . . . . . Bus active data transmission timing specification Requirements for VIO-initiated reset . . . . . . . Application circuit . . . . . . . . . . . . . . . . . . Pin configuration (top view) . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . Marking . . . . . . . . . . . . . . . . . . . . . . . Land pattern and stencil mask . . . . . . . . . . Tape dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 11 12 12 13 13 15 15 16 16 17 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 7 7 7 8 8 9 9 9 10 11 13 14 List of Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Ordering information . . . . Maximum ratings, Table I . Maximum ratings, Table II . Thermal Resistance . . . . Operation ranges . . . . . . RF input power . . . . . . . RF characteristics . . . . . IMD2 Testcases . . . . . . IMD3 Testcases . . . . . . Switching Time . . . . . . . Register mapping . . . . . . MIPI RFFE operating timing Truth table . . . . . . . . . . Pin configuration . . . . . . Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Revision 3.1 - June 23, 2016 BGS110MN20 SP10T Diversity Antenna Switch 1 Features • Suitable for multi-mode WCDMA / LTE diversity applications • Ultra-low insertion loss and harmonics generation • 10 high-linearity, interchangeable RX ports • 0.1 to 2.7 GHz coverage • High port-to-port-isolation • Direct to battery supply enabled by large supply voltage range from 2.5 V to 5.5 V • Integrated MIPI RFFE interface supporting 1.2 and 1.8 V bus voltage • Software programmable MIPI RFFE USID • No decoupling capacitors required if no DC applied on RF lines • Small form factor 2.3 mm x 2.3 mm • 1 kV HBM ESD protection • RoHS and WEEE compliant package 2 Product Description The BGS110MN20 is a Single Pole Ten Throw (SP10T) Diversity Switch Module optimized for wireless applications up to 2.7 GHz. It is a perfect solution for multi-mode handsets based on quadband GSM, WCDMA and LTE. The switch module configuration is shown in Fig. 1. The module comes in a miniature TSNP package and comprises of a high power CMOS SP10T switch with integrated MIPI RFFE interface. No external DC blocking capacitors are required in typical applications as long as no DC is applied to any RF port. Table 1: Ordering Information Type Package Marking BGS110MN20 PG-TSNP-20-1 1AM2 Data Sheet 5 Revision 3.1 - June 23, 2016 BGS110MN20 ANT SP10T RX01 RX02 RX03 RX04 RX05 RX06 RX07 RX08 RX09 RX10 VDD VIO MIPI-RFFE ControlcInterface GND SCLK SDATA Figure 1: BGS110MN20 block diagram 3 Maximum Ratings Attention: stresses above the maximum ratings listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings. Exceeding only one of these values may cause irreversible damage to the integrated circuit. Table 2: Maximum Ratings, Table I at TA = 25 ◦ C, unless otherwise specified Parameter Symbol 1) Frequency range 2) Supply voltage Unit Min. Values Typ. Max. f 0.1 – – GHz VDD -0.5 – 6.0 V – C – C – Junction temperature Tj – – 125 ◦ Storage temperature range3) TSTG -55 – 150 ◦ PRF _RX – – 32 2) 2) RF input power at all RX ports dBm Note / Test Condition CW, all ports terminated with 50 Ohm ESD capability, CDM 3)4) VESDCDM −500 – +500 V All pins ESD capability, HBM 3)5) VESDHBM −1 – +1 kV Digital, digital versus RF −1 – +1 kV RF −8 – +8 kV ANT versus system GND, 3)6) ESD capability, system level VESDANT with 27 nH shunt inductor 1) Switch has no highpass response. There is also a DC connection between switched paths. The DC voltage at RF ports VRFDC has to be 0V. 2) Guaranteed by design. 3) Guaranteed by characterization. 4) Field-Induced Charged-Device Model JESD22-C101. Simulates charging/discharging events that occur in production equipment and processes. Potential for CDM ESD events occurs whenever there is metal-to-metal contact in manufacturing. 5) Human Body Model ANSI/ESDA/JEDEC JS-001-2012 (R = 1.5 kΩ, C = 100 pF). 6) IEC 61000-4-2 (R = 330 Ω, C = 150 pF), contact discharge. Data Sheet 6 Revision 3.1 - June 23, 2016 BGS110MN20 Table 3: Maximum Ratings, Table II at TA = 25 ◦ C, unless otherwise specified Parameter Symbol Maximum DC-voltage on RF ports VRFDC Values Min. Typ. Max. 0 – 0 Unit Note / Test Condition V No DC voltages allowed on 1) and RF ground RF ports 1) RFFE supply voltage 1) RFFE control voltage levels VIO -0.5 – 3.6 V – VSCLK , -0.7 – VIO +0.7 V – Unit Note / Test Condition K/W – Unit Note / Test Condition VSDATA 1) Guaranteed by design. Table 4: Thermal Resistance at TA = 25 ◦ C, unless otherwise specified Parameter Symbol Thermal resistance junction - solder- RthJS Values Min. Typ. Max. – 54 – 1) ing point 1) Guaranteed by design. 4 Operation Ranges Table 5: Operation Ranges Parameter Symbol Values Min. Typ. Max. TA -30 25 85 ◦ 1) VDD 2.5 3.5 5.5 V – 2) Supply current IDD – 80 200 µA – Supply current in user low ILP - 0.6 1 µA – ISD - 0.5 1 µA VDD =0V RFFE supply voltage1) VIO 1.1 1.8 1.95 V – RFFE input high voltage2)3) VIH 0.7*VIO – VIO V – VIL 0 – 0.3*VIO V – VOH 0.8*VIO – VIO V – VOL 0 – 0.2*VIO V – CCtrl – – 2 pF – IVIO – 15 – µA Idle state Ambient temperature Supply voltage C – 2) power mode Supply current in shutdown 1) state 2)3) RFFE input low voltage 2)3) RFFE output high voltage 2)3) RFFE output low voltage RFFE control input 4) capacitance RFFE supply current2) 1) Guaranteed by characterization. Guaranteed by test. 3) SCLK and SDATA 4) Guaranteed by design. 2) Data Sheet 7 Revision 3.1 - June 23, 2016 BGS110MN20 Table 6: RF Input Power Parameter Symbol RX ports (50Ω)1) 1) PRF _RX Values Min. Typ. Max. – – 27 Unit Note / Test Condition dBm TA = -30 ◦ C...+85 ◦ C Guaranteed by characterization. 5 RF Characteristics Table 7: RF Characteristics at TA = −30... + 85◦ C, PIN = 0 dBm, VDD = 2.5...5.5 V , Z0 =50Ω, unless otherwise specified Parameter Symbol Values Unit Note / Test Condition Min. Typ. Max. – 0.30 0.45 dB 0.1 to 1.0 GHz 1) – 0.40 0.60 dB 1.0 to 2.0 GHz 2) – 0.50 0.80 dB 2.0 to 2.7 GHz 2) – 0.30 0.45 dB 0.1 to 1.0 GHz 1) – 0.40 0.65 dB 1.0 to 2.0 GHz 2) – 0.60 0.85 dB 2.0 to 2.7 GHz 2) 18 25 – dB 0.1 to 1.0 GHz 2) 12 20 – dB 1.0 to 2.0 GHz 1) 10 16 – dB 2.0 to 2.7 GHz 2) 28 40 – dB 0.1 to 1.0 GHz 1) 22 35 – dB 1.0 to 2.0 GHz 2) 19 30 – dB 2.0 to 2.7 GHz 2) 3) Insertion Loss RX01-04, RX07-10 IL Insertion Loss3) RX05, RX06 IL Return Loss3) RX01-10 RL 3) Isolation (ANT-RX) RX01-10 ISO Intermodulation Distortion (UMTS Band 1, Band 5)2)3) 2nd order intermodulation IMD2 low – -105 -95 dBm IMT, US Cell (see Tab. 8) 3rd order intermodulation IMD3 – -110 -100 dBm IMT, US Cell (see Tab. 9) 2nd order intermodulation IMD2 high – -110 -100 dBm IMT, US Cell (see Tab. 8) 2)3) Harmonic Generation (UMTS Band 1, Band 5) H2 PHarm 80 90 – dBc 25 dBm, 50Ω, CW mode H3 PHarm 80 90 – dBc 25 dBm, 50Ω, CW mode 1) Guaranteed by test. 2) Guaranteed by characterization. 3) On application board with application circuit according to Fig. 8 Data Sheet 8 Revision 3.1 - June 23, 2016 BGS110MN20 Table 8: IMD2 Testcases Band CW tone 1 (MHz) CW tone 1 (dBm) IMT 1950 20 US Cell 835 20 CW tone 2 (MHz) 190 (IMD2 low) CW tone 2 (dBm) -15 4090 (IMD2 high) 45 (IMD2 low) -15 1715 (IMD2 high) Table 9: IMD3 Testcases Band CW tone 1 (MHz) CW tone 1 (dBm) CW tone 2 (MHz) CW tone 2 (dBm) IMT 1950 20 1760 -15 US Cell 835 20 790 -15 Table 10: Switching Time at TA = -30 ◦ C...+85 ◦ C, PIN = 0 dBm, Supply Voltage = 2.5 V...5.5 V, unless otherwise specified Parameter Symbol Values Unit Min. Typ. Max. tINT – 1.5 2 µs tPUP – 10 25 µs Note / Test Condition Switching Time MIPI to RF time1) 1) Power up settling time 1) 50 % last SCLK falling edge to 90 % ON, see Fig. 2 After power down mode Guaranteed by characterization. SDATA TINT SCLK 90% RF Signal Figure 2: MIPI to RF Time Data Sheet 9 Revision 3.1 - June 23, 2016 BGS110MN20 6 MIPI RFFE Specification Supported MIPI Functions The MIPI RFFE interface supports following functions: • Register write command sequence • Register read command sequence • Register 0 write command sequence • Programmable USID • Trigger function All sequences are implemented according to the ’MIPI Alliance Specification for RF Front-End Control Interface’ document version 1.10 - 26. July 2011. By default the device goes into low power mode after power on. Table 11: Register Mapping Register Address Register Name 0x0000 REGISTER_0 7:0 MODE_CTRL 0x001C PM_TRIG 7:6 5 4 3 2 1 0 PWR_MODE TRIGGER_MASK_2 TRIGGER_MASK_1 TRIGGER_MASK_0 TRIGGER_2 TRIGGER_1 TRIGGER_0 0x001D PRODUCT_ID 7:0 0x001E MANUFACTURER_ID 7:0 0x001F 0x001B Data Sheet Data Bits Function Default Broadcast Support Trigger Support R/W 00000000 No Yes R/W 10 0 0 0 0 0 0 Yes No No No Yes Yes Yes No No No No No No No R/W PRODUCT_ID 10000101 No No R MANUFACTURER_ID [7:0] 00011010 No No R MAN_USID 7:6 5:4 3:0 SPARE MANUFACTURER_ID [9:8] USID 00 01 1010 No No R/W GROUP_SID 7:4 3:0 RESERVED GROUP_SID 0 0 No No R/W 10 Revision 3.1 - June 23, 2016 BGS110MN20 Table 12: MIPI RFFE Operating Timing1) Parameter Symbol SCLK Frequency FSCLK SCLK Period TSCLK SCLK Low Period TSCLKIL SCLK High Period TSCLKIH SDATA Setup Time TS SDATA Hold Time TH SDATA Release Time TSDATAZ Values Unit Note / Test Condition Min. Typ. Max. 0.032 – 26 MHz Full speed2) 0.032 – 13 MHz Half speed2) 0.038 – 32 µs Full speed 0.077 – 32 µs Half speed 11.25 – – ns Full speed, see Fig. 3 24 – – ns Half speed, see Fig. 3 11.25 – – ns Full speed, see Fig. 3 24 – – ns Half speed, see Fig. 3 1 – – ns Full speed, see Fig. 4 2 – – ns Half speed, see Fig. 4 5 – – ns Full speed, see Fig. 4 5 – – ns Half speed, see Fig. 4 – – 10 ns Full speed, see Fig. 5 – – 18 ns Half speed, see Fig. 5 – – – – 10.25 22 ns ns Full speed, see Fig. 6 Half speed, see Fig. 6 2.1 – 6.5 ns Full speed, see Fig. 6 2.1 – 10 ns Half speed, see Fig. 6 Time for Data Output TD SDATA Rise/Fall Time TSDATAOTR VIO Rise Time TVIO-R 10 – 450 µs See Fig. 7 VIO Reset Time TVIO-RST 10 – – µs See Fig. 7 Reset Delay Time TSIGOL 0.12 – – µs See Fig. 7 1) Guaranteed by design unless otherwise specified. 2) Guaranteed by characterization. TSCLKIH TSCLKIL VTPmax VTNmin Figure 3: Received clock signal constraints Data Sheet 11 Revision 3.1 - June 23, 2016 BGS110MN20 VTPmax SCLK VTPmin TS TH TS TH VTPmax SDATA VTPmin Figure 4: Bus active data receiver timing requirements VTPmax SCLK VTNmin TSDATAZ VOHmin SDATA VOLmax Bus Park Cycle Signal driven Signal not driven, pull down only TSDATAZ is measured from SCLK VTN level for a device receiving SCLK and driving SDATA lines Figure 5: Bus park cycle timing Data Sheet 12 Revision 3.1 - June 23, 2016 BGS110MN20 VTPmax SCLK VTPmin TD TD TSDATAOTR TSDATAOTR VOHmin SDATA VOLmax Figure 6: Bus active data transmission timing specification TSIGOL VIO (V) Not To Scale VIOmax VIOmin SCLK & SDATA must be held at low level from deassertion of VIO until the end of TSIGOL TVIO-RST All slave registers set/reset to manufacturer‘s defaults TVIO-R VVIO-RST (0.2V) Time Figure 7: Requirements for VIO-initiated reset Table 13: Modes of Operation (Truth Table) REGISTER_0 Bits State Mode D7 D6 D5 D4 D3 D2 D1 D0 1 Isolation x 0 0 0 0 0 0 0 2 RX01 x 0 0 0 0 0 1 0 3 RX02 x 0 0 0 1 0 1 0 4 RX03 x 0 0 0 1 1 1 0 5 RX04 x 0 0 0 1 0 1 1 6 RX05 x 0 0 0 0 0 0 1 7 RX06 x 0 0 0 1 0 0 1 8 RX07 x 0 0 0 0 1 1 0 9 RX08 x 0 0 0 0 1 0 0 10 RX09 x 0 0 0 1 1 0 0 11 RX10 x 0 0 0 1 0 0 0 Data Sheet 13 Revision 3.1 - June 23, 2016 BGS110MN20 7 Pin Definition and Package Outline Table 14: Pin Configuration No. Name Pin Type 0 GND GND 1 NC 2 RX10 I/O RX port 10 3 RX09 I/O RX port 9 4 RX08 I/O RX port 8 5 RX07 I/O RX port 7 6 RX06 I/O RX port 6 7 GND GND RF ground 8 GND GND RF ground 9 ANT I/O Antenna port 10 GND GND RF ground 11 RX05 I/O RX port 5 12 RX04 I/O RX port 4 13 RX03 I/O RX port 3 14 RX02 I/O RX port 2 15 RX01 I/O RX port 1 16 GND GND RF ground 17 VDD PWR VDD supply 18 VIO PWR MIPI RFFE supply 19 SDATA I/O MIPI RFFE data 20 SCLK I MIPI RFFE clock Data Sheet Buffer Type Function RF ground; die pad Not connected 14 Revision 3.1 - June 23, 2016 BGS110MN20 ANT BGS110MN20 SP10T 27nH VDD 15 14 13 RX4 RX3 16 RX2 GND RX1 Figure 8: Application circuit 11 RX5 17 10 GND VIO 18 9 ANT SDATA 19 8 GND SCLK 20 7 GND 1 2 3 4 5 6 NC RX10 RX9 RX8 RX7 RX6 12 Figure 9: Pin configuration (top view) Data Sheet 15 Revision 3.1 - June 23, 2016 BGS110MN20 Bottom view 0.73 ±0.04 2.3 ±0.05 A 0.2 ±0.025 20x 0.02 MAX. STANDOFF 0.1 A 1.4 ±0.025 12 13 14 0.1 B Top view 0.1 A 15 16 9 18 8 19 7 Pin 1 marking 5 4 3 2 0.4 1 0.1 B 20 6 B 0.2 ±0.025 20x 17 1.4 ±0.025 10 0.2 x 45° 0.4 2.3 ±0.05 5 x 0.4 = 2 11 5 x 0.4 = 2 Figure 10: Package outline 123456 Type code Date code (YYWW) Pin 1 marking Figure 11: Marking Data Sheet 16 Revision 3.1 - June 23, 2016 BGS110MN20 20x 0.25 Optional solder mask dam 20x 0.25 1.4 0.4 0.4 0.4 0.2 0.2 1 1 Copper 1 0.2 1.4 1 0.2 1.4 0.4 0.25 0.25 (stencil thickness max. 100 µm) Stencil apertures Solder mask Figure 12: Land pattern and stencil mask 4 0.95 8 2.7 Pin 1 marking 2.7 Figure 13: Tape dimensions Data Sheet 17 Revision 3.1 - June 23, 2016 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG