LSIs for DAB MN66710 Full-Function DAB Receiver LSI ■ Overview The MN66710 is a single-chip digital signal processing LSI for a DAB (digital audio broadcast) receiver, including OFDM demodulation, service selection, error correction, and MPEG audio decoding. The MN66710 conforms to the European DAB standard (ETS 300 401). Since the MN66710 includes an on-chip A/D converter for the IF signal input, it can be directly input the 3.072 MHz center frequency analog IF signal output from the DAB high-frequency circuit. A DAB receiver is implemented easily by combining MN66710 with a small number of additional components, in particular, 4M DRAMs for working memory, audio D/A converters, microcontrollers, and etc. ■ Features • The DAB signal-processing block is integrated on a single chip. (with external 4M DRAMs) • Supports all of DAB modes I, II, III, and IV. • Achieves a processing data rate of up to 1.536 Mbps. • Up to 4 MSC sub-channels can be selected. • MPEG audio decoder (Also supports LSF.) • Supports the standard audio D/A converter interface. • Digital audio output unit conforming EIAJ CP-1201 (External driver required.) • RDI output and dedicated audio RDI input units (For high capacity mode only.) • F-PAD and X-PAD extraction function • AIC support function provided in hardware. • Supports multiplex restructuring with no interruption of the audio signal. • TII decoding function (basic mode) • Low supply voltage: 3.3 V±0.3 V • Low power: Under 500 mW ■ Applications • DAB (digital audio broadcast) receivers Publication date: November 2001 SDC00041BEM 1 MN66710 ■ Block Diagram RAD0 to RAD9 RDT0 to RDT3 ADVRT ADIN ADC I/Q Gen. OFDM De-Interleave ADVRB NRAMOE NRRAS NRCAS NRAMWE IQMOD UEP/EEP NULDET FSYO MCLK24 NRST CTLLR FERF3 DSP Core (Sync/AFC/MPEG Dec.) CTLDAT CTLCLK FDAT3 Timing Gen. Viterbi Dec. FWFIC AFC CIR I/F FW1 to FW4 FD3EN CIRSYN DSPMON0 to DSPMON6 DSPMNEN RDIOUT RDI I/F MPUSYNC SDAT MPUTX MPU I/F Audio I/F SCLK DAC I/F MPUCLK SLRCK SMCK NPADRDY AUXDAT TEST0 to TEST3 2 RDIIN RDIU0 to RDIU5 MPUMOD MPURX FCLK3 DAI I/F SDC00041BEM DAOUT MN66710 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 DSPMON1 DSPMON0 VSS3 RDT3 RDT2 RDT0 RDT1 NRAMWE NRRAS RAD9 NRCAS NRAMOE RAD8 RAD7 VDD2 VSS2 RAD0 RAD1 RAD2 RAD3 RAD6 ■ Pin Arrangement 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 RAD5 RAD4 FDAT3 FERF3 FCLK3 FWFIC FW1 FW2 FW3 FW4 FD3EN VDD1 VSS1 RDIOUT RDIU5 RDIU4 RDIU3 RDIIN RDIU2 RDIU1 RDIU0 MPUSYNC NPADRDY MPUCLK MPURX MPUTX MPUMOD TEST0 TEST1 TEST2 TEST3 NRST VSS0 VDD0 MCLK24 MCLKO DAOUT AUXDAT SMCK SLRCK SCLK SDAT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DSPMON2 DSPMON3 DSPMON4 DSPMON5 DSPMON6 DSPMNEN CIRSYN CTLLR CTLCLK CTLDAT VSS4 VDD3 FSYO NULDET AVSS ADVRB ADIN ADVRT AVDD VREF IQMOD (TOP VIEW) Note) Do not leave any of the VDD and VSS pins open. Connect the TEST0 to TEST3 pin to VSS. SDC00041BEM 3 MN66710 ■ Pin Descriptions Pin No. Pin Name I/O Descriptions 1 MPUSYNC O Microcontroller operation reference signal Timing signal with a 24 ms period 2 NPADRDY O PAD data ready signal Indicates that the PAD register can be read 3 MPUCLK I Microcontroller interface data clock 4 MPURX I Microcontroller interface reception data 5 MPUTX O Microcontroller interface transmission data 6 MPUMOD I Microcontroller interface mode 7 TEST0 I Test mode setup Normally connect to VSS 8 TEST1 I Test mode setup Normally connect to VSS 9 TEST2 I Test mode setup Normally connect to VSS 10 TEST3 I Test mode setup Normally connect to VSS 11 NRST I Master reset input The IC is reset when this input is set low 12 VSS0 Digital system ground 13 VDD0 Digital system power supply 14 MCLK24 I Master clock input (24.576 MHz) 15 MCLKO O Master clock oscillator circuit output 16 DAOUT O SPDIF digital audio interface output 17 AUXDAT I Audio A/D converter serial data input 18 SMCK O Audio A/D and D/A converter master clock Outputs a 256 fs clock 19 SLRCK O Audio A/D and D/A converter left/right clock 20 SCLK O Audio A/D and D/A converter serial clock output 21 SDAT O Audio D/A converter serial data output Audio output D/A converter connection 22 RDIU0 O Auxiliary outputs for RDI expansion Normally left open 23 RDIU1 O Auxiliary outputs for RDI expansion Normally left open 24 RDIU2 O Auxiliary outputs for RDI expansion Normally left open 25 RDIIN I RDI input RDI back channel (audio only) 26 RDIU3 O Auxiliary outputs for RDI expansion Normally left open 27 RDIU4 O Auxiliary outputs for RDI expansion Normally left open 28 RDIU5 I Auxiliary inputs for RDI expansion Normally connect to VSS 29 RDIOUT O RDI output For high capacity mode only 30 VSS1 Digital system ground 31 VDD1 Digital system power supply 32 FD3EN I General-purpose data output enable Output enable for FDAT3, FERF3, and FCLK3 33 FW4 O General-purpose output window 4 Window for sub-channel 4 34 FW3 O General-purpose output window 3 Window for sub-channel 3 35 FW2 O General-purpose output window 2 Window for sub-channel 2 4 SDC00041BEM Note For use with a crystal oscillator element Auxiliary input A/D converter connection MN66710 ■ Pin Descriptions (continued) Pin No. Pin Name I/O Descriptions 36 FW1 O General-purpose output window 1 Window for sub-channel 1 (audio) 37 FWFIC O General-purpose output window 0 FIC window 38 FCLK3 O General-purpose data output clock 1.536 MHz continuous clock 39 FERF3 O General-purpose data output error flag Flag that indicates Viterbi-corrected bits 40 FDAT3 O General-purpose data output data 41 RAD4 O External DRAM address, bit 4 For connecting external DRAM 42 RAD5 O External DRAM address, bit 5 For connecting external DRAM 43 RAD6 O External DRAM address, bit 6 For connecting external DRAM 44 RAD3 O External DRAM address, bit 3 For connecting external DRAM 45 RAD2 O External DRAM address, bit 2 For connecting external DRAM 46 RAD1 O External DRAM address, bit 1 For connecting external DRAM 47 RAD0 O External DRAM address, bit 0 For connecting external DRAM 48 VSS2 Digital system ground 49 VDD2 Digital system power supply 50 RAD7 O External DRAM address, bit 7 For connecting external DRAM 51 RAD8 O External DRAM address, bit 8 For connecting external DRAM 52 NRAMOE O External DRAM output enable For connecting external DRAM 53 NRCAS O External DRAM column address strobe For connecting external DRAM 54 RAD9 O External DRAM address, bit 9 For connecting external DRAM 55 NRRAS O External DRAM row address strobe For connecting external DRAM 56 NRAMWE O External DRAM write enable For connecting external DRAM 57 RDT1 I/O External DRAM data, bit 1 For connecting external DRAM 58 RDT0 I/O External DRAM data, bit 0 For connecting external DRAM 59 RDT2 I/O External DRAM data, bit 2 For connecting external DRAM 60 RDT3 I/O External DRAM data, bit 3 For connecting external DRAM 61 VSS3 Digital system ground 62 DSPMON0 O DSP monitor, bit 0 Normally left open 63 DSPMON1 O DSP monitor, bit 1 Normally left open 64 DSPMON2 O DSP monitor, bit 2 Normally left open 65 DSPMON3 O DSP monitor, bit 3 Normally left open 66 DSPMON4 O DSP monitor, bit 4 Normally left open 67 DSPMON5 O DSP monitor, bit 5 Normally left open 68 DSPMON6 O DSP monitor, bit 6 Normally left open 69 DSPMNEN I DSP monitor output enable A low level disables DSP monitor output 70 CIRSYN O CIR display cycle signal CIR monitor display trigger signal 71 CTLLR O AFC/CIR D/A converter left/right clock For AFC control and CIR monitor display 72 CTLCLK O AFC/CIR D/A converter clock SDC00041BEM Note For AFC control and CIR monitor display 5 MN66710 ■ Pin Descriptions (continued) Pin No. Pin Name I/O Descriptions Note 73 CTLDAT O AFC/CIR D/A converter data 74 VSS4 Digital system ground 75 VDD3 Digital system power supply 76 FSYO O Frame sync signal output 77 NULDET I Null symbol detection signal input 78 AVSS Analog system ground 79 ADVRB A/D converter low side reference voltage 80 ADIN I 81 ADVRT A/D converter high side reference voltage 82 AVDD Analog system power supply 83 VREF Reference supply for 5 V input pads 84 IQMOD I For AFC control and CIR monitor display A/D converter analog input Digital IQ generation switching input Normally connect to VDD ■ Electrical Characteristics 1. Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Rating Unit Supply voltage (digital) VDD − 0.3 to +4.6 V Supply voltage (analog) AVDD − 0.3 to +4.6 V *1 VREF5 − 0.3 to +5.7 V VI − 0.3 to VDD+0.3 V 5 V reference voltage Input pin voltage (except for the type A and type B) VI5 − 0.3 to +6.0 Input pin voltage (type B) VI5 − 0.3 to VREF5+0.3 Output pin voltage (except for the type B) VO − 0.3 to VDD+0.3 Output pin voltage (type B) VO5 − 0.3 to VREF5+0.3 Output current (type HL1) IO ±3 mA Output current (type HL2) IO ±6 mA Output current (type HL4) IO ±12 mA Output current (type HL8) IO ±24 mA Power dissipation PD 1030 mW Storage temperature Tstg −55 to +125 °C Input pin voltage (type A) 6 SDC00041BEM *2 V *2 V V *2 V MN66710 ■ Electrical Characteristics (continued) 1. Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V (continued) Note) 1. *1 : The power supply rise and fall sequences must meet the stipulations shown below. VDD 0V t3-5 t5-3 VREF5 0 V The times t3-5 and t5-3 must be non-negative. VDD and VREF5 should change smoothly. *2 : If VDD ≤ 1.4 V: − 0.3 V to +4.6 V 2. Type A pins : RDIU5, MPURX, RDIIN, MPUCLK, MPUMOD, NULDET Type B pins : RAD9, RDT0 to RDT3, FSYO, CTLLR, DAOUT, NRCAS, NRRAS, CIRSYN, CTLCLK, CTLDAT, DSPMON0 to DSPMON6, NRAMOE, NRAMWE, DSPMNEN Type HL1 pins : FW1 to FW4, FCLK3, FDAT3, FERF3, FWFIC, DSPMON0 to DSPMON6, DSPMNEN Type HL2 pins : RDIU0 to RDIU4 Type HL4 pins : FSYO, SCLK, SDAT, SMCK, CTLLR, DAOUT, MPUTX, SLRCK, AUXDAT, CIRSYN, CTLCLK, CTLDAT, RDIOUT, MPUSYNC, NPADRDY Type HL8 pins : RAD0 to RAD9, RDT0 to RDT3, NRCAS, NRRAS, NRAMOE, NRAMWE 3. The absolute maximum ratings are limiting values under which the chip will not be destroyed. Operation is not guaranteed within these ranges. 4. External power and ground levels must be connected directly to all of the VDD and VSS pins respectively. 5. Connect the MINTEST pin to ground. 6. When used in car audio equipment, insert bypass capacitors (recommended value: 0.1 µF) between VDD and VSS. 2. Recommended Operating Conditions at VSS = 0 V Parameter Symbol Conditions Min Typ Max Unit Supply voltage (digital) VDD 3.0 3.3 3.6 V Supply voltage (analog) AVDD 3.0 3.3 3.6 V 5 V reference voltage VREF5 4.75 5.0 5.25 V Ambient temperature Ta −30 85 °C Input rise time tr 0 100 ns Input fall time tf 0 100 ns Oscillator frequency fOSC1 24.576 MHz Xtal 24.576 MHz Recommended external capacitor value CXI7 VDD = 3.3 V 47 pF CXO7 Built-in feedback resistor 47 pF XI XO CXI CXO Note) 1. Since the oscillator characteristics depend on the oscillator element itself, external capacitances, and other factors, consult the manufacturer of the oscillator element to determine the circuit constants. 2. Apply 5 V to 5 V reference voltage if 5 V inputs are used. This has no steady-state current consumption. Do not apply the 5 V if the 3.3 V is not being applied to the LSI. 3.3 V may be supplied to this pin if only a single 3.3 V power supply is used. SDC00041BEM 7 MN66710 ■ Electrical Characteristics (continued) 3. DC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = −30°C to +85°C Parameter Operating supply current Symbol Conditions Min Typ Max Unit IDDO VI = VDD or VSS f = 24.576 MHz VDD = 3.3 V, outputs open 110 200 mA Oscillator circuit: MCLK24, MCLKO High-level input voltage VIH VDD × 0.8 VDD V Low-level input voltage VIL 0 VDD × 0.2 V Internal feedback resistor Rf7 313 940 2820 kΩ VI = VDD or VSS VDD = 3.3 V CMOS level input pins: FD3EN, TEST0, TEST1, TEST2, IQMOD High-level input voltage VIH VDD × 0.8 VDD V Low-level input voltage VIL 0 VDD × 0.2 V Input leakage current ILI ±5 µA 1.85 VDD × 0.8 V VDD × 0.2 1.45 ±5 µA VI = VDD or VSS CMOS level input pin with Schmitt trigger circuit: NRST Input threshold voltage VT+ VDD = 3.0 V to 3.6 V VT− Input leakage current ILI VI = VDD or VSS CMOS level input pin with built-in pull-down resistor: TEST3 High-level input voltage VIH VDD × 0.85 VDD V Low-level input voltage VIL 0 VDD × 0.15 V Pull-down resistor RIL VI = VDD 10 30 90 kΩ Input leakage current ILI VI = VSS ±10 µA TTL level input pins: RDIU5, MPURX, RDIIN, MPUCLK, MPUMOD, NULDET High-level input voltage VIH 2.2 5.25 V Low-level input voltage VIL 0 0.6 V Input leakage current ILI ±10 µA VI = 5.25 V or VSS Push-pull output pins: FW1 to FW4, FCLK3, FDAT3, FERF3, FWFIC High-level output voltage VOH IOH = −1.0 mA VI = VDD or VSS VDD − 0.5 V Low-level output voltage VOL IOL = 1.0 mA VI = VDD or VSS 0.4 V Push-pull output pins: MPUTX, MPUSYNC, NPADRDY 8 High-level output voltage VOH IOH = −4.0 mA VI = VDD or VSS VDD − 0.5 V Low-level output voltage VOL IOL = 4.0 mA VI = VDD or VSS 0.4 V SDC00041BEM MN66710 ■ Electrical Characteristics (continued) 3. DC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = −30°C to +85°C (continued) Parameter Symbol Conditions Min Typ Max Unit Push-pull output pins: RAD0 to RAD8 High-level output voltage VOH IOH = −8.0 mA VI = VDD or VSS VDD − 0.5 V Low-level output voltage VOL IOL = 8.0 mA VI = VDD or VSS 0.4 V VDD × 0.8 VDD V CMOS level I/O pins: RDIU0 to RDIU4 High-level input voltage VIH Low-level input voltage VIL 0 VDD × 0.2 V High-level output voltage VOH IOH = −2.0 mA VI = VDD or VSS VDD − 0.5 V Low-level output voltage VOL IOL = 2.0 mA VI = VDD or VSS 0.4 V Output leakage current ILO VO = High-impedance state VI = VDD or VSS VO = VDD or VSS ±5 µA CMOS level I/O pins: SCLK, SDAT, SMCK, SLRCK, AUXDAT, RDIOUT High-level input voltage VIH VDD × 0.8 VDD V Low-level input voltage VIL 0 VDD × 0.2 V High-level output voltage VOH IOH = −4.0 mA VI = VDD or VSS VDD − 0.5 V Low-level output voltage VOL IOL = 4.0 mA VI = VDD or VSS 0.4 V Output leakage current ILO VO = High-impedance state VI = VDD or VSS VO = VDD or VSS ±5 µA TTL level I/O pins: DSPMON0 to DSPMON6, DSPMNEN High-level input voltage VIH 2.2 VREF5 V Low-level input voltage VIL 0 0.6 V High-level output voltage VOH IOH = −1.0 mA VI = VDD or VSS 2.4 V Low-level output voltage VOL IOL = 1.0 mA VI = VDD or VSS 0.4 V Output leakage current ILO VO = High-impedance state VI = 5.25 V or VSS VO = 5.25 V or VSS ±10 µA SDC00041BEM 9 MN66710 ■ Electrical Characteristics (continued) 3. DC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = −30°C to +85°C (continued) Parameter Symbol Conditions Min Typ Max Unit TTL level I/O pins: FSYO, CTLLR, DAOUT, CIRSYN, CTLCLK, CTLDAT High-level input voltage VIH 2.2 VREF5 V Low-level input voltage VIL 0 0.6 V High-level output voltage VOH IOH = −4.0 mA VI = VDD or VSS 2.4 V Low-level output voltage VOL IOL = 4.0 mA VI = VDD or VSS 0.4 V Output leakage current ILO VO = High-impedance state VI = 5.25 V or VSS VO = 5.25 V or VSS ±10 µA TTL level I/O pins: RAD9, RDT0 to RDT3, NRCAS, NRRAS, NRAMOE, NRAMWE High-level input voltage VIH 2.2 VREF5 V Low-level input voltage VIL 0 0.6 V High-level output voltage VOH IOH = −8.0 mA VI = VDD or VSS 2.4 V Low-level output voltage VOL IOL = 8.0 mA VI = VDD or VSS 0.4 V Output leakage current ILO VO = High-impedance state VI = 5.25 V or VSS VO = 5.25 V or VSS ±10 µA 4. AC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = −30°C to +85°C Parameter Symbol Conditions Min Typ Max Unit 36 40.69 45 ns Clock input MCLK24 clock period tMCLK See figure 1. MCLK24 high-level period tMCLKH 18 ns MCLK24 low-level period tMCLKL 15 ns 4×T ns Microcontroller interface MPUCLK clock period tMPUC MPUCLK high-level period tMPUCH 72 ns MPUCLK low-level period tMPUCL 60 ns See figure 2. Note) The symbol T in the table refers to the MCLK24 period, tMCLK. 10 SDC00041BEM MN66710 ■ Electrical Characteristics (continued) 4. AC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = −30°C to +85°C (continued) Parameter Symbol Conditions Min Typ Max Unit 0 ns Microcontroller interface (continued) MPUMOD setup time tMODS See figure 3,4. MPUMOD hold time tMODH 2×T ns MPURX setup time tRXS 0 ns MPURX hold time tRXH 2×T ns MPUTX delay time tTXD 2×T ns Write disabled period 1 tWRNG1 6×T ns Write disabled period 2 tWRNG2 4×T 8×T ns Read disabled period tRDNG 4×T 8×T ns DRAM interface 120 ns tRP 37.5 40 ns RAS pulse width tRAS 75 80 ns CAS pulse width tCAS 17.5 20 ns Row address setup time tASR 10 ns Row address hold time tRAH 17.5 ns Column address setup time tASC 10 ns Column address hold time tCAH 17.5 ns RAS/CAS delay time tRCD 35 45 ns RAS column address delay time tRAD 17.5 25 ns RAS hold time tRSH 35 ns CAS hold time tCSH 60 ns CAS/RAS precharge time tCRP 37.5 40 ns OE/data input delay time tODD 20 ns Write command setup time tWCS 40 ns Write command hold time tWCH 15 ns Data input setup time tDS 12.5 ns Data input hold time tDH 17.5 ns Fast page mode cycle time tPC 40 ns Fast page mode precharge time tCP 15 17.5 ns Random read/write cycle time tRC RAS precharge time See figure 5. Note) The symbol T in the table refers to the MCLK24 period, tMCLK. SDC00041BEM 11 MN66710 ■ Electrical Characteristics (continued) 4. AC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = −30°C to +85°C (continued) Parameter Symbol Conditions Min Typ Max Unit 7 32.5 ns DRAM interface (continued) Master clock/RAS delay time t1 See figure 5. Master clock/CAS delay time t2 7 32.5 ns Master clock/address delay time t3 27.5 57.5 ns Master clock/WE delay time t4 7 32.5 ns Master clock/data input delay time t5 27.5 57.5 ns Master clock/OE delay time t6 7 30 ns Data output setup time t7 0 ns Data output hold time t8 20 ns 72 81.38 ns Audio interface SMCK clock period tSMCK See figure 6. SMCK high-level period tSMCKH 31 ns SMCK low-level period tSMCKL 31 ns ns SCLK period tSCLK See figure 7. 288 325.52 SCLK high-level period tSCLKH 100 ns SCLK low-level period tSCLKL 100 ns SCLK delay time tSCLKD 41 ns SDAT delay time tSDATD 40 ns SLRCK delay time tSLRD 41 ns AUXDAT setup time tAUXS 8.5 ns ns General-purpose data outputs FCLK3 clock period tFCLK FCLK3 high-level period tFCLKH 200 ns FCLK3 low-level period tFCLKL 200 ns FCLK3 delay time tFCLKD 15.5 ns FDAT3 delay time tFDATD 21.5 ns FERF3 delay time tFERFD 21 ns tFWD 18 ns FWFIC and FW1:4 delay time 12 See figure 8. SDC00041BEM 576 651.04 MN66710 ■ Electrical Characteristics (continued) 4. AC Characteristics at VDD = 3.0 V to 3.6 V, VREF5 = 4.75 V to 5.25 V, VSS = 0.00 V, fTEST = 24.576 MHz, Ta = −30°C to +85°C (continued) Parameter Symbol Conditions Min Typ Max Unit 576 651.04 ns CIR/AFC Output Timing CTLCLK clock period tCCLK See figure 9. CTLCLK high-level period tCCLKH 200 ns CTLCLK low-level period tCCLKL 200 ns CIRSYN delay time tCIRD 241 ns CTLCLK delay time tCCLKD 35 ns CTLDAT delay time tCDATD 35 ns CTLLR delay time tCLRD 37 ns 5. A/D Converter Characteristics at VDD = 3.30 V, VREF5 = 5.00 V, VSS = 0.00 V, Ta = 25°C Parameter Resolution Nonlinearity error Differential nonlinearity error Symbol Conditions RES Min Typ Max Unit 8 bit NLE1 fMSPCK = 24.576 MHz VRT = 2.6 V, VRB = 0.6 V ±1.5 ±2.0 LSB DNLE1 fMSPCK = 24.576 MHz VRT = 2.6 V, VRB = 0.6 V ±0.5 ±1.5 LSB tMCLK tMCLKL tMCLKH MCLK24 Figure 1. Clock input tMPUC tMPUCH tMPUCL MPUCLK Figure 2. Microcontroller interface (data clock) SDC00041BEM 13 14 SDC00041BEM MPUTX MPURX MPUMOD MPUCLK MPUTX MPURX MPUMOD MPUCLK tMODS tMODS b7 b7 unknown b6 tRXH tRXS b6 tRXH tRXS tWRNG1 unknown b7 b6 tRXS tRXH b0 b7 tTXD b6 Figure 4. Microcontroller interface (data read time) b0 tMODH b0 Figure 3. Microcontroller interface (data write time) b0 tMODH tRDNG tWRNG2 b7 b7 b6 b6 b0 MN66710 ■ Electrical Characteristics (continued) SDC00041BEM MCLK24 NRAMOE RDT3-RDT0 NRAMWE RAD9-RAD0 NRCAS NRRAS t3 t1 row t2 tRAD tCSH t7 t8 row dataout column tRAS tRC tASR tRAH tCRP dataout column tRCD tRSH tRP Read cycle t4 col. tRSH Figure 5. DRAM interface t6 col. tPC datain datain datain datain tODD t5 col. tDH tDS col. tWCS row tCAS tCP tCAH tASC tRCD tCSH Fast page mode early write cycle tWCH row dataout column Read cycle row RAS only refresh cycle row MN66710 ■ Electrical Characteristics (continued) 15 MN66710 ■ Electrical Characteristics (continued) tSMCK tSMCKH tSMCKL SMCK Figure 6. Audio interface MCLK24 tAUXS AUXDAT tSCLKD tSCLK tSCLKH tSCLKL SCLK tSDATD SDAT tSLRD SLRCK Figure 7. Audio output timing 16 SDC00041BEM MN66710 ■ Electrical Characteristics (continued) MCLK24 tFCLK tFCLKD tFCLKH tFCLKL FCLK3 tFDATD FDAT3 tFERFD FERF3 tFWD FWFIC FW1 to FW4 Figure 8. General-purpose data output MCLK24 tCIRD CIRSYN tCCLKD CTLCLK tCCLK tCCLKH tCCLKL tCDATD CTLDAT tCLRD CTLLR Figure 9. CIR/AFC output timing SDC00041BEM 17 MN66710 ■ Package Dimensions (Unit: mm) • QFP084-P-1818E (Lead-free package) 22.90±0.20 18.00±0.10 43 63 42 84 22 Seating plane 18 0.15 SDC00041BEM (2.45) 0.15±0.05 21 0.35±0.05 2.45±0.20 0.80 0.10±0.10 1 (1.00) 2.85 max. 18.00±0.10 22.90±0.20 (1.00) 64 1.30±0.20 0° to 10° Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. It does not constitute the warranting of industrial property, the granting of relative rights, or the granting of any license. (3) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: • Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. • Any applications other than the standard applications intended. (4) The products and product specifications described in this material are subject to change without notice for reasons of modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (5) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, redundant design is recommended, so that such equipment may not violate relevant laws or regulations because of the function of our products. (6) When using products for which dry packing is required, observe the conditions (including shelf life and after-unpacking standby time) agreed upon when specification sheets are individually exchanged. (7) No part of this material may be reprinted or reproduced by any means without written permission from our company. Please read the following notes before using the datasheets A. These materials are intended as a reference to assist customers with the selection of Panasonic semiconductor products best suited to their applications. Due to modification or other reasons, any information contained in this material, such as available product types, technical data, and so on, is subject to change without notice. Customers are advised to contact our semiconductor sales office and obtain the latest information before starting precise technical research and/or purchasing activities. B. Panasonic is endeavoring to continually improve the quality and reliability of these materials but there is always the possibility that further rectifications will be required in the future. Therefore, Panasonic will not assume any liability for any damages arising from any errors etc. that may appear in this material. C. These materials are solely intended for a customer's individual use. Therefore, without the prior written approval of Panasonic, any other use such as reproducing, selling, or distributing this material to a third party, via the Internet or in any other way, is prohibited. 2001 MAR