DATA SHEET Part No. MN662793 Package Code No. LQFP100-P-1414 SEMICONDUCTOR COMPANY MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. Publication date: December. 2004 SDD00031AEM 1 MN662793 Contents Overview ………………………………………………….…………………………………………………………. 3 Features ………………………………………………….…………………………………………………………. 3 Applications .…………………………………………….…………………………………………………………. 4 Application Circuit ……………………………………….…………………………………………………………. 5 Block Diagram ………………………………………….…………………………………………………………. 6 Pin Assignment ………………………………………….…………………………………………………………. 7 Pin Descriptions …………………………………………….………………………………………………………. 8 Absolute Maximum Ratings …………………………….…………………………………………………………. 12 Operating Supply Voltage Range……………………….…………………………………………………………. 13 Electrical Characteristics …………………………….……………………………………………………………. 15 SDD00031AEM 2 MN662793 MN662793 Silicon CMOS IC Overview Features (Optical Servo) y Focus, tracking, and traverse servos y Automatic adjustment functions (Focus / Tracking gain, Focus / Tracking offset, Focus / Tracking balance) y Provided with a countermeasure for dropout y Provided with an anti-shock detection function y Provided with a track-cross function y Drive output PWM drive function supported y Provided with supply voltage monitoring and a servo gain automatic adjustment function (Digital Signal Processing) y Containing DSL and analog / digital PLL y Provided with a frame synchronous detection / protection / interpolation y Subcode data processing Q-data CRC check On-chip Q-data register On-chip CD-TEXT data register y CIRC error correction C1 decoder: double error correction C2 decoder: triple / quadruple error correction On-chip deinterleaving 16-K RAM y CD-ROM error correction Q decoder: an error correction P decoder: an error correction Mode1 and Mode 2 compatible y Audio data interpolation processing 4-sampling average value interpolation and previous value hold (Spindle Motor Servo) y CLV digital servo y Servo gain setting function y Shaft loss compensation setting function (Audio Circuit) y Soft muting y Digital attenuation (2048 levels) y Soft attenuation (2048 levels) y Digital audio interface (EIAJ format) y 8 × -oversampling digital filter y On-chip low-voltage OP amp y Bass boost filter, high-band notch filter, and surround function y On-chip digital de-emphasis SDD00031AEM 3 MN662793 Features (continued) (MP3 Decoding) y Decoding of asignals recorded in MPEG1-layer3 or MPEG2-layer3 format y Decoding of asignals recorded in MPEG1-layer2 or MPEG2-layer2 format y Decoding of asignals recorded in MPEG2.5 format y Sampling rate conversion from signals recorded at Fs = 32 kHz or 48 kHz to 44.1 kHz (WMA Decoding) y Decoding of signals recorded in WMA Ver. 8 format (Sampling rate: 48 kHz to 22.05 kHz) y Supporting special playback (forward, reverse, and resume playback) (SD Interface) y Stream serial input from SD available (Anti-shock Memory Controller) y ADPCM 4-bit compression or expansion / decompression in full-bit (16 bits) mode y External DRAM selectable Async DRAM (Data bus width: 4 bits) 64M-bit DRAM × 1 16M-bit DRAM × 2 16M-bit DRAM × 1 + 4M-bit DRAM × 1 16M-bit DRAM × 1 4M-bit DRAM × 2 4M-bit DRAM × 1 1M-bit DRAM × 2 1M-bit DRAM × 1 Async DRAM (Data bus width: 16 bits) 128M-bit DRAM × 1 64M-bit DRAM × 1 16M-bit DRAM × 1 4M-bit DRAM × 1 SDRAM (Data bus width: 16 bits) 128M-bit DRAM × 1 64M-bit DRAM × 1 16M-bit DRAM × 1 4M-bit DRAM × 1 (Others) y Disc rotation mechanism has a synchronous playback (jitter-free) mode (– 50 % to + 50 %) y 8 × -speed playback (when using jitter-free function) y TX output (1 × -, 2 × -, 3 ×-and 4 ×-speed) supported y Serial data output pitch shift function A patent license must be acquired from the management company when using MPEG Layer3 products. Applications y Signal processing LSI for CDs (Compact Discs) SDD00031AEM 4 LOVDD2 IOVDD1, 2 DRVDD1, 2 SDD00031AEM LOVSS2 LOVSS2 DVSS1, 2, 3 DVSS AVSS AVSS OUTR LOVSS1 LOVDD1 OUTL AVDD AVDD 100 µF 1 kΩ 0.1 µF 1 kΩ LOVSS1 + - 15 Ω LOVDD1 47 kΩ 0.0018 µF + 22 µF 47 kΩ 0.0018 µF + 47 kΩ 47 kΩ 22 µF 100 pF 47 kΩ 100 pF 100 pF 47 kΩ 100 pF 2.2 kΩ 1.5 kΩ + 2.2 kΩ 1.5 kΩ + 0.001 µF 22 µF 560 Ω 0.001 µF 22 µF 560 Ω 47 kΩ 47 kΩ y D/A Converter MN6627932CF LOVDD2 IOVDD DRVDD MN662793 Application Circuit 5 MN662793 Block Diagram SDD00031AEM 6 MN662793 Pin Arrangement Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands. SDD00031AEM 7 MN662793 Pin Descriptions Pin No. Symbol I/O Function 1 D11 I/O DRAM data signal I/O 11 2 D10 I/O DRAM data signal I/O 10 3 D9 I/O DRAM data signal I/O 9 4 D8 I/O DRAM data signal I/O 8 5 UDQM O SDRAM upper byte data mask signal output 6 SDRCK O SDRAM clock signal output 7 A11 O DRAM address signal output 11 8 A9 O DRAM address signal output 9 9 A8 O DRAM address signal output 8 10 A7 O DRAM address signal output 7 11 A6 O DRAM address signal output 6 12 A5 O DRAM address signal output 5 13 A4 O DRAM address signal output 4 14 LDQM O SDRAM lower byte data mask signal output 15 NWE O DRAM write enable signal output 16 NCAS O DRAM CAS control signal output 17 NRAS O DRAM RAS control signal output 18 NCS O SDRAM chip select signal output 19 A3 O DRAM address signal output 3 20 A2 O DRAM address signal output 2 21 A1 O DRAM address signal output 1 22 A0 O DRAM address signal output 0 23 DRVDD1 I Power supply 1 for DRAM interface I/O 24 DVSS1 I Ground 1 for digital circuits 25 A10 O DRAM address signal output 10 26 *BA1 O SDRAM bank selection signal output 1 27 *BA0 O SDRAM bank selection signal output 0 28 DVDD1 I Power supply 1 for internal digital circuits 29 SPOUT O Spindle drive signal output (absolute value) 30 *SPPOL O Spindle drive signal output (polarity) 31 TRVP O Traverse drive signal output (positive polarity) Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands. The specifications of the DRAM pins depend on their type and capacitance. SDD00031AEM 8 MN662793 Pin Descriptions (continued) Pin No. Symbol I/O Function 32 *TRVM O Traverse drive signal output (negative polarity) 33 *TRVP2 O Traverse drive signal output 2 (positive polarity) 34 *TRVM2 O Traverse drive signal output 2 (negative polarity) 35 TRP O Tracking drive signal output (positive polarity) 36 *TRM O Tracking drive signal output (negative polarity) 37 FOP O Focus drive signal output (positive polarity) 38 *FOM O Focus drive signal output (negative polarity) 39 IOVDD1 I Power supply 1 for digital I/O 40 TBAL O Tracking balance adjustment signal output 41 FBAL O Focus balance adjustment signal output 42 FE I Focus error signal input 43 TE I Tracking error signal input 44 ADPVCC I Voltage input for supply voltage monitor 45 RFENV I RF envelope signal input 46 LDON O Laser ON signal output 47 NRFDET I RF detection signal input 48 OFT I Off-track signal input 49 BDO I Dropout signal input 50 AVDD I Power supply for analog circuits 51 IREF I Analog reference current input 52 ARF I RF signal input 53 DSLF O DSL loop filter pin 54 PWMSEL I PWM output mode selection input Low: Direct High: 3-state 55 PLLF O PLL loop filter pin (for phase comparison output) 56 PLLFO O PLL loop filter pin (for speed comparison output) 57 AVSS I Ground for analog circuits 58 LOOUTL O L-ch. audio output for line-out output 59 LOVSS1 I Ground for line-out output 60 LOOUTR O R-ch. audio output for line-out output 61 LOVDD1 I Power supply for line-out output 62 NTEST2 I Test mode setting input (L fix) 63 TMON1 O Test monitor output 1 Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands. SDD00031AEM 9 MN662793 Pin Descriptions (continued) Pin No. Symbol I/O 64 LOVDD2 I Power supply for Audio output 65 LOVSS2 I Ground for Audio output 66 TMON2 O Test monitor output 2 67 DVDD3 I Power supply 3 for digital circuits 68 DVSS2 I Ground 2 for digital circuits 69 *EXT0 I/O Expansion I/O port 0 70 * EXT1 I/O Expansion I/O port 1 71 *EXT2 I/O Expansion I/O port 2 72 MCLK I Microcontroller command clock signal input 73 MDATA I Microcontroller command data signal input 74 MLD I Microcontroller command load signal input STAT O Status signal output 76 *BLKCK O Subcode block clock signal output 77 *SMCK O 4.2336 MHz / 8.4672 MHz clock signal output 78 *PMCK O 88.2 kHz clock signal output 79 *TX O Digital audio interface signal output 80 *FLAG O Flag signal output 81 NRST I LSI reset signal input 82 NTEST I Test mode setting input 83 DVSS3 I Ground 3 for digital circuits 84 X1 I Crystal oscillator circuit input 85 X2 O Crystao oscillator circuit output 86 IOVDD2 I Power supply 2 for digital I/O 87 DVDD2 I Power supply 2 for internal digital circuits 88 D2 I/O DRAM data signal I/O 2 89 D1 I/O DRAM data signal I/O 1 90 D0 I/O DRAM data signal I/O 0 91 D3 I/O DRAM data signal I/O 3 92 D4 I/O DRAM data signal I/O 4 93 D5 I/O DRAM data signal I/O 5 94 D6 I/O DRAM data signal I/O 6 95 D7 I/O DRAM data signal I/O 7 75 * Function Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands. SDD00031AEM 10 MN662793 Pin Descriptions (continued) Pin No. Symbol I/O Function 96 D15 I/O DRAM data signal I/O 15 97 D14 I/O DRAM data signal I/O 14 98 DRVDD2 I 99 D13 I/O DRAM data signal I/O 13 100 D12 I/O DRAM data signal I/O 12 Power supply 2 for DRAM interface I/O Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands. The specifications of the DRAM pins depend on their type and capacitance. SDD00031AEM 11 MN662793 Absolute Maximum Ratings Parameter Ta = 25°C±2°C Symbol Rating Unit Note – 0.3 to + 4.6 V DVSS1, 2, 3 = 0 V AVSS = 0 V LOVSS1, 2 = 0 V A1 Supply voltage DRVDD1, 2 IOVDD1, 2 AVDD LOVDD1, 2 A2 Internal supply voltage DVDD1, 2, 3 – 0.3 to + 2.0 V DVSS1, 2 = 0 V AVSS1, 2 = 0 V LOVSS1, 2 = 0 V VI DVSS1, 2, 3 – 0.3 to DRVDD1, 2 + 0.3 (Upper limit: 4.6 V) DVSS1, 2, 3 – 0.3 to IOVDD1, 2 + 0.3 (Upper limit: 4.6 V) AVSS – 0.3 to AVDD + 0.3 (Upper limit: 4.6 V) LOVSS1, 2 – 0.3 to LOVDD1, 2 + 0.3 (Upper limit: 4.6 V) V DVSS1, 2, 3 = 0 V AVSS = 0 V LOVSS1, 2 = 0 V V DVSS1, 2, 3 = 0 V AVSS = 0 V LOVSS1 = 0 V DVSS1, 2, 3 = 0 V AVSS = 0 V LOVSS1, 2 = 0 V A3 Input voltage A4 Output voltage VO DVSS1, 2, 3 – 0.3 to DRVDD1, 2 + 0.3 (Upper limit: 4.6 V) DVSS1, 2, 3 – 0.3 to IOVDD1, 2 + 0.3 (Upper limit: 4.6 V) AVSS – 0.3 to AVDD + 0.3 (Upper limit: 4.6 V) LOVSS1, 2 – 0.3 to LOVDD1, 2 + 0.3 (Upper limit: 4.6 V) A5 Power dissipation PD 560 mW A6 Operating ambient temperature TOPR – 30 to + 85 °C A7 Storage temperature TSTG – 50 to + 125 °C Note) 1. 2. 3. 4. The absolute maximum ratings are the limit values beyond which the IC may be broken. They do not assure operations. Connect each of the DVSS1 , DVSS2 , DVSS3 , AVSS and LOVSS1, 2 pins directly to ground and use at the same voltage. Connect each of the DRVDD1 , DRVDD2 , IOVDD1 , IOVDD2 , AVDD and LOVDD1, 2 pins directly to the specified power supply and use at the same voltage. DRVDD , IOVDD1 , IOVDD2 , AVDD1 and AVDD2 should be powered up at the same time before power up the DVDD1 , DVDD2 , DVDD3 pins at the same time when not using an internal regulator. 5. Connect a bypass capacitor of 0.1 µF or larger between each of the power supply pins and ground. SDD00031AEM 12 MN662793 Operating Supply Voltage Range Ta = –30°C ~ +85°C, DVSS1, 2, 3 = 0 V, AVSS = 0 V, LOVSS1, 2 = 0 V Limits Parameter Symbol Conditions Unit Min Typ Max B1 I/O system supply voltage IOVDD1, 2 2.2 3.3 3.6 V B2 Digital system supply voltage DVDD1, 2, 3 1.35 1.5 1.65 V B3 Analog system supply voltage AVDD 2.4 3.3 3.6 V B4 Audio system 1 supply voltage LOVDD1 2.4 3.3 3.6 V B5 Audio system 2 supply voltage LOVDD2 2.0 2.5 3.6 V B6 D-RAM interface voltage DRVDD1, 2 2.2 3.3 3.6 V SDD00031AEM 13 MN662793 Operating Supply Voltage Range (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V Limits Parameter Symbol Conditions Unit Min Typ Max Self-excited Oscillation 1 *1 B7 Oscillator frequency fxtal 16.9344 B8 Recommended external capacitance 1 C1 15 B9 Recommended external capacitance 2 C2 B10 Recommended external feedback resistance R1 1 MΩ B11 Recommended external dumping resistance Rd 470 Ω fxtal 33.8688 MHz C1 15 MHz pF 15 16.9344 MHz Oscillator *2 Self-excited Oscillation 2 *1 B12 Oscillator frequency B13 Recommended external capacitance 1 B14 Recommended external capacitance 2 C2 B15 Recommended external feedback resistance R1 1 MΩ B16 Recommended externaldumping resistance Rd 100 Ω pF 15 33.8688 MHz Oscillator *3 Note) *1: Oscillation circuit CSTCE16M9V53, CSTCG33M8V53 Rd C2 X2 Oscillator MN662793CF X1 R1 C1 *2: Values for C1 and C2 specified above are standard values when use CSTCE16M9V53 made in Murata Manufacturing Co., Ltd. as an oscillator. However, CSTCE16M9V53 builds in C1 and C2 of the above standard value. The appropriate capacitors' values differ according to the oscillator used. Use the values specified by the oscillator manufacturer. *3: Values for C1 and C2 specified above are standard values when use CSTCG33M8V53 made in Murata Manufacturing Co., Ltd. as an oscillator. However, CSTCG33M8V53builds in C1 and C2 of the above standard value. The appropriate capacitors' values differ according to the oscillator used. Use the values specified by the oscillator manufacturer. SDD00031AEM 14 MN662793 Electrical Characteristics DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (1) DC Characteristics Limits Parameter Symbol Conditions Unit Min IDD C1 Supply current C2 I/O / analog system supply current C3 Audio system 2 current C4 Total power consumption PT C5 Supply current IDD C6 I/O / analog system supply current C7 Audio system 2 current C8 Total power consumption PT C9 Supply current IDD C10 I/O / analog system supply current C11 Audio system 2 current C12 Total power consumption PT C13 Supply current IDD C14 I/O / analog system supply current C15 Audio system 2 current C16 Total power consumption IDD(A, L1) IDD(L2) IDD(A, L1) IDD(L2) IDD(A, L1) IDD(L2) IDD(A, L1) IDD(L2) PT Anti-shock memory function used. No external load connected. (in 2x-speed playback mode) ADPCM compression: ON MP3 decode: OFF CD-ROM decode: OFF Digital PLL: OFF Anti-shock memory function used. No external load connected. (in 4x-speed playback mode) MP3 decode: ON CD-ROM decode: ON Digital PLL: OFF Anti-shock memory function used. No external load connected. (in 4x-speed playback mode) WMA decode: ON CD-ROM decode: ON Digital PLL: OFF Anti-shock memory function used. No external load connected. (in 8x-speed playback mode) MP3 decode: OFF CD-ROM decode: OFF Digital PLL: OFF SDD00031AEM Typ Max 22 65 mA 12 24 mA 8 20 mA 92.6 227 mW 24 70 mA 14 28 mA 2 20 mA 102.2 247 mW 25 75 mA 16 32 mA 8 20 mA 110.3 278 mW 24 70 mA 16 32 mA 8 20 mA 108.8 261 mW 15 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (1) DC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Input Pins 1 DRVDD voltage type Typ Max D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 C17 High-level input voltage VIH1 2.31 3.30 V C18 Low-level input voltage VIL1 0.0 0.99 V C19 Input leakage current ILK1 ±1 µA Input Pins 2 IOVDD voltage type VIN = 0 V or 3.3 V EXT0, EXT1, EXT2, MCLK, MDATA, MLD, NRST, TEST C20 High-level input voltage VIH2 2.31 3.30 V C21 Low-level input voltage VIL2 0.0 0.99 V C22 Input leakage current ILK2 ±1 µA Input Pins 3 AVDD voltage type VIN = 0 V or 3.3 V NRFDET, OFT , BDO, PWMSEL C23 High-level input voltage VIH3 2.31 3.30 V C24 Low-level input voltage VIL3 0.0 0.99 V C25 Input leakage current ILK3 ±1 µA VIN = 0 V or 3.3 V SDD00031AEM 16 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (1) DC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Typ Max Output Pins 1 DRVDD voltage type D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, UDQM, LDQM, SDRCK, NWE, NCAS, NRAS, NCS C26 High-level output voltage VOH1 IOH1 = – 1.0 mA C27 Low-level output voltage VOL1 IOL1 = 1.0 mA Output Pins 2 DRVDD voltage type 2.7 V 0.4 V BA0, BA1 C28 High-level output voltage VOH2 IOH2 = – 1.0 mA C29 Low-level output voltage VOL2 IOL2 = 1.0 mA 0.4 V C30 Output leakage current OLK2 Hi-Z state VO = 0 V or 3.3 V ±1 µΩ Output Pins 3 IOVDD voltage type 2.7 V SPPOL, TRVM, TRM, FOM, STAT, TX C31 High-level output voltage VOH3 IOH3 = – 1.0 mA C32 Low-level output voltage VOL3 IOL3 = 1.0 mA 2.7 V 0.4 V Output Pin 4 IOVDD voltage type SPOUT, TRVP, TRVP2, TRVM2, TRP, FOP, TMON1, TMON2, EXT0, EXT1, EXT2, BLKCK, SMCK, PMCK, FLAG C33 High-level output voltage VOH4 IOH4 = – 1.0 mA C34 Low-level output voltage VOL4 IOL4 = 1.0 mA 0.4 V C35 Output leakage current OLK4 Hi-Z state VO = 0 V or 3.3 V ±1 µA Output Pins 5 AVDD voltage type 2.7 V LDON C36 High-level output voltage VOH5 IOH5 = – 1.0 mA C37 Low-level output voltage VOL5 IOL5 = 1.0 mA 0.4 V C38 Output leakage current OLK5 Hi-Z state VO = 0 V or 3.3 V ±1 µA SDD00031AEM 2.7 V 17 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (1) DC Characteristics (continued) Limits Parameter Analog System Input Pin 1 C39 C41 Unit Min Typ Max 41 IREF When pulled up with an 82-k Ω resistor. 18 29 VARF EFM signal input level in an application circuit of DSL block. 0.5 1.0 REGSEL: R1 + R2 + R3 setting 65 100 135 REGSEL: R2 + R3 setting 26 40 54 REGSEL: R3 setting 13 20 27 REGSEL: R1 + R2 + R3 and RFSW = ON setting 32 50 68 µA ARF nput signal amplitude Internal resistance between ARF and DSLF pins Analog System Input Pin 3 Conditions IREF Input current Analog System Input Pin 2 C40 Symbol RARF V[P-P] kΩ TE, FE, RFENV, ADPVCC C42 High-level input voltage VIH4 C43 Low-level input voltage VIL4 LOVDD2 System Input Pin 5 2.97 0.33 V V NTEST2 C44 High-level input voltage VIH5 1.75 2.50 V C45 Low-level input voltage VIL5 0.00 0.75 V C46 Input leakage current ILK5 ± 1.0 µA 8 bit A/D Converter (for servo) C47 Resolution RES C48 Integral nonlinearity INL C49 Differential nonlinearity DNL A/D output = 99 to 66 (2's complement) SDD00031AEM ±2 ±3 LSB 18 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (1) DC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Analog System Output Pin 1 Typ Max DSLF (IREF pin is pulled up to AVDD with an 82 kΩ resistor) C50 Output current (N) IDSH BDO: Low, Tracking ON state DSLF = 1.65 V 56 80 104 C51 Output current (P) IDSH BDO: Low, Tracking ON state DSLF = 1.65 V – 104 – 80 – 56 C52 Output unbalance current IDSEL BDO: Low, Tracking ON state Normal current mode –7 0 7 Analog System Output Pin 2 PLLF (IREF pin is pulled up to AVDD with an 82 kΩ resistor) C53 Phase comparator output current (N) IPFH PLLF = 1.65 V 56 80 104 C54 Phase comparator output current (P) IPFH PLLF = 1.65 V – 104 – 80 – 56 C55 Input leakage current ILKP Hi-Z state C56 Output unbalance current IPLBL PLLF = 1.65 V C57 VCO oscillator frequency for PLL fVCO1 Analog System Output Pin 3 µA ±1 – 10 0 25.9 10 103.7 MHz PLLFO (IREF pin is pulled up to AVDD with an 82 kΩ resistor) C58 Output current (N) IPFHO 59 85 111 C59 Output current (P) IPFHO – 111 – 85 – 59 C60 Input leakage current ILKPO Analog System Output Pin 4 µA µA ±1 Hi-Z state TBAL, FBAL (IREF pin is pulled up to AVDD with an 82 kΩ resistor) C61 Output current (N) IBAH At default setting (× 1) 15 22 29 C62 Output current (P) IBAL At default setting (× 1) – 29 – 22 – 15 SDD00031AEM µA 19 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (1) DC Characteristics (continued) Recommended Circuit for DSL and PLL Blocks (AVDD = 3.3V) Note) The above is a basic circuit. Calculate the constants and other factors of the circuit in consideration of playability when making use of this circuit for actual applications. SDD00031AEM 20 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (1) DC Characteristics (continued) Recommended Circuit for DSL and PLL Blocks (AVDD = 2.4 V) Note) The above is a basic circuit. Calculate the constants and other factors of the circuit in consideration of playability when making use of this circuit for actual applications. SDD00031AEM 21 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (1) DC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Typ Max D/A Converter Analog Characteristics C63 Signal-to-noise ratio S/N EIAJ 90 97 dB C64 Dynamic range D. R. EIAJ 86 94 dB C65 Total harmonic distortion ratio THD + N EIAJ C66 Crosstalk EIAJ C67 Output level 1 1 kHz F. S. *1 C68 Output level difference Difference between OUTL and OUTR pins at output level 20 log (VR / VL) C69 Output level 2 1 kHz F.S. *2 0.005 80 85 1.04 1.33 – 0.99 0.69 0.88 0.009 % dB 1.62 V[rms] + 0.99 dB 1.07 V[rms] Note) 1. The analog characteristics show the measured values when inserting a 15 0Ω resistor between LOVDD1 and power supply. The analog characteristics is prescribed when LOVDD1 voltage is 3.3V. The above typical values are only reference values and not guaranteed. 2. With no anti-shock memory function used, the operation of the D/A converter will not be guaranteed in modes other than normal-speed playback. 3. *1: The output level 1 shows the measured value at the output pin of the application circuit below. *2: The output level 2 shows a value at the output pin of the IC and is calculated by taking the measured value of output level 1, dividing it by the circuit gain. SDD00031AEM 22 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics Limits Parameter Symbol Conditions Unit Min Typ Max Reset Timing *1 C70 TNRSTL NRST pulse width µs 200 Power Supply Ripple Noise *2 C71 Ripple amplitude VRIP 15 mV[p-p] C72 Ripple noise amplitude VNZ 30 mV[p-p] Note) *1: When the power is turned on, reset with the NRST pulse which is equal to or exceeds the above pulse width only after the clock oscillation is stabilized within ±10% of error of the specified oscillator frequency. Keep noise on the reset line as low as possible. TNRSTL NRST 0.2 VDD 0.2 VDD *2: The standard ripple noise values of the IC are guaranteed on condition that the values apply to typical 50-Hz to 100-Hz ripples with 500 kHz typical noise and that both the ripples and noise are in sine waveform as shown below. The values, however, vary under the influence of other parts located on the PCB. Therefore, be sure to apply the IC to practical applications and check the actual ripple noise values. Noise frequency: 500 kHz VNZ VRIP Ripple frequency: 50 Hz to 100 Hz SDD00031AEM 23 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Transition Time 1 Typ Max MCLK, MLD C73 Rise time TR1 250 ns C74 Fall time TF1 250 ns Transition Time 2 * SBCK, TXTCK C75 Rise time TR2 50 ns C76 Fall time TF2 50 ns 0.7 IOVDD 0.3 IOVDD 0.7 IOVDD 0.3 IOVDD TR1, 2 TF1, 2 Note) *: SBCK and TXTCK are output from EXT1. SDD00031AEM 24 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Typ Max Microcontroller Command Input Timing C77 Clock frequency fMCLK C78 Clock pulse width TCH,CL 150 ns C79 Data setup time TDSU 150 ns C80 Data hold time TDH 150 ns C81 MLD delay time TLDD 150 ns C82 Latch pulse time TLDW 0.5 C83 MCLK delay time TCKD 300 2 10 MHz µs ns 1/fMCLK MCLK TCH TCL MDATA TDSU TDH MLD TLDD SDD00031AEM TLDW TCKD 25 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Sub code Interface *1 Typ Max SBCK, SUBC, TXNCLDCK C84 Clock width TCK 909 ns C85 High-level pulse width TCKH 400 ns C86 Low-level pulse width TCKL 400 ns C87 Delay time TSBD C88 When digital filter is used. *2 350 ns When no filter is used. *2 173 ns 150 ns TSD Setup delay time TCK TCKL SBCK TCKH SUBC TSD TSBD TXNCLDCK Note) *1: SBCK is output from EXT1, SUBC is output from EXT0, and TXNCLDCK is output from EXT2. *2: SBCK,TXTCK noise filter command is SBCKNF (by setting the D5 and D4 bits of the 67 command) . SDD00031AEM 26 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Subcode Interface Typ Max TXTCK, TXTD, DQSY C89 Clock frequency TCK 2500 ns C90 High-level pulse width TCKH 1200 ns C91 Low-level pulse width TCKL 1200 ns C92 Delay time TSBD 1150 ns C93 Setup delay time TSD 1100 ns TCK TCKH TXTCK TCKL TXTD TSD TSBD DQSY Note) 1. TXTCK is input or output from EXT1, TXTD is input or output from EXT0, and DQSY is input or output from EXT2. 2. The cycle width of the readout clock TXTCK is proportional to disc rotation speed. High-speed readout such as high-speed CLV playback or high-speed jitter-free playback using MSON (Memory system setting) is possible. Example) When in 2x speed mode TSBD2 = 450 ns (Typ.) SDD00031AEM 27 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Typ Max STAT Output Interface (When analog filter 1 is used.) C94 Clock width TMT 909 ns C95 High-level pulse width TMTH 300 ns C96 Low-level pulse width TMTL 300 ns C97 Delay time TMTD 225 ns STAT Output Interface (When analog filter 2 is used.) C98 Clock width TMT 500 ns C99 High-level pulse width TMTH 220 ns C100 Low-level pulse width TMTL 220 ns C101 Delay time TMTD 200 ns STAT Output Interface (When no noise filter is used.) C102 Clock width TMT 500 ns C103 High-level pulse width TMTH 220 ns C104 Low-level pulse width TMTL 220 ns C105 Delay time TMTD 173 ns TMT TMTL TMTH MCLK STAT TMTD Note) 1. In multiple-byte read mode using REGRD command (96h), VWA_ID command (97h), or VWAIDRD command (98h), it is necessary to set the high-level pulse width TMTH to more than 450 ns in 1-byte increments. 2. MCLK,MDATA,MLD noise filter command is MCIFNF (by setting the D5 and D4 bits of the 67 command) . SDD00031AEM 28 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Typ Max D/A Output Interface 1 C106 Clock width TBCLK 354 Ns C107 High-level pulse width TBCLKH 177 Ns C108 Low-level pulse width TBCLKL 177 Ns C109 Setup time TST 70 Ns C110 Hold time THD 70 Ns In normal-speed playback mode (64fs) D/A Output Interface 2 C111 Clock width TBCLK C112 High-level pulse width TBCLKH TBCLKL In 4x-speed playback mode (48fs) 118 Ns 59 Ns 59 Ns C113 Low-level pulse width C114 Setup time TST 30 Ns C115 Hold time THD 30 Ns D/A Output Interface 3 C116 Clock width TBCLK 59 Ns C117 High-level pulse width TBCLKH 29.5 Ns C118 Low-level pulse width TBCLKL 29.5 Ns C119 Setup time TST 15 Ns C120 Hold time THD 15 Ns D/A Output Interface In 8x-speed playback mode (48fs) TBCLK TBCLKL TBCLKH BCLK SRDATA LRCK TST THD Note) SRDATA, BCLK, and LRCK are output in combination with PMCK (BCLK), FLAG (SRDATA), and SMCK (LRCK) or EXT0 (SRDATA), EXT1 (LRCK), and EXT2 (BCLK). SDD00031AEM 29 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Typ Max D/A Converter Input Timing 1 (When no noise filter is used.) C121 BCLK frequency fBCLK 2.8 C122 SCLK pulse width TCH,CL 100 Ns C123 Data setup time TDSU 100 Ns C124 Data hold time TDH 100 Ns C125 LRCK frequency fLRCK C126 BCLK-LRCK timing 44.1 TBL,TLB Ns KHz 100 Ns D/A Converter Input Timing 2 (When digital filter is used.) C127 BCLK frequency fBCLK 2.8 C128 SCLK pulse width TCH,CL 150 Ns C129 Data setup time TDSU 100 Ns C130 Data hold time TDH 100 Ns C131 LRCK frequency fLRCK C132 BCLK-LRCK timing 44.1 TBL,TLB Ns KHz 100 Ns 1/fBCLK BCLKIN TCH TCL SRDATAIN TDSU TDH LRCKIN TBL TLB TBL TLB 1/fLRCK Note) 1. SRDATAIN,BCLK,LRCK noise filter command is SRDATANF (by setting the D7 and D6 bits of the 67 command) . 2. SRDATAIN, LRCKIN, and BCLKIN are input from EXT0 (SRDATAIN), EXT1 (LRCKIN), and EXT2 (BCLKIN) respectively. SDD00031AEM 30 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) In BCKSEL = 0 mode Limits Parameter Symbol Conditions Unit Min Typ Max EDO, First-Page DRAM Interface Read / Write Cycle C133 A0 to A11 row address setup time tASR 2 cycle C134 A0 to A11 row address hold time tRAH 1 cycle C135 A0 to A11 column address setup time tASC 1 cycle C136 A0 to A11 column address hold time tCAH 2 cycle C137 RAS-CAS delay time (NCAS0, NCAS1) tRCD 2 cycle C138 RAS access time tRAC 4 cycle C139 CAS access time tCAC 2 cycle C140 Write enable signal NWE setup time tWCS 2 cycle C141 Write enable signal NWE hold time tWCH 2 cycle C142 D0 to D15 write data setup time tDWDS 1 cycle C143 D0 to D15 write data hold time tDWDH 2 cycle EDO, First-Page DRAM Interface Page Mode Data Transfer C144 CAS pre-charge pulse width tCP 1 cycle C145 CAS low-level pulse width tCAS 2 cycle C146 RAS hold time tRSH 2 cycle EDO, First-Page DRAM Interface CAS Before RAS Refresh C147 CAS-RAS delay time tCRD 1 cycle C148 Refresh RAS low-level pulse width tRRAS 4 cycle C149 Refresh CAS low-level pulse width tRCAS 5 cycle Note) One cycle is the system clock cycle of 1 / (16.9344 MHz or 33.8688 MHz) [s]. The system clock frequencies, 16.9344 MHz and 33.8688 MHz, are determined according to the DCKSEL command (65h command D6 and D5). SDD00031AEM 31 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) In BCKSEL = 1 mode Limits Parameter Symbol Conditions Unit Min Typ Max EDO, First-Page DRAM Interface Read / Write Cycle C150 A0 to A11 row address setup time tASR 2 cycle C151 A0 to A11 row address hold time tRAH 1 cycle C152 A0 to A11 column address setup time tASC 1 cycle C153 A0 to A11 column address hold time tCAH 1 cycle C154 RAS-CAS delay time (NCAS0, NCAS1) tRCD 2 cycle C155 RAS access time tRAC 4 cycle C156 CAS access time tCAC 1 cycle C157 Write enable signal NWE setup time tWCS 2 cycle C158 Write enable signal NWE hold time tWCH 1 cycle C159 D0 to D15 write data setup time tDWDS 1 cycle C160 D0 to D15 write data hold time tDWDH 1 cycle EDO, First-Page DRAM Interface Page Mode Data Transfer C161 CAS pre-charge pulse width tCP 1 cycle C162 CAS low-level pulse width tCAS 1 cycle C163 RAS hold time tRSH 1 cycle EDO, First-Page DRAM Interface CAS Before RAS Refresh C164 CAS-RAS delay time tCRD 1 cycle C165 Refresh RAS low-level pulse width tRRAS 4 cycle C166 Refresh CAS low-level pulse width tRCAS 5 cycle Note) One cycle is the system clock cycle of 1 / (16.9344 MHz or 33.8688 MHz) [s]. The system clock frequencies, 16.9344 MHz and 33.8688 MHz, are determined according to the DCKSEL command (65h command D6 and D5). SDD00031AEM 32 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) y EDO, First-Page DRAM Access Timing (NRAS, NCAS0, NCAS1, NWE, A0 to A11, D0 to D15) (Normal mode) A11 to A0 Row Address tASR Column Address tRAH tASC tCAH NRAS NCAS0， NCAS1 tRCD [READ] NEW (＝ H) D15 to D0 tRAC tCAC [WRITE] NWE tWCS tWCH D15 to D0 tDWDS SDD00031AEM tDWDH 33 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) y EDO, First-Page DRAM Access Timing (NRAS, NCAS0, NCAS1, NWE, A0 to A11, D0 to D15) (Page mode) A11 to A0 Row Address Column Address Column Address Column Address tCAH tASC NRAS tRSH NCAS0， NCAS1 tCAS tCP [READ] NEW (＝ H) D15 to D0 tCAC [WRITE] NWE D15 to D0 tDWDS tDWDH (CAS Before RAS Refresh Mode) NRAS tCRD tRRAS NCAS0， NCAS1 tRCAS SDD00031AEM 34 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Typ Max SDRAM Interface C167 SDRCK cycle time tCLK 1 cycle C168 SDRCK high-level pulse width tCH 0.5 cycle C169 SDRCK low-level pulse width tCL 0.5 cycle C170 NCS input setup time tCSS 0.5 cycle C171 NCS input hold time tCSH 0.5 cycle C172 NRAS input setup time tRAS 0.5 cycle C173 NRAS input hold time tRAH 0.5 cycle C174 NCAS input setup time tCAS 0.5 cycle C175 NCAS input hold time tCAH 0.5 cycle C176 New input setup time tWES 0.5 cycle C177 New input hold time tWEH 0.5 cycle C178 LDQM, UDQM input setup time tDMS 0.5 cycle C179 LDQM, UDQM input hold time tDMH 0.5 cycle C180 D0 to D15 input setup time tDQS 1 cycle C181 D0 to D15 input hold time tDQH 1 cycle C182 A0 to A11, BA0,BA1 input setup time tAS 1 cycle C183 A0 to A11, BA0, BA1 input hold time tAH 1 cycle Note) 1. One cycle is the system clock cycle of 1 / (16.9344 MHz or 33.8688 MHz) [s]. 2. Connect SDRAM near this LSI as much as possible. Connect the wiring load of the SDRCK pin specially within 5pF. SDD00031AEM 35 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) Limits Parameter Symbol Conditions Unit Min Typ Max SDRAM Interface C184 access time from SDRCK tAC C185 Hi-Z output time from SDRCK tOH 0 ns C186 low impedance output time from SDRCK tOLZ 0 ns C187 high impedance output time from SDRCK tOHZ 0 ns 15 ns Note) One cycle is the system clock cycle of 1 / (16.9344 MHz or 33.8688 MHz) [s]. SDD00031AEM 36 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) y SDRAM Access Timing (SDRCK, NCS, NCAS, NWE, LDQM, UDQM, A0 to A11, BA0, BA1, D0 to D15) tCLK [WRITE] tCH tCL SDRCK tCSS tCSH tRAS tRAH NCS NRAS tCAS tCAH NCAS tWES tWEH NWE tDMS tDMH tDMS tDMH UDQM LDQM tDQS D0 to D15 VALID tAS A0 to A11, BA0, BA1 tDQH tAH RAS address tAS tAH CAS address SDD00031AEM 37 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) y SDRAM Access Timing (continued) (SDRCK, NCS, NCAS, NWE, LDQM, UDQM, A0 to A11, BA0, BA1, D0 to D15) tCLK [READ] tCH tCL SDRCK tCSS tCSH tRAS tRAH NCS NRAS tCAS tCAH NCAS tDMS tDMH tWES tWEH UDQM tDMS tDMH LDQM tAC tOLZ D0 to D15 tAS A0 to A11, BA0, BA1 tAH RAS address tAS tAH tOHZ tOH Output decision CAS address : Invalid data SDD00031AEM 38 SDRAM Initialize Sequence (SDRCK, NCS, NCAS, NWE, A0 to A11, BA0, BA1) MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) y SDRAM Initialize Sequence (SDRCK, NCS, NCAS, NWE, A0 to A11, BA0, BA1) PALL REF REF ………. REF MRS 16 refresh 10 cycle to 15 cycle 6 cycle 6 cycle NRST SDRCK NCS NRAS NCAS NWR BA0,BA1 A0 to A11 SDD00031AEM 39 MN662793 Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V (2) AC Characteristics (continued) y SDRAM Page Access Timing (SDRCK, NCS, NRAS, NCAS, NWE, A0 to A11, BA0, BA1) Row Address Column Address RAS address CAS address1 Column Address …. Precharge SDRCK NCS NRAS NCAS UDQM LDQM A0 to A11, BA0, BA1 CAS address2 [WRITE] NWE D0 to D15 VALID2 VALID1 [READ] NWE D0 to D15 VALID1 SDD00031AEM VALID2 40 Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technical information described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the technical information as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: • Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. • Any applications other than the standard applications intended. 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Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd. 2003 SEP