Video Camera LSI MN673274 Signal-Processing IC for Multipurpose Cameras ■ Overview The MN673274 is designed for surveillance and PC input cameras. In addition to the basic functions of luminance signal and chrominance signal processing, it also integrates microcontroller functions (ALC, AWB, and AGC) and SSG, CG, and I2C-bus circuits on a single chip. ■ Features • Input: Analog signal (A/D converter input) • Output: Digital output YUV signal: 8 bits Analog outputs Y signal C signal Composite video output RGB outputs • Operating supply voltage: 3.3 V ± 0.3 V • Operating frequency: 9.5 MHz to 28.7 MHz • Main functions • 10-bit A/D converter • 10-bit D/A converter • 2-channel 8-bit D/A converter • Support for analog AGC (NN2038, NN2039) • CG and SSG functions • 510H and 768H (Supports NTSC and PAL ) • Supports progressive scan readout CCDs with complementary color filters for VGA • Supports black-and-white CCD signal processing • CCD white defect/black defect correction circuit • Maximum digital AGC gain: 24 dB • Left/right reversing function • Variable gamma correction (γ = 0.3 to 1) • ZV port conforming mode, BT656 conforming mode • External synchronization support: HD/VD, VD2, Sync., LL mode • On-chip I2C-bus circuit • ELC/AGC (Also supports external AGC) • Two-mode white balance (manual/ATW) with ATW lock function • Automatic OB correction function ■ Applications • Surveillance cameras, PC cameras 1 MN673274 Video Camera LSI ■ Block Diagram YUVOE YUV0 to 7 Y VIN 10-bit A/D AGC Y signal processing Y/C MPX 10-bit D/A C C signal processing ENC 8-bit D/A RGB CNV Horizontal drive pulse output White balance gain CG Vertical drive Sync system pulse output SSG FCK 2FCK FCKO 2FCKO 2 YUVOE 2 Composite Y/C video signal output (2-ch) Y output, G C output, B Read and write of registers for each circuit block Data Carrier signal YLPF Digital AGC control ALC ATN Sub control WE RE I2C-bus control BLK CSYNC SCL SDA PWM PWM0 PWM PWM1 PWM PWM2 PWM PWM3 Video Camera LSI MN673274 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 FCK2O FCKO VSS3 VDD3 YUV7 YUV6 YUV5 YUV4 YUV3 YUV2 YUV1 YUV0 PWM3 PWM2 PWM1 PWM0 VSS2 VDD2 A2 A1 A0 SCL SDA RESET CCDSEL2 CCDSEL1 CCDSEL0 TEST0 TEST1 TEST2 TEST3 TEST4 ■ Pin Arrangement 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VIN VREFL VREFML ADVDD ADVSS VREFM VREFHM VREFH VREF23 IREF23 COMP23 BSIG DAVSS1 DAVDD1 RSIG VREF1 IREF1 COMP1 GSIG DAVSS2 DAVDD2 VCXO LPFI FVR MINTEST SCANT HREFCBLK VCSYNCVD YUVOE NTPL PCO EXTMOD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 N.C. V4 V3 VSS5 VDD5 V2 N.C. V1 N.C. SUB N.C. CH2 N.C. CH1 OSCCNT CXIN CXOUT OSCVDD OSCVSS OSCSEL WHD FVD FWHD CPOB PBLK HCLR LLDET FLC VDD1 VSS1 EXTIN0 EXTIN1 COIN OBCTL EXTAGC IRIS ALCELC ATWLOCK APGAIN BLCSW DIN8 DIN7 DIN6 DIN5 DIN4 VDD4 VSS4 DIN3 DIN2 DIN1 DIN0 DS2 DS1 TESTDC2 N.C. R N.C. TGVDD TGVSS N.C. H2 N.C. H1 N.C. (TOP VIEW) 3 MN673274 Video Camera LSI ■ Pin Descriptions Pin No. Pin Name I/O Description 1 N.C. 2 V4 O φ V4 charge pulse 3 V3 O φ V3 charge pulse 4 VSS5 VSS Digital system ground 5 VDD5 VDD Digital system power supply (3.3 V) 6 V2 O 7 N.C. 8 V1 O 9 N.C. 10 SUB O 11 N.C. 12 CH2 O 13 N.C. 14 CH1 O V1 charge pulse 15 OSCCNT O Oscillator control test 16 CXIN I Synchronization oscillator connection (crystal oscillator) 17 CXOUT O Synchronization oscillator connection (crystal oscillator) 18 OSCVDD VDD Oscillator cell power supply 19 OSCVSS VSS Oscillator cell ground 20 OSCSEL I Source oscillator 2FCK/4FCK switching 21 WHD O WHD signal with a normal phase to Sync 22 FVD O VD signal with a normal phase to Sync 23 FWHD O WHD for CG drive 24 CPOB O A/D converter input signal clamping pulse/ D/A converter output clamping pulse 25 PBLK O Pre-blanking pulse 26 HCLR O Horizontal reference signal 27 LLDET I Power supply synchronization switching φ V2 charge pulse φ V1 charge pulse Vertical exclusion pulse V3 charge pulse Low: internal synchronization, high: LL synchronization 28 FLC I Flicker correction (pulled-up input) High: flicker correction on 29 VDD1 VDD Digital system power supply (3.3 V) 30 VSS1 VSS Digital system ground 31 EXTIN0 I External synchronization input 1 32 EXTIN1 I External synchronization input 2 33 EXTMOD I Surveillance/automotive mode switching (pulled-up input) High: automotive mode (HDVD/Sync synchronization mode) 4 34 PCO O Phase comparator output 35 NTPL I NTSC/PAL switching Low: NTSC, high: PAL (pulled-down input) Video Camera LSI MN673274 ■ Pin Descriptions (continued) Pin No. Pin Name I/O Description 36 YUVOE I Digital output system output enable 37 VCSYNCVD O VCSYNC output/VD output (VGA mode: CSYNC, IT mode: register switching) 38 HREFCBLK O HREF output/CBLK output (VGA mode: HREF, IT mode: register switching) 39 SCANT I Test input (Normally connect low) 40 MINTEST I Test input (Normally connect low) 41 FVR I DC level input used for frequency control 42 LPFI I Low-pass filter analog switch input 43 VCXO O Analog switch output - LC oscillator 44 DAVDD2 VDD D/A converter power supply 45 DAVSS2 VSS D/A converter ground 46 GSIG O Video output (composite/G signal) Connect the resistor RL between GSIG and DAVSS2 47 COMP1 I Phase compensation Connect a 1 µF capacitor between COMP1 and DAVDD2 48 IREF1 I Bias current resistor connection Connect the resistor RIREF between IREGF1 and DAVSS2 49 VREF1 I Reference voltage input 50 RSIG O Video output (luminance/R signal) Connect the resistor RL between RSIG and DAVSS1 51 DAVDD1 VDD D/A converter power supply 52 DAVSS1 VSS D/A converter ground 53 BSIG O Video output (chrominance/B signal) Connect the resistor RL between BSIG and DAVSS1 54 COMP23 I Phase compensation Connect a 1 µF capacitor between this pin and DAVDD1 55 IREF23 I Bias current resistor connection Connect the resistor RIREF between this pin and DAVSS1 56 VREF23 I Reference voltage input 57 VREFH I High-level reference voltage input 58 VREFHM I Intermediate reference potential Connect a capacitor between this pin and ADVSS 59 VREFM I Intermediate reference potential Connect a capacitor between this pin and ADVSS 60 ADVSS VSS A/D converter power supply 61 ADVDD VDD A/D converter ground 62 VREFML I Intermediate reference potential Connect a capacitor between this pin and ADVSS 63 VREFL I Low-level reference voltage input 64 VIN I Analog signal input 65 TEST4 I Test input (Normally connect low) 66 TEST3 I Test input (Normally connect low) 67 TEST2 I Test input (Normally connect low) 68 TEST1 I Test input (Normally connect low) 69 TEST0 I Test input (Normally connect low) 70 CCDSEL0 I CCD switching 71 CCDSEL1 I CCD switching 72 CCDSEL2 I CCD switching 5 MN673274 Video Camera LSI ■ Pin Descriptions (continued) Pin No. Pin Name I/O 73 RESET I 74 SDA I/O I2C-bus (data) 75 SCL I/O I2C-bus (clock) 76 A0 I EEPROM address (pulled-down input) 77 A1 I EEPROM address (pulled-down input) 78 A2 I EEPROM address (pulled-down input) 79 VDD2 VDD Digital system power supply (3.3 V) 80 VSS2 VSS Digital system ground 81 PWM0 O PWM signal output 82 PWM1 O PWM signal output 83 PWM2 O PWM signal output 84 PWM3 O PWM signal output 85 YUV0 O Digital Y/U/V output (LSB) 86 YUV1 O Digital Y/U/V output 87 YUV2 O Digital Y/U/V output 88 YUV3 O Digital Y/U/V output 89 YUV4 O Digital Y/U/V output 90 YUV5 O Digital Y/U/V output 91 YUV6 O Digital Y/U/V output 92 YUV7 O Digital Y/U/V output (MSB) 93 VDD3 VDD Digital system power supply (3.3 V) 94 VSS3 VSS Digital system ground 95 FCKO O FCK output 96 FCK2O O 2FCK output 97 COIN I Synchronization oscillator cell (LC oscillator) 98 OBCTL O Automatic OB correction output 99 EXTAGC O External AGC control 100 IRIS O Mechanical iris locking (PWM output) 101 ALCELC I Locked/ELC switching Low: ELC, high: locked 102 ATWLOCK I ATW stop. Low: normal, high: ATWLOCK 103 APGAIN I Aperture gain switching Low: register value, high: register value divided by 2 104 BLCSW I Backlighting correction Low: normal, high: ATWLOCK 105 DIN8 I Digital signal input (MSB) 106 DIN7 I Digital signal input 107 DIN6 I Digital signal input 108 DIN5 I Digital signal input 109 DIN4 I Digital signal input 6 Description Logic system initialization Video Camera LSI MN673274 ■ Pin Descriptions (continued) Pin No. Pin Name I/O Description 110 VDD4 VDD Digital system power supply (3.3 V) 111 VSS4 VSS Digital system ground 112 DIN3 I Digital signal input 113 DIN2 I Digital signal input 114 DIN1 I Digital signal input 115 DIN0 I Digital signal input (LSB) 116 DS2 O CDS pulse 2 117 DS1 O CDS pulse 1 118 TESTDC2 I Test input (Normally connect low) 119 N.C. 120 R O 121 N.C. 122 TGVDD VDD CG power supply 123 TGVSS VSS CG ground 124 N.C. 125 H2 O 126 N.C. 127 H1 O 128 N.C. φR pulse φH1 transfer pulse φH2 transfer pulse ■ Electrical Characteristics 1. Absolute Maximum Ratings Item Symbol Rating Unit Supply voltage (digital system) VDD − 0.3 to +4.6 V Supply voltage (analog system) AVDD − 0.3 to +4.6 V Input voltage VI − 0.3 to VDD+ 0.3 V Output voltage VO − 0.3 to VDD+ 0.3 V Output current IO ±48 mA Power dissipation PD 750 mW Operating temperature Topr −20 to +70 °C Storage temperature Tstg −55 to +150 °C Notes: 1. The absolute maximum ratings are the limiting values for which chip destruction will not occur if that level is applied. Operation is not guaranteed at these levels. 2. The VDD1, VDD2, VDD3, VDD4, VDD5, VDDTG, ADVDD, and DAVDD pins must always be held at the same potential. The VSS1, VSS2, VSS3, VSS4, VSS5, VSSTG, ADVSS, and DAVSS pins must always be held at the same potential. 7 MN673274 Video Camera LSI ■ Electrical Characteristics (continued) 2. Recommended Operating Conditions VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V Item Supply voltage (digital) Symbol VDD Condition Digital system power supply Min Typ Max Unit 3.0 3.3 3.6 V Supply voltage (digital) OSCVDD Oscillator pin power supply 3.0 3.3 3.6 V Supply voltage (analog) ADVDD A/D converter power supply 3.3 V Supply voltage (analog) DAVDD D/A converter power supply 3.3 V Duty 50% 9.5 28.7 MHz Operating frequency FOSC 3. DC Characteristics VDD = TGVDD = OSCVDD = 3.0 V to 3.6 V, ADVDD = DAVDD = 3.0 V to 3.6 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = −20°C to +70°C Item Operating supply current Symbol Min Typ Max Unit VDD = TGVDD = TGVDD = 3.6 V 80 120 mA DAIDD ADVDD = DAVDD = 3.6 V 23 33 ADIDD FCLK = 28.7 MHz, Ta = 25°C 20 40 IDD Condition Input pins 1-1 Standard input pins EXTIN0, EXTIN1, YUVOE, CCDSEL0 to CCDSEL2, RESET, COIN, ALCELC, ATWLOCK, APGAIN, BLCSW, DIN0 to DIN8, H12BSTP, VDDSW, LLDET Input voltage High level VIH VDD × 0.8 VDD Low level VIL 0 VDD × 0.2 −5 5 µA V Input leakage current ILIPD VI = VDD or VSS V Input pins 1-2 Pulled-up input pins FLC, EXTMOD Input voltage High level VIH VDD × 0.8 VDD Low level VIL 0 VDD × 0.2 Input leakage current ILIPD VI = VDD −10 10 µA Pull-up resistance RPU1 VDD = 3.3 V, VI = VSS 10 30 90 kΩ V Input pins 1-3 Pulled-down input pins OSCSEL, NTPL, SCANT, A0 to A2, TEST4 to TEST0, MINTEST Input voltage High level VIH VDD × 0.8 VDD Low level VIL 0 VDD × 0.2 Input leakage current ILIPD VI = VSS −10 10 µA Pull-down resistance PPD1 VI = VDD 10 30 90 kΩ Output pins 1-1 V4 to V1, SUB, CH2, CH1, OSCCNT, PCO, WHD, CPOB, PBLK, HCLR, PWM0 to PWM3, OBCTL, EXTAGC, IRIS Output voltage 8 High level VOH IO = − 1 mA Low level VOL IO = 1 mA VDD − 0.6 0.4 V Video Camera LSI MN673274 ■ Electrical Characteristics (continued) 3. DC Characteristics (continued) VDD = TGVDD = OSCVDD = 3.0 V to 3.6 V, ADVDD = DAVDD = 3.0 V to 3.6 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = −20°C to +70°C Item Symbol Condition Min Typ Max Unit VDD − 0.6 V 0.4 VDD − 0.6 0.4 VDD − 0.6 0.4 VDD − 0.6 Output pins 1-2 YUV7 to YUV0 Output voltage High level VOH IO = − 2 mA Low level VOL IO = 2 mA Output pins 1-3 VCSYNCVD, HREFCBLK Output voltage High level VOH IO = − 4 mA Low level VOL IO = 4 mA V Output pins 1-4 FVD, EWHD, FCKO, FCK2O Output voltage Output pins 1-5 Output voltage High level VOH IO = − 8 mA Low level VOL IO = 8 mA V DS1, DS2, R, H2, H1 High level VOH IO = − 16 mA Low level VOL IO = 16 mA 0.4 V I/O pins 1 SDA, SCL TTL Input VT+ VDD = 3.0 V to 3.6 V 1.6 2.2 Schmitt trigger input voltage Threshold voltage VT− VREF5 = 4.75 V to 5.25 V (VREF5 is an external reference voltage.) 0.6 1.2 Output voltage Low level VOL IO = 4 mA 0.4 V ILO VO = VDD or VSS − 10 10 µA 15 30 MHz Output leakage current V Oscillator pins 1 CXIN, CXOUT Standard oscillator frequency FOSC VDD = 3.3 V Using an external crystal Internal feedback resistor RFB VDD = 3.3 V VI (XI) = VDD or VSS 0.73 2.2 6.6 kΩ Output voltage High level IOH VDD = 3.3 V VI = VSS,VO = VSS − 9.2 − 23 − 57.5 mA Low level IOL VDD = 3.3 V VI = VDD,VO = VDD 9.6 24 60 9 MN673274 Video Camera LSI ■ Electrical Characteristics (continued) 4. AC Characteristics Item Symbol Condition Min Typ Max Unit 34.8 105.3 ns 50 % Input pins 2-1 CXIN Clock Period tcyc See figure 1 waveform Clock duty dclk See figure 1 dclk = thi/tcyc Output pins 1 OSCCNT, PCO, PWM0 to PWM3, YUV0 to YUV7, WHD, CPOB, PBLK, HCLR, VCSYNCVD, HREFCBLK, FVD, EWHD, OBCTL, EXTAGC, IRIS, FCKO, FCK2O, V1 to V4, SUB, CH1, CH2, DS1, DS2, R, H2, H1 tcyc thi Clock CLK Vclk/2 tclk tod VDD/2 Output Figure 1. I/O Timing 5. A/D Converter VDD = TGVDD = OSCVDD = 3.3 V, ADVDD = DAVDD = 3.3 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = 25°C Pins: VIN, VREFH, VREFL, VREFM, VREFML, and VREFHM Item Symbol Condition Min Typ Max Unit A/D Converter Recommended Operating Conditions Analog input voltage VAIN VIN VREFL VREFH V Analog input pin capacitance CAI VIN 330 pF Reference voltage high level VREFH VREFH 2.5 V Reference voltage low level VREFL VREFL 0.5 V Reference resistor (VREFL−VREFH) RREF 440 Ω Resolution RES 10 bit Nonlinearity error NLE FADCK = 20 MHz ± 5.0 ± 7.5 LSB VREFH = 2.5 V VREFL = 0.5 V ± 2.0 ± 6.5 LSB VREFH − VREFL V[p-p] A/D converter characteristics Differential nonlinearity error DNLE Analog input dynamic range VAIN 10 Video Camera LSI MN673274 6. D/A Converter VDD = TGVDD = OSCVDD = 3.3 V, ADVDD = DAVDD = 3.3 V, VSS = TGVSS = OSCVSS = ADVSS = DAVSS = 0 V, Ta = 25°C 1) Pins: VREF23, IREF23, COMP23, BSIG, and RSIG Item Symbol Condition Min Typ Max Unit RL = 75 Ω RIREF23 = 820 Ω 1.37 V Connect between the COMP23 pin and AVDD. 1.0 µF Connect these between the BSIG and RSIG pins respectively, and AVSS. 75 Ω Connect between the IREF23 pin and AVSS. 820 Ω 8 bit D/A Converter Recommended Operating Conditions Reference voltage VREF External phase assurance capacitor CCOMP External output resistors RL External bias current setting resistor RIREF D/A converter characteristics Resolution RES Nonlinearity error INLE RL = 75 Ω ± 2.5 LSB Differential nonlinearity error DNLE VREF23 = 1.37 V RIREF23 = 820 Ω ± 2.5 LSB Full-scale voltage VOFS 1.0 V Zero-scale voltage VOZS 0 V Min Typ Max Unit RL = 75 Ω RIREF1 = 1.13 kΩ 1.5 V Connect between the COMP1 pin and AVDD. 1.0 µF 2) Pins: VREF1, IREF1, COMP1, and GSIG Item Symbol Condition D/A Converter Recommended Operating Conditions Reference voltage VREF External phase assurance capacitor CCOMP External output resistors RL Connect between the GSIG pin and AVSS. 75 Ω RIREF Connect between the IREF1 pin and AVSS. 1.13 kΩ 10 bit External bias current setting resistor D/A converter characteristics Resolution RES Nonlinearity error INLE RL = 75 Ω ± 2.5 LSB Differential nonlinearity error DNLE VREF1 = 1.5 V RIREF1 = 1.13 kΩ ± 2.5 LSB Full-scale voltage VOFS 1.0 V Zero-scale voltage VOZS 0 V 11 MN673274 Video Camera LSI ■ Application System Examples 1. Example A (Minimum configuration) • Internal synchronization • Composite video output EEPROM Color CCD CDS MN673274 75 Ω driver Vertical driver EEPROM 2. Example C • Internal synchronization • RGB output Color CCD CDS MN673274 Vertical driver 75 Ω driver R 75 Ω driver G 75 Ω driver B EEPROM 3. Example D (Surveillance camera) • External synchronization • YC output LL pulse Color CCD CDS AGC MN673274 YC mixer Vertical driver Analog switch 4. Example E (PC camera) • Internal synchronization • Digital output VCXO VCXO EEPROM Color CCD CDS YUV MN673274 8-bit Vertical driver 5. Example F • Internal synchronization • Y output EEPROM Black-andwhite CCD Vertical driver 12 CDS MN673274 75 Ω driver 75 Ω driver VD2 separation Video Camera LSI MN673274 ■ Package Dimensions (units: mm) • LQFP128-P-1818C 20.00±0.20 18.00±0.10 96 65 64 128 33 18.00±0.10 20.00±0.20 (1.25) 97 32 0.20±0.05 0.10 M 0.10 Seating plane 0.10±0.10 1.70max. 1.40±0.10 0.50 0.15±0.05 1 (1.25) (1.00) 0° to 10° 0.50±0.20 13 Request for your special attention and precautions in using the technical information and semiconductors described in this material (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuit examples of the products. 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